From: cand@51b69dee28eeccfe0f04790433b843689895c6e3 <cand@web>
Date: Sat, 12 Dec 2020 17:14:30 +0000 (+0000)
Subject: Examples of different width ops
X-Git-Tag: convert-csv-opcode-to-binary~1384
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de7002dca60609ede6b1f5f1bdf502c5d34600cb;p=libreriscv.git

Examples of different width ops
---

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 3b0830295..0bb8fc2e5 100644
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -81,6 +81,14 @@ Note:
   be proven using the lower will lead to the same result
 * saturation is done on the result at the **dest** elwidth
 
+Some examples on different operation widths:
+
+    u16 / u16 = u8
+    256 / 2 = 128 # if we used the smaller width, we'd get 0. Wrong
+
+    u8 * u8 = u16
+    255 * 2 = 510 # if we used the smaller width, we'd get 254. Wrong
+
 # Notes about rounding, clamp and saturate
 
 One of the issues with vector ops is that in integer DSP ops for example in Audio the operation must clamp or saturate rather than overflow or ignore the upper bits and become a modulo operation.  This for Audio is extremely important, also to provide an indicator as to whether saturation occurred.  see  [[av_opcodes]].