From: Tom Stellard Date: Sat, 2 Jun 2012 11:09:16 +0000 (-0400) Subject: radeon/llvm: Remove AMDIL VCREATE* instructions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de7366701d21842787d65320c12e6b4ecaea3807;p=mesa.git radeon/llvm: Remove AMDIL VCREATE* instructions This obsoletes the AMDGPULowerInstruction pass. --- diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h index 9d81bc22336..191f495eaa4 100644 --- a/src/gallium/drivers/radeon/AMDGPU.h +++ b/src/gallium/drivers/radeon/AMDGPU.h @@ -28,7 +28,6 @@ FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm); FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); // Passes common to R600 and SI -FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm); FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm); } // End namespace llvm diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td index 28ea93d06ed..9ec9c4d0356 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstructions.td +++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td @@ -104,6 +104,12 @@ class Insert_Element ; +// Vector Build pattern +class Vector_Build : Pat < + (IL_vbuild elemClass:$src), + (INSERT_SUBREG (vecType (IMPLICIT_DEF)), elemClass:$src, sel_x) +>; + // bitconvert pattern class BitConvert : Pat < (dt (bitconvert (st rc:$src0))), diff --git a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp b/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp deleted file mode 100644 index d129a3bbb21..00000000000 --- a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp +++ /dev/null @@ -1,88 +0,0 @@ -//===-- AMDGPULowerInstructions.cpp - AMDGPU lowering pass ----------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This pass lowers unsupported AMDIL MachineInstrs to LLVM pseudo -// MachineInstrs for hw codegen targets. -// -//===----------------------------------------------------------------------===// - - -#include "AMDGPU.h" -#include "AMDGPURegisterInfo.h" -#include "AMDIL.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" - -using namespace llvm; - -namespace { - -class AMDGPULowerInstructionsPass : public MachineFunctionPass { - -private: - static char ID; - TargetMachine &TM; - void lowerVCREATE_v4(MachineInstr &MI, MachineBasicBlock::iterator I, - MachineBasicBlock &MBB, MachineFunction &MF); - -public: - AMDGPULowerInstructionsPass(TargetMachine &tm) : - MachineFunctionPass(ID), TM(tm) { } - - virtual bool runOnMachineFunction(MachineFunction &MF); - - virtual const char *getPassName() const {return "AMDGPU Lower Instructions";} - -}; - -} // End anonymous namespace - -char AMDGPULowerInstructionsPass::ID = 0; - -FunctionPass *llvm::createAMDGPULowerInstructionsPass(TargetMachine &tm) { - return new AMDGPULowerInstructionsPass(tm); -} - -bool AMDGPULowerInstructionsPass::runOnMachineFunction(MachineFunction &MF) -{ - for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); - BB != BB_E; ++BB) { - MachineBasicBlock &MBB = *BB; - for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I); - I != MBB.end(); I = Next, Next = llvm::next(I) ) { - MachineInstr &MI = *I; - - switch (MI.getOpcode()) { - default: continue; - case AMDIL::VCREATE_v4f32: - case AMDIL::VCREATE_v4i32: - lowerVCREATE_v4(MI, I, MBB, MF); break; - } - MI.eraseFromParent(); - } - } - return false; -} - -void AMDGPULowerInstructionsPass::lowerVCREATE_v4(MachineInstr &MI, - MachineBasicBlock::iterator I, MachineBasicBlock &MBB, MachineFunction &MF) -{ - MachineRegisterInfo & MRI = MF.getRegInfo(); - unsigned tmp = MRI.createVirtualRegister( - MRI.getRegClass(MI.getOperand(0).getReg())); - - BuildMI(MBB, I, DebugLoc(), TM.getInstrInfo()->get(AMDIL::IMPLICIT_DEF), tmp); - - BuildMI(MBB, I, DebugLoc(), TM.getInstrInfo()->get(AMDIL::INSERT_SUBREG)) - .addOperand(MI.getOperand(0)) - .addReg(tmp) - .addOperand(MI.getOperand(1)) - .addImm(AMDIL::sel_x); -} diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp index b4d2a2f5ea1..c6a2412f970 100644 --- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp +++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp @@ -138,7 +138,6 @@ bool AMDGPUPassConfig::addPreRegAlloc() { if (ST.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) { PM->add(createSIAssignInterpRegsPass(*TM)); } - PM->add(createAMDGPULowerInstructionsPass(*TM)); PM->add(createAMDGPUConvertToISAPass(*TM)); return false; } diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td index 586d18d0105..afddefebce6 100644 --- a/src/gallium/drivers/radeon/AMDILInstructions.td +++ b/src/gallium/drivers/radeon/AMDILInstructions.td @@ -731,12 +731,6 @@ def LCREATE_v2i64 : TwoInOneOut; -//===---------------------------------------------------------------------===// -// Scalar ==> Vector conversion functions -//===---------------------------------------------------------------------===// -// This opcode has custom swizzle pattern encoded in Swizzle Encoder -defm VCREATE : UnaryOpMCVec; - //===---------------------------------------------------------------------===// // Vector ==> Scalar conversion functions //===---------------------------------------------------------------------===// diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index 9742e6b7790..b5665ce95f3 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -33,7 +33,6 @@ CPP_SOURCES := \ AMDGPUTargetMachine.cpp \ AMDGPUISelLowering.cpp \ AMDGPUConvertToISA.cpp \ - AMDGPULowerInstructions.cpp \ AMDGPUInstrInfo.cpp \ AMDGPURegisterInfo.cpp \ AMDGPUUtil.cpp \ diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index 27744d1ab66..9caaf1c86a0 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -1122,6 +1122,9 @@ def : Insert_Element ; def : Insert_Element ; def : Insert_Element ; +def : Vector_Build ; +def : Vector_Build ; + // bitconvert patterns def : BitConvert ; diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 4408777a5f1..8fd0c4933fd 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -905,6 +905,9 @@ def : Insert_Element ; def : Insert_Element ; def : Insert_Element ; +def : Vector_Build ; +def : Vector_Build ; + /* def : Pat< (int_SI_vs_load_buffer_index),