From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 25 Apr 2013 18:18:45 +0000 (+0200)
Subject: Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all... 
X-Git-Tag: 24jan2021_ls180~2968
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de76faf7577c23fba99365afda5377237f4b6f20;p=litex.git

Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark.
---

diff --git a/build.py b/build.py
index 2b2125ab..8d9fa95b 100755
--- a/build.py
+++ b/build.py
@@ -20,6 +20,11 @@ INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
 
 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "vga_clk" TNM_NET = "GRPvga_clk";
+NET "sys_clk" TNM_NET = "GRPsys_clk";
+TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
+TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
+
 NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
 NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
 TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;