From: whitequark <cz@m-labs.hk>
Date: Wed, 12 Dec 2018 10:11:16 +0000 (+0000)
Subject: fhdl.ast.Signal: implement reset_less signals.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de82f784a45c88de6389c469251f322c6d1e5b8a;p=nmigen.git

fhdl.ast.Signal: implement reset_less signals.
---

diff --git a/nmigen/fhdl/ast.py b/nmigen/fhdl/ast.py
index b78021f..1de1ce7 100644
--- a/nmigen/fhdl/ast.py
+++ b/nmigen/fhdl/ast.py
@@ -492,6 +492,10 @@ class Signal(Value, DUID):
         domain is reset, the ``Signal`` assumes the given value. When this ``Signal`` is unassigned
         in combinatorial context (due to conditional assignments not being taken), the ``Signal``
         assumes its ``reset`` value. Defaults to 0.
+    reset_less : bool
+        If ``True``, do not generate reset logic for this ``Signal`` in synchronous statements.
+        The ``reset`` value is only used as a combinatorial default or as the initial value.
+        Defaults to ``False``.
 
     Attributes
     ----------
@@ -501,7 +505,7 @@ class Signal(Value, DUID):
     reset : int
     """
 
-    def __init__(self, bits_sign=1, reset=0, name=None):
+    def __init__(self, bits_sign=1, name=None, reset=0, reset_less=False):
         super().__init__()
 
         if name is None:
@@ -517,6 +521,7 @@ class Signal(Value, DUID):
         if not isinstance(self.nbits, int) or self.nbits < 0:
             raise TypeError("Width must be a positive integer")
         self.reset = reset
+        self.reset_less = reset_less
 
     def bits_sign(self):
         return self.nbits, self.signed
diff --git a/nmigen/fhdl/xfrm.py b/nmigen/fhdl/xfrm.py
index 0e95ec4..5bc1ec2 100644
--- a/nmigen/fhdl/xfrm.py
+++ b/nmigen/fhdl/xfrm.py
@@ -114,7 +114,7 @@ class _ControlInserter:
 
 class ResetInserter(_ControlInserter):
     def _wrap_control(self, fragment, cd_name, signals):
-        stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals]
+        stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals if not s.reset_less]
         fragment.add_statements(Switch(self.controls[cd_name], {1: stmts}))