From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 10 Jul 2020 16:39:04 +0000 (+0200)
Subject: Put every gram component in the dramsync clock domain
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de8fc88455530830b331055cf58fa272cc7cb402;p=gram.git

Put every gram component in the dramsync clock domain
---

diff --git a/examples/headless-ecpix5.py b/examples/headless-ecpix5.py
index 2b68182..69dba0a 100644
--- a/examples/headless-ecpix5.py
+++ b/examples/headless-ecpix5.py
@@ -35,19 +35,19 @@ class DDR3SoC(SoC, Elaboratable):
         self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
         self._arbiter.add(self.ub.bus)
 
-        self.ddrphy = ECP5DDRPHY(platform.request("ddr3", 0))
+        self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"})))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 
         ddrmodule = MT41K256M16(platform.default_clk_frequency, "1:2")
 
-        self.dramcore = gramCore(
+        self.dramcore = DomainRenamer("dramsync")(gramCore(
             phy=self.ddrphy,
             geom_settings=ddrmodule.geom_settings,
             timing_settings=ddrmodule.timing_settings,
             clk_freq=platform.default_clk_frequency))
         self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
 
-        self.drambone = gramWishbone(self.dramcore)
+        self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
         self._decoder.add(self.drambone.bus, addr=ddr_addr)
 
         self.memory_map = self._decoder.bus.memory_map