From: whitequark <cz@m-labs.hk>
Date: Fri, 23 Aug 2019 08:53:48 +0000 (+0000)
Subject: back.pysim: implement sim.add_clock(if_exists=True).
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=deb5de556dba94526c9f867b94bdb9592ad5f2cf;p=nmigen.git

back.pysim: implement sim.add_clock(if_exists=True).
---

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 8471b51..3c73eae 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -438,7 +438,7 @@ class Simulator:
         sync_process = sync_process()
         self.add_process(sync_process)
 
-    def add_clock(self, period, phase=None, domain="sync"):
+    def add_clock(self, period, *, phase=None, domain="sync", if_exists=False):
         if self._fastest_clock == self._epsilon or period < self._fastest_clock:
             self._fastest_clock = period
         if domain in self._all_clocks:
@@ -453,8 +453,11 @@ class Simulator:
                 clk = domain_obj.clk
                 break
         else:
-            raise ValueError("Domain '{}' is not present in simulation"
-                             .format(domain))
+            if if_exists:
+                return
+            else:
+                raise ValueError("Domain '{}' is not present in simulation"
+                                 .format(domain))
         def clk_process():
             yield Passive()
             yield Delay(phase)
diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index c9cdcb7..585bbeb 100644
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -403,7 +403,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
                         "a generator function"):
                 sim.add_process(1)
 
-    def test_add_clock_wrong(self):
+    def test_add_clock_wrong_twice(self):
         m = Module()
         s = Signal()
         m.d.sync += s.eq(0)
@@ -413,13 +413,18 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
                     msg="Domain 'sync' already has a clock driving it"):
                 sim.add_clock(1)
 
-    def test_add_clock_wrong(self):
+    def test_add_clock_wrong_missing(self):
         m = Module()
         with self.assertSimulation(m) as sim:
             with self.assertRaises(ValueError,
                     msg="Domain 'sync' is not present in simulation"):
                 sim.add_clock(1)
 
+    def test_add_clock_if_exists(self):
+        m = Module()
+        with self.assertSimulation(m) as sim:
+            sim.add_clock(1, if_exists=True)
+
     def test_eq_signal_unused_wrong(self):
         self.setUp_lhs_rhs()
         self.s = Signal()