From: lkcl <lkcl@web>
Date: Fri, 10 Jun 2022 10:54:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1873
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dec1b79bf8622b4a36f985876ca965207f1fe464;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 9b0e66782..fafb38b9d 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -216,6 +216,34 @@ for the type of operation (Branch, CRs, Memory, Arithmetic),
 and each Category has its own relevant but
 ultimately rational quirks.
 
+# Single Predication
+
+So named because there is a Twin Predication concept as well, Single
+Predication is also unlike other Vector ISAs because it allows zeroing
+on both the source and destination.  This takes some explaining.
+
+In Vector ISAs, there is a choice of actions when a Predicate Mask bit
+is zero:
+
+* set the destination element to zero 
+* skip that element operation entirely, leaving the result unmodified
+
+Some Vector ISAs strongly advocate Zeroing because to leave one single
+element at a small bitwidth in amongst other elements where the register
+file does not have the prerequisite access granularity is very expensive,
+requiring a Read-Modify-Write cycle to preserve the untouched elements.
+Putting zero into the destination avoids that Read.
+This is technically very easy to solve: use a Register File that does
+in fact have the smallest element-level write-enable granularity.
+
+With that technical issue solved there is nothing in the way of choosing
+to support both zeroing and non-zeroing (skipping) at the ISA level:
+SV chooses to support both *on both the source and destination*.
+This can result in the source and destination
+element indices getting "out-of-sync" even though the Predicate Mask
+is the same because the behaviour is different when zeros in the
+Predicate are encountered.
+
 # Twin Predication
 
 Twin Predication is an entirely new concept not present in any commercial