From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 5 May 2016 00:03:45 +0000 (-0700)
Subject: Renamed module parameter
X-Git-Tag: yosys-0.7~233^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dee1c27a19f91fb44df67b2ab9834ee8140772c4;p=yosys.git

Renamed module parameter
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 6c3ffcaa0..6cf29fe6e 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -278,9 +278,9 @@ endmodule
 
 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 
-	parameter OUTA_DELAY = 1;
+	parameter OUTA_TAP = 1;
 	parameter OUTA_INVERT = 0;
-	parameter OUTB_DELAY = 1;
+	parameter OUTB_TAP = 1;
 	
 	reg[15:0] shreg = 0;
 	
@@ -294,8 +294,8 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 		
 	end
 	
-	assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
-	assign OUTB = shreg[OUTB_DELAY - 1];
+	assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
+	assign OUTB = shreg[OUTB_TAP - 1];
 
 endmodule