From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri, 3 Nov 2017 01:32:39 +0000 (-0700)
Subject: intel/fs/nir: Use Q immediates for load_const on gen8+
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dee58ecd2e3b23d1a3d2cdffb99d3dd314421b39;p=mesa.git

intel/fs/nir: Use Q immediates for load_const on gen8+

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
---

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 99e652a4a0c..342ac8170b0 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1442,9 +1442,17 @@ fs_visitor::nir_emit_load_const(const fs_builder &bld,
       break;
 
    case 64:
-      for (unsigned i = 0; i < instr->def.num_components; i++)
-         bld.MOV(offset(reg, bld, i),
-                 setup_imm_df(bld, instr->value.f64[i]));
+      assert(devinfo->gen >= 7);
+      if (devinfo->gen == 7) {
+         /* We don't get 64-bit integer types until gen8 */
+         for (unsigned i = 0; i < instr->def.num_components; i++) {
+            bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_DF),
+                    setup_imm_df(bld, instr->value.f64[i]));
+         }
+      } else {
+         for (unsigned i = 0; i < instr->def.num_components; i++)
+            bld.MOV(offset(reg, bld, i), brw_imm_q(instr->value.i64[i]));
+      }
       break;
 
    default: