From: Jakub Jelinek <jakub@redhat.com>
Date: Wed, 8 Nov 2017 20:15:42 +0000 (+0100)
Subject: re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=deef5083cda7b805977fe537f05b23da9406894e;p=gcc.git

re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)

	PR target/82855
	* config/i386/sse.md (<avx512>_eq<mode>3<mask_scalar_merge_name>,
	<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Use
	nonimmediate_operand predicate for operand 1 instead of
	register_operand.

From-SVN: r254552
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 805625f8f3d..15bba026063 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2017-11-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/82855
+	* config/i386/sse.md (<avx512>_eq<mode>3<mask_scalar_merge_name>,
+	<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Use
+	nonimmediate_operand predicate for operand 1 instead of
+	register_operand.
+
 2017-11-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/aarch64/aarch64-simd.md (store_pair_lanes<mode>):
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 200aad65e24..919b6c674e0 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -11127,7 +11127,7 @@
 (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand")
 	(unspec:<avx512fmaskmode>
-	  [(match_operand:VI12_AVX512VL 1 "register_operand")
+	  [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand")
 	   (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")]
 	  UNSPEC_MASKED_EQ))]
   "TARGET_AVX512BW"
@@ -11136,7 +11136,7 @@
 (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand")
 	(unspec:<avx512fmaskmode>
-	  [(match_operand:VI48_AVX512VL 1 "register_operand")
+	  [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
 	   (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")]
 	  UNSPEC_MASKED_EQ))]
   "TARGET_AVX512F"
@@ -11145,7 +11145,7 @@
 (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
 	(unspec:<avx512fmaskmode>
-	  [(match_operand:VI12_AVX512VL 1 "register_operand" "%v")
+	  [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "%v")
 	   (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
 	  UNSPEC_MASKED_EQ))]
   "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -11158,7 +11158,7 @@
 (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
 	(unspec:<avx512fmaskmode>
-	  [(match_operand:VI48_AVX512VL 1 "register_operand" "%v")
+	  [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v")
 	   (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
 	  UNSPEC_MASKED_EQ))]
   "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"