From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Mon, 25 Jul 2022 13:10:19 +0000 (+0300)
Subject: ppc/svp64: support svremap instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df0030b531e13446c010c33f1c1c7400c9777807;p=binutils-gdb.git

ppc/svp64: support svremap instruction

https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svremap
https://libre-soc.org/openpower/isa/simplev/
---

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index ea1c591a1ed..9f02fa75c21 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -158,3 +158,4 @@ run_dump_test "raw"
 run_dump_test "setvl"
 run_dump_test "svstep"
 run_dump_test "svshape"
+run_dump_test "svremap"
diff --git a/gas/testsuite/gas/ppc/svremap.d b/gas/testsuite/gas/ppc/svremap.d
new file mode 100644
index 00000000000..18646ec37dd
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:	(39 00 00 58|58 00 00 39) 	svremap 0,0,0,0,0,0,0
+.*:	(39 00 e0 5b|5b e0 00 39) 	svremap 31,0,0,0,0,0,0
+.*:	(39 00 18 58|58 18 00 39) 	svremap 0,3,0,0,0,0,0
+.*:	(39 00 06 58|58 06 00 39) 	svremap 0,0,3,0,0,0,0
+.*:	(39 80 01 58|58 01 80 39) 	svremap 0,0,0,3,0,0,0
+.*:	(39 60 00 58|58 00 60 39) 	svremap 0,0,0,0,3,0,0
+.*:	(39 18 00 58|58 00 18 39) 	svremap 0,0,0,0,0,3,0
+.*:	(39 04 18 58|58 18 04 39) 	svremap 0,3,0,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svremap.s b/gas/testsuite/gas/ppc/svremap.s
new file mode 100644
index 00000000000..860040afc5a
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.s
@@ -0,0 +1,8 @@
+svremap 0,0,0,0,0,0,0
+svremap 31,0,0,0,0,0,0
+svremap 0,3,0,0,0,0,0
+svremap 0,0,3,0,0,0,0
+svremap 0,0,0,3,0,0,0
+svremap 0,0,0,0,3,0,0
+svremap 0,0,0,0,0,3,0
+svremap 0,3,0,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index c8fd3b15d69..af67d6dce82 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2849,6 +2849,7 @@ const struct powerpc_operand powerpc_operands[] =
   /* The RM field in an X form instruction.  */
 #define RM BOP + 1
 #define DD RM
+#define mo1 RM
   { 0x3, 11, NULL, NULL, 0 },
 
 #define BH RM + 1
@@ -3507,6 +3508,7 @@ const struct powerpc_operand powerpc_operands[] =
   /* The TO field in a D or X form instruction.  */
 #define TO TBR + 1
 #define DUI TO
+#define SVme TO
 #define TO_MASK (0x1f << 21)
   { 0x1f, 21, NULL, NULL, 0 },
 
@@ -3620,6 +3622,8 @@ const struct powerpc_operand powerpc_operands[] =
 #define PSWM WS + 1
   /* The BO16 field in a BD8 form instruction.  */
 #define BO16 PSWM
+  /* The pst field in a SVRM form instruction.  */
+#define pst PSWM
   {  0x1, 10, 0, 0, 0 },
 
   /* IDX bits for quantization in the pair singles instructions.  */
@@ -3657,6 +3661,7 @@ const struct powerpc_operand powerpc_operands[] =
   { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
 #define SP PRS + 1
+#define mi0 SP
   { 0x3, 19, NULL, NULL, 0 },
 
 #define S SP + 1
@@ -3824,6 +3829,7 @@ const struct powerpc_operand powerpc_operands[] =
   { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
 
 #define HH DDD + 1
+#define mo0 HH
   { 0x3, 13, NULL, NULL, 0 },
 
 #define SVi HH + 1
@@ -3852,6 +3858,12 @@ const struct powerpc_operand powerpc_operands[] =
 
 #define SVrm SVzd + 1
   { 0xf, 7, NULL, NULL, 0 },
+
+#define mi1 SVrm + 1
+  { 0x3, 17, NULL, NULL, 0 },
+
+#define mi2 mi1 + 1
+  { 0x3, 15, NULL, NULL, 0 },
 };
 
 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4740,6 +4752,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
    | (((uint64_t)(xop)) & 0x3f))
 #define SVM_MASK	SVM (0x3f, 0x3f)
 
+/* An SVRM form instruction. */
+#define SVRM(op, xop)				\
+  (OP (op)					\
+   | (((uint64_t)(xop)) & 0x3f))
+#define SVRM_MASK	SVRM (0x3f, 0x3f)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF	(0x0)
 #define BODNZFP	(0x1)
@@ -6817,6 +6835,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"setvl",	SVL(22,27,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
 {"setvl.",	SVL(22,27,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
 
+{"svremap",	SVRM(22,57),	SVRM_MASK,	SVP64,	PPCVLE,	{SVme, mi0, mi1, mi2, mo0, mo1, pst}},
+
 {"rotlw",	MME(23,31,0),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RB}},
 {"rlwnm",	M(23,0),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
 {"rlnm",	M(23,0),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},