From: lkcl <lkcl@web>
Date: Sun, 26 Mar 2023 13:54:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls001_v3~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df01f2fb5794becfc62b4a58c60a567e6fd2f64c;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn
index 40d0b142d..e5d46ef0a 100644
--- a/openpower/sv/rfc/ls008.mdwn
+++ b/openpower/sv/rfc/ls008.mdwn
@@ -32,7 +32,6 @@
 **Summary**
 
 ```
-    Instructions added
     setvl    - Cray-style "Set Vector Length" instruction
     svstep   - Vertical-First Mode explicit Step and Status
     svremap  - Re-Mapping of Register Element Offsets
@@ -52,8 +51,6 @@
     Management Instructions which can be implemented extremely efficiently
     and effectively by inserting an additional phase between Decode and Issue.
     More complex designs are NOT adversely impacted and in fact greatly benefit
-    whilst still retaining an obvious linear sequential execution programming model.
-```
 
 **Impact on software**:
 
@@ -84,8 +81,7 @@ and beyond.
 
 1. SVP64 is very much designed for ultra-light-weight Embedded use-cases all the
   way up to moving the bar of Supercomputing orders of magnitude above its present
-  perception, whilst retaining at all times the Sequential Programming Execution
-  Model.
+  perception, whilst retaining at all times Sequential Programming Execution.
 2. This proposal is the **base** for further Extensions.  These include
   extending SVP64 onto the Scalar VSX instructions (with a **LONG TERM** view in 10+ years
   to deprecating the PackedSIMD aspects of VSX), to be discussed at a later
@@ -95,11 +91,7 @@ and beyond.
   with SVP64, which is far beyond anything ever achieved by any *general-purpose*
   ISA Extension added to any ISA in the history of Computing. Normal reductions
   expected are of the order of 5 to 10% being considered a highly worthwhile exercise
-  to pursue inclusion. not fractions of former sizes.
-4. Other potential extensions include work inspired by EXTRA-V and Eth-Zurich "Snitch"
-  to reduce CPU workload by 95% in the case of EXTRA-V and power consumption by
-  85% in the case of Snitch.  Addition massive reductions from ZOLC Research are
-  also anticipated.
+  to pursue inclusion.
 
 **Changes**