From: Florent Kermarrec Date: Sat, 28 Feb 2015 09:38:28 +0000 (+0100) Subject: litescope: create example_designs directory X-Git-Tag: 24jan2021_ls180~2573 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df0ba1b03ce9f506816594ad19c5947eaec93057;p=litex.git litescope: create example_designs directory --- diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py index 73de00fd..b29f2696 100644 --- a/misoclib/com/liteeth/example_designs/make.py +++ b/misoclib/com/liteeth/example_designs/make.py @@ -10,7 +10,7 @@ from migen.bank.description import CSRStatus from mibuild import tools from mibuild.xilinx_common import * -sys.path.append("../../../") # Temporary +sys.path.append("../../../../") # Temporary from misoclib.com.liteeth.common import * def get_csr_csv(regions): diff --git a/misoclib/tools/litescope/example_designs/make.py b/misoclib/tools/litescope/example_designs/make.py new file mode 100644 index 00000000..e73294f5 --- /dev/null +++ b/misoclib/tools/litescope/example_designs/make.py @@ -0,0 +1,151 @@ +#!/usr/bin/env python3 + +import sys, os, argparse, subprocess, struct, importlib + +from mibuild.tools import write_to_file +from migen.util.misc import autotype +from migen.fhdl import verilog, edif +from migen.fhdl.structure import _Fragment +from migen.bank.description import CSRStatus +from mibuild import tools +from mibuild.xilinx.common import * + +sys.path.append("../../../../") # Temporary +from misoclib.tools.litescope.common import * + +def get_csr_csv(regions): + r = "" + for name, origin, busword, obj in regions: + if not isinstance(obj, Memory): + for csr in obj: + nr = (csr.size + busword - 1)//busword + r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw") + origin += 4*nr + return r + +def _import(default, name): + return importlib.import_module(default + "." + name) + +def _get_args(): + parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter, + description="""\ +LiteScope - based on Migen. + +This program builds and/or loads LiteScope components. +One or several actions can be specified: + +clean delete previous build(s). +build-rtl build verilog rtl. +build-bitstream build-bitstream build FPGA bitstream. +build-csr-csv save CSR map into CSV file. + +load-bitstream load bitstream into volatile storage. + +all clean, build-csr-csv, build-bitstream, load-bitstream. +""") + + parser.add_argument("-t", "--target", default="simple", help="Core type to build") + parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build") + parser.add_argument("-p", "--platform", default=None, help="platform to build for") + parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option") + parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option") + parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into") + + parser.add_argument("action", nargs="+", help="specify an action") + + return parser.parse_args() + +# Note: misoclib need to be installed as a python library + +if __name__ == "__main__": + args = _get_args() + + # create top-level Core object + target_module = _import("targets", args.target) + if args.sub_target: + top_class = getattr(target_module, args.sub_target) + else: + top_class = target_module.default_subtarget + + if args.platform is None: + platform_name = top_class.default_platform + else: + platform_name = args.platform + platform_module = _import("mibuild.platforms", platform_name) + platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) + platform = platform_module.Platform(**platform_kwargs) + + build_name = top_class.__name__.lower() + "-" + platform_name + top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) + soc = top_class(platform, **top_kwargs) + soc.finalize() + + # decode actions + action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"] + actions = {k: False for k in action_list} + for action in args.action: + if action in actions: + actions[action] = True + else: + print("Unknown action: "+action+". Valid actions are:") + for a in action_list: + print(" "+a) + sys.exit(1) + + print(""" + __ _ __ ____ + / / (_) /____ / __/______ ___ ___ + / /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_) + /____/_/\__/\__/___/\__/\___/ .__/\__/ + /_/ + + A small footprint and configurable embedded FPGA + logic analyzer core powered by Migen + +====== Building parameters: ====== +LiscopeIO +--------- +Width: {} + +LiscopeLA +--------- +Width: {} +Depth: {} +Subsampler: {} +RLE: {} +===============================""".format( + soc.io.dw, + soc.la.dw, + soc.la.depth, + str(soc.la.with_subsampler), + str(soc.la.with_rle) + ) +) + + # dependencies + if actions["all"]: + actions["build-csr-csv"] = True + actions["build-bitstream"] = True + actions["load-bitstream"] = True + + if actions["build-bitstream"]: + actions["build-csr-csv"] = True + actions["build-bitstream"] = True + actions["load-bitstream"] = True + + if actions["clean"]: + subprocess.call(["rm", "-rf", "build/*"]) + + if actions["build-csr-csv"]: + csr_csv = get_csr_csv(soc.cpu_csr_regions) + write_to_file(args.csr_csv, csr_csv) + + if actions["build-bitstream"]: + vns = platform.build(soc, build_name=build_name, run=True) + if hasattr(soc, "do_exit") and vns is not None: + if hasattr(soc.do_exit, '__call__'): + soc.do_exit(vns) + + if actions["load-bitstream"]: + prog = platform.create_programmer() + prog.load_bitstream("build/" + build_name + platform.bitstream_ext) diff --git a/misoclib/tools/litescope/example_designs/targets/__init__.py b/misoclib/tools/litescope/example_designs/targets/__init__.py new file mode 100644 index 00000000..85efe5d9 --- /dev/null +++ b/misoclib/tools/litescope/example_designs/targets/__init__.py @@ -0,0 +1,26 @@ +import subprocess + +from migen.fhdl.std import * +from migen.bank.description import * + +def get_id(): + output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii") + return int(output[:8], 16) + +class Identifier(Module, AutoCSR): + def __init__(self, sysid, frequency, revision=None): + self._r_sysid = CSRStatus(16) + self._r_revision = CSRStatus(32) + self._r_frequency = CSRStatus(32) + + ### + + if revision is None: + revision = get_id() + + self.comb += [ + self._r_sysid.status.eq(sysid), + self._r_revision.status.eq(revision), + self._r_frequency.status.eq(frequency), + ] + diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py new file mode 100644 index 00000000..95a81e50 --- /dev/null +++ b/misoclib/tools/litescope/example_designs/targets/simple.py @@ -0,0 +1,109 @@ +import os + +from migen.bank import csrgen +from migen.bus import wishbone, csr +from migen.bus import wishbone2csr +from migen.bank.description import * + +from targets import * + +from misoclib.tools.litescope.common import * +from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB +from misoclib.tools.litescope.frontend.io import LiteScopeIO +from misoclib.tools.litescope.frontend.la import LiteScopeLA +from misoclib.tools.litescope.core.port import LiteScopeTerm + +class _CRG(Module): + def __init__(self, clk_in): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + + # Power on Reset (vendor agnostic) + rst_n = Signal() + self.sync.por += rst_n.eq(1) + self.comb += [ + self.cd_sys.clk.eq(clk_in), + self.cd_por.clk.eq(clk_in), + self.cd_sys.rst.eq(~rst_n) + ] + +class GenSoC(Module): + csr_base = 0x00000000 + csr_data_width = 32 + csr_map = { + "bridge": 0, + "identifier": 1, + } + interrupt_map = {} + cpu_type = None + def __init__(self, platform, clk_freq): + self.clk_freq = clk_freq + # UART <--> Wishbone bridge + self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200) + + # CSR bridge 0x00000000 (shadow @0x00000000) + self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) + self._wb_masters = [self.uart2wb.wishbone] + self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)] + self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory) + + # CSR + self.submodules.identifier = Identifier(0, int(clk_freq)) + + def add_cpu_memory_region(self, name, origin, length): + self.cpu_memory_regions.append((name, origin, length)) + + def add_cpu_csr_region(self, name, origin, busword, obj): + self.cpu_csr_regions.append((name, origin, busword, obj)) + + def do_finalize(self): + # Wishbone + self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, + self._wb_slaves, register=True) + + # CSR + self.submodules.csrbankarray = csrgen.BankArray(self, + lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], + data_width=self.csr_data_width) + self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) + for name, csrs, mapaddr, rmap in self.csrbankarray.banks: + self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) + for name, memory, mapaddr, mmap in self.csrbankarray.srams: + self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) + +class LiteScopeSoC(GenSoC, AutoCSR): + default_platform = "de0nano" + csr_map = { + "io": 10, + "la": 11 + } + csr_map.update(GenSoC.csr_map) + def __init__(self, platform): + clk_freq = 50*1000000 + GenSoC.__init__(self, platform, clk_freq) + self.submodules.crg = _CRG(platform.request("clk50")) + + self.submodules.io = LiteScopeIO(8) + self.leds = Cat(*[platform.request("user_led", i) for i in range(8)]) + self.comb += self.leds.eq(self.io.o) + + self.submodules.counter0 = counter0 = Counter(bits_sign=8) + self.submodules.counter1 = counter1 = Counter(bits_sign=8) + self.comb += [ + counter0.ce.eq(1), + If(counter0.value == 16, + counter0.reset.eq(1), + counter1.ce.eq(1) + ) + ] + + self.debug = ( + counter1.value + ) + self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True) + self.la.trigger.add_port(LiteScopeTerm(self.la.dw)) + + def do_exit(self, vns): + self.la.export(vns, "test/la.csv") + +default_subtarget = LiteScopeSoC diff --git a/misoclib/tools/litescope/example_designs/test/make.py b/misoclib/tools/litescope/example_designs/test/make.py new file mode 100644 index 00000000..335623c0 --- /dev/null +++ b/misoclib/tools/litescope/example_designs/test/make.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +import argparse, importlib + +def _get_args(): + parser = argparse.ArgumentParser() + parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use") + parser.add_argument("--port", default=3, help="UART port") + parser.add_argument("--baudrate", default=115200, help="UART baudrate") + parser.add_argument("--ip_address", default="192.168.1.40", help="Etherbone IP address") + parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port") + parser.add_argument("--busword", default=32, help="CSR busword") + + parser.add_argument("test", nargs="+", help="specify a test") + + return parser.parse_args() + +if __name__ == "__main__": + args = _get_args() + if args.bridge == "uart": + from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver + wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False) + elif args.bridge == "etherbone": + from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver + wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False) + else: + ValueError("Invalid bridge {}".format(args.bridge)) + + def _import(name): + return importlib.import_module(name) + + for test in args.test: + t = _import("test_"+test) + t.main(wb) diff --git a/misoclib/tools/litescope/example_designs/test/test_io.py b/misoclib/tools/litescope/example_designs/test/test_io.py new file mode 100644 index 00000000..135de36a --- /dev/null +++ b/misoclib/tools/litescope/example_designs/test/test_io.py @@ -0,0 +1,34 @@ +import time +from misoclib.tools.litescope.host.driver.io import LiteScopeIODriver + +def led_anim0(io): + for i in range(10): + io.write(0xA5) + time.sleep(0.1) + io.write(0x5A) + time.sleep(0.1) + +def led_anim1(io): + for j in range(4): + #Led << + led_data = 1 + for i in range(8): + io.write(led_data) + time.sleep(i*i*0.0020) + led_data = (led_data<<1) + #Led >> + ledData = 128 + for i in range(8): + io.write(led_data) + time.sleep(i*i*0.0020) + led_data = (led_data>>1) + +def main(wb): + io = LiteScopeIODriver(wb.regs, "io") + wb.open() + ### + led_anim0(io) + led_anim1(io) + print("%02X" %io.read()) + ### + wb.close() diff --git a/misoclib/tools/litescope/example_designs/test/test_la.py b/misoclib/tools/litescope/example_designs/test/test_la.py new file mode 100644 index 00000000..7a4b79e8 --- /dev/null +++ b/misoclib/tools/litescope/example_designs/test/test_la.py @@ -0,0 +1,26 @@ +from misoclib.tools.litescope.host.driver.la import LiteScopeLADriver + +def main(wb): + wb.open() + ### + la = LiteScopeLADriver(wb.regs, "la", debug=True) + + #cond = {"cnt0" : 128} # trigger on cnt0 = 128 + cond = {} # trigger on cnt0 = 128 + la.configure_term(port=0, cond=cond) + la.configure_sum("term") + la.configure_subsampler(1) + #la.configure_qualifier(1) + la.configure_rle(1) + la.run(offset=128, length=256) + + while not la.done(): + pass + la.upload() + + la.save("dump.vcd") + la.save("dump.csv") + la.save("dump.py") + la.save("dump.sr") + ### + wb.close() diff --git a/misoclib/tools/litescope/example_designs/test/test_regs.py b/misoclib/tools/litescope/example_designs/test/test_regs.py new file mode 100644 index 00000000..c0ef387f --- /dev/null +++ b/misoclib/tools/litescope/example_designs/test/test_regs.py @@ -0,0 +1,9 @@ +def main(wb): + wb.open() + regs = wb.regs + ### + print("sysid : 0x%04x" %regs.identifier_sysid.read()) + print("revision : 0x%04x" %regs.identifier_revision.read()) + print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000)) + ### + wb.close() diff --git a/misoclib/tools/litescope/make.py b/misoclib/tools/litescope/make.py deleted file mode 100644 index 5c0c85f3..00000000 --- a/misoclib/tools/litescope/make.py +++ /dev/null @@ -1,150 +0,0 @@ -#!/usr/bin/env python3 - -import sys, os, argparse, subprocess, struct, importlib - -from mibuild.tools import write_to_file -from migen.util.misc import autotype -from migen.fhdl import verilog, edif -from migen.fhdl.structure import _Fragment -from migen.bank.description import CSRStatus -from mibuild import tools -from mibuild.xilinx_common import * - -from misoclib.tools.litescope.common import * - -def get_csr_csv(regions): - r = "" - for name, origin, busword, obj in regions: - if not isinstance(obj, Memory): - for csr in obj: - nr = (csr.size + busword - 1)//busword - r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw") - origin += 4*nr - return r - -def _import(default, name): - return importlib.import_module(default + "." + name) - -def _get_args(): - parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter, - description="""\ -LiteScope - based on Migen. - -This program builds and/or loads LiteScope components. -One or several actions can be specified: - -clean delete previous build(s). -build-rtl build verilog rtl. -build-bitstream build-bitstream build FPGA bitstream. -build-csr-csv save CSR map into CSV file. - -load-bitstream load bitstream into volatile storage. - -all clean, build-csr-csv, build-bitstream, load-bitstream. -""") - - parser.add_argument("-t", "--target", default="simple", help="Core type to build") - parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build") - parser.add_argument("-p", "--platform", default=None, help="platform to build for") - parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option") - parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option") - parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into") - - parser.add_argument("action", nargs="+", help="specify an action") - - return parser.parse_args() - -# Note: misoclib need to be installed as a python library - -if __name__ == "__main__": - args = _get_args() - - # create top-level Core object - target_module = _import("targets", args.target) - if args.sub_target: - top_class = getattr(target_module, args.sub_target) - else: - top_class = target_module.default_subtarget - - if args.platform is None: - platform_name = top_class.default_platform - else: - platform_name = args.platform - platform_module = _import("mibuild.platforms", platform_name) - platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) - platform = platform_module.Platform(**platform_kwargs) - - build_name = top_class.__name__.lower() + "-" + platform_name - top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) - soc = top_class(platform, **top_kwargs) - soc.finalize() - - # decode actions - action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"] - actions = {k: False for k in action_list} - for action in args.action: - if action in actions: - actions[action] = True - else: - print("Unknown action: "+action+". Valid actions are:") - for a in action_list: - print(" "+a) - sys.exit(1) - - print(""" - __ _ __ ____ - / / (_) /____ / __/______ ___ ___ - / /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_) - /____/_/\__/\__/___/\__/\___/ .__/\__/ - /_/ - - A small footprint and configurable embedded FPGA - logic analyzer core powered by Migen - -====== Building parameters: ====== -LiscopeIO ---------- -Width: {} - -LiscopeLA ---------- -Width: {} -Depth: {} -Subsampler: {} -RLE: {} -===============================""".format( - soc.io.dw, - soc.la.dw, - soc.la.depth, - str(soc.la.with_subsampler), - str(soc.la.with_rle) - ) -) - - # dependencies - if actions["all"]: - actions["build-csr-csv"] = True - actions["build-bitstream"] = True - actions["load-bitstream"] = True - - if actions["build-bitstream"]: - actions["build-csr-csv"] = True - actions["build-bitstream"] = True - actions["load-bitstream"] = True - - if actions["clean"]: - subprocess.call(["rm", "-rf", "build/*"]) - - if actions["build-csr-csv"]: - csr_csv = get_csr_csv(soc.cpu_csr_regions) - write_to_file(args.csr_csv, csr_csv) - - if actions["build-bitstream"]: - vns = platform.build(soc, build_name=build_name, run=True) - if hasattr(soc, "do_exit") and vns is not None: - if hasattr(soc.do_exit, '__call__'): - soc.do_exit(vns) - - if actions["load-bitstream"]: - prog = platform.create_programmer() - prog.load_bitstream("build/" + build_name + platform.bitstream_ext) diff --git a/misoclib/tools/litescope/targets/__init__.py b/misoclib/tools/litescope/targets/__init__.py deleted file mode 100644 index 85efe5d9..00000000 --- a/misoclib/tools/litescope/targets/__init__.py +++ /dev/null @@ -1,26 +0,0 @@ -import subprocess - -from migen.fhdl.std import * -from migen.bank.description import * - -def get_id(): - output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii") - return int(output[:8], 16) - -class Identifier(Module, AutoCSR): - def __init__(self, sysid, frequency, revision=None): - self._r_sysid = CSRStatus(16) - self._r_revision = CSRStatus(32) - self._r_frequency = CSRStatus(32) - - ### - - if revision is None: - revision = get_id() - - self.comb += [ - self._r_sysid.status.eq(sysid), - self._r_revision.status.eq(revision), - self._r_frequency.status.eq(frequency), - ] - diff --git a/misoclib/tools/litescope/targets/simple.py b/misoclib/tools/litescope/targets/simple.py deleted file mode 100644 index 95a81e50..00000000 --- a/misoclib/tools/litescope/targets/simple.py +++ /dev/null @@ -1,109 +0,0 @@ -import os - -from migen.bank import csrgen -from migen.bus import wishbone, csr -from migen.bus import wishbone2csr -from migen.bank.description import * - -from targets import * - -from misoclib.tools.litescope.common import * -from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB -from misoclib.tools.litescope.frontend.io import LiteScopeIO -from misoclib.tools.litescope.frontend.la import LiteScopeLA -from misoclib.tools.litescope.core.port import LiteScopeTerm - -class _CRG(Module): - def __init__(self, clk_in): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_por = ClockDomain(reset_less=True) - - # Power on Reset (vendor agnostic) - rst_n = Signal() - self.sync.por += rst_n.eq(1) - self.comb += [ - self.cd_sys.clk.eq(clk_in), - self.cd_por.clk.eq(clk_in), - self.cd_sys.rst.eq(~rst_n) - ] - -class GenSoC(Module): - csr_base = 0x00000000 - csr_data_width = 32 - csr_map = { - "bridge": 0, - "identifier": 1, - } - interrupt_map = {} - cpu_type = None - def __init__(self, platform, clk_freq): - self.clk_freq = clk_freq - # UART <--> Wishbone bridge - self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200) - - # CSR bridge 0x00000000 (shadow @0x00000000) - self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) - self._wb_masters = [self.uart2wb.wishbone] - self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)] - self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory) - - # CSR - self.submodules.identifier = Identifier(0, int(clk_freq)) - - def add_cpu_memory_region(self, name, origin, length): - self.cpu_memory_regions.append((name, origin, length)) - - def add_cpu_csr_region(self, name, origin, busword, obj): - self.cpu_csr_regions.append((name, origin, busword, obj)) - - def do_finalize(self): - # Wishbone - self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, - self._wb_slaves, register=True) - - # CSR - self.submodules.csrbankarray = csrgen.BankArray(self, - lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], - data_width=self.csr_data_width) - self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) - for name, csrs, mapaddr, rmap in self.csrbankarray.banks: - self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) - for name, memory, mapaddr, mmap in self.csrbankarray.srams: - self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) - -class LiteScopeSoC(GenSoC, AutoCSR): - default_platform = "de0nano" - csr_map = { - "io": 10, - "la": 11 - } - csr_map.update(GenSoC.csr_map) - def __init__(self, platform): - clk_freq = 50*1000000 - GenSoC.__init__(self, platform, clk_freq) - self.submodules.crg = _CRG(platform.request("clk50")) - - self.submodules.io = LiteScopeIO(8) - self.leds = Cat(*[platform.request("user_led", i) for i in range(8)]) - self.comb += self.leds.eq(self.io.o) - - self.submodules.counter0 = counter0 = Counter(bits_sign=8) - self.submodules.counter1 = counter1 = Counter(bits_sign=8) - self.comb += [ - counter0.ce.eq(1), - If(counter0.value == 16, - counter0.reset.eq(1), - counter1.ce.eq(1) - ) - ] - - self.debug = ( - counter1.value - ) - self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True) - self.la.trigger.add_port(LiteScopeTerm(self.la.dw)) - - def do_exit(self, vns): - self.la.export(vns, "test/la.csv") - -default_subtarget = LiteScopeSoC diff --git a/misoclib/tools/litescope/test/Makefile b/misoclib/tools/litescope/test/Makefile deleted file mode 100644 index da182725..00000000 --- a/misoclib/tools/litescope/test/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -LSDIR = ../ -PYTHON = python3 - -CMD = PYTHONPATH=$(LSDIR) $(PYTHON) - -test_regs: - $(CMD) test_regs.py - -test_io: - $(CMD) test_io.py - -test_la: - $(CMD) test_la.py diff --git a/misoclib/tools/litescope/test/make.py b/misoclib/tools/litescope/test/make.py deleted file mode 100644 index 335623c0..00000000 --- a/misoclib/tools/litescope/test/make.py +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env python3 -import argparse, importlib - -def _get_args(): - parser = argparse.ArgumentParser() - parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use") - parser.add_argument("--port", default=3, help="UART port") - parser.add_argument("--baudrate", default=115200, help="UART baudrate") - parser.add_argument("--ip_address", default="192.168.1.40", help="Etherbone IP address") - parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port") - parser.add_argument("--busword", default=32, help="CSR busword") - - parser.add_argument("test", nargs="+", help="specify a test") - - return parser.parse_args() - -if __name__ == "__main__": - args = _get_args() - if args.bridge == "uart": - from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver - wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False) - elif args.bridge == "etherbone": - from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver - wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False) - else: - ValueError("Invalid bridge {}".format(args.bridge)) - - def _import(name): - return importlib.import_module(name) - - for test in args.test: - t = _import("test_"+test) - t.main(wb) diff --git a/misoclib/tools/litescope/test/test_io.py b/misoclib/tools/litescope/test/test_io.py deleted file mode 100644 index 135de36a..00000000 --- a/misoclib/tools/litescope/test/test_io.py +++ /dev/null @@ -1,34 +0,0 @@ -import time -from misoclib.tools.litescope.host.driver.io import LiteScopeIODriver - -def led_anim0(io): - for i in range(10): - io.write(0xA5) - time.sleep(0.1) - io.write(0x5A) - time.sleep(0.1) - -def led_anim1(io): - for j in range(4): - #Led << - led_data = 1 - for i in range(8): - io.write(led_data) - time.sleep(i*i*0.0020) - led_data = (led_data<<1) - #Led >> - ledData = 128 - for i in range(8): - io.write(led_data) - time.sleep(i*i*0.0020) - led_data = (led_data>>1) - -def main(wb): - io = LiteScopeIODriver(wb.regs, "io") - wb.open() - ### - led_anim0(io) - led_anim1(io) - print("%02X" %io.read()) - ### - wb.close() diff --git a/misoclib/tools/litescope/test/test_la.py b/misoclib/tools/litescope/test/test_la.py deleted file mode 100644 index 7a4b79e8..00000000 --- a/misoclib/tools/litescope/test/test_la.py +++ /dev/null @@ -1,26 +0,0 @@ -from misoclib.tools.litescope.host.driver.la import LiteScopeLADriver - -def main(wb): - wb.open() - ### - la = LiteScopeLADriver(wb.regs, "la", debug=True) - - #cond = {"cnt0" : 128} # trigger on cnt0 = 128 - cond = {} # trigger on cnt0 = 128 - la.configure_term(port=0, cond=cond) - la.configure_sum("term") - la.configure_subsampler(1) - #la.configure_qualifier(1) - la.configure_rle(1) - la.run(offset=128, length=256) - - while not la.done(): - pass - la.upload() - - la.save("dump.vcd") - la.save("dump.csv") - la.save("dump.py") - la.save("dump.sr") - ### - wb.close() diff --git a/misoclib/tools/litescope/test/test_regs.py b/misoclib/tools/litescope/test/test_regs.py deleted file mode 100644 index c0ef387f..00000000 --- a/misoclib/tools/litescope/test/test_regs.py +++ /dev/null @@ -1,9 +0,0 @@ -def main(wb): - wb.open() - regs = wb.regs - ### - print("sysid : 0x%04x" %regs.identifier_sysid.read()) - print("revision : 0x%04x" %regs.identifier_revision.read()) - print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000)) - ### - wb.close()