From: H.J. Lu <hongjiu.lu@intel.com>
Date: Wed, 15 May 2019 15:09:50 +0000 (+0000)
Subject: i386: Emulate MMX mmx_andnot<mode>3 with SSE
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df0e1979a8f5f0d3bdaff06393cf1bddfd725e6d;p=gcc.git

i386: Emulate MMX mmx_andnot<mode>3 with SSE

Emulate MMX mmx_andnot<mode>3 with SSE.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_andnot<mode>3): Also allow
	TARGET_MMX_WITH_SSE.  Add SSE support.

From-SVN: r271223
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7bee1506223..12ab4d0873e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/89021
+	* config/i386/mmx.md (mmx_andnot<mode>3): Also allow
+	TARGET_MMX_WITH_SSE.  Add SSE support.
+
 2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/89021
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 058d805de66..d3201d89fd6 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1074,14 +1074,18 @@
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (define_insn "mmx_andnot<mode>3"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv")
 	(and:MMXMODEI
-	  (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0"))
-	  (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
-  "TARGET_MMX"
-  "pandn\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxadd")
-   (set_attr "mode" "DI")])
+	  (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,Yv"))
+	  (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))]
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
+  "@
+   pandn\t{%2, %0|%0, %2}
+   pandn\t{%2, %0|%0, %2}
+   vpandn\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxadd,sselog,sselog")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_<code><mode>3"
   [(set (match_operand:MMXMODEI 0 "register_operand")