From: Richard Sandiford Date: Thu, 9 Jan 2020 16:24:15 +0000 (+0000) Subject: [AArch64] Add banner comments to aarch64-sve2.md X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df0f21028edd919421080f52a99a9b400ba8ba08;p=gcc.git [AArch64] Add banner comments to aarch64-sve2.md This patch imposes the same sort of structure on aarch64-sve2.md as we already have for aarch64-sve.md, before it grows a lot more patterns. 2020-01-09 Richard Sandiford gcc/ * config/aarch64/aarch64-sve2.md: Add banner comments. (mulhs3): Move further up file. (mull, shrnb, shrnt) (*aarch64_sve2_sra): Move further down file. * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too. From-SVN: r280058 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 121146d855c..8910d8622bf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-01-09 Richard Sandiford + + * config/aarch64/aarch64-sve2.md: Add banner comments. + (mulhs3): Move further up file. + (mull, shrnb, shrnt) + (*aarch64_sve2_sra): Move further down file. + * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too. + 2020-01-09 Richard Sandiford * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 349d0c4df82..1b2b6b2959b 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -18,6 +18,75 @@ ;; along with GCC; see the file COPYING3. If not see ;; . +;; The file is organised into the following sections (search for the full +;; line): +;; +;; == Uniform binary arithmnetic +;; ---- [INT] Scaled high-part multiplication +;; ---- [INT] General binary arithmetic that maps to unspecs +;; +;; == Uniform ternary arithmnetic +;; ---- [INT] Ternary logic operations +;; ---- [INT] Shift-and-accumulate operations +;; +;; == Extending arithmetic +;; ---- [INT] Long binary arithmetic +;; +;; == Narrowing arithnetic +;; ---- [INT] Narrowing right shifts +;; +;; == General +;; ---- Check for aliases between pointers + +;; ========================================================================= +;; == Uniform binary arithmnetic +;; ========================================================================= + +;; ------------------------------------------------------------------------- +;; ---- [INT] Scaled high-part multiplication +;; ------------------------------------------------------------------------- +;; The patterns in this section are synthetic. +;; ------------------------------------------------------------------------- + +;; Unpredicated integer multiply-high-with-(round-and-)scale. +(define_expand "mulhs3" + [(set (match_operand:SVE_FULL_BHSI 0 "register_operand") + (unspec:SVE_FULL_BHSI + [(match_dup 3) + (unspec:SVE_FULL_BHSI + [(match_operand:SVE_FULL_BHSI 1 "register_operand") + (match_operand:SVE_FULL_BHSI 2 "register_operand")] + MULHRS)] + UNSPEC_PRED_X))] + "TARGET_SVE2" + { + operands[3] = aarch64_ptrue_reg (mode); + + rtx prod_b = gen_reg_rtx (mode); + rtx prod_t = gen_reg_rtx (mode); + emit_insn (gen_mullb (prod_b, operands[1], operands[2])); + emit_insn (gen_mullt (prod_t, operands[1], operands[2])); + + rtx shift = GEN_INT (GET_MODE_UNIT_BITSIZE (mode) - 1); + emit_insn (gen_shrnb (operands[0], prod_b, shift)); + emit_insn (gen_shrnt (operands[0], operands[0], prod_t, shift)); + + DONE; + } +) + +;; ------------------------------------------------------------------------- +;; ---- [INT] General binary arithmetic that maps to unspecs +;; ------------------------------------------------------------------------- +;; Includes: +;; - SHADD +;; - SHSUB +;; - SRHADD +;; - UHADD +;; - UHSUB +;; - URHADD +;; ------------------------------------------------------------------------- + ;; Integer average (floor). (define_expand "avg3_floor" [(set (match_operand:SVE_FULL_I 0 "register_operand") @@ -67,85 +136,20 @@ [(set_attr "movprfx" "*,yes")] ) -;; Multiply long top / bottom. -(define_insn "mull" - [(set (match_operand: 0 "register_operand" "=w") - (unspec: - [(match_operand:SVE_FULL_BHSI 1 "register_operand" "w") - (match_operand:SVE_FULL_BHSI 2 "register_operand" "w")] - MULLBT))] - "TARGET_SVE2" - "mull\t%0., %1., %2." -) - -;; (Rounding) Right shift narrow bottom. -(define_insn "shrnb" - [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w") - (unspec:SVE_FULL_BHSI - [(match_operand: 1 "register_operand" "w") - (match_operand 2 "aarch64_simd_shift_imm_offset_" "")] - SHRNB))] - "TARGET_SVE2" - "shrnb\t%0., %1., #%2" -) - -;; (Rounding) Right shift narrow top. -(define_insn "shrnt" - [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w") - (unspec:SVE_FULL_BHSI - [(match_operand:SVE_FULL_BHSI 1 "register_operand" "0") - (match_operand: 2 "register_operand" "w") - (match_operand 3 "aarch64_simd_shift_imm_offset_" "i")] - SHRNT))] - "TARGET_SVE2" - "shrnt\t%0., %2., #%3" -) - -;; Unpredicated integer multiply-high-with-(round-and-)scale. -(define_expand "mulhs3" - [(set (match_operand:SVE_FULL_BHSI 0 "register_operand") - (unspec:SVE_FULL_BHSI - [(match_dup 3) - (unspec:SVE_FULL_BHSI - [(match_operand:SVE_FULL_BHSI 1 "register_operand") - (match_operand:SVE_FULL_BHSI 2 "register_operand")] - MULHRS)] - UNSPEC_PRED_X))] - "TARGET_SVE2" - { - operands[3] = aarch64_ptrue_reg (mode); - - rtx prod_b = gen_reg_rtx (mode); - rtx prod_t = gen_reg_rtx (mode); - emit_insn (gen_mullb (prod_b, operands[1], operands[2])); - emit_insn (gen_mullt (prod_t, operands[1], operands[2])); - - rtx shift = GEN_INT (GET_MODE_UNIT_BITSIZE (mode) - 1); - emit_insn (gen_shrnb (operands[0], prod_b, shift)); - emit_insn (gen_shrnt (operands[0], operands[0], prod_t, shift)); +;; ========================================================================= +;; == Uniform ternary arithmnetic +;; ========================================================================= - DONE; - } -) - -;; Unpredicated signed / unsigned shift-right accumulate. -(define_insn_and_rewrite "*aarch64_sve2_sra" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w") - (plus:SVE_FULL_I - (unspec:SVE_FULL_I - [(match_operand 4) - (SHIFTRT:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w") - (match_operand:SVE_FULL_I 3 "aarch64_simd_rshift_imm" "Dr"))] - UNSPEC_PRED_X) - (match_operand:SVE_FULL_I 1 "register_operand" "0")))] - "TARGET_SVE2" - "sra\t%0., %2., #%3" - "&& !CONSTANT_P (operands[4])" - { - operands[4] = CONSTM1_RTX (mode); - } -) +;; ------------------------------------------------------------------------- +;; ---- [INT] Ternary logic operations +;; ------------------------------------------------------------------------- +;; Includes: +;; - BSL +;; - BSL1N +;; - BSL2N +;; - EOR3 +;; - NBSL +;; ------------------------------------------------------------------------- ;; Unpredicated 3-way exclusive OR. (define_insn "*aarch64_sve2_eor3" @@ -332,6 +336,106 @@ [(set_attr "movprfx" "*,yes")] ) +;; ------------------------------------------------------------------------- +;; ---- [INT] Shift-and-accumulate operations +;; ------------------------------------------------------------------------- +;; Includes: +;; - SSRA +;; - USRA +;; ------------------------------------------------------------------------- + +;; Unpredicated signed / unsigned shift-right accumulate. +(define_insn_and_rewrite "*aarch64_sve2_sra" + [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w") + (plus:SVE_FULL_I + (unspec:SVE_FULL_I + [(match_operand 4) + (SHIFTRT:SVE_FULL_I + (match_operand:SVE_FULL_I 2 "register_operand" "w") + (match_operand:SVE_FULL_I 3 "aarch64_simd_rshift_imm" "Dr"))] + UNSPEC_PRED_X) + (match_operand:SVE_FULL_I 1 "register_operand" "0")))] + "TARGET_SVE2" + "sra\t%0., %2., #%3" + "&& !CONSTANT_P (operands[4])" + { + operands[4] = CONSTM1_RTX (mode); + } +) + +;; ========================================================================= +;; == Extending arithmetic +;; ========================================================================= + +;; ------------------------------------------------------------------------- +;; ---- [INT] Long binary arithmetic +;; ------------------------------------------------------------------------- +;; Includes: +;; - SMULLB +;; - SMULLT +;; - UMULLB +;; - UMULLT +;; ------------------------------------------------------------------------- + +;; Multiply long top / bottom. +(define_insn "mull" + [(set (match_operand: 0 "register_operand" "=w") + (unspec: + [(match_operand:SVE_FULL_BHSI 1 "register_operand" "w") + (match_operand:SVE_FULL_BHSI 2 "register_operand" "w")] + MULLBT))] + "TARGET_SVE2" + "mull\t%0., %1., %2." +) + +;; ========================================================================= +;; == Narrowing arithnetic +;; ========================================================================= + +;; ------------------------------------------------------------------------- +;; ---- [INT] Narrowing right shifts +;; ------------------------------------------------------------------------- +;; Includes: +;; - RSHRNB +;; - RSHRNT +;; - SHRNB +;; - SHRNT +;; ------------------------------------------------------------------------- + +;; (Rounding) Right shift narrow bottom. +(define_insn "shrnb" + [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w") + (unspec:SVE_FULL_BHSI + [(match_operand: 1 "register_operand" "w") + (match_operand 2 "aarch64_simd_shift_imm_offset_" "")] + SHRNB))] + "TARGET_SVE2" + "shrnb\t%0., %1., #%2" +) + +;; (Rounding) Right shift narrow top. +(define_insn "shrnt" + [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w") + (unspec:SVE_FULL_BHSI + [(match_operand:SVE_FULL_BHSI 1 "register_operand" "0") + (match_operand: 2 "register_operand" "w") + (match_operand 3 "aarch64_simd_shift_imm_offset_" "i")] + SHRNT))] + "TARGET_SVE2" + "shrnt\t%0., %2., #%3" +) + +;; ========================================================================= +;; == General +;; ========================================================================= + +;; ------------------------------------------------------------------------- +;; ---- Check for aliases between pointers +;; ------------------------------------------------------------------------- +;; The patterns in this section are synthetic: WHILERW and WHILEWR are +;; defined in aarch64-sve.md instead. +;; ------------------------------------------------------------------------- + ;; Use WHILERW and WHILEWR to accelerate alias checks. This is only ;; possible if the accesses we're checking are exactly the same size ;; as an SVE vector. diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64 index 475d5c5e8af..2bdb4a922fe 100644 --- a/gcc/config/aarch64/t-aarch64 +++ b/gcc/config/aarch64/t-aarch64 @@ -147,7 +147,10 @@ MULTILIB_DIRNAMES = $(subst $(comma), ,$(TM_MULTILIB_CONFIG)) insn-conditions.md: s-check-sve-md s-check-sve-md: $(srcdir)/config/aarch64/check-sve-md.awk \ - $(srcdir)/config/aarch64/aarch64-sve.md + $(srcdir)/config/aarch64/aarch64-sve.md \ + $(srcdir)/config/aarch64/aarch64-sve2.md $(AWK) -f $(srcdir)/config/aarch64/check-sve-md.awk \ $(srcdir)/config/aarch64/aarch64-sve.md + $(AWK) -f $(srcdir)/config/aarch64/check-sve-md.awk \ + $(srcdir)/config/aarch64/aarch64-sve2.md $(STAMP) s-check-sve-md