From: Florent Kermarrec Date: Fri, 6 Feb 2015 11:22:24 +0000 (+0100) Subject: add icmp_tb X-Git-Tag: 24jan2021_ls180~2604^2~69 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df0f27fefef4e3e3502cd054ce3d60a37555cbb9;p=litex.git add icmp_tb --- diff --git a/liteeth/core/icmp/__init__.py b/liteeth/core/icmp/__init__.py index 8dff0319..8d65583b 100644 --- a/liteeth/core/icmp/__init__.py +++ b/liteeth/core/icmp/__init__.py @@ -118,16 +118,23 @@ class LiteEthICMPEcho(Module): self.sink = Sink(eth_icmp_user_description(8)) self.source = Source(eth_icmp_user_description(8)) ### + self.submodules.fifo = SyncFIFO(eth_icmp_user_description(8), 1024) self.comb += [ - Record.connect(self.sink, self.source), + Record.connect(self.sink, self.fifo.sink), + Record.connect(self.fifo.source, self.source), self.source.msgtype.eq(0x0), - self.source.checksum.eq(~((~self.sink.checksum)-0x0800)) + self.source.checksum.eq(~((~self.fifo.source.checksum)-0x0800)) ] class LiteEthICMP(Module): def __init__(self, ip, ip_address): self.submodules.tx = LiteEthICMPTX(ip_address) self.submodules.rx = LiteEthICMPRX(ip_address) + self.submodules.echo = LiteEthICMPEcho() + self.comb += [ + Record.connect(self.rx.source, self.echo.sink), + Record.connect(self.echo.source, self.tx.sink) + ] ip_port = ip.crossbar.get_port(icmp_protocol) self.comb += [ Record.connect(self.tx.source, ip_port.sink), diff --git a/liteeth/test/Makefile b/liteeth/test/Makefile index f02ba1fb..43dd6771 100644 --- a/liteeth/test/Makefile +++ b/liteeth/test/Makefile @@ -22,5 +22,8 @@ arp_tb: ip_tb: $(CMD) ip_tb.py -udpip_tb: - $(CMD) udpip_tb.py +udp_tb: + $(CMD) udp_tb.py + +icmp_tb: + $(CMD) icmp_tb.py diff --git a/liteeth/test/common.py b/liteeth/test/common.py index bbdca435..d780565b 100644 --- a/liteeth/test/common.py +++ b/liteeth/test/common.py @@ -83,6 +83,10 @@ class PacketStreamer(Module): def send(self, packet): packet = copy.deepcopy(packet) self.packets.append(packet) + return packet + + def send_blocking(self, packet): + packet = self.send(packet) while not packet.done: yield diff --git a/liteeth/test/icmp_tb.py b/liteeth/test/icmp_tb.py new file mode 100644 index 00000000..f5e2d907 --- /dev/null +++ b/liteeth/test/icmp_tb.py @@ -0,0 +1,58 @@ +from migen.fhdl.std import * +from migen.bus import wishbone +from migen.bus.transactions import * +from migen.sim.generic import run_simulation + +from liteeth.common import * +from liteeth.core import LiteEthIPCore + +from liteeth.test.common import * +from liteeth.test.model.dumps import * +from liteeth.test.model.mac import * +from liteeth.test.model.ip import * +from liteeth.test.model.icmp import * +from liteeth.test.model import phy, mac, arp, ip, icmp + +ip_address = 0x12345678 +mac_address = 0x12345678abcd + +class TB(Module): + def __init__(self): + self.submodules.phy_model = phy.PHY(8, debug=True) + self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False) + self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True) + self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False) + self.submodules.icmp_model = icmp.ICMP(self.ip_model, ip_address, debug=True) + + self.submodules.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000) + + # use sys_clk for each clock_domain + self.clock_domains.cd_eth_rx = ClockDomain() + self.clock_domains.cd_eth_tx = ClockDomain() + self.comb += [ + self.cd_eth_rx.clk.eq(ClockSignal()), + self.cd_eth_rx.rst.eq(ResetSignal()), + self.cd_eth_tx.clk.eq(ClockSignal()), + self.cd_eth_tx.rst.eq(ResetSignal()), + ] + + def gen_simulation(self, selfp): + selfp.cd_eth_rx.rst = 1 + selfp.cd_eth_tx.rst = 1 + yield + selfp.cd_eth_rx.rst = 0 + selfp.cd_eth_tx.rst = 0 + + for i in range(100): + yield + + packet = MACPacket(ping_request) + packet.decode_remove_header() + packet = IPPacket(packet) + packet.decode() + packet = ICMPPacket(packet) + packet.decode() + self.icmp_model.send(packet) + +if __name__ == "__main__": + run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True) diff --git a/liteeth/test/model/icmp.py b/liteeth/test/model/icmp.py index 5ee08042..8a27b61f 100644 --- a/liteeth/test/model/icmp.py +++ b/liteeth/test/model/icmp.py @@ -42,7 +42,6 @@ class ICMP(Module): self.ip = ip self.ip_address = ip_address self.debug = debug - self.loopback = loopback self.tx_packets = [] self.tx_packet = ICMPPacket() self.rx_packet = ICMPPacket() @@ -74,10 +73,7 @@ class ICMP(Module): if self.debug: print_icmp("<<<<<<<<") print_icmp(packet) - if self.loopback: - self.send(packet) - else: - self.process(packet) + self.process(packet) def process(self, packet): pass diff --git a/liteeth/test/model/ip.py b/liteeth/test/model/ip.py index 58b95e3d..96428447 100644 --- a/liteeth/test/model/ip.py +++ b/liteeth/test/model/ip.py @@ -68,11 +68,10 @@ class IP(Module): self.ip_address = ip_address self.debug = debug self.loopback = loopback - self.tx_packets = [] - self.tx_packet = IPPacket() self.rx_packet = IPPacket() self.table = {} self.request_pending = False + self.udp_callback = None self.icmp_callback = None @@ -102,7 +101,7 @@ class IP(Module): received = packet.get_checksum() packet.insert_checksum() expected = packet.get_checksum() - raise ValueError("Checksum error received %04x / expected %04x" %(received, expected)) # XXX maybe too restrictive + raise ValueError("Checksum error received %04x / expected %04x" %(received, expected)) packet.decode() if self.debug: print_ip("<<<<<<<<") diff --git a/liteeth/test/model/mac.py b/liteeth/test/model/mac.py index f3528835..f18f4990 100644 --- a/liteeth/test/model/mac.py +++ b/liteeth/test/model/mac.py @@ -88,13 +88,13 @@ class MAC(Module): self.phy = phy self.debug = debug self.loopback = loopback - self.tx_packets = [] - self.tx_packet = MACPacket() self.rx_packet = MACPacket() self.ip_callback = None self.arp_callback = None + phy.set_mac_callback(self.callback) + def set_ip_callback(self, callback): self.ip_callback = callback @@ -106,7 +106,7 @@ class MAC(Module): print_mac(">>>>>>>>") print_mac(packet) packet.encode() - self.tx_packets.append(packet) + self.phy.send(packet) def callback(self, datas): packet = MACPacket(datas) @@ -126,16 +126,6 @@ class MAC(Module): else: raise ValueError # XXX handle this properly - def gen_simulation(self, selfp): - self.tx_packet.done = True - while True: - yield from self.phy.receive() - self.callback(self.phy.packet) - # XXX add full duplex - if len(self.tx_packets) != 0: - tx_packet = self.tx_packets.pop(0) - yield from self.phy.send(tx_packet) - if __name__ == "__main__": from liteeth.test.model.dumps import * errors = 0 diff --git a/liteeth/test/model/phy.py b/liteeth/test/model/phy.py index 9f388f5b..8fc71629 100644 --- a/liteeth/test/model/phy.py +++ b/liteeth/test/model/phy.py @@ -37,7 +37,7 @@ class PHY(Module): for d in datas: r += "%02x" %d print_phy(r) - yield from self.phy_source.send(packet) + self.phy_source.send(packet) def receive(self): yield from self.phy_sink.receive() @@ -48,3 +48,9 @@ class PHY(Module): r += "%02x" %d print_phy(r) self.packet = self.phy_sink.packet + + def gen_simulation(self, selfp): + while True: + yield from self.receive() + if self.mac_callback is not None: + self.mac_callback(self.packet) diff --git a/liteeth/test/udp_tb.py b/liteeth/test/udp_tb.py new file mode 100644 index 00000000..4718cb94 --- /dev/null +++ b/liteeth/test/udp_tb.py @@ -0,0 +1,66 @@ +from migen.fhdl.std import * +from migen.bus import wishbone +from migen.bus.transactions import * +from migen.sim.generic import run_simulation + +from liteeth.common import * +from liteeth.core import LiteEthUDPIPCore + +from liteeth.test.common import * +from liteeth.test.model import phy, mac, arp, ip, udp + +ip_address = 0x12345678 +mac_address = 0x12345678abcd + +class TB(Module): + def __init__(self): + self.submodules.phy_model = phy.PHY(8, debug=False) + self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False) + self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False) + self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False) + self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True) + + self.submodules.udp = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000) + self.submodules.streamer = PacketStreamer(eth_udp_user_description(8)) + self.submodules.logger = PacketLogger(eth_udp_user_description(8)) + self.comb += [ + Record.connect(self.streamer.source, self.udp.sink), + self.udp.sink.ip_address.eq(0x12345678), + self.udp.sink.src_port.eq(0x1234), + self.udp.sink.dst_port.eq(0x5678), + self.udp.sink.length.eq(64), + Record.connect(self.udp.source, self.logger.sink) + ] + + # use sys_clk for each clock_domain + self.clock_domains.cd_eth_rx = ClockDomain() + self.clock_domains.cd_eth_tx = ClockDomain() + self.comb += [ + self.cd_eth_rx.clk.eq(ClockSignal()), + self.cd_eth_rx.rst.eq(ResetSignal()), + self.cd_eth_tx.clk.eq(ClockSignal()), + self.cd_eth_tx.rst.eq(ResetSignal()), + ] + + def gen_simulation(self, selfp): + selfp.cd_eth_rx.rst = 1 + selfp.cd_eth_tx.rst = 1 + yield + selfp.cd_eth_rx.rst = 0 + selfp.cd_eth_tx.rst = 0 + + for i in range(100): + yield + + while True: + packet = Packet([i for i in range(64)]) + yield from self.streamer.send(packet) + yield from self.logger.receive() + + # check results + s, l, e = check(packet, self.logger.packet) + print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) + + +if __name__ == "__main__": + run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True) diff --git a/liteeth/test/udpip_tb.py b/liteeth/test/udpip_tb.py deleted file mode 100644 index fada83fb..00000000 --- a/liteeth/test/udpip_tb.py +++ /dev/null @@ -1,66 +0,0 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bus.transactions import * -from migen.sim.generic import run_simulation - -from liteeth.common import * -from liteeth.core import LiteEthUDPIPCore - -from liteeth.test.common import * -from liteeth.test.model import phy, mac, arp, ip, udp - -ip_address = 0x12345678 -mac_address = 0x12345678abcd - -class TB(Module): - def __init__(self): - self.submodules.phy_model = phy.PHY(8, debug=False) - self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False) - self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False) - self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False) - self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True) - - self.submodules.udp_ip = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000) - self.submodules.streamer = PacketStreamer(eth_udp_user_description(8)) - self.submodules.logger = PacketLogger(eth_udp_user_description(8)) - self.comb += [ - Record.connect(self.streamer.source, self.udp_ip.sink), - self.udp_ip.sink.ip_address.eq(0x12345678), - self.udp_ip.sink.src_port.eq(0x1234), - self.udp_ip.sink.dst_port.eq(0x5678), - self.udp_ip.sink.length.eq(64), - Record.connect(self.udp_ip.source, self.logger.sink) - ] - - # use sys_clk for each clock_domain - self.clock_domains.cd_eth_rx = ClockDomain() - self.clock_domains.cd_eth_tx = ClockDomain() - self.comb += [ - self.cd_eth_rx.clk.eq(ClockSignal()), - self.cd_eth_rx.rst.eq(ResetSignal()), - self.cd_eth_tx.clk.eq(ClockSignal()), - self.cd_eth_tx.rst.eq(ResetSignal()), - ] - - def gen_simulation(self, selfp): - selfp.cd_eth_rx.rst = 1 - selfp.cd_eth_tx.rst = 1 - yield - selfp.cd_eth_rx.rst = 0 - selfp.cd_eth_tx.rst = 0 - - for i in range(100): - yield - - while True: - packet = Packet([i for i in range(64)]) - yield from self.streamer.send(packet) - yield from self.logger.receive() - - # check results - s, l, e = check(packet, self.logger.packet) - print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) - - -if __name__ == "__main__": - run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)