From: lkcl <lkcl@web>
Date: Sun, 10 Apr 2022 23:51:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2798
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df159a6230c100afe5c2412d07c1f6ba2c8fa9ef;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index e5b353d60..feba1ab45 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -188,18 +188,26 @@ The following fields are common to all Remapped Encodings:
 | Field Name | Field bits | Description                            |
 |------------|------------|----------------------------------------|
 | MASKMODE   | `0`        | Execution (predication) Mask Kind      |
-| MASK          | `1:3`      | Execution Mask                      |
+| MASK       | `1:3`      | Execution Mask                      |
+| SUBVL      | `8:9`      | Sub-vector length                   |                          
+
+The following fields are optional or encoded differently depending
+on context after decoding of the Scalar suffix:
+
+| Field Name | Field bits | Description                            |
+|------------|------------|----------------------------------------|
 | ELWIDTH       | `4:5`      | Element Width                       |
 | ELWIDTH_SRC   | `6:7`      | Element Width for Source      |
-| SUBVL         | `8:9`      | Sub-vector length                   |                          
+| EXTRA         | `10:18`    | Register Extra encoding                |                          
 | MODE          | `19:23`    | changes Vector behaviour               |
 
+
 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
+* Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
 
-Bits 10 to 18 are further decoded depending on RM category for the instruction.
 Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
 
 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.