From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 9 Sep 2018 00:10:50 +0000 (+0200)
Subject: soc_sdram: update with litedram
X-Git-Tag: 24jan2021_ls180~1617
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df3f003ecd4710ee971b625cc9226a463adfa7db;p=litex.git

soc_sdram: update with litedram
---

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 238ede4c..30548cef 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -15,8 +15,12 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
 
 class ControllerInjector(Module, AutoCSR):
     def __init__(self, phy, geom_settings, timing_settings, **kwargs):
-        self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
-                phy.settings.dfi_databits, phy.settings.nphases)
+        self.submodules.dfii = dfii.DFIInjector(
+            geom_settings.addressbits,
+            geom_settings.bankbits,
+            phy.settings.nranks,
+            phy.settings.dfi_databits,
+            phy.settings.nphases)
         self.comb += self.dfii.master.connect(phy.dfi)
 
         self.submodules.controller = controller = core.LiteDRAMController(