From: Luke Kenneth Casson Leighton Date: Thu, 3 Dec 2020 15:36:00 +0000 (+0000) Subject: added 3 more 4k SRAMs X-Git-Tag: ls180-24jan2020~11 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df409461a7320964e5459bf9ea130ee10d338887;p=soclayout.git added 3 more 4k SRAMs --- diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index dfa10f3..435fe72 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -220710,2498 +220710,2686 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-10555.10" +attribute \src "ls180.v:4.1-10811.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:10043.1-10053.4" - wire width 7 $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 - attribute \src "ls180.v:10043.1-10053.4" - wire width 32 $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 - attribute \src "ls180.v:10043.1-10053.4" - wire width 32 $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 - attribute \src "ls180.v:10043.1-10053.4" - wire width 7 $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 - attribute \src "ls180.v:10043.1-10053.4" - wire width 32 $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 - attribute \src "ls180.v:10043.1-10053.4" - wire width 32 $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 - attribute \src "ls180.v:10043.1-10053.4" - wire width 7 $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 - attribute \src "ls180.v:10043.1-10053.4" - wire width 32 $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 - attribute \src "ls180.v:10043.1-10053.4" - wire width 32 $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 - attribute \src "ls180.v:10043.1-10053.4" - wire width 7 $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 - attribute \src "ls180.v:10043.1-10053.4" - wire width 32 $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 - attribute \src "ls180.v:10043.1-10053.4" - wire width 32 $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 - attribute \src "ls180.v:10063.1-10067.4" - wire width 3 $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 - attribute \src "ls180.v:10063.1-10067.4" - wire width 25 $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 - attribute \src "ls180.v:10063.1-10067.4" - wire width 25 $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 - attribute \src "ls180.v:10077.1-10081.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 - attribute \src "ls180.v:10077.1-10081.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 - attribute \src "ls180.v:10077.1-10081.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 - attribute \src "ls180.v:10091.1-10095.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 - attribute \src "ls180.v:10091.1-10095.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 - attribute \src "ls180.v:10091.1-10095.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 - attribute \src "ls180.v:10105.1-10109.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 - attribute \src "ls180.v:10105.1-10109.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 - attribute \src "ls180.v:10105.1-10109.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 - attribute \src "ls180.v:10120.1-10124.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 - attribute \src "ls180.v:10120.1-10124.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 - attribute \src "ls180.v:10120.1-10124.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 - attribute \src "ls180.v:10137.1-10141.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 - attribute \src "ls180.v:10137.1-10141.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 - attribute \src "ls180.v:10137.1-10141.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 - attribute \src "ls180.v:10153.1-10157.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 - attribute \src "ls180.v:10153.1-10157.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 - attribute \src "ls180.v:10153.1-10157.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 - attribute \src "ls180.v:10167.1-10171.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 - attribute \src "ls180.v:10167.1-10171.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 - attribute \src "ls180.v:10167.1-10171.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0$memwr$\mem$ls180.v:10209$1_ADDR[8:0]$2823 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10209$1_DATA[63:0]$2824 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10209$1_EN[63:0]$2825 + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0$memwr$\mem$ls180.v:10211$2_ADDR[8:0]$2826 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10211$2_DATA[63:0]$2827 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10211$2_EN[63:0]$2828 + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0$memwr$\mem$ls180.v:10213$3_ADDR[8:0]$2829 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10213$3_DATA[63:0]$2830 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10213$3_EN[63:0]$2831 + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0$memwr$\mem$ls180.v:10215$4_ADDR[8:0]$2832 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10215$4_DATA[63:0]$2833 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10215$4_EN[63:0]$2834 + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0$memwr$\mem$ls180.v:10217$5_ADDR[8:0]$2835 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10217$5_DATA[63:0]$2836 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10217$5_EN[63:0]$2837 + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0$memwr$\mem$ls180.v:10219$6_ADDR[8:0]$2838 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10219$6_DATA[63:0]$2839 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10219$6_EN[63:0]$2840 + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0$memwr$\mem$ls180.v:10221$7_ADDR[8:0]$2841 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10221$7_DATA[63:0]$2842 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10221$7_EN[63:0]$2843 + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0$memwr$\mem$ls180.v:10223$8_ADDR[8:0]$2844 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10223$8_DATA[63:0]$2845 + attribute \src "ls180.v:10207.1-10225.4" + wire width 64 $0$memwr$\mem$ls180.v:10223$8_EN[63:0]$2846 + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0$memwr$\mem_1$ls180.v:10237$9_ADDR[8:0]$2849 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10237$9_DATA[63:0]$2850 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10237$9_EN[63:0]$2851 + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0$memwr$\mem_1$ls180.v:10239$10_ADDR[8:0]$2852 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10239$10_DATA[63:0]$2853 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10239$10_EN[63:0]$2854 + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0$memwr$\mem_1$ls180.v:10241$11_ADDR[8:0]$2855 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10241$11_DATA[63:0]$2856 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10241$11_EN[63:0]$2857 + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0$memwr$\mem_1$ls180.v:10243$12_ADDR[8:0]$2858 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10243$12_DATA[63:0]$2859 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10243$12_EN[63:0]$2860 + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0$memwr$\mem_1$ls180.v:10245$13_ADDR[8:0]$2861 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10245$13_DATA[63:0]$2862 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10245$13_EN[63:0]$2863 + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0$memwr$\mem_1$ls180.v:10247$14_ADDR[8:0]$2864 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10247$14_DATA[63:0]$2865 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10247$14_EN[63:0]$2866 + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0$memwr$\mem_1$ls180.v:10249$15_ADDR[8:0]$2867 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10249$15_DATA[63:0]$2868 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10249$15_EN[63:0]$2869 + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0$memwr$\mem_1$ls180.v:10251$16_ADDR[8:0]$2870 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10251$16_DATA[63:0]$2871 + attribute \src "ls180.v:10235.1-10253.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10251$16_EN[63:0]$2872 + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0$memwr$\mem_2$ls180.v:10265$17_ADDR[8:0]$2875 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10265$17_DATA[63:0]$2876 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10265$17_EN[63:0]$2877 + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0$memwr$\mem_2$ls180.v:10267$18_ADDR[8:0]$2878 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10267$18_DATA[63:0]$2879 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10267$18_EN[63:0]$2880 + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0$memwr$\mem_2$ls180.v:10269$19_ADDR[8:0]$2881 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10269$19_DATA[63:0]$2882 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10269$19_EN[63:0]$2883 + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0$memwr$\mem_2$ls180.v:10271$20_ADDR[8:0]$2884 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10271$20_DATA[63:0]$2885 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10271$20_EN[63:0]$2886 + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0$memwr$\mem_2$ls180.v:10273$21_ADDR[8:0]$2887 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10273$21_DATA[63:0]$2888 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10273$21_EN[63:0]$2889 + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0$memwr$\mem_2$ls180.v:10275$22_ADDR[8:0]$2890 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10275$22_DATA[63:0]$2891 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10275$22_EN[63:0]$2892 + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0$memwr$\mem_2$ls180.v:10277$23_ADDR[8:0]$2893 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10277$23_DATA[63:0]$2894 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10277$23_EN[63:0]$2895 + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0$memwr$\mem_2$ls180.v:10279$24_ADDR[8:0]$2896 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10279$24_DATA[63:0]$2897 + attribute \src "ls180.v:10263.1-10281.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10279$24_EN[63:0]$2898 + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0$memwr$\mem_3$ls180.v:10293$25_ADDR[8:0]$2901 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10293$25_DATA[63:0]$2902 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10293$25_EN[63:0]$2903 + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0$memwr$\mem_3$ls180.v:10295$26_ADDR[8:0]$2904 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10295$26_DATA[63:0]$2905 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10295$26_EN[63:0]$2906 + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0$memwr$\mem_3$ls180.v:10297$27_ADDR[8:0]$2907 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10297$27_DATA[63:0]$2908 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10297$27_EN[63:0]$2909 + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0$memwr$\mem_3$ls180.v:10299$28_ADDR[8:0]$2910 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10299$28_DATA[63:0]$2911 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10299$28_EN[63:0]$2912 + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0$memwr$\mem_3$ls180.v:10301$29_ADDR[8:0]$2913 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10301$29_DATA[63:0]$2914 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10301$29_EN[63:0]$2915 + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0$memwr$\mem_3$ls180.v:10303$30_ADDR[8:0]$2916 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10303$30_DATA[63:0]$2917 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10303$30_EN[63:0]$2918 + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0$memwr$\mem_3$ls180.v:10305$31_ADDR[8:0]$2919 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10305$31_DATA[63:0]$2920 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10305$31_EN[63:0]$2921 + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0$memwr$\mem_3$ls180.v:10307$32_ADDR[8:0]$2922 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10307$32_DATA[63:0]$2923 + attribute \src "ls180.v:10291.1-10309.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10307$32_EN[63:0]$2924 + attribute \src "ls180.v:10319.1-10323.4" + wire width 3 $0$memwr$\storage$ls180.v:10321$33_ADDR[2:0]$2927 + attribute \src "ls180.v:10319.1-10323.4" + wire width 25 $0$memwr$\storage$ls180.v:10321$33_DATA[24:0]$2928 + attribute \src "ls180.v:10319.1-10323.4" + wire width 25 $0$memwr$\storage$ls180.v:10321$33_EN[24:0]$2929 + attribute \src "ls180.v:10333.1-10337.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10335$34_ADDR[2:0]$2934 + attribute \src "ls180.v:10333.1-10337.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10335$34_DATA[24:0]$2935 + attribute \src "ls180.v:10333.1-10337.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10335$34_EN[24:0]$2936 + attribute \src "ls180.v:10347.1-10351.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10349$35_ADDR[2:0]$2941 + attribute \src "ls180.v:10347.1-10351.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10349$35_DATA[24:0]$2942 + attribute \src "ls180.v:10347.1-10351.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10349$35_EN[24:0]$2943 + attribute \src "ls180.v:10361.1-10365.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10363$36_ADDR[2:0]$2948 + attribute \src "ls180.v:10361.1-10365.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10363$36_DATA[24:0]$2949 + attribute \src "ls180.v:10361.1-10365.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10363$36_EN[24:0]$2950 + attribute \src "ls180.v:10376.1-10380.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10378$37_ADDR[3:0]$2955 + attribute \src "ls180.v:10376.1-10380.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10378$37_DATA[9:0]$2956 + attribute \src "ls180.v:10376.1-10380.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10378$37_EN[9:0]$2957 + attribute \src "ls180.v:10393.1-10397.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10395$38_ADDR[3:0]$2962 + attribute \src "ls180.v:10393.1-10397.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10395$38_DATA[9:0]$2963 + attribute \src "ls180.v:10393.1-10397.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10395$38_EN[9:0]$2964 + attribute \src "ls180.v:10409.1-10413.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10411$39_ADDR[4:0]$2969 + attribute \src "ls180.v:10409.1-10413.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10411$39_DATA[9:0]$2970 + attribute \src "ls180.v:10409.1-10413.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10411$39_EN[9:0]$2971 + attribute \src "ls180.v:10423.1-10427.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10425$40_ADDR[4:0]$2976 + attribute \src "ls180.v:10423.1-10427.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10425$40_DATA[9:0]$2977 + attribute \src "ls180.v:10423.1-10427.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10425$40_EN[9:0]$2978 + attribute \src "ls180.v:3320.1-3413.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6516.1-6532.4" + attribute \src "ls180.v:6653.1-6669.4" wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6737.1-6753.4" + attribute \src "ls180.v:6874.1-6890.4" wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6754.1-6770.4" + attribute \src "ls180.v:6891.1-6907.4" wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6822.1-6829.4" + attribute \src "ls180.v:6959.1-6966.4" wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6830.1-6837.4" + attribute \src "ls180.v:6967.1-6974.4" wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6838.1-6845.4" + attribute \src "ls180.v:6975.1-6982.4" wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6846.1-6853.4" + attribute \src "ls180.v:6983.1-6990.4" wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6854.1-6861.4" + attribute \src "ls180.v:6991.1-6998.4" wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6862.1-6869.4" + attribute \src "ls180.v:6999.1-7006.4" wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6870.1-6877.4" + attribute \src "ls180.v:7007.1-7014.4" wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6878.1-6885.4" + attribute \src "ls180.v:7015.1-7022.4" wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6533.1-6549.4" + attribute \src "ls180.v:6670.1-6686.4" wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6886.1-6893.4" + attribute \src "ls180.v:7023.1-7030.4" wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6894.1-6901.4" + attribute \src "ls180.v:7031.1-7038.4" wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:6902.1-6909.4" + attribute \src "ls180.v:7039.1-7046.4" wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:6910.1-6917.4" + attribute \src "ls180.v:7047.1-7054.4" wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:6918.1-6937.4" + attribute \src "ls180.v:7055.1-7074.4" wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:6938.1-6957.4" - wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:6958.1-6977.4" - wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:6978.1-6997.4" + attribute \src "ls180.v:7075.1-7094.4" + wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:7095.1-7114.4" + wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:7115.1-7134.4" wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:6998.1-7017.4" + attribute \src "ls180.v:7135.1-7154.4" wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7018.1-7037.4" + attribute \src "ls180.v:7155.1-7174.4" wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6550.1-6566.4" + attribute \src "ls180.v:6687.1-6703.4" wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7038.1-7057.4" + attribute \src "ls180.v:7175.1-7194.4" wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7058.1-7077.4" + attribute \src "ls180.v:7195.1-7214.4" wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6567.1-6583.4" + attribute \src "ls180.v:6704.1-6720.4" wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6584.1-6600.4" + attribute \src "ls180.v:6721.1-6737.4" wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6601.1-6617.4" + attribute \src "ls180.v:6738.1-6754.4" wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6669.1-6685.4" + attribute \src "ls180.v:6806.1-6822.4" wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6686.1-6702.4" + attribute \src "ls180.v:6823.1-6839.4" wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6703.1-6719.4" + attribute \src "ls180.v:6840.1-6856.4" wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6720.1-6736.4" + attribute \src "ls180.v:6857.1-6873.4" wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6618.1-6634.4" + attribute \src "ls180.v:6755.1-6771.4" wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6635.1-6651.4" + attribute \src "ls180.v:6772.1-6788.4" wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6652.1-6668.4" + attribute \src "ls180.v:6789.1-6805.4" wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6771.1-6787.4" + attribute \src "ls180.v:6908.1-6924.4" wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6788.1-6804.4" + attribute \src "ls180.v:6925.1-6941.4" wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6805.1-6821.4" + attribute \src "ls180.v:6942.1-6958.4" wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2786.1-2832.4" + attribute \src "ls180.v:2838.1-2884.4" wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2846.1-2892.4" + attribute \src "ls180.v:2898.1-2944.4" wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2958.1-3004.4" wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5756.1-5767.4" + attribute \src "ls180.v:5893.1-5904.4" wire $0\builder_error[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:5755.1-5791.4" wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:5755.1-5791.4" wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:1925.5-1925.55" + wire $0\builder_libresocsim_converted_interface_ack[0:0] + attribute \src "ls180.v:1921.12-1921.65" + wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] + attribute \src "ls180.v:1929.5-1929.55" + wire $0\builder_libresocsim_converted_interface_err[0:0] + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:5755.1-5791.4" wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:5755.1-5791.4" wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:5755.1-5791.4" wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:5755.1-5791.4" wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:5755.1-5791.4" wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:1911.12-1911.52" + wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] + attribute \src "ls180.v:1915.5-1915.44" + wire $0\builder_libresocsim_wishbone_cyc[0:0] + attribute \src "ls180.v:5755.1-5791.4" wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1877.5-1877.44" - wire $0\builder_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:1766.5-1766.27" + attribute \src "ls180.v:1912.12-1912.54" + wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] + attribute \src "ls180.v:1914.11-1914.50" + wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] + attribute \src "ls180.v:1916.5-1916.44" + wire $0\builder_libresocsim_wishbone_stb[0:0] + attribute \src "ls180.v:1918.5-1918.43" + wire $0\builder_libresocsim_wishbone_we[0:0] + attribute \src "ls180.v:1810.5-1810.27" wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1767.5-1767.27" + attribute \src "ls180.v:1811.5-1811.27" wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1768.5-1768.27" + attribute \src "ls180.v:1812.5-1812.27" wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1769.5-1769.27" + attribute \src "ls180.v:1813.5-1813.27" wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5645.1-5681.4" + attribute \src "ls180.v:5755.1-5791.4" wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3128.1-3158.4" + attribute \src "ls180.v:3226.1-3256.4" wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5455.1-5494.4" + attribute \src "ls180.v:5553.1-5592.4" wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:5612.1-5649.4" wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5552.1-5588.4" + attribute \src "ls180.v:5650.1-5686.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4432.1-4508.4" + attribute \src "ls180.v:4530.1-4606.4" wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4669.1-4696.4" + attribute \src "ls180.v:4767.1-4794.4" wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4398.1-4431.4" + attribute \src "ls180.v:4496.1-4529.4" wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5756.1-5767.4" + attribute \src "ls180.v:5893.1-5904.4" wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5756.1-5767.4" + attribute \src "ls180.v:5893.1-5904.4" wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5706.1-5713.4" - wire width 5 $0\builder_slave_sel[4:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 5 $0\builder_slave_sel_r[4:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:5816.1-5826.4" + wire width 8 $0\builder_slave_sel[7:0] + attribute \src "ls180.v:7564.1-10203.4" + wire width 8 $0\builder_slave_sel_r[7:0] + attribute \src "ls180.v:4327.1-4375.4" wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7197.1-7225.4" + attribute \src "ls180.v:7334.1-7362.4" wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7226.1-7254.4" + attribute \src "ls180.v:7363.1-7391.4" wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7078.1-7094.4" + attribute \src "ls180.v:7215.1-7231.4" wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7095.1-7111.4" + attribute \src "ls180.v:7232.1-7248.4" wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7112.1-7128.4" + attribute \src "ls180.v:7249.1-7265.4" wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7129.1-7145.4" + attribute \src "ls180.v:7266.1-7282.4" wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7146.1-7162.4" + attribute \src "ls180.v:7283.1-7299.4" wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7163.1-7179.4" + attribute \src "ls180.v:7300.1-7316.4" wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7180.1-7196.4" + attribute \src "ls180.v:7317.1-7333.4" wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" + wire $0\main_converter0_counter[0:0] + attribute \src "ls180.v:2838.1-2884.4" + wire $0\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2838.1-2884.4" + wire $0\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7564.1-10203.4" + wire width 64 $0\main_converter0_dat_r[63:0] + attribute \src "ls180.v:2838.1-2884.4" + wire $0\main_converter0_skip[0:0] + attribute \src "ls180.v:7564.1-10203.4" + wire $0\main_converter1_counter[0:0] + attribute \src "ls180.v:2898.1-2944.4" + wire $0\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2898.1-2944.4" + wire $0\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7564.1-10203.4" + wire width 64 $0\main_converter1_dat_r[63:0] + attribute \src "ls180.v:2898.1-2944.4" + wire $0\main_converter1_skip[0:0] + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 24 $0\main_dummy[23:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_gpio_oe_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_gpio_out_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_gpio_out_storage[15:0] - attribute \src "ls180.v:7312.1-7330.4" + attribute \src "ls180.v:7449.1-7467.4" wire width 16 $0\main_gpio_status[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7351.1-7353.4" + attribute \src "ls180.v:7488.1-7490.4" wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1554.11-1554.41" + attribute \src "ls180.v:1598.11-1598.41" wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1553.11-1553.41" + attribute \src "ls180.v:1597.11-1597.41" wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:2838.1-2884.4" + wire $0\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:257.5-257.51" + wire $0\main_interface0_converted_interface_err[0:0] + attribute \src "ls180.v:7564.1-10203.4" + wire $0\main_interface0_ram_bus_ack[0:0] + attribute \src "ls180.v:212.5-212.39" + wire $0\main_interface0_ram_bus_err[0:0] + attribute \src "ls180.v:5612.1-5649.4" wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1645.11-1645.41" + attribute \src "ls180.v:1689.11-1689.41" wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1644.11-1644.41" + attribute \src "ls180.v:1688.11-1688.41" wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:5612.1-5649.4" wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1637.12-1637.45" - wire width 32 $0\main_interface1_bus_dat_w[31:0] - attribute \src "ls180.v:5514.1-5551.4" - wire width 4 $0\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:1681.12-1681.45" + wire width 64 $0\main_interface1_bus_dat_w[63:0] + attribute \src "ls180.v:5612.1-5649.4" + wire width 8 $0\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:5612.1-5649.4" wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:5612.1-5649.4" wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:2898.1-2944.4" + wire $0\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:272.5-272.51" + wire $0\main_interface1_converted_interface_err[0:0] + attribute \src "ls180.v:7564.1-10203.4" + wire $0\main_interface1_ram_bus_ack[0:0] + attribute \src "ls180.v:227.5-227.39" + wire $0\main_interface1_ram_bus_err[0:0] + attribute \src "ls180.v:7564.1-10203.4" + wire $0\main_interface2_ram_bus_ack[0:0] + attribute \src "ls180.v:242.5-242.39" + wire $0\main_interface2_ram_bus_err[0:0] + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7427.1-10039.4" - wire $0\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:2786.1-2832.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2786.1-2832.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:2786.1-2832.4" - wire $0\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:7427.1-10039.4" - wire $0\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:2846.1-2892.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2846.1-2892.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:2846.1-2892.4" - wire $0\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:7427.1-10039.4" - wire $0\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:2786.1-2832.4" - wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:167.11-167.69" - wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] - attribute \src "ls180.v:166.11-166.69" - wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:2786.1-2832.4" - wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:2774.1-2784.4" - wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2786.1-2832.4" - wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:2786.1-2832.4" - wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:2786.1-2832.4" - wire $0\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:2846.1-2892.4" - wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:182.11-182.69" - wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] - attribute \src "ls180.v:181.11-181.69" - wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:2846.1-2892.4" - wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:2834.1-2844.4" - wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2846.1-2892.4" - wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:2846.1-2892.4" - wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:2846.1-2892.4" - wire $0\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:2906.1-2952.4" - wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:197.11-197.69" - wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] - attribute \src "ls180.v:196.11-196.69" - wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:2894.1-2904.4" - wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2906.1-2952.4" - wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:2846.1-2892.4" - wire $0\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:74.5-74.46" - wire $0\main_libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:2786.1-2832.4" - wire $0\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:83.5-83.46" - wire $0\main_libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:2767.1-2772.4" + attribute \src "ls180.v:75.11-75.52" + wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] + attribute \src "ls180.v:74.11-74.52" + wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] + attribute \src "ls180.v:86.11-86.52" + wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] + attribute \src "ls180.v:85.11-85.52" + wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] + attribute \src "ls180.v:2819.1-2824.4" wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:114.5-114.49" - wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:115.11-115.55" + wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + attribute \src "ls180.v:114.11-114.55" + wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + attribute \src "ls180.v:2838.1-2884.4" + wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:2838.1-2884.4" + wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:2826.1-2836.4" + wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:2838.1-2884.4" + wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:2838.1-2884.4" + wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:2838.1-2884.4" + wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:2898.1-2944.4" + wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:2898.1-2944.4" + wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:2886.1-2896.4" + wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:2898.1-2944.4" + wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:2898.1-2944.4" + wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:2898.1-2944.4" + wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:213.5-213.40" + attribute \src "ls180.v:170.5-170.40" wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:2955.1-2961.4" - wire width 4 $0\main_libresocsim_we[3:0] - attribute \src "ls180.v:2967.1-2972.4" + attribute \src "ls180.v:3007.1-3017.4" + wire width 8 $0\main_libresocsim_we[7:0] + attribute \src "ls180.v:3023.1-3028.4" wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4027.1-4037.4" + attribute \src "ls180.v:4125.1-4135.4" wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 2 $0\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" + wire width 3 $0\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" + wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:7564.1-10203.4" + wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1578.5-1578.41" + attribute \src "ls180.v:1622.5-1622.41" wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5422.1-5429.4" + attribute \src "ls180.v:5520.1-5527.4" wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5455.1-5494.4" + attribute \src "ls180.v:5553.1-5592.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5455.1-5494.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:5455.1-5494.4" + attribute \src "ls180.v:5553.1-5592.4" + wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:5553.1-5592.4" wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5455.1-5494.4" + attribute \src "ls180.v:5553.1-5592.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5455.1-5494.4" + attribute \src "ls180.v:5553.1-5592.4" wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5455.1-5494.4" + attribute \src "ls180.v:5553.1-5592.4" wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5455.1-5494.4" + attribute \src "ls180.v:5553.1-5592.4" wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1387.5-1387.34" + attribute \src "ls180.v:1431.5-1431.34" wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5110.1-5117.4" + attribute \src "ls180.v:5208.1-5215.4" wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5166.1-5173.4" + attribute \src "ls180.v:5264.1-5271.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5120.1-5127.4" + attribute \src "ls180.v:5218.1-5225.4" wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5176.1-5183.4" + attribute \src "ls180.v:5274.1-5281.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5130.1-5137.4" + attribute \src "ls180.v:5228.1-5235.4" wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5186.1-5193.4" + attribute \src "ls180.v:5284.1-5291.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5140.1-5147.4" + attribute \src "ls180.v:5238.1-5245.4" wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5196.1-5203.4" + attribute \src "ls180.v:5294.1-5301.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5155.1-5162.4" + attribute \src "ls180.v:5253.1-5260.4" wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1493.5-1493.50" + attribute \src "ls180.v:1537.5-1537.50" wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5149.1-5154.4" + attribute \src "ls180.v:5247.1-5252.4" wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5102.1-5107.4" + attribute \src "ls180.v:5200.1-5205.4" wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:4984.1-4991.4" + attribute \src "ls180.v:5082.1-5089.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:4994.1-5001.4" + attribute \src "ls180.v:5092.1-5099.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5004.1-5011.4" + attribute \src "ls180.v:5102.1-5109.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5014.1-5021.4" + attribute \src "ls180.v:5112.1-5119.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1450.5-1450.51" + attribute \src "ls180.v:1494.5-1494.51" wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5022.1-5101.4" + attribute \src "ls180.v:5120.1-5199.4" wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:4962.1-4969.4" + attribute \src "ls180.v:5060.1-5067.4" wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 2 $0\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:5600.1-5616.4" + attribute \src "ls180.v:7564.1-10203.4" + wire width 3 $0\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:5698.1-5726.4" wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7427.1-10039.4" - wire width 32 $0\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:5514.1-5551.4" - wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:7564.1-10203.4" + wire width 64 $0\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:5612.1-5649.4" + wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:5612.1-5649.4" wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5552.1-5588.4" + attribute \src "ls180.v:5650.1-5686.4" wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5552.1-5588.4" + attribute \src "ls180.v:5650.1-5686.4" wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5552.1-5588.4" + attribute \src "ls180.v:5650.1-5686.4" wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5552.1-5588.4" + attribute \src "ls180.v:5650.1-5686.4" wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5552.1-5588.4" + attribute \src "ls180.v:5650.1-5686.4" wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:5612.1-5649.4" wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5552.1-5588.4" + attribute \src "ls180.v:5650.1-5686.4" wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1658.5-1658.45" + attribute \src "ls180.v:1702.5-1702.45" wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:5612.1-5649.4" wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5514.1-5551.4" - wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:5514.1-5551.4" + attribute \src "ls180.v:5612.1-5649.4" + wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:5612.1-5649.4" wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1714.5-1714.41" + attribute \src "ls180.v:1758.5-1758.41" wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5630.1-5637.4" + attribute \src "ls180.v:5740.1-5747.4" wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4368.1-4396.4" + attribute \src "ls180.v:4466.1-4494.4" wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1179.5-1179.53" + attribute \src "ls180.v:1223.5-1223.53" wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1180.5-1180.52" + attribute \src "ls180.v:1224.5-1224.52" wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1160.5-1160.46" + attribute \src "ls180.v:1204.5-1204.46" wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1133.5-1133.49" + attribute \src "ls180.v:1177.5-1177.49" wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1134.5-1134.48" + attribute \src "ls180.v:1178.5-1178.48" wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1135.5-1135.55" + attribute \src "ls180.v:1179.5-1179.55" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1137.5-1137.57" + attribute \src "ls180.v:1181.5-1181.57" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1138.5-1138.58" + attribute \src "ls180.v:1182.5-1182.58" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1140.11-1140.64" + attribute \src "ls180.v:1184.11-1184.64" wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1141.5-1141.59" + attribute \src "ls180.v:1185.5-1185.59" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1146.11-1146.57" + attribute \src "ls180.v:1190.11-1190.57" wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1147.5-1147.52" + attribute \src "ls180.v:1191.5-1191.52" wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4542.1-4635.4" + attribute \src "ls180.v:4640.1-4733.4" wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4432.1-4508.4" + attribute \src "ls180.v:4530.1-4606.4" wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4432.1-4508.4" + attribute \src "ls180.v:4530.1-4606.4" wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4432.1-4508.4" + attribute \src "ls180.v:4530.1-4606.4" wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4432.1-4508.4" + attribute \src "ls180.v:4530.1-4606.4" wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4432.1-4508.4" + attribute \src "ls180.v:4530.1-4606.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4432.1-4508.4" + attribute \src "ls180.v:4530.1-4606.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1123.11-1123.57" + attribute \src "ls180.v:1167.11-1167.57" wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1124.5-1124.52" + attribute \src "ls180.v:1168.5-1168.52" wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4432.1-4508.4" + attribute \src "ls180.v:4530.1-4606.4" wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1335.5-1335.55" + attribute \src "ls180.v:1379.5-1379.55" wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1336.5-1336.54" + attribute \src "ls180.v:1380.5-1380.54" wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1316.5-1316.48" + attribute \src "ls180.v:1360.5-1360.48" wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1287.5-1287.50" + attribute \src "ls180.v:1331.5-1331.50" wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1288.5-1288.49" + attribute \src "ls180.v:1332.5-1332.49" wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1289.5-1289.56" + attribute \src "ls180.v:1333.5-1333.56" wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1291.5-1291.58" + attribute \src "ls180.v:1335.5-1335.58" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1292.5-1292.59" + attribute \src "ls180.v:1336.5-1336.59" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1294.11-1294.65" + attribute \src "ls180.v:1338.11-1338.65" wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1295.5-1295.60" + attribute \src "ls180.v:1339.5-1339.60" wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1298.5-1298.51" + attribute \src "ls180.v:1342.5-1342.51" wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1299.5-1299.52" + attribute \src "ls180.v:1343.5-1343.52" wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1300.11-1300.58" + attribute \src "ls180.v:1344.11-1344.58" wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1301.5-1301.53" + attribute \src "ls180.v:1345.5-1345.53" wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1308.5-1308.41" + attribute \src "ls180.v:1352.5-1352.41" wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4803.1-4904.4" + attribute \src "ls180.v:4901.1-5002.4" wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1257.5-1257.54" + attribute \src "ls180.v:1301.5-1301.54" wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1258.5-1258.53" + attribute \src "ls180.v:1302.5-1302.53" wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1238.5-1238.47" + attribute \src "ls180.v:1282.5-1282.47" wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4669.1-4696.4" + attribute \src "ls180.v:4767.1-4794.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4669.1-4696.4" + attribute \src "ls180.v:4767.1-4794.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4669.1-4696.4" + attribute \src "ls180.v:4767.1-4794.4" wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4669.1-4696.4" + attribute \src "ls180.v:4767.1-4794.4" wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1225.5-1225.50" + attribute \src "ls180.v:1269.5-1269.50" wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1226.5-1226.49" + attribute \src "ls180.v:1270.5-1270.49" wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1227.5-1227.56" + attribute \src "ls180.v:1271.5-1271.56" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1228.5-1228.58" + attribute \src "ls180.v:1272.5-1272.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1229.5-1229.58" + attribute \src "ls180.v:1273.5-1273.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1230.5-1230.59" + attribute \src "ls180.v:1274.5-1274.59" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1231.11-1231.65" + attribute \src "ls180.v:1275.11-1275.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1232.11-1232.65" + attribute \src "ls180.v:1276.11-1276.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1233.5-1233.60" + attribute \src "ls180.v:1277.5-1277.60" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1223.5-1223.50" + attribute \src "ls180.v:1267.5-1267.50" wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1212.5-1212.51" + attribute \src "ls180.v:1256.5-1256.51" wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1213.5-1213.52" + attribute \src "ls180.v:1257.5-1257.52" wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5204.1-5394.4" + attribute \src "ls180.v:5302.1-5492.4" wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4697.1-4769.4" + attribute \src "ls180.v:4795.1-4867.4" wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4669.1-4696.4" + attribute \src "ls180.v:4767.1-4794.4" wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4398.1-4431.4" + attribute \src "ls180.v:4496.1-4529.4" wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4398.1-4431.4" + attribute \src "ls180.v:4496.1-4529.4" wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1105.5-1105.40" + attribute \src "ls180.v:1149.5-1149.40" wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4398.1-4431.4" + attribute \src "ls180.v:4496.1-4529.4" wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4398.1-4431.4" + attribute \src "ls180.v:4496.1-4529.4" wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4398.1-4431.4" + attribute \src "ls180.v:4496.1-4529.4" wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4398.1-4431.4" + attribute \src "ls180.v:4496.1-4529.4" wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4398.1-4431.4" + attribute \src "ls180.v:4496.1-4529.4" wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3184.1-3191.4" + attribute \src "ls180.v:3282.1-3289.4" wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:445.5-445.64" + attribute \src "ls180.v:477.5-477.64" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:428.5-428.67" + attribute \src "ls180.v:460.5-460.67" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:429.5-429.66" + attribute \src "ls180.v:461.5-461.66" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3206.1-3213.4" + attribute \src "ls180.v:3304.1-3311.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3173.1-3180.4" + attribute \src "ls180.v:3271.1-3278.4" wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3871.1-3879.4" + attribute \src "ls180.v:3969.1-3977.4" wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3222.1-3315.4" + attribute \src "ls180.v:3320.1-3413.4" wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:487.32-487.76" + attribute \src "ls180.v:519.32-519.76" wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:485.32-485.75" + attribute \src "ls180.v:517.32-517.75" wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3341.1-3348.4" + attribute \src "ls180.v:3439.1-3446.4" wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:527.5-527.64" + attribute \src "ls180.v:559.5-559.64" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:510.5-510.67" + attribute \src "ls180.v:542.5-542.67" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:511.5-511.66" + attribute \src "ls180.v:543.5-543.66" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3363.1-3370.4" + attribute \src "ls180.v:3461.1-3468.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3330.1-3337.4" + attribute \src "ls180.v:3428.1-3435.4" wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3880.1-3888.4" + attribute \src "ls180.v:3978.1-3986.4" wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3379.1-3472.4" + attribute \src "ls180.v:3477.1-3570.4" wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:569.32-569.76" + attribute \src "ls180.v:601.32-601.76" wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:567.32-567.75" + attribute \src "ls180.v:599.32-599.75" wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3498.1-3505.4" + attribute \src "ls180.v:3596.1-3603.4" wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:609.5-609.64" + attribute \src "ls180.v:641.5-641.64" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:592.5-592.67" + attribute \src "ls180.v:624.5-624.67" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:593.5-593.66" + attribute \src "ls180.v:625.5-625.66" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3520.1-3527.4" + attribute \src "ls180.v:3618.1-3625.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3487.1-3494.4" + attribute \src "ls180.v:3585.1-3592.4" wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3889.1-3897.4" + attribute \src "ls180.v:3987.1-3995.4" wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3536.1-3629.4" + attribute \src "ls180.v:3634.1-3727.4" wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:651.32-651.76" + attribute \src "ls180.v:683.32-683.76" wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:649.32-649.75" + attribute \src "ls180.v:681.32-681.75" wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3655.1-3662.4" + attribute \src "ls180.v:3753.1-3760.4" wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:691.5-691.64" + attribute \src "ls180.v:723.5-723.64" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:674.5-674.67" + attribute \src "ls180.v:706.5-706.67" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:675.5-675.66" + attribute \src "ls180.v:707.5-707.66" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3677.1-3684.4" + attribute \src "ls180.v:3775.1-3782.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3644.1-3651.4" + attribute \src "ls180.v:3742.1-3749.4" wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3898.1-3906.4" + attribute \src "ls180.v:3996.1-4004.4" wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3693.1-3786.4" + attribute \src "ls180.v:3791.1-3884.4" wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:733.32-733.76" + attribute \src "ls180.v:765.32-765.76" wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:731.32-731.75" + attribute \src "ls180.v:763.32-763.75" wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3820.1-3825.4" + attribute \src "ls180.v:3918.1-3923.4" wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3826.1-3831.4" + attribute \src "ls180.v:3924.1-3929.4" wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3832.1-3837.4" + attribute \src "ls180.v:3930.1-3935.4" wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:741.5-741.43" + attribute \src "ls180.v:773.5-773.43" wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3806.1-3812.4" + attribute \src "ls180.v:3904.1-3910.4" wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:739.5-739.48" + attribute \src "ls180.v:771.5-771.48" wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:738.5-738.43" + attribute \src "ls180.v:770.5-770.43" wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:736.5-736.44" + attribute \src "ls180.v:768.5-768.44" wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:737.5-737.45" + attribute \src "ls180.v:769.5-769.45" wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3853.1-3858.4" + attribute \src "ls180.v:3951.1-3956.4" wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3859.1-3864.4" + attribute \src "ls180.v:3957.1-3962.4" wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3865.1-3870.4" + attribute \src "ls180.v:3963.1-3968.4" wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3839.1-3845.4" + attribute \src "ls180.v:3937.1-3943.4" wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3128.1-3158.4" + attribute \src "ls180.v:3226.1-3256.4" wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:389.5-389.42" + attribute \src "ls180.v:421.5-421.42" wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:390.5-390.43" + attribute \src "ls180.v:422.5-422.43" wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3128.1-3158.4" + attribute \src "ls180.v:3226.1-3256.4" wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:325.5-325.38" + attribute \src "ls180.v:357.5-357.38" wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:374.5-374.35" + attribute \src "ls180.v:406.5-406.35" wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4007.1-4020.4" + attribute \src "ls180.v:4105.1-4118.4" wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4007.1-4020.4" + attribute \src "ls180.v:4105.1-4118.4" wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:275.5-275.36" + attribute \src "ls180.v:307.5-307.36" wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3069.1-3085.4" + attribute \src "ls180.v:3167.1-3183.4" wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3069.1-3085.4" + attribute \src "ls180.v:3167.1-3183.4" wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3069.1-3085.4" + attribute \src "ls180.v:3167.1-3183.4" wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3069.1-3085.4" + attribute \src "ls180.v:3167.1-3183.4" wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:772.12-772.36" + attribute \src "ls180.v:804.12-804.36" wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:773.11-773.35" + attribute \src "ls180.v:805.11-805.35" wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3128.1-3158.4" + attribute \src "ls180.v:3226.1-3256.4" wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3011.1-3065.4" + attribute \src "ls180.v:3109.1-3163.4" wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:775.5-775.31" + attribute \src "ls180.v:807.5-807.31" wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:776.5-776.31" + attribute \src "ls180.v:808.5-808.31" wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3911.1-3983.4" + attribute \src "ls180.v:4009.1-4081.4" wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:780.32-780.63" + attribute \src "ls180.v:812.32-812.63" wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:778.32-778.63" + attribute \src "ls180.v:810.32-810.63" wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:2958.1-3004.4" + wire $0\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:859.5-859.54" + wire $0\main_socbushandler_converted_interface_err[0:0] + attribute \src "ls180.v:7564.1-10203.4" + wire $0\main_socbushandler_counter[0:0] + attribute \src "ls180.v:2958.1-3004.4" + wire $0\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:2958.1-3004.4" + wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7564.1-10203.4" + wire width 64 $0\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:2958.1-3004.4" + wire $0\main_socbushandler_skip[0:0] + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:4327.1-4375.4" wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:4327.1-4375.4" wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:4327.1-4375.4" wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:4327.1-4375.4" wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:4327.1-4375.4" wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:4327.1-4375.4" wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:4327.1-4375.4" wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4229.1-4277.4" + attribute \src "ls180.v:4327.1-4375.4" wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:996.12-996.47" + attribute \src "ls180.v:1040.12-1040.47" wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6281.1-6286.4" + attribute \src "ls180.v:6418.1-6423.4" wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4288.1-4336.4" + attribute \src "ls180.v:4386.1-4434.4" wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6327.1-6332.4" + attribute \src "ls180.v:6464.1-6469.4" wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:4147.1-4151.4" + attribute \src "ls180.v:3032.1-3042.4" + wire width 8 $0\main_sram0_we[7:0] + attribute \src "ls180.v:3046.1-3056.4" + wire width 8 $0\main_sram1_we[7:0] + attribute \src "ls180.v:3060.1-3070.4" + wire width 8 $0\main_sram2_we[7:0] + attribute \src "ls180.v:4245.1-4249.4" wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4136.1-4140.4" + attribute \src "ls180.v:4234.1-4238.4" wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:851.5-851.38" + attribute \src "ls180.v:895.5-895.38" wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:852.5-852.37" + attribute \src "ls180.v:896.5-896.37" wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:978.5-978.27" + attribute \src "ls180.v:1022.5-1022.27" wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4141.1-4146.4" + attribute \src "ls180.v:4239.1-4244.4" wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:960.5-960.37" + attribute \src "ls180.v:1004.5-1004.37" wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4199.1-4206.4" + attribute \src "ls180.v:4297.1-4304.4" wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4130.1-4135.4" + attribute \src "ls180.v:4228.1-4233.4" wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:923.5-923.37" + attribute \src "ls180.v:967.5-967.37" wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:906.5-906.40" + attribute \src "ls180.v:950.5-950.40" wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:907.5-907.39" + attribute \src "ls180.v:951.5-951.39" wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4169.1-4176.4" + attribute \src "ls180.v:4267.1-4274.4" wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4039.1-4085.4" + attribute \src "ls180.v:4137.1-4183.4" wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:819.5-819.29" - wire $0\main_wb_sdram_err[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:2958.1-3004.4" + wire width 30 $0\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:2958.1-3004.4" + wire $0\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:2946.1-2956.4" + wire width 32 $0\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:2958.1-3004.4" + wire width 4 $0\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:2958.1-3004.4" + wire $0\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:2958.1-3004.4" + wire $0\main_wb_sdram_we[0:0] + attribute \src "ls180.v:7564.1-10203.4" wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10043.1-10053.4" - wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:10063.1-10067.4" + attribute \src "ls180.v:10207.1-10225.4" + wire width 9 $0\memadr[8:0] + attribute \src "ls180.v:10235.1-10253.4" + wire width 9 $0\memadr_1[8:0] + attribute \src "ls180.v:10263.1-10281.4" + wire width 9 $0\memadr_2[8:0] + attribute \src "ls180.v:10291.1-10309.4" + wire width 9 $0\memadr_3[8:0] + attribute \src "ls180.v:10319.1-10323.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10077.1-10081.4" + attribute \src "ls180.v:10333.1-10337.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10091.1-10095.4" + attribute \src "ls180.v:10347.1-10351.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10105.1-10109.4" + attribute \src "ls180.v:10361.1-10365.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10120.1-10124.4" + attribute \src "ls180.v:10376.1-10380.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10126.1-10129.4" + attribute \src "ls180.v:10382.1-10385.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10137.1-10141.4" + attribute \src "ls180.v:10393.1-10397.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10143.1-10146.4" + attribute \src "ls180.v:10399.1-10402.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10153.1-10157.4" + attribute \src "ls180.v:10409.1-10413.4" wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10167.1-10171.4" + attribute \src "ls180.v:10423.1-10427.4" wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7355.1-7425.4" + attribute \src "ls180.v:7492.1-7562.4" wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7427.1-10039.4" + attribute \src "ls180.v:7564.1-10203.4" wire $0\uart_tx[0:0] - attribute \src "ls180.v:1745.11-1745.49" + attribute \src "ls180.v:1789.11-1789.49" wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1744.11-1744.44" + attribute \src "ls180.v:1788.11-1788.44" wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1747.11-1747.49" + attribute \src "ls180.v:1791.11-1791.49" wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1746.11-1746.44" + attribute \src "ls180.v:1790.11-1790.44" wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1749.11-1749.49" + attribute \src "ls180.v:1793.11-1793.49" wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1748.11-1748.44" + attribute \src "ls180.v:1792.11-1792.44" wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1751.11-1751.49" + attribute \src "ls180.v:1795.11-1795.49" wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1750.11-1750.44" + attribute \src "ls180.v:1794.11-1794.44" wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2596.5-2596.41" + attribute \src "ls180.v:2648.5-2648.41" wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2609.5-2609.42" + attribute \src "ls180.v:2661.5-2661.42" wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2610.5-2610.42" + attribute \src "ls180.v:2662.5-2662.42" wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2614.12-2614.50" + attribute \src "ls180.v:2666.12-2666.50" wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2615.5-2615.42" + attribute \src "ls180.v:2667.5-2667.42" wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2616.5-2616.42" + attribute \src "ls180.v:2668.5-2668.42" wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2617.12-2617.50" + attribute \src "ls180.v:2669.12-2669.50" wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2618.5-2618.42" + attribute \src "ls180.v:2670.5-2670.42" wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2619.5-2619.42" + attribute \src "ls180.v:2671.5-2671.42" wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2620.12-2620.50" + attribute \src "ls180.v:2672.12-2672.50" wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2621.5-2621.42" + attribute \src "ls180.v:2673.5-2673.42" wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2597.12-2597.49" + attribute \src "ls180.v:2649.12-2649.49" wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2622.5-2622.42" + attribute \src "ls180.v:2674.5-2674.42" wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2623.12-2623.50" + attribute \src "ls180.v:2675.12-2675.50" wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2624.5-2624.42" + attribute \src "ls180.v:2676.5-2676.42" wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2625.5-2625.42" + attribute \src "ls180.v:2677.5-2677.42" wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2626.12-2626.50" + attribute \src "ls180.v:2678.12-2678.50" wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2627.12-2627.50" - wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:2628.11-2628.48" - wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:2629.5-2629.42" + attribute \src "ls180.v:2679.12-2679.50" + wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:2680.11-2680.48" + wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:2681.5-2681.42" wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2630.5-2630.42" + attribute \src "ls180.v:2682.5-2682.42" wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2631.5-2631.42" + attribute \src "ls180.v:2683.5-2683.42" wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2598.11-2598.47" + attribute \src "ls180.v:2650.11-2650.47" wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2632.11-2632.48" + attribute \src "ls180.v:2684.11-2684.48" wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2633.11-2633.48" + attribute \src "ls180.v:2685.11-2685.48" wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2599.5-2599.41" + attribute \src "ls180.v:2651.5-2651.41" wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2600.5-2600.41" + attribute \src "ls180.v:2652.5-2652.41" wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2601.5-2601.41" + attribute \src "ls180.v:2653.5-2653.41" wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2605.5-2605.41" + attribute \src "ls180.v:2657.5-2657.41" wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2606.12-2606.49" + attribute \src "ls180.v:2658.12-2658.49" wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2607.11-2607.47" + attribute \src "ls180.v:2659.11-2659.47" wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2608.5-2608.41" + attribute \src "ls180.v:2660.5-2660.41" wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2602.5-2602.39" + attribute \src "ls180.v:2654.5-2654.39" wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2603.5-2603.39" + attribute \src "ls180.v:2655.5-2655.39" wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2604.5-2604.39" + attribute \src "ls180.v:2656.5-2656.39" wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2611.5-2611.39" + attribute \src "ls180.v:2663.5-2663.39" wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2612.5-2612.39" + attribute \src "ls180.v:2664.5-2664.39" wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2613.5-2613.39" + attribute \src "ls180.v:2665.5-2665.39" wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1731.5-1731.41" + attribute \src "ls180.v:1775.5-1775.41" wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1730.5-1730.36" + attribute \src "ls180.v:1774.5-1774.36" wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1735.5-1735.41" + attribute \src "ls180.v:1779.5-1779.41" wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1734.5-1734.36" + attribute \src "ls180.v:1778.5-1778.36" wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1739.5-1739.41" + attribute \src "ls180.v:1783.5-1783.41" wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1738.5-1738.36" + attribute \src "ls180.v:1782.5-1782.36" wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1776.5-1776.40" + attribute \src "ls180.v:1820.5-1820.40" wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1775.5-1775.35" + attribute \src "ls180.v:1819.5-1819.35" wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1896.12-1896.39" + attribute \src "ls180.v:1948.12-1948.39" wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1893.5-1893.25" + attribute \src "ls180.v:1945.5-1945.25" wire $1\builder_error[0:0] - attribute \src "ls180.v:1890.11-1890.31" + attribute \src "ls180.v:1942.11-1942.31" wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:1900.11-1900.51" + attribute \src "ls180.v:1952.11-1952.51" wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2402.11-2402.52" + attribute \src "ls180.v:2454.11-2454.52" wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2435.11-2435.52" + attribute \src "ls180.v:2487.11-2487.52" wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2476.11-2476.52" + attribute \src "ls180.v:2528.11-2528.52" wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2541.11-2541.52" + attribute \src "ls180.v:2593.11-2593.52" wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2566.11-2566.52" + attribute \src "ls180.v:2618.11-2618.52" wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1941.11-1941.51" + attribute \src "ls180.v:1993.11-1993.51" wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1970.11-1970.51" + attribute \src "ls180.v:2022.11-2022.51" wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1983.11-1983.51" + attribute \src "ls180.v:2035.11-2035.51" wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2024.11-2024.51" + attribute \src "ls180.v:2076.11-2076.51" wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2065.11-2065.51" + attribute \src "ls180.v:2117.11-2117.51" wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2130.11-2130.51" + attribute \src "ls180.v:2182.11-2182.51" wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2263.11-2263.51" + attribute \src "ls180.v:2315.11-2315.51" wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2344.11-2344.51" + attribute \src "ls180.v:2396.11-2396.51" wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2361.11-2361.51" + attribute \src "ls180.v:2413.11-2413.51" wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1863.12-1863.43" + attribute \src "ls180.v:1907.12-1907.43" wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2592.12-2592.55" + attribute \src "ls180.v:2644.12-2644.55" wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2593.5-2593.50" + attribute \src "ls180.v:2645.5-2645.50" wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1865.11-1865.43" + attribute \src "ls180.v:1909.11-1909.43" wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2590.11-2590.55" + attribute \src "ls180.v:2642.11-2642.55" wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2591.5-2591.52" + attribute \src "ls180.v:2643.5-2643.52" wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1864.5-1864.34" + attribute \src "ls180.v:1908.5-1908.34" wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2594.5-2594.46" + attribute \src "ls180.v:2646.5-2646.46" wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2595.5-2595.49" + attribute \src "ls180.v:2647.5-2647.49" wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1873.5-1873.44" + attribute \src "ls180.v:1917.5-1917.44" wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1869.12-1869.54" + attribute \src "ls180.v:1913.12-1913.54" wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1753.11-1753.48" + attribute \src "ls180.v:1797.11-1797.48" wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1752.11-1752.43" + attribute \src "ls180.v:1796.11-1796.43" wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2699.32-2699.66" + attribute \src "ls180.v:2751.32-2751.66" wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2700.32-2700.66" + attribute \src "ls180.v:2752.32-2752.66" wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2719.32-2719.67" + attribute \src "ls180.v:2771.32-2771.67" wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2720.32-2720.67" + attribute \src "ls180.v:2772.32-2772.67" wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2721.32-2721.67" + attribute \src "ls180.v:2773.32-2773.67" wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2722.32-2722.67" + attribute \src "ls180.v:2774.32-2774.67" wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2723.32-2723.67" + attribute \src "ls180.v:2775.32-2775.67" wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2724.32-2724.67" + attribute \src "ls180.v:2776.32-2776.67" wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2725.32-2725.67" + attribute \src "ls180.v:2777.32-2777.67" wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2726.32-2726.67" + attribute \src "ls180.v:2778.32-2778.67" wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2727.32-2727.67" + attribute \src "ls180.v:2779.32-2779.67" wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2728.32-2728.67" + attribute \src "ls180.v:2780.32-2780.67" wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2729.32-2729.67" + attribute \src "ls180.v:2781.32-2781.67" wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2730.32-2730.67" + attribute \src "ls180.v:2782.32-2782.67" wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2731.32-2731.67" + attribute \src "ls180.v:2783.32-2783.67" wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2732.32-2732.67" + attribute \src "ls180.v:2784.32-2784.67" wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2701.32-2701.66" + attribute \src "ls180.v:2753.32-2753.66" wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2702.32-2702.66" + attribute \src "ls180.v:2754.32-2754.66" wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2703.32-2703.66" + attribute \src "ls180.v:2755.32-2755.66" wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2704.32-2704.66" + attribute \src "ls180.v:2756.32-2756.66" wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2705.32-2705.66" + attribute \src "ls180.v:2757.32-2757.66" wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2706.32-2706.66" + attribute \src "ls180.v:2758.32-2758.66" wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2707.32-2707.66" + attribute \src "ls180.v:2759.32-2759.66" wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2708.32-2708.66" + attribute \src "ls180.v:2760.32-2760.66" wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2709.32-2709.66" + attribute \src "ls180.v:2761.32-2761.66" wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2710.32-2710.66" + attribute \src "ls180.v:2762.32-2762.66" wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2711.32-2711.66" + attribute \src "ls180.v:2763.32-2763.66" wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2712.32-2712.66" + attribute \src "ls180.v:2764.32-2764.66" wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2713.32-2713.66" + attribute \src "ls180.v:2765.32-2765.66" wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2714.32-2714.66" + attribute \src "ls180.v:2766.32-2766.66" wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2715.32-2715.66" + attribute \src "ls180.v:2767.32-2767.66" wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2716.32-2716.66" + attribute \src "ls180.v:2768.32-2768.66" wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2717.32-2717.66" + attribute \src "ls180.v:2769.32-2769.66" wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2718.32-2718.66" + attribute \src "ls180.v:2770.32-2770.66" wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1771.5-1771.43" + attribute \src "ls180.v:1815.5-1815.43" wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1772.5-1772.43" + attribute \src "ls180.v:1816.5-1816.43" wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1773.5-1773.43" + attribute \src "ls180.v:1817.5-1817.43" wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1774.5-1774.43" + attribute \src "ls180.v:1818.5-1818.43" wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1770.5-1770.42" + attribute \src "ls180.v:1814.5-1814.42" wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2589.11-2589.36" + attribute \src "ls180.v:2641.11-2641.36" wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1743.11-1743.46" + attribute \src "ls180.v:1787.11-1787.46" wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1742.11-1742.41" + attribute \src "ls180.v:1786.11-1786.41" wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1852.11-1852.51" + attribute \src "ls180.v:1896.11-1896.51" wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1851.11-1851.46" + attribute \src "ls180.v:1895.11-1895.46" wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1820.5-1820.57" + attribute \src "ls180.v:1864.5-1864.57" wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1819.5-1819.52" + attribute \src "ls180.v:1863.5-1863.52" wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1832.11-1832.47" + attribute \src "ls180.v:1876.11-1876.47" wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1831.11-1831.42" + attribute \src "ls180.v:1875.11-1875.42" wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1856.5-1856.49" + attribute \src "ls180.v:1900.5-1900.49" wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1855.5-1855.44" + attribute \src "ls180.v:1899.5-1899.44" wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1860.11-1860.65" + attribute \src "ls180.v:1904.11-1904.65" wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1859.11-1859.60" + attribute \src "ls180.v:1903.11-1903.60" wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1808.11-1808.46" + attribute \src "ls180.v:1852.11-1852.46" wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1807.11-1807.41" + attribute \src "ls180.v:1851.11-1851.41" wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1796.11-1796.52" + attribute \src "ls180.v:1840.11-1840.52" wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1795.11-1795.47" + attribute \src "ls180.v:1839.11-1839.47" wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1792.11-1792.52" + attribute \src "ls180.v:1836.11-1836.52" wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1791.11-1791.47" + attribute \src "ls180.v:1835.11-1835.47" wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1804.5-1804.46" + attribute \src "ls180.v:1848.5-1848.46" wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1803.5-1803.41" + attribute \src "ls180.v:1847.5-1847.41" wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1812.11-1812.53" + attribute \src "ls180.v:1856.11-1856.53" wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1811.11-1811.48" + attribute \src "ls180.v:1855.11-1855.48" wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1788.5-1788.46" + attribute \src "ls180.v:1832.5-1832.46" wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1787.5-1787.41" + attribute \src "ls180.v:1831.5-1831.41" wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1884.5-1884.30" + attribute \src "ls180.v:1936.5-1936.30" wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1880.12-1880.40" + attribute \src "ls180.v:1932.12-1932.40" wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1891.11-1891.35" - wire width 5 $1\builder_slave_sel[4:0] - attribute \src "ls180.v:1892.11-1892.37" - wire width 5 $1\builder_slave_sel_r[4:0] - attribute \src "ls180.v:1780.11-1780.47" + attribute \src "ls180.v:1943.11-1943.35" + wire width 8 $1\builder_slave_sel[7:0] + attribute \src "ls180.v:1944.11-1944.37" + wire width 8 $1\builder_slave_sel_r[7:0] + attribute \src "ls180.v:1824.11-1824.47" wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1779.11-1779.42" + attribute \src "ls180.v:1823.11-1823.42" wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1784.11-1784.47" + attribute \src "ls180.v:1828.11-1828.47" wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1783.11-1783.42" + attribute \src "ls180.v:1827.11-1827.42" wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2588.11-2588.31" + attribute \src "ls180.v:2640.11-2640.31" wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2641.5-2641.39" + attribute \src "ls180.v:2693.5-2693.39" wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2642.5-2642.39" + attribute \src "ls180.v:2694.5-2694.39" wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2634.11-2634.47" + attribute \src "ls180.v:2686.11-2686.47" wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2635.12-2635.49" + attribute \src "ls180.v:2687.12-2687.49" wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2636.5-2636.41" + attribute \src "ls180.v:2688.5-2688.41" wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2637.5-2637.41" + attribute \src "ls180.v:2689.5-2689.41" wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2638.5-2638.41" + attribute \src "ls180.v:2690.5-2690.41" wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2639.5-2639.41" + attribute \src "ls180.v:2691.5-2691.41" wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2640.5-2640.41" + attribute \src "ls180.v:2692.5-2692.41" wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:832.5-832.29" + attribute \src "ls180.v:876.5-876.29" wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:829.5-829.34" + attribute \src "ls180.v:259.5-259.35" + wire $1\main_converter0_counter[0:0] + attribute \src "ls180.v:1776.5-1776.57" + wire $1\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1777.5-1777.60" + wire $1\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:261.12-261.41" + wire width 64 $1\main_converter0_dat_r[63:0] + attribute \src "ls180.v:258.5-258.32" + wire $1\main_converter0_skip[0:0] + attribute \src "ls180.v:274.5-274.35" + wire $1\main_converter1_counter[0:0] + attribute \src "ls180.v:1780.5-1780.57" + wire $1\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1781.5-1781.60" + wire $1\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:276.12-276.41" + wire width 64 $1\main_converter1_dat_r[63:0] + attribute \src "ls180.v:273.5-273.32" + wire $1\main_converter1_skip[0:0] + attribute \src "ls180.v:873.5-873.34" wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1777.5-1777.55" + attribute \src "ls180.v:1821.5-1821.55" wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1778.5-1778.58" + attribute \src "ls180.v:1822.5-1822.58" wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:831.12-831.40" + attribute \src "ls180.v:875.12-875.40" wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:828.5-828.31" + attribute \src "ls180.v:872.5-872.31" wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:263.12-263.38" + attribute \src "ls180.v:295.12-295.38" wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:264.5-264.36" + attribute \src "ls180.v:296.5-296.36" wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1063.12-1063.30" + attribute \src "ls180.v:1107.12-1107.30" wire width 24 $1\main_dummy[23:0] - attribute \src "ls180.v:980.5-980.27" + attribute \src "ls180.v:1024.5-1024.27" wire $1\main_gpio_oe_re[0:0] - attribute \src "ls180.v:979.12-979.40" + attribute \src "ls180.v:1023.12-1023.40" wire width 16 $1\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:984.5-984.28" + attribute \src "ls180.v:1028.5-1028.28" wire $1\main_gpio_out_re[0:0] - attribute \src "ls180.v:983.12-983.41" + attribute \src "ls180.v:1027.12-1027.41" wire width 16 $1\main_gpio_out_storage[15:0] - attribute \src "ls180.v:981.12-981.36" + attribute \src "ls180.v:1025.12-1025.36" wire width 16 $1\main_gpio_status[15:0] - attribute \src "ls180.v:1088.5-1088.23" + attribute \src "ls180.v:1132.5-1132.23" wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1087.11-1087.34" + attribute \src "ls180.v:1131.11-1131.34" wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:248.5-248.24" + attribute \src "ls180.v:280.5-280.24" wire $1\main_int_rst[0:0] - attribute \src "ls180.v:1636.12-1636.43" + attribute \src "ls180.v:253.5-253.51" + wire $1\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:208.5-208.39" + wire $1\main_interface0_ram_bus_ack[0:0] + attribute \src "ls180.v:1680.12-1680.43" wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1640.5-1640.35" + attribute \src "ls180.v:1684.5-1684.35" wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1639.11-1639.41" - wire width 4 $1\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:1641.5-1641.35" + attribute \src "ls180.v:1683.11-1683.41" + wire width 8 $1\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:1685.5-1685.35" wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1643.5-1643.34" + attribute \src "ls180.v:1687.5-1687.34" wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:268.5-268.51" + wire $1\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:223.5-223.39" + wire $1\main_interface1_ram_bus_ack[0:0] + attribute \src "ls180.v:238.5-238.39" + wire $1\main_interface2_ram_bus_ack[0:0] attribute \src "ls180.v:63.12-63.47" wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:170.5-170.47" - wire $1\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1732.5-1732.69" - wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1733.5-1733.72" - wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:172.12-172.53" - wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:169.5-169.44" - wire $1\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:185.5-185.47" - wire $1\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1736.5-1736.69" - wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1737.5-1737.72" - wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:187.12-187.53" - wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:184.5-184.44" - wire $1\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:200.5-200.47" - wire $1\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1740.5-1740.69" - wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1741.5-1741.72" - wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:202.12-202.53" - wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:199.5-199.44" - wire $1\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:223.5-223.34" + attribute \src "ls180.v:180.5-180.34" wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:222.5-222.39" + attribute \src "ls180.v:179.5-179.39" wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:243.5-243.44" + attribute \src "ls180.v:200.5-200.44" wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:242.5-242.49" + attribute \src "ls180.v:199.5-199.49" wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:158.12-158.71" - wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:162.5-162.63" - wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:159.12-159.73" - wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:161.11-161.69" - wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:163.5-163.63" - wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:165.5-165.62" - wire $1\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:173.12-173.71" - wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:177.5-177.63" - wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:174.12-174.73" - wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:176.11-176.69" - wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:178.5-178.63" - wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:180.5-180.62" - wire $1\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:188.12-188.71" - wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:192.5-192.63" - wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:189.12-189.73" - wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:191.11-191.69" - wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:193.5-193.63" - wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:195.5-195.62" - wire $1\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:72.5-72.46" - wire $1\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:81.5-81.46" - wire $1\main_libresocsim_libresoc_ibus_ack[0:0] attribute \src "ls180.v:65.12-65.55" wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:112.5-112.49" - wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:219.5-219.36" + attribute \src "ls180.v:88.12-88.58" + wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:92.5-92.50" + wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:89.12-89.60" + wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:91.11-91.56" + wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:93.5-93.50" + wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:95.5-95.49" + wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:97.12-97.58" + wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:101.5-101.50" + wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:98.12-98.60" + wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:100.11-100.56" + wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:102.5-102.50" + wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:104.5-104.49" + wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:176.5-176.36" wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:218.12-218.49" + attribute \src "ls180.v:175.12-175.49" wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:209.5-209.40" + attribute \src "ls180.v:166.5-166.40" wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:221.5-221.38" + attribute \src "ls180.v:178.5-178.38" wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:220.12-220.51" + attribute \src "ls180.v:177.12-177.51" wire width 32 $1\main_libresocsim_reload_storage[31:0] attribute \src "ls180.v:56.5-56.37" wire $1\main_libresocsim_reset_re[0:0] @@ -223211,8148 +223399,8590 @@ module \ls180 wire $1\main_libresocsim_scratch_re[0:0] attribute \src "ls180.v:57.12-57.60" wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:225.5-225.44" + attribute \src "ls180.v:182.5-182.44" wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:224.5-224.49" + attribute \src "ls180.v:181.5-181.49" wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:244.12-244.42" + attribute \src "ls180.v:201.12-201.42" wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:226.12-226.49" + attribute \src "ls180.v:183.12-183.49" wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:216.11-216.37" - wire width 4 $1\main_libresocsim_we[3:0] - attribute \src "ls180.v:232.5-232.39" + attribute \src "ls180.v:173.11-173.37" + wire width 8 $1\main_libresocsim_we[7:0] + attribute \src "ls180.v:189.5-189.39" wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:233.5-233.45" + attribute \src "ls180.v:190.5-190.45" wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:230.5-230.41" + attribute \src "ls180.v:187.5-187.41" wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:820.12-820.40" + attribute \src "ls180.v:864.12-864.40" wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:824.5-824.32" + attribute \src "ls180.v:868.5-868.32" wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:821.12-821.42" + attribute \src "ls180.v:865.12-865.42" wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:823.11-823.38" + attribute \src "ls180.v:867.11-867.38" wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:825.5-825.32" + attribute \src "ls180.v:869.5-869.32" wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:827.5-827.31" + attribute \src "ls180.v:871.5-871.31" wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1067.12-1067.37" + attribute \src "ls180.v:1111.12-1111.37" wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1069.5-1069.31" + attribute \src "ls180.v:1113.5-1113.31" wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1068.5-1068.36" + attribute \src "ls180.v:1112.5-1112.36" wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1073.5-1073.31" + attribute \src "ls180.v:1117.5-1117.31" wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1072.12-1072.44" + attribute \src "ls180.v:1116.12-1116.44" wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1071.5-1071.30" + attribute \src "ls180.v:1115.5-1115.30" wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1070.12-1070.43" + attribute \src "ls180.v:1114.12-1114.43" wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1077.12-1077.37" + attribute \src "ls180.v:1121.12-1121.37" wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1079.5-1079.31" + attribute \src "ls180.v:1123.5-1123.31" wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1078.5-1078.36" + attribute \src "ls180.v:1122.5-1122.36" wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1083.5-1083.31" + attribute \src "ls180.v:1127.5-1127.31" wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1082.12-1082.44" + attribute \src "ls180.v:1126.12-1126.44" wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1081.5-1081.30" + attribute \src "ls180.v:1125.5-1125.30" wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1080.12-1080.43" + attribute \src "ls180.v:1124.12-1124.43" wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:265.11-265.32" + attribute \src "ls180.v:297.11-297.32" wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1605.11-1605.50" - wire width 2 $1\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:1601.5-1601.51" + attribute \src "ls180.v:1649.11-1649.50" + wire width 3 $1\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:1645.5-1645.51" wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1602.5-1602.50" + attribute \src "ls180.v:1646.5-1646.50" wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1603.12-1603.66" - wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:1604.11-1604.77" - wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:1607.5-1607.49" + attribute \src "ls180.v:1647.12-1647.66" + wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:1648.11-1648.77" + wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1651.5-1651.49" wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1580.11-1580.47" + attribute \src "ls180.v:1624.11-1624.47" wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1577.11-1577.45" + attribute \src "ls180.v:1621.11-1621.45" wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1579.11-1579.47" + attribute \src "ls180.v:1623.11-1623.47" wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1581.11-1581.50" + attribute \src "ls180.v:1625.11-1625.50" wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1615.12-1615.62" + attribute \src "ls180.v:1659.12-1659.62" wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1616.12-1616.60" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:1613.5-1613.45" + attribute \src "ls180.v:1660.12-1660.60" + wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:1657.5-1657.45" wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1623.5-1623.54" + attribute \src "ls180.v:1667.5-1667.54" wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1622.12-1622.67" + attribute \src "ls180.v:1666.12-1666.67" wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1627.5-1627.56" + attribute \src "ls180.v:1671.5-1671.56" wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1626.5-1626.61" + attribute \src "ls180.v:1670.5-1670.61" wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1625.5-1625.56" + attribute \src "ls180.v:1669.5-1669.56" wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1624.12-1624.69" + attribute \src "ls180.v:1668.12-1668.69" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1631.5-1631.54" + attribute \src "ls180.v:1675.5-1675.54" wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1630.5-1630.59" + attribute \src "ls180.v:1674.5-1674.59" wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1633.12-1633.61" + attribute \src "ls180.v:1677.12-1677.61" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1853.12-1853.87" + attribute \src "ls180.v:1897.12-1897.87" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1854.5-1854.82" + attribute \src "ls180.v:1898.5-1898.82" wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1618.5-1618.57" + attribute \src "ls180.v:1662.5-1662.57" wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1628.5-1628.53" + attribute \src "ls180.v:1672.5-1672.53" wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1397.5-1397.38" + attribute \src "ls180.v:1441.5-1441.38" wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1396.12-1396.51" + attribute \src "ls180.v:1440.12-1440.51" wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1395.5-1395.39" + attribute \src "ls180.v:1439.5-1439.39" wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1394.11-1394.51" + attribute \src "ls180.v:1438.11-1438.51" wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1381.5-1381.39" + attribute \src "ls180.v:1425.5-1425.39" wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1380.12-1380.52" + attribute \src "ls180.v:1424.12-1424.52" wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1383.5-1383.38" + attribute \src "ls180.v:1427.5-1427.38" wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1382.12-1382.51" + attribute \src "ls180.v:1426.12-1426.51" wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1536.11-1536.39" + attribute \src "ls180.v:1580.11-1580.39" wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1837.11-1837.62" + attribute \src "ls180.v:1881.11-1881.62" wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1838.5-1838.59" + attribute \src "ls180.v:1882.5-1882.59" wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1537.5-1537.32" + attribute \src "ls180.v:1581.5-1581.32" wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1833.5-1833.55" + attribute \src "ls180.v:1877.5-1877.55" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1834.5-1834.58" + attribute \src "ls180.v:1878.5-1878.58" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1538.5-1538.33" + attribute \src "ls180.v:1582.5-1582.33" wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1841.5-1841.56" + attribute \src "ls180.v:1885.5-1885.56" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1842.5-1842.59" + attribute \src "ls180.v:1886.5-1886.59" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1388.13-1388.53" + attribute \src "ls180.v:1432.13-1432.53" wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1849.13-1849.76" + attribute \src "ls180.v:1893.13-1893.76" wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1850.5-1850.69" + attribute \src "ls180.v:1894.5-1894.69" wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1539.5-1539.35" + attribute \src "ls180.v:1583.5-1583.35" wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1843.5-1843.58" + attribute \src "ls180.v:1887.5-1887.58" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1844.5-1844.61" + attribute \src "ls180.v:1888.5-1888.61" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1497.11-1497.47" + attribute \src "ls180.v:1541.11-1541.47" wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1503.5-1503.46" + attribute \src "ls180.v:1547.5-1547.46" wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1502.12-1502.54" + attribute \src "ls180.v:1546.12-1546.54" wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1498.12-1498.58" + attribute \src "ls180.v:1542.12-1542.58" wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1510.5-1510.46" + attribute \src "ls180.v:1554.5-1554.46" wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1509.12-1509.54" + attribute \src "ls180.v:1553.12-1553.54" wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1505.12-1505.58" + attribute \src "ls180.v:1549.12-1549.58" wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1517.5-1517.46" + attribute \src "ls180.v:1561.5-1561.46" wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1516.12-1516.54" + attribute \src "ls180.v:1560.12-1560.54" wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1512.12-1512.58" + attribute \src "ls180.v:1556.12-1556.58" wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1524.5-1524.46" + attribute \src "ls180.v:1568.5-1568.46" wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1523.12-1523.54" + attribute \src "ls180.v:1567.12-1567.54" wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1519.12-1519.58" + attribute \src "ls180.v:1563.12-1563.58" wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1526.12-1526.53" + attribute \src "ls180.v:1570.12-1570.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1527.12-1527.53" + attribute \src "ls180.v:1571.12-1571.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1528.12-1528.53" + attribute \src "ls180.v:1572.12-1572.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1529.12-1529.53" + attribute \src "ls180.v:1573.12-1573.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1531.12-1531.51" + attribute \src "ls180.v:1575.12-1575.51" wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1532.12-1532.51" + attribute \src "ls180.v:1576.12-1576.51" wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1533.12-1533.51" + attribute \src "ls180.v:1577.12-1577.51" wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1534.12-1534.51" + attribute \src "ls180.v:1578.12-1578.51" wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1488.5-1488.48" + attribute \src "ls180.v:1532.5-1532.48" wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1489.5-1489.47" + attribute \src "ls180.v:1533.5-1533.47" wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1490.11-1490.61" + attribute \src "ls180.v:1534.11-1534.61" wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1487.5-1487.48" + attribute \src "ls180.v:1531.5-1531.48" wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1486.5-1486.48" + attribute \src "ls180.v:1530.5-1530.48" wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1491.5-1491.50" + attribute \src "ls180.v:1535.5-1535.50" wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1496.11-1496.47" + attribute \src "ls180.v:1540.11-1540.47" wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1530.5-1530.43" + attribute \src "ls180.v:1574.5-1574.43" wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1453.11-1453.48" + attribute \src "ls180.v:1497.11-1497.48" wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1829.11-1829.87" + attribute \src "ls180.v:1873.11-1873.87" wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1830.5-1830.84" + attribute \src "ls180.v:1874.5-1874.84" wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1458.12-1458.55" + attribute \src "ls180.v:1502.12-1502.55" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1454.12-1454.59" + attribute \src "ls180.v:1498.12-1498.59" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1465.12-1465.55" + attribute \src "ls180.v:1509.12-1509.55" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1461.12-1461.59" + attribute \src "ls180.v:1505.12-1505.59" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1472.12-1472.55" + attribute \src "ls180.v:1516.12-1516.55" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1468.12-1468.59" + attribute \src "ls180.v:1512.12-1512.59" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1479.12-1479.55" + attribute \src "ls180.v:1523.12-1523.55" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1475.12-1475.59" + attribute \src "ls180.v:1519.12-1519.59" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1482.12-1482.54" + attribute \src "ls180.v:1526.12-1526.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1821.12-1821.93" + attribute \src "ls180.v:1865.12-1865.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1822.5-1822.88" + attribute \src "ls180.v:1866.5-1866.88" wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1483.12-1483.54" + attribute \src "ls180.v:1527.12-1527.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1823.12-1823.93" + attribute \src "ls180.v:1867.12-1867.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1824.5-1824.88" + attribute \src "ls180.v:1868.5-1868.88" wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1484.12-1484.54" + attribute \src "ls180.v:1528.12-1528.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1825.12-1825.93" + attribute \src "ls180.v:1869.12-1869.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1826.5-1826.88" + attribute \src "ls180.v:1870.5-1870.88" wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1485.12-1485.54" + attribute \src "ls180.v:1529.12-1529.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1827.12-1827.93" + attribute \src "ls180.v:1871.12-1871.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1828.5-1828.88" + attribute \src "ls180.v:1872.5-1872.88" wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1444.5-1444.49" + attribute \src "ls180.v:1488.5-1488.49" wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1451.5-1451.50" + attribute \src "ls180.v:1495.5-1495.50" wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1452.11-1452.64" + attribute \src "ls180.v:1496.11-1496.64" wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1449.5-1449.51" + attribute \src "ls180.v:1493.5-1493.51" wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1448.5-1448.51" + attribute \src "ls180.v:1492.5-1492.51" wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1440.11-1440.47" + attribute \src "ls180.v:1484.11-1484.47" wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1398.11-1398.51" + attribute \src "ls180.v:1442.11-1442.51" wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1541.12-1541.42" + attribute \src "ls180.v:1585.12-1585.42" wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1839.12-1839.65" + attribute \src "ls180.v:1883.12-1883.65" wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1840.5-1840.60" + attribute \src "ls180.v:1884.5-1884.60" wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1542.5-1542.33" + attribute \src "ls180.v:1586.5-1586.33" wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1835.5-1835.56" + attribute \src "ls180.v:1879.5-1879.56" wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1836.5-1836.59" + attribute \src "ls180.v:1880.5-1880.59" wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1543.5-1543.34" + attribute \src "ls180.v:1587.5-1587.34" wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1845.5-1845.57" + attribute \src "ls180.v:1889.5-1889.57" wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1846.5-1846.60" + attribute \src "ls180.v:1890.5-1890.60" wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1544.5-1544.36" + attribute \src "ls180.v:1588.5-1588.36" wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1847.5-1847.59" + attribute \src "ls180.v:1891.5-1891.59" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1848.5-1848.62" + attribute \src "ls180.v:1892.5-1892.62" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1689.11-1689.48" - wire width 2 $1\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:1687.11-1687.64" + attribute \src "ls180.v:1733.11-1733.48" + wire width 3 $1\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:1731.11-1731.64" wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1663.5-1663.40" + attribute \src "ls180.v:1707.5-1707.40" wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1662.12-1662.53" + attribute \src "ls180.v:1706.12-1706.53" wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1661.12-1661.45" - wire width 32 $1\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:1857.12-1857.75" - wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:1858.5-1858.70" + attribute \src "ls180.v:1705.12-1705.45" + wire width 64 $1\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:1901.12-1901.75" + wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:1902.5-1902.70" wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1668.5-1668.44" + attribute \src "ls180.v:1712.5-1712.44" wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1667.5-1667.42" + attribute \src "ls180.v:1711.5-1711.42" wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1666.5-1666.47" + attribute \src "ls180.v:1710.5-1710.47" wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1665.5-1665.42" + attribute \src "ls180.v:1709.5-1709.42" wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1664.12-1664.55" + attribute \src "ls180.v:1708.12-1708.55" wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1671.5-1671.40" + attribute \src "ls180.v:1715.5-1715.40" wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1670.5-1670.45" + attribute \src "ls180.v:1714.5-1714.45" wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1675.12-1675.47" + attribute \src "ls180.v:1719.12-1719.47" wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1861.12-1861.87" + attribute \src "ls180.v:1905.12-1905.87" wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1862.5-1862.82" + attribute \src "ls180.v:1906.5-1906.82" wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1654.5-1654.42" + attribute \src "ls180.v:1698.5-1698.42" wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1655.12-1655.61" + attribute \src "ls180.v:1699.12-1699.61" wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1653.5-1653.43" + attribute \src "ls180.v:1697.5-1697.43" wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1652.5-1652.43" + attribute \src "ls180.v:1696.5-1696.43" wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1659.5-1659.44" + attribute \src "ls180.v:1703.5-1703.44" wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1660.12-1660.60" - wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:1656.5-1656.45" + attribute \src "ls180.v:1704.12-1704.60" + wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:1700.5-1700.45" wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1716.11-1716.47" + attribute \src "ls180.v:1760.11-1760.47" wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1713.11-1713.45" + attribute \src "ls180.v:1757.11-1757.45" wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1715.11-1715.47" + attribute \src "ls180.v:1759.11-1759.47" wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1717.11-1717.50" + attribute \src "ls180.v:1761.11-1761.50" wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1097.5-1097.35" + attribute \src "ls180.v:1141.5-1141.35" wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1100.5-1100.35" + attribute \src "ls180.v:1144.5-1144.35" wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1101.5-1101.36" + attribute \src "ls180.v:1145.5-1145.36" wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1099.11-1099.41" + attribute \src "ls180.v:1143.11-1143.41" wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1095.5-1095.33" + attribute \src "ls180.v:1139.5-1139.33" wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1094.11-1094.46" + attribute \src "ls180.v:1138.11-1138.46" wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1203.5-1203.49" + attribute \src "ls180.v:1247.5-1247.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1204.5-1204.48" + attribute \src "ls180.v:1248.5-1248.48" wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1205.11-1205.62" + attribute \src "ls180.v:1249.11-1249.62" wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1201.5-1201.49" + attribute \src "ls180.v:1245.5-1245.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1188.11-1188.54" + attribute \src "ls180.v:1232.11-1232.54" wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1184.5-1184.55" + attribute \src "ls180.v:1228.5-1228.55" wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1185.5-1185.54" + attribute \src "ls180.v:1229.5-1229.54" wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1186.11-1186.68" + attribute \src "ls180.v:1230.11-1230.68" wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1187.11-1187.81" + attribute \src "ls180.v:1231.11-1231.81" wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1190.5-1190.53" + attribute \src "ls180.v:1234.5-1234.53" wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1206.5-1206.38" + attribute \src "ls180.v:1250.5-1250.38" wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1801.5-1801.66" + attribute \src "ls180.v:1845.5-1845.66" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1802.5-1802.69" + attribute \src "ls180.v:1846.5-1846.69" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1176.5-1176.36" + attribute \src "ls180.v:1220.5-1220.36" wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1171.5-1171.53" + attribute \src "ls180.v:1215.5-1215.53" wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1158.11-1158.39" + attribute \src "ls180.v:1202.11-1202.39" wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1797.11-1797.67" + attribute \src "ls180.v:1841.11-1841.67" wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1798.5-1798.64" + attribute \src "ls180.v:1842.5-1842.64" wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1143.5-1143.48" + attribute \src "ls180.v:1187.5-1187.48" wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1144.5-1144.50" + attribute \src "ls180.v:1188.5-1188.50" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1145.5-1145.51" + attribute \src "ls180.v:1189.5-1189.51" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1150.5-1150.37" + attribute \src "ls180.v:1194.5-1194.37" wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1151.11-1151.53" + attribute \src "ls180.v:1195.11-1195.53" wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1149.5-1149.38" + attribute \src "ls180.v:1193.5-1193.38" wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1148.5-1148.38" + attribute \src "ls180.v:1192.5-1192.38" wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1154.5-1154.39" + attribute \src "ls180.v:1198.5-1198.39" wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1155.11-1155.53" + attribute \src "ls180.v:1199.11-1199.53" wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1156.11-1156.55" + attribute \src "ls180.v:1200.11-1200.55" wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1153.5-1153.40" + attribute \src "ls180.v:1197.5-1197.40" wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1152.5-1152.40" + attribute \src "ls180.v:1196.5-1196.40" wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1157.12-1157.48" + attribute \src "ls180.v:1201.12-1201.48" wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1799.12-1799.71" + attribute \src "ls180.v:1843.12-1843.71" wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1800.5-1800.66" + attribute \src "ls180.v:1844.5-1844.66" wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1130.11-1130.39" + attribute \src "ls180.v:1174.11-1174.39" wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1793.11-1793.66" + attribute \src "ls180.v:1837.11-1837.66" wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1794.5-1794.63" + attribute \src "ls180.v:1838.5-1838.63" wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1129.5-1129.32" + attribute \src "ls180.v:1173.5-1173.32" wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1120.5-1120.48" + attribute \src "ls180.v:1164.5-1164.48" wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1121.5-1121.50" + attribute \src "ls180.v:1165.5-1165.50" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1122.5-1122.51" + attribute \src "ls180.v:1166.5-1166.51" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1127.5-1127.37" + attribute \src "ls180.v:1171.5-1171.37" wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1128.11-1128.51" + attribute \src "ls180.v:1172.11-1172.51" wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1126.5-1126.38" + attribute \src "ls180.v:1170.5-1170.38" wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1125.5-1125.38" + attribute \src "ls180.v:1169.5-1169.38" wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1314.11-1314.41" + attribute \src "ls180.v:1358.11-1358.41" wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1813.11-1813.70" + attribute \src "ls180.v:1857.11-1857.70" wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1814.5-1814.66" + attribute \src "ls180.v:1858.5-1858.66" wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1359.5-1359.51" + attribute \src "ls180.v:1403.5-1403.51" wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1360.5-1360.50" + attribute \src "ls180.v:1404.5-1404.50" wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1361.11-1361.64" + attribute \src "ls180.v:1405.11-1405.64" wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1357.5-1357.51" + attribute \src "ls180.v:1401.5-1401.51" wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1344.5-1344.50" + attribute \src "ls180.v:1388.5-1388.50" wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1340.5-1340.57" + attribute \src "ls180.v:1384.5-1384.57" wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1341.5-1341.56" + attribute \src "ls180.v:1385.5-1385.56" wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1342.11-1342.70" + attribute \src "ls180.v:1386.11-1386.70" wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1343.11-1343.83" + attribute \src "ls180.v:1387.11-1387.83" wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1346.5-1346.55" + attribute \src "ls180.v:1390.5-1390.55" wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1362.5-1362.40" + attribute \src "ls180.v:1406.5-1406.40" wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1817.5-1817.69" + attribute \src "ls180.v:1861.5-1861.69" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1818.5-1818.72" + attribute \src "ls180.v:1862.5-1862.72" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1332.5-1332.38" + attribute \src "ls180.v:1376.5-1376.38" wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1327.5-1327.55" + attribute \src "ls180.v:1371.5-1371.55" wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1297.5-1297.49" + attribute \src "ls180.v:1341.5-1341.49" wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1304.5-1304.38" + attribute \src "ls180.v:1348.5-1348.38" wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1305.11-1305.61" + attribute \src "ls180.v:1349.11-1349.61" wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1303.5-1303.39" + attribute \src "ls180.v:1347.5-1347.39" wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1302.5-1302.39" + attribute \src "ls180.v:1346.5-1346.39" wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1309.5-1309.40" + attribute \src "ls180.v:1353.5-1353.40" wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1310.11-1310.54" + attribute \src "ls180.v:1354.11-1354.54" wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1311.11-1311.56" + attribute \src "ls180.v:1355.11-1355.56" wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1307.5-1307.41" + attribute \src "ls180.v:1351.5-1351.41" wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1306.5-1306.41" + attribute \src "ls180.v:1350.5-1350.41" wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1312.5-1312.33" + attribute \src "ls180.v:1356.5-1356.33" wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1313.12-1313.49" + attribute \src "ls180.v:1357.12-1357.49" wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1815.12-1815.73" + attribute \src "ls180.v:1859.12-1859.73" wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1816.5-1816.68" + attribute \src "ls180.v:1860.5-1860.68" wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1222.11-1222.40" + attribute \src "ls180.v:1266.11-1266.40" wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1809.11-1809.61" + attribute \src "ls180.v:1853.11-1853.61" wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1810.5-1810.58" + attribute \src "ls180.v:1854.5-1854.58" wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1281.5-1281.50" + attribute \src "ls180.v:1325.5-1325.50" wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1282.5-1282.49" + attribute \src "ls180.v:1326.5-1326.49" wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1283.11-1283.63" + attribute \src "ls180.v:1327.11-1327.63" wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1279.5-1279.50" + attribute \src "ls180.v:1323.5-1323.50" wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1266.11-1266.55" + attribute \src "ls180.v:1310.11-1310.55" wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1262.5-1262.56" + attribute \src "ls180.v:1306.5-1306.56" wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1263.5-1263.55" + attribute \src "ls180.v:1307.5-1307.55" wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1264.11-1264.69" + attribute \src "ls180.v:1308.11-1308.69" wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1265.11-1265.82" + attribute \src "ls180.v:1309.11-1309.82" wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1268.5-1268.54" + attribute \src "ls180.v:1312.5-1312.54" wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1284.5-1284.39" + attribute \src "ls180.v:1328.5-1328.39" wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1805.5-1805.66" + attribute \src "ls180.v:1849.5-1849.66" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1806.5-1806.69" + attribute \src "ls180.v:1850.5-1850.69" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1254.5-1254.37" + attribute \src "ls180.v:1298.5-1298.37" wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1249.5-1249.54" + attribute \src "ls180.v:1293.5-1293.54" wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1236.5-1236.34" + attribute \src "ls180.v:1280.5-1280.34" wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1211.5-1211.49" + attribute \src "ls180.v:1255.5-1255.49" wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1214.11-1214.58" + attribute \src "ls180.v:1258.11-1258.58" wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1215.5-1215.53" + attribute \src "ls180.v:1259.5-1259.53" wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1218.5-1218.39" + attribute \src "ls180.v:1262.5-1262.39" wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1219.5-1219.38" + attribute \src "ls180.v:1263.5-1263.38" wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1220.11-1220.52" + attribute \src "ls180.v:1264.11-1264.52" wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1217.5-1217.39" + attribute \src "ls180.v:1261.5-1261.39" wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1216.5-1216.39" + attribute \src "ls180.v:1260.5-1260.39" wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1234.5-1234.34" + attribute \src "ls180.v:1278.5-1278.34" wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1221.5-1221.33" + attribute \src "ls180.v:1265.5-1265.33" wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1235.5-1235.34" + attribute \src "ls180.v:1279.5-1279.34" wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1115.11-1115.39" + attribute \src "ls180.v:1159.11-1159.39" wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1789.11-1789.66" + attribute \src "ls180.v:1833.11-1833.66" wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1790.5-1790.63" + attribute \src "ls180.v:1834.5-1834.63" wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1110.5-1110.48" + attribute \src "ls180.v:1154.5-1154.48" wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1111.5-1111.50" + attribute \src "ls180.v:1155.5-1155.50" wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1112.5-1112.51" + attribute \src "ls180.v:1156.5-1156.51" wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1113.11-1113.57" + attribute \src "ls180.v:1157.11-1157.57" wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1114.5-1114.52" + attribute \src "ls180.v:1158.5-1158.52" wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1364.5-1364.35" + attribute \src "ls180.v:1408.5-1408.35" wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1367.11-1367.42" + attribute \src "ls180.v:1411.11-1411.42" wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:327.5-327.33" + attribute \src "ls180.v:359.5-359.33" wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:326.12-326.46" + attribute \src "ls180.v:358.12-358.46" wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:329.5-329.34" + attribute \src "ls180.v:361.5-361.34" wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:328.11-328.45" + attribute \src "ls180.v:360.11-360.45" wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:425.5-425.50" + attribute \src "ls180.v:457.5-457.50" wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:447.11-447.70" + attribute \src "ls180.v:479.11-479.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:444.11-444.68" + attribute \src "ls180.v:476.11-476.68" wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:446.11-446.70" + attribute \src "ls180.v:478.11-478.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:448.11-448.73" + attribute \src "ls180.v:480.11-480.73" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:471.5-471.59" + attribute \src "ls180.v:503.5-503.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:472.5-472.58" + attribute \src "ls180.v:504.5-504.58" wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:474.12-474.74" + attribute \src "ls180.v:506.12-506.74" wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:473.5-473.64" + attribute \src "ls180.v:505.5-505.64" wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:469.5-469.59" + attribute \src "ls180.v:501.5-501.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:417.12-417.57" + attribute \src "ls180.v:449.12-449.57" wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:419.5-419.51" + attribute \src "ls180.v:451.5-451.51" wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:422.5-422.54" + attribute \src "ls180.v:454.5-454.54" wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:423.5-423.55" + attribute \src "ls180.v:455.5-455.55" wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:424.5-424.56" + attribute \src "ls180.v:456.5-456.56" wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:420.5-420.51" + attribute \src "ls180.v:452.5-452.51" wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:421.5-421.50" + attribute \src "ls180.v:453.5-453.50" wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:416.5-416.45" + attribute \src "ls180.v:448.5-448.45" wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:415.5-415.45" + attribute \src "ls180.v:447.5-447.45" wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:414.5-414.47" + attribute \src "ls180.v:446.5-446.47" wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:412.5-412.51" + attribute \src "ls180.v:444.5-444.51" wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:411.5-411.51" + attribute \src "ls180.v:443.5-443.51" wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:475.12-475.47" + attribute \src "ls180.v:507.12-507.47" wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:479.5-479.45" + attribute \src "ls180.v:511.5-511.45" wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:480.5-480.54" + attribute \src "ls180.v:512.5-512.54" wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:478.5-478.44" + attribute \src "ls180.v:510.5-510.44" wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:476.5-476.46" + attribute \src "ls180.v:508.5-508.46" wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:483.11-483.55" + attribute \src "ls180.v:515.11-515.55" wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:482.32-482.76" + attribute \src "ls180.v:514.32-514.76" wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:507.5-507.50" + attribute \src "ls180.v:539.5-539.50" wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:529.11-529.70" + attribute \src "ls180.v:561.11-561.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:526.11-526.68" + attribute \src "ls180.v:558.11-558.68" wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:528.11-528.70" + attribute \src "ls180.v:560.11-560.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:530.11-530.73" + attribute \src "ls180.v:562.11-562.73" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:553.5-553.59" + attribute \src "ls180.v:585.5-585.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:554.5-554.58" + attribute \src "ls180.v:586.5-586.58" wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:556.12-556.74" + attribute \src "ls180.v:588.12-588.74" wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:555.5-555.64" + attribute \src "ls180.v:587.5-587.64" wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:551.5-551.59" + attribute \src "ls180.v:583.5-583.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:499.12-499.57" + attribute \src "ls180.v:531.12-531.57" wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:501.5-501.51" + attribute \src "ls180.v:533.5-533.51" wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:504.5-504.54" + attribute \src "ls180.v:536.5-536.54" wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:505.5-505.55" + attribute \src "ls180.v:537.5-537.55" wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:506.5-506.56" + attribute \src "ls180.v:538.5-538.56" wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:502.5-502.51" + attribute \src "ls180.v:534.5-534.51" wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:503.5-503.50" + attribute \src "ls180.v:535.5-535.50" wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:498.5-498.45" + attribute \src "ls180.v:530.5-530.45" wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:497.5-497.45" + attribute \src "ls180.v:529.5-529.45" wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:496.5-496.47" + attribute \src "ls180.v:528.5-528.47" wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:494.5-494.51" + attribute \src "ls180.v:526.5-526.51" wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:493.5-493.51" + attribute \src "ls180.v:525.5-525.51" wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:557.12-557.47" + attribute \src "ls180.v:589.12-589.47" wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:561.5-561.45" + attribute \src "ls180.v:593.5-593.45" wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:562.5-562.54" + attribute \src "ls180.v:594.5-594.54" wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:560.5-560.44" + attribute \src "ls180.v:592.5-592.44" wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:558.5-558.46" + attribute \src "ls180.v:590.5-590.46" wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:565.11-565.55" + attribute \src "ls180.v:597.11-597.55" wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:564.32-564.76" + attribute \src "ls180.v:596.32-596.76" wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:589.5-589.50" + attribute \src "ls180.v:621.5-621.50" wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:611.11-611.70" + attribute \src "ls180.v:643.11-643.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:608.11-608.68" + attribute \src "ls180.v:640.11-640.68" wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:610.11-610.70" + attribute \src "ls180.v:642.11-642.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:612.11-612.73" + attribute \src "ls180.v:644.11-644.73" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:635.5-635.59" + attribute \src "ls180.v:667.5-667.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:636.5-636.58" + attribute \src "ls180.v:668.5-668.58" wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:638.12-638.74" + attribute \src "ls180.v:670.12-670.74" wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:637.5-637.64" + attribute \src "ls180.v:669.5-669.64" wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:633.5-633.59" + attribute \src "ls180.v:665.5-665.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:581.12-581.57" + attribute \src "ls180.v:613.12-613.57" wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:583.5-583.51" + attribute \src "ls180.v:615.5-615.51" wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:586.5-586.54" + attribute \src "ls180.v:618.5-618.54" wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:587.5-587.55" + attribute \src "ls180.v:619.5-619.55" wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:588.5-588.56" + attribute \src "ls180.v:620.5-620.56" wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:584.5-584.51" + attribute \src "ls180.v:616.5-616.51" wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:585.5-585.50" + attribute \src "ls180.v:617.5-617.50" wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:580.5-580.45" + attribute \src "ls180.v:612.5-612.45" wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:579.5-579.45" + attribute \src "ls180.v:611.5-611.45" wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:578.5-578.47" + attribute \src "ls180.v:610.5-610.47" wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:576.5-576.51" + attribute \src "ls180.v:608.5-608.51" wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:575.5-575.51" + attribute \src "ls180.v:607.5-607.51" wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:639.12-639.47" + attribute \src "ls180.v:671.12-671.47" wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:643.5-643.45" + attribute \src "ls180.v:675.5-675.45" wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:644.5-644.54" + attribute \src "ls180.v:676.5-676.54" wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:642.5-642.44" + attribute \src "ls180.v:674.5-674.44" wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:640.5-640.46" + attribute \src "ls180.v:672.5-672.46" wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:647.11-647.55" + attribute \src "ls180.v:679.11-679.55" wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:646.32-646.76" + attribute \src "ls180.v:678.32-678.76" wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:671.5-671.50" + attribute \src "ls180.v:703.5-703.50" wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:693.11-693.70" + attribute \src "ls180.v:725.11-725.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:690.11-690.68" + attribute \src "ls180.v:722.11-722.68" wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:692.11-692.70" + attribute \src "ls180.v:724.11-724.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:694.11-694.73" + attribute \src "ls180.v:726.11-726.73" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:717.5-717.59" + attribute \src "ls180.v:749.5-749.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:718.5-718.58" + attribute \src "ls180.v:750.5-750.58" wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:720.12-720.74" + attribute \src "ls180.v:752.12-752.74" wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:719.5-719.64" + attribute \src "ls180.v:751.5-751.64" wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:715.5-715.59" + attribute \src "ls180.v:747.5-747.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:663.12-663.57" + attribute \src "ls180.v:695.12-695.57" wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:665.5-665.51" + attribute \src "ls180.v:697.5-697.51" wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:668.5-668.54" + attribute \src "ls180.v:700.5-700.54" wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:669.5-669.55" + attribute \src "ls180.v:701.5-701.55" wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:670.5-670.56" + attribute \src "ls180.v:702.5-702.56" wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:666.5-666.51" + attribute \src "ls180.v:698.5-698.51" wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:667.5-667.50" + attribute \src "ls180.v:699.5-699.50" wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:662.5-662.45" + attribute \src "ls180.v:694.5-694.45" wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:661.5-661.45" + attribute \src "ls180.v:693.5-693.45" wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:660.5-660.47" + attribute \src "ls180.v:692.5-692.47" wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:658.5-658.51" + attribute \src "ls180.v:690.5-690.51" wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:657.5-657.51" + attribute \src "ls180.v:689.5-689.51" wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:721.12-721.47" + attribute \src "ls180.v:753.12-753.47" wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:725.5-725.45" + attribute \src "ls180.v:757.5-757.45" wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:726.5-726.54" + attribute \src "ls180.v:758.5-758.54" wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:724.5-724.44" + attribute \src "ls180.v:756.5-756.44" wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:722.5-722.46" + attribute \src "ls180.v:754.5-754.46" wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:729.11-729.55" + attribute \src "ls180.v:761.11-761.55" wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:728.32-728.76" + attribute \src "ls180.v:760.32-760.76" wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:744.5-744.49" + attribute \src "ls180.v:776.5-776.49" wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:745.5-745.49" + attribute \src "ls180.v:777.5-777.49" wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:746.5-746.48" + attribute \src "ls180.v:778.5-778.48" wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:752.11-752.45" + attribute \src "ls180.v:784.11-784.45" wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:750.11-750.46" + attribute \src "ls180.v:782.11-782.46" wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:762.5-762.49" + attribute \src "ls180.v:794.5-794.49" wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:763.5-763.49" + attribute \src "ls180.v:795.5-795.49" wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:764.5-764.48" + attribute \src "ls180.v:796.5-796.48" wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:759.5-759.43" + attribute \src "ls180.v:791.5-791.43" wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:770.11-770.45" + attribute \src "ls180.v:802.11-802.45" wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:768.11-768.46" + attribute \src "ls180.v:800.11-800.46" wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:757.5-757.48" + attribute \src "ls180.v:789.5-789.48" wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:754.5-754.44" + attribute \src "ls180.v:786.5-786.44" wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:755.5-755.45" + attribute \src "ls180.v:787.5-787.45" wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:383.5-383.31" + attribute \src "ls180.v:415.5-415.31" wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:384.12-384.44" + attribute \src "ls180.v:416.12-416.44" wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:385.11-385.43" + attribute \src "ls180.v:417.11-417.43" wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:386.5-386.38" + attribute \src "ls180.v:418.5-418.38" wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:387.5-387.38" + attribute \src "ls180.v:419.5-419.38" wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:388.5-388.37" + attribute \src "ls180.v:420.5-420.37" wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:382.5-382.32" + attribute \src "ls180.v:414.5-414.32" wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:381.5-381.32" + attribute \src "ls180.v:413.5-413.32" wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:321.5-321.33" + attribute \src "ls180.v:353.5-353.33" wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:320.11-320.44" + attribute \src "ls180.v:352.11-352.44" wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:365.12-365.45" + attribute \src "ls180.v:397.12-397.45" wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:366.11-366.40" + attribute \src "ls180.v:398.11-398.40" wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:367.5-367.35" + attribute \src "ls180.v:399.5-399.35" wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:368.5-368.34" + attribute \src "ls180.v:400.5-400.34" wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:369.5-369.35" + attribute \src "ls180.v:401.5-401.35" wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:378.5-378.39" + attribute \src "ls180.v:410.5-410.39" wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:370.5-370.34" + attribute \src "ls180.v:402.5-402.34" wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:376.5-376.39" + attribute \src "ls180.v:408.5-408.39" wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:789.5-789.26" + attribute \src "ls180.v:821.5-821.26" wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:792.5-792.26" + attribute \src "ls180.v:824.5-824.26" wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:362.12-362.46" + attribute \src "ls180.v:394.12-394.46" wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:363.11-363.47" + attribute \src "ls180.v:395.11-395.47" wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:268.5-268.36" + attribute \src "ls180.v:300.5-300.36" wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:269.5-269.35" + attribute \src "ls180.v:301.5-301.35" wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:270.5-270.36" + attribute \src "ls180.v:302.5-302.36" wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:280.12-280.45" + attribute \src "ls180.v:312.12-312.45" wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:281.5-281.43" + attribute \src "ls180.v:313.5-313.43" wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:271.5-271.35" + attribute \src "ls180.v:303.5-303.35" wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:307.5-307.38" + attribute \src "ls180.v:339.5-339.38" wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:298.12-298.48" + attribute \src "ls180.v:330.12-330.48" wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:299.11-299.43" + attribute \src "ls180.v:331.11-331.43" wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:300.5-300.38" + attribute \src "ls180.v:332.5-332.38" wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:304.5-304.36" + attribute \src "ls180.v:336.5-336.36" wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:301.5-301.37" + attribute \src "ls180.v:333.5-333.37" wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:305.5-305.36" + attribute \src "ls180.v:337.5-337.36" wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:302.5-302.38" + attribute \src "ls180.v:334.5-334.38" wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:311.5-311.42" + attribute \src "ls180.v:343.5-343.42" wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:306.5-306.40" + attribute \src "ls180.v:338.5-338.40" wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:303.5-303.37" + attribute \src "ls180.v:335.5-335.37" wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:308.12-308.47" + attribute \src "ls180.v:340.12-340.47" wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:309.5-309.42" + attribute \src "ls180.v:341.5-341.42" wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:310.11-310.50" + attribute \src "ls180.v:342.11-342.50" wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:399.5-399.38" + attribute \src "ls180.v:431.5-431.38" wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:398.5-398.38" + attribute \src "ls180.v:430.5-430.38" wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:319.5-319.25" + attribute \src "ls180.v:351.5-351.25" wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:405.5-405.38" + attribute \src "ls180.v:437.5-437.38" wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:404.11-404.46" + attribute \src "ls180.v:436.11-436.46" wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:403.5-403.38" + attribute \src "ls180.v:435.5-435.38" wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:400.5-400.39" + attribute \src "ls180.v:432.5-432.39" wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:296.12-296.46" + attribute \src "ls180.v:328.12-328.46" wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:297.5-297.44" + attribute \src "ls180.v:329.5-329.44" wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:332.12-332.37" + attribute \src "ls180.v:364.12-364.37" wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:774.11-774.40" + attribute \src "ls180.v:806.11-806.40" wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:318.11-318.36" + attribute \src "ls180.v:350.11-350.36" wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:783.5-783.36" + attribute \src "ls180.v:815.5-815.36" wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:782.32-782.63" + attribute \src "ls180.v:814.32-814.63" wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:791.11-791.34" + attribute \src "ls180.v:823.11-823.34" wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:794.11-794.34" + attribute \src "ls180.v:826.11-826.34" wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:396.11-396.44" + attribute \src "ls180.v:428.11-428.44" wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:786.11-786.42" + attribute \src "ls180.v:818.11-818.42" wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:785.32-785.63" + attribute \src "ls180.v:817.32-817.63" wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:331.5-331.32" + attribute \src "ls180.v:363.5-363.32" wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:330.12-330.45" + attribute \src "ls180.v:362.12-362.45" wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:999.12-999.44" + attribute \src "ls180.v:855.5-855.54" + wire $1\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:861.5-861.38" + wire $1\main_socbushandler_counter[0:0] + attribute \src "ls180.v:1784.5-1784.60" + wire $1\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1785.5-1785.63" + wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:863.12-863.44" + wire width 64 $1\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:860.5-860.35" + wire $1\main_socbushandler_skip[0:0] + attribute \src "ls180.v:1043.12-1043.44" wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1000.5-1000.31" + attribute \src "ls180.v:1044.5-1044.31" wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1004.11-1004.42" + attribute \src "ls180.v:1048.11-1048.42" wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1005.5-1005.31" + attribute \src "ls180.v:1049.5-1049.31" wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1061.5-1061.30" + attribute \src "ls180.v:1105.5-1105.30" wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1060.12-1060.45" + attribute \src "ls180.v:1104.12-1104.45" wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1009.5-1009.36" + attribute \src "ls180.v:1053.5-1053.36" wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1010.5-1010.31" + attribute \src "ls180.v:1054.5-1054.31" wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1011.5-1011.36" + attribute \src "ls180.v:1055.5-1055.36" wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1012.5-1012.31" + attribute \src "ls180.v:1056.5-1056.31" wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1013.5-1013.39" + attribute \src "ls180.v:1057.5-1057.39" wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1014.5-1014.38" + attribute \src "ls180.v:1058.5-1058.38" wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1015.11-1015.40" + attribute \src "ls180.v:1059.11-1059.40" wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1781.11-1781.62" + attribute \src "ls180.v:1825.11-1825.62" wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1782.5-1782.59" + attribute \src "ls180.v:1826.5-1826.59" wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1016.5-1016.39" + attribute \src "ls180.v:1060.5-1060.39" wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1017.5-1017.39" + attribute \src "ls180.v:1061.5-1061.39" wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:990.5-990.32" + attribute \src "ls180.v:1034.5-1034.32" wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1018.12-1018.48" + attribute \src "ls180.v:1062.12-1062.48" wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1021.11-1021.44" + attribute \src "ls180.v:1065.11-1065.44" wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1022.11-1022.43" + attribute \src "ls180.v:1066.11-1066.43" wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1023.11-1023.44" + attribute \src "ls180.v:1067.11-1067.44" wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:991.5-991.31" + attribute \src "ls180.v:1035.5-1035.31" wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:993.11-993.38" + attribute \src "ls180.v:1037.11-1037.38" wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:997.5-997.33" + attribute \src "ls180.v:1041.5-1041.33" wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1054.12-1054.47" + attribute \src "ls180.v:1098.12-1098.47" wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1049.5-1049.37" + attribute \src "ls180.v:1093.5-1093.37" wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1036.5-1036.37" + attribute \src "ls180.v:1080.5-1080.37" wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1035.12-1035.50" + attribute \src "ls180.v:1079.12-1079.50" wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1051.11-1051.38" + attribute \src "ls180.v:1095.11-1095.38" wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1785.11-1785.60" + attribute \src "ls180.v:1829.11-1829.60" wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1786.5-1786.57" + attribute \src "ls180.v:1830.5-1830.57" wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1050.5-1050.36" + attribute \src "ls180.v:1094.5-1094.36" wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1046.5-1046.32" + attribute \src "ls180.v:1090.5-1090.32" wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1045.5-1045.37" + attribute \src "ls180.v:1089.5-1089.37" wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1026.5-1026.32" + attribute \src "ls180.v:1070.5-1070.32" wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1027.5-1027.30" + attribute \src "ls180.v:1071.5-1071.30" wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1048.5-1048.38" + attribute \src "ls180.v:1092.5-1092.38" wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1047.5-1047.43" + attribute \src "ls180.v:1091.5-1091.43" wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1029.11-1029.37" + attribute \src "ls180.v:1073.11-1073.37" wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1059.11-1059.42" + attribute \src "ls180.v:1103.11-1103.42" wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1053.5-1053.37" + attribute \src "ls180.v:1097.5-1097.37" wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1057.11-1057.42" + attribute \src "ls180.v:1101.11-1101.42" wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1052.5-1052.37" + attribute \src "ls180.v:1096.5-1096.37" wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1041.5-1041.34" + attribute \src "ls180.v:1085.5-1085.34" wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1058.11-1058.41" + attribute \src "ls180.v:1102.11-1102.41" wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1040.11-1040.45" + attribute \src "ls180.v:1084.11-1084.45" wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1033.5-1033.33" + attribute \src "ls180.v:1077.5-1077.33" wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:887.11-887.50" + attribute \src "ls180.v:215.11-215.31" + wire width 8 $1\main_sram0_we[7:0] + attribute \src "ls180.v:230.11-230.31" + wire width 8 $1\main_sram1_we[7:0] + attribute \src "ls180.v:245.11-245.31" + wire width 8 $1\main_sram2_we[7:0] + attribute \src "ls180.v:931.11-931.50" wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:889.5-889.37" + attribute \src "ls180.v:933.5-933.37" wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:883.11-883.49" + attribute \src "ls180.v:927.11-927.49" wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:888.11-888.48" + attribute \src "ls180.v:932.11-932.48" wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:855.12-855.54" + attribute \src "ls180.v:899.12-899.54" wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:845.12-845.54" + attribute \src "ls180.v:889.12-889.54" wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:838.5-838.28" + attribute \src "ls180.v:882.5-882.28" wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:859.11-859.43" + attribute \src "ls180.v:903.11-903.43" wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:860.5-860.33" + attribute \src "ls180.v:904.5-904.33" wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:857.5-857.30" + attribute \src "ls180.v:901.5-901.30" wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:858.11-858.38" + attribute \src "ls180.v:902.11-902.38" wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:840.5-840.36" + attribute \src "ls180.v:884.5-884.36" wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:853.11-853.51" + attribute \src "ls180.v:897.11-897.51" wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:849.5-849.38" + attribute \src "ls180.v:893.5-893.38" wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:837.12-837.47" + attribute \src "ls180.v:881.12-881.47" wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:847.11-847.43" + attribute \src "ls180.v:891.11-891.43" wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:848.5-848.33" + attribute \src "ls180.v:892.5-892.33" wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:846.11-846.38" + attribute \src "ls180.v:890.11-890.38" wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:854.5-854.39" + attribute \src "ls180.v:898.5-898.39" wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:844.5-844.39" + attribute \src "ls180.v:888.5-888.39" wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:878.5-878.30" + attribute \src "ls180.v:922.5-922.30" wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:962.11-962.43" + attribute \src "ls180.v:1006.11-1006.43" wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:959.11-959.42" + attribute \src "ls180.v:1003.11-1003.42" wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:961.11-961.43" + attribute \src "ls180.v:1005.11-1005.43" wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:952.5-952.38" + attribute \src "ls180.v:996.5-996.38" wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:963.11-963.46" + attribute \src "ls180.v:1007.11-1007.46" wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:879.5-879.36" + attribute \src "ls180.v:923.5-923.36" wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:876.5-876.32" + attribute \src "ls180.v:920.5-920.32" wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:873.5-873.30" + attribute \src "ls180.v:917.5-917.30" wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:925.11-925.43" + attribute \src "ls180.v:969.11-969.43" wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:922.11-922.42" + attribute \src "ls180.v:966.11-966.42" wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:924.11-924.43" + attribute \src "ls180.v:968.11-968.43" wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:915.5-915.38" + attribute \src "ls180.v:959.5-959.38" wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:926.11-926.46" + attribute \src "ls180.v:970.11-970.46" wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:874.5-874.36" + attribute \src "ls180.v:918.5-918.36" wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:871.5-871.32" + attribute \src "ls180.v:915.5-915.32" wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:815.5-815.29" + attribute \src "ls180.v:847.5-847.29" wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:833.5-833.31" + attribute \src "ls180.v:841.12-841.37" + wire width 30 $1\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:845.5-845.29" + wire $1\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:842.12-842.39" + wire width 32 $1\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:844.11-844.35" + wire width 4 $1\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:846.5-846.29" + wire $1\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:848.5-848.28" + wire $1\main_wb_sdram_we[0:0] + attribute \src "ls180.v:877.5-877.31" wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2815.68-2815.110" - wire $add$ls180.v:2815$22_Y - attribute \src "ls180.v:2875.68-2875.110" - wire $add$ls180.v:2875$33_Y - attribute \src "ls180.v:2935.68-2935.110" - wire $add$ls180.v:2935$44_Y - attribute \src "ls180.v:4068.54-4068.83" - wire $add$ls180.v:4068$537_Y - attribute \src "ls180.v:4168.36-4168.89" - wire width 5 $add$ls180.v:4168$583_Y - attribute \src "ls180.v:4198.36-4198.89" - wire width 5 $add$ls180.v:4198$594_Y - attribute \src "ls180.v:4253.54-4253.83" - wire width 3 $add$ls180.v:4253$607_Y - attribute \src "ls180.v:4312.52-4312.79" - wire width 3 $add$ls180.v:4312$615_Y - attribute \src "ls180.v:4416.58-4416.86" - wire width 8 $add$ls180.v:4416$643_Y - attribute \src "ls180.v:4473.58-4473.86" - wire width 8 $add$ls180.v:4473$646_Y - attribute \src "ls180.v:4490.58-4490.86" - wire width 8 $add$ls180.v:4490$648_Y - attribute \src "ls180.v:4583.59-4583.87" - wire width 8 $add$ls180.v:4583$665_Y - attribute \src "ls180.v:4608.59-4608.87" - wire width 8 $add$ls180.v:4608$668_Y - attribute \src "ls180.v:4730.53-4730.82" - wire width 8 $add$ls180.v:4730$685_Y - attribute \src "ls180.v:4841.65-4841.114" - wire width 10 $add$ls180.v:4841$699_Y - attribute \src "ls180.v:4846.62-4846.91" - wire width 10 $add$ls180.v:4846$702_Y - attribute \src "ls180.v:4872.61-4872.90" - wire width 10 $add$ls180.v:4872$705_Y - attribute \src "ls180.v:5076.80-5076.117" - wire width 3 $add$ls180.v:5076$890_Y - attribute \src "ls180.v:5270.54-5270.82" - wire width 3 $add$ls180.v:5270$965_Y - attribute \src "ls180.v:5322.55-5322.84" - wire width 32 $add$ls180.v:5322$975_Y - attribute \src "ls180.v:5348.57-5348.86" - wire width 32 $add$ls180.v:5348$983_Y - attribute \src "ls180.v:5469.51-5469.134" - wire width 32 $add$ls180.v:5469$999_Y - attribute \src "ls180.v:5472.77-5472.125" - wire width 32 $add$ls180.v:5472$1001_Y - attribute \src "ls180.v:5565.50-5565.105" - wire width 32 $add$ls180.v:5565$1010_Y - attribute \src "ls180.v:5567.77-5567.111" - wire width 32 $add$ls180.v:5567$1011_Y - attribute \src "ls180.v:7487.36-7487.70" - wire width 32 $add$ls180.v:7487$2403_Y - attribute \src "ls180.v:7572.37-7572.72" - wire width 4 $add$ls180.v:7572$2424_Y - attribute \src "ls180.v:7589.60-7589.119" - wire width 3 $add$ls180.v:7589$2428_Y - attribute \src "ls180.v:7592.60-7592.119" - wire width 3 $add$ls180.v:7592$2429_Y - attribute \src "ls180.v:7596.59-7596.116" - wire width 4 $add$ls180.v:7596$2434_Y - attribute \src "ls180.v:7635.60-7635.119" - wire width 3 $add$ls180.v:7635$2444_Y - attribute \src "ls180.v:7638.60-7638.119" - wire width 3 $add$ls180.v:7638$2445_Y - attribute \src "ls180.v:7642.59-7642.116" - wire width 4 $add$ls180.v:7642$2450_Y - attribute \src "ls180.v:7681.60-7681.119" - wire width 3 $add$ls180.v:7681$2460_Y - attribute \src "ls180.v:7684.60-7684.119" - wire width 3 $add$ls180.v:7684$2461_Y - attribute \src "ls180.v:7688.59-7688.116" - wire width 4 $add$ls180.v:7688$2466_Y - attribute \src "ls180.v:7727.60-7727.119" - wire width 3 $add$ls180.v:7727$2476_Y - attribute \src "ls180.v:7730.60-7730.119" - wire width 3 $add$ls180.v:7730$2477_Y - attribute \src "ls180.v:7734.59-7734.116" - wire width 4 $add$ls180.v:7734$2482_Y - attribute \src "ls180.v:7964.34-7964.66" - wire width 4 $add$ls180.v:7964$2536_Y - attribute \src "ls180.v:7980.73-7980.131" - wire width 33 $add$ls180.v:7980$2539_Y - attribute \src "ls180.v:7993.34-7993.66" - wire width 4 $add$ls180.v:7993$2543_Y - attribute \src "ls180.v:8012.73-8012.131" - wire width 33 $add$ls180.v:8012$2546_Y - attribute \src "ls180.v:8038.33-8038.65" - wire width 4 $add$ls180.v:8038$2554_Y - attribute \src "ls180.v:8041.33-8041.65" - wire width 4 $add$ls180.v:8041$2555_Y - attribute \src "ls180.v:8045.33-8045.64" - wire width 5 $add$ls180.v:8045$2560_Y - attribute \src "ls180.v:8060.33-8060.65" - wire width 4 $add$ls180.v:8060$2565_Y - attribute \src "ls180.v:8063.33-8063.65" - wire width 4 $add$ls180.v:8063$2566_Y - attribute \src "ls180.v:8067.33-8067.64" - wire width 5 $add$ls180.v:8067$2571_Y - attribute \src "ls180.v:8088.35-8088.70" - wire width 16 $add$ls180.v:8088$2573_Y - attribute \src "ls180.v:8123.34-8123.68" - wire width 16 $add$ls180.v:8123$2578_Y - attribute \src "ls180.v:8159.25-8159.49" - wire width 32 $add$ls180.v:8159$2583_Y - attribute \src "ls180.v:8173.25-8173.49" - wire width 32 $add$ls180.v:8173$2587_Y - attribute \src "ls180.v:8187.31-8187.61" - wire width 9 $add$ls180.v:8187$2592_Y - attribute \src "ls180.v:8210.45-8210.88" - wire width 3 $add$ls180.v:8210$2596_Y - attribute \src "ls180.v:8256.71-8256.114" - wire width 4 $add$ls180.v:8256$2602_Y - attribute \src "ls180.v:8291.46-8291.90" - wire width 3 $add$ls180.v:8291$2608_Y - attribute \src "ls180.v:8337.72-8337.116" - wire width 4 $add$ls180.v:8337$2614_Y - attribute \src "ls180.v:8370.47-8370.92" - wire $add$ls180.v:8370$2620_Y - attribute \src "ls180.v:8398.73-8398.118" - wire width 2 $add$ls180.v:8398$2626_Y - attribute \src "ls180.v:8510.39-8510.75" - wire width 4 $add$ls180.v:8510$2639_Y - attribute \src "ls180.v:8571.37-8571.73" - wire width 5 $add$ls180.v:8571$2643_Y - attribute \src "ls180.v:8574.37-8574.73" - wire width 5 $add$ls180.v:8574$2644_Y - attribute \src "ls180.v:8578.36-8578.70" - wire width 6 $add$ls180.v:8578$2649_Y - attribute \src "ls180.v:8593.41-8593.80" - wire width 2 $add$ls180.v:8593$2653_Y - attribute \src "ls180.v:8627.67-8627.106" - wire width 3 $add$ls180.v:8627$2659_Y - attribute \src "ls180.v:8653.39-8653.76" - wire width 2 $add$ls180.v:8653$2661_Y - attribute \src "ls180.v:8657.37-8657.73" - wire width 5 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"ls180.v:5240.7-5240.44" + wire $eq$ls180.v:5240$1027_Y + attribute \src "ls180.v:5364.36-5364.64" + wire $eq$ls180.v:5364$1078_Y + attribute \src "ls180.v:5370.10-5370.39" + wire $eq$ls180.v:5370$1081_Y + attribute \src "ls180.v:5371.11-5371.39" + wire $eq$ls180.v:5371$1082_Y + attribute \src "ls180.v:5383.34-5383.63" + wire $eq$ls180.v:5383$1083_Y + attribute \src "ls180.v:5384.9-5384.37" + wire $eq$ls180.v:5384$1084_Y + attribute \src "ls180.v:5391.10-5391.55" + wire $eq$ls180.v:5391$1085_Y + attribute \src "ls180.v:5397.12-5397.41" + wire $eq$ls180.v:5397$1086_Y + attribute \src "ls180.v:5400.13-5400.42" + wire $eq$ls180.v:5400$1087_Y + attribute \src "ls180.v:5422.10-5422.76" + wire $eq$ls180.v:5422$1092_Y + attribute \src "ls180.v:5437.35-5437.101" + wire $eq$ls180.v:5437$1095_Y + attribute \src "ls180.v:5439.10-5439.56" + wire $eq$ls180.v:5439$1096_Y + attribute \src "ls180.v:5448.12-5448.78" + wire $eq$ls180.v:5448$1100_Y + attribute \src "ls180.v:5455.11-5455.57" + wire $eq$ls180.v:5455$1101_Y + attribute \src "ls180.v:5572.10-5572.105" + wire $eq$ls180.v:5572$1118_Y + attribute \src "ls180.v:5662.39-5662.106" + wire $eq$ls180.v:5662$1124_Y + attribute \src "ls180.v:5692.44-5692.82" + wire $eq$ls180.v:5692$1127_Y + attribute \src "ls180.v:5693.43-5693.81" + wire $eq$ls180.v:5693$1128_Y + attribute \src "ls180.v:5805.68-5805.89" + wire $eq$ls180.v:5805$1144_Y + attribute \src "ls180.v:5806.68-5806.89" + wire $eq$ls180.v:5806$1146_Y + attribute \src "ls180.v:5807.71-5807.92" + wire $eq$ls180.v:5807$1148_Y + attribute \src "ls180.v:5808.57-5808.78" + wire $eq$ls180.v:5808$1150_Y + attribute \src "ls180.v:5809.57-5809.78" + wire $eq$ls180.v:5809$1152_Y + attribute \src "ls180.v:5810.68-5810.89" + wire $eq$ls180.v:5810$1154_Y + attribute \src "ls180.v:5811.68-5811.89" + wire $eq$ls180.v:5811$1156_Y + attribute \src "ls180.v:5812.71-5812.92" + wire $eq$ls180.v:5812$1158_Y + attribute \src "ls180.v:5813.57-5813.78" + wire $eq$ls180.v:5813$1160_Y + attribute \src "ls180.v:5814.57-5814.78" + wire $eq$ls180.v:5814$1162_Y + attribute \src "ls180.v:5818.27-5818.59" + wire $eq$ls180.v:5818$1165_Y + attribute \src "ls180.v:5819.27-5819.59" + wire $eq$ls180.v:5819$1166_Y + attribute \src "ls180.v:5820.27-5820.59" + wire $eq$ls180.v:5820$1167_Y + attribute \src "ls180.v:5821.27-5821.59" + wire $eq$ls180.v:5821$1168_Y + attribute \src "ls180.v:5822.27-5822.68" + wire $eq$ls180.v:5822$1169_Y + attribute \src "ls180.v:5823.27-5823.65" + wire $eq$ls180.v:5823$1170_Y + attribute \src "ls180.v:5824.27-5824.61" + wire $eq$ls180.v:5824$1171_Y + attribute \src "ls180.v:5825.27-5825.65" + wire $eq$ls180.v:5825$1172_Y + attribute \src "ls180.v:5905.24-5905.45" + wire $eq$ls180.v:5905$1214_Y + attribute \src "ls180.v:5906.32-5906.77" + wire $eq$ls180.v:5906$1215_Y + attribute \src "ls180.v:5908.97-5908.141" + wire $eq$ls180.v:5908$1217_Y + attribute \src "ls180.v:5909.100-5909.144" + wire $eq$ls180.v:5909$1221_Y + attribute \src "ls180.v:5911.99-5911.143" + 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$eq$ls180.v:5930$1270_Y + attribute \src "ls180.v:5932.102-5932.146" + wire $eq$ls180.v:5932$1273_Y + attribute \src "ls180.v:5933.105-5933.149" + wire $eq$ls180.v:5933$1277_Y + attribute \src "ls180.v:5944.32-5944.77" + wire $eq$ls180.v:5944$1279_Y + attribute \src "ls180.v:5946.94-5946.138" + wire $eq$ls180.v:5946$1281_Y + attribute \src "ls180.v:5947.97-5947.141" + wire $eq$ls180.v:5947$1285_Y + attribute \src "ls180.v:5949.94-5949.138" + wire $eq$ls180.v:5949$1288_Y + attribute \src "ls180.v:5950.97-5950.141" + wire $eq$ls180.v:5950$1292_Y + attribute \src "ls180.v:5952.94-5952.138" + wire $eq$ls180.v:5952$1295_Y + attribute \src "ls180.v:5953.97-5953.141" + wire $eq$ls180.v:5953$1299_Y + attribute \src "ls180.v:5955.94-5955.138" + wire $eq$ls180.v:5955$1302_Y + attribute \src "ls180.v:5956.97-5956.141" + wire $eq$ls180.v:5956$1306_Y + attribute \src "ls180.v:5958.95-5958.139" + wire $eq$ls180.v:5958$1309_Y + attribute \src "ls180.v:5959.98-5959.142" + wire $eq$ls180.v:5959$1313_Y + attribute \src "ls180.v:5961.95-5961.139" + wire $eq$ls180.v:5961$1316_Y + attribute \src "ls180.v:5962.98-5962.142" + wire $eq$ls180.v:5962$1320_Y + attribute \src "ls180.v:5970.32-5970.78" + wire $eq$ls180.v:5970$1322_Y + attribute \src "ls180.v:5972.93-5972.135" + wire $eq$ls180.v:5972$1324_Y + attribute \src "ls180.v:5973.96-5973.138" + wire $eq$ls180.v:5973$1328_Y + attribute \src "ls180.v:5975.92-5975.134" + wire $eq$ls180.v:5975$1331_Y + attribute \src "ls180.v:5976.95-5976.137" + wire $eq$ls180.v:5976$1335_Y + attribute \src "ls180.v:5984.32-5984.77" + wire $eq$ls180.v:5984$1337_Y + attribute \src "ls180.v:5986.98-5986.142" + wire $eq$ls180.v:5986$1339_Y + attribute \src "ls180.v:5987.101-5987.145" + wire $eq$ls180.v:5987$1343_Y + attribute \src "ls180.v:5989.97-5989.141" + wire $eq$ls180.v:5989$1346_Y + attribute \src "ls180.v:5990.100-5990.144" + wire $eq$ls180.v:5990$1350_Y + attribute \src "ls180.v:5992.97-5992.141" + wire $eq$ls180.v:5992$1353_Y + attribute \src "ls180.v:5993.100-5993.144" + wire $eq$ls180.v:5993$1357_Y + attribute \src "ls180.v:5995.97-5995.141" + wire $eq$ls180.v:5995$1360_Y + attribute \src "ls180.v:5996.100-5996.144" + wire $eq$ls180.v:5996$1364_Y + attribute \src "ls180.v:5998.97-5998.141" + wire $eq$ls180.v:5998$1367_Y + attribute \src "ls180.v:5999.100-5999.144" + wire $eq$ls180.v:5999$1371_Y + attribute \src "ls180.v:6001.98-6001.142" + wire $eq$ls180.v:6001$1374_Y + attribute \src "ls180.v:6002.101-6002.145" + wire $eq$ls180.v:6002$1378_Y + attribute \src "ls180.v:6004.98-6004.142" + wire $eq$ls180.v:6004$1381_Y + attribute \src "ls180.v:6005.101-6005.145" + wire $eq$ls180.v:6005$1385_Y + attribute \src "ls180.v:6007.98-6007.142" + wire $eq$ls180.v:6007$1388_Y + attribute \src "ls180.v:6008.101-6008.145" + wire $eq$ls180.v:6008$1392_Y + attribute \src "ls180.v:6010.98-6010.142" + wire $eq$ls180.v:6010$1395_Y + attribute \src "ls180.v:6011.101-6011.145" + wire $eq$ls180.v:6011$1399_Y + attribute \src "ls180.v:6021.32-6021.78" + wire $eq$ls180.v:6021$1401_Y + attribute \src "ls180.v:6023.98-6023.142" + wire $eq$ls180.v:6023$1403_Y + attribute \src "ls180.v:6024.101-6024.145" + wire $eq$ls180.v:6024$1407_Y + attribute \src "ls180.v:6026.97-6026.141" + wire $eq$ls180.v:6026$1410_Y + attribute \src "ls180.v:6027.100-6027.144" + wire $eq$ls180.v:6027$1414_Y + attribute \src "ls180.v:6029.97-6029.141" + wire $eq$ls180.v:6029$1417_Y + attribute \src "ls180.v:6030.100-6030.144" + wire $eq$ls180.v:6030$1421_Y + attribute \src "ls180.v:6032.97-6032.141" + wire $eq$ls180.v:6032$1424_Y + attribute \src "ls180.v:6033.100-6033.144" + wire $eq$ls180.v:6033$1428_Y + attribute \src "ls180.v:6035.97-6035.141" + wire $eq$ls180.v:6035$1431_Y + attribute \src "ls180.v:6036.100-6036.144" + wire $eq$ls180.v:6036$1435_Y + attribute \src "ls180.v:6038.98-6038.142" + wire $eq$ls180.v:6038$1438_Y + attribute \src "ls180.v:6039.101-6039.145" + wire $eq$ls180.v:6039$1442_Y + attribute \src "ls180.v:6041.98-6041.142" + wire $eq$ls180.v:6041$1445_Y + attribute \src "ls180.v:6042.101-6042.145" + wire $eq$ls180.v:6042$1449_Y + attribute \src "ls180.v:6044.98-6044.142" + wire $eq$ls180.v:6044$1452_Y + attribute \src "ls180.v:6045.101-6045.145" + wire $eq$ls180.v:6045$1456_Y + attribute \src "ls180.v:6047.98-6047.142" + wire $eq$ls180.v:6047$1459_Y + attribute \src "ls180.v:6048.101-6048.145" + wire $eq$ls180.v:6048$1463_Y + attribute \src "ls180.v:6058.32-6058.78" + wire $eq$ls180.v:6058$1465_Y + attribute \src "ls180.v:6060.100-6060.144" + wire $eq$ls180.v:6060$1467_Y + attribute \src "ls180.v:6061.103-6061.147" + wire $eq$ls180.v:6061$1471_Y + attribute \src "ls180.v:6063.100-6063.144" + wire $eq$ls180.v:6063$1474_Y + attribute \src "ls180.v:6064.103-6064.147" + wire $eq$ls180.v:6064$1478_Y + attribute \src "ls180.v:6066.100-6066.144" + wire $eq$ls180.v:6066$1481_Y + attribute \src "ls180.v:6067.103-6067.147" + wire $eq$ls180.v:6067$1485_Y + attribute \src "ls180.v:6069.100-6069.144" + wire $eq$ls180.v:6069$1488_Y + attribute \src "ls180.v:6070.103-6070.147" + wire $eq$ls180.v:6070$1492_Y + attribute \src "ls180.v:6072.100-6072.144" + wire $eq$ls180.v:6072$1495_Y + attribute \src "ls180.v:6073.103-6073.147" + wire $eq$ls180.v:6073$1499_Y + attribute \src "ls180.v:6075.100-6075.144" + wire $eq$ls180.v:6075$1502_Y + attribute \src "ls180.v:6076.103-6076.147" + wire $eq$ls180.v:6076$1506_Y + attribute \src "ls180.v:6078.100-6078.144" + wire $eq$ls180.v:6078$1509_Y + attribute \src "ls180.v:6079.103-6079.147" + wire $eq$ls180.v:6079$1513_Y + attribute \src "ls180.v:6081.100-6081.144" + wire $eq$ls180.v:6081$1516_Y + attribute \src "ls180.v:6082.103-6082.147" + wire $eq$ls180.v:6082$1520_Y + attribute \src "ls180.v:6084.102-6084.146" + wire $eq$ls180.v:6084$1523_Y + attribute \src "ls180.v:6085.105-6085.149" + wire $eq$ls180.v:6085$1527_Y + attribute \src "ls180.v:6087.102-6087.146" + wire $eq$ls180.v:6087$1530_Y + attribute \src "ls180.v:6088.105-6088.149" + wire $eq$ls180.v:6088$1534_Y + attribute \src "ls180.v:6090.102-6090.147" + wire $eq$ls180.v:6090$1537_Y + attribute \src "ls180.v:6091.105-6091.150" + wire $eq$ls180.v:6091$1541_Y + attribute \src "ls180.v:6093.102-6093.147" + wire $eq$ls180.v:6093$1544_Y + attribute \src "ls180.v:6094.105-6094.150" + wire $eq$ls180.v:6094$1548_Y + attribute \src "ls180.v:6096.102-6096.147" + wire $eq$ls180.v:6096$1551_Y + attribute \src "ls180.v:6097.105-6097.150" + wire $eq$ls180.v:6097$1555_Y + attribute \src "ls180.v:6099.99-6099.144" + wire $eq$ls180.v:6099$1558_Y + attribute \src "ls180.v:6100.102-6100.147" + wire $eq$ls180.v:6100$1562_Y + attribute \src "ls180.v:6102.100-6102.145" + wire $eq$ls180.v:6102$1565_Y + attribute \src "ls180.v:6103.103-6103.148" + wire $eq$ls180.v:6103$1569_Y + attribute \src "ls180.v:6120.32-6120.78" + wire $eq$ls180.v:6120$1571_Y + attribute \src "ls180.v:6122.104-6122.148" + wire $eq$ls180.v:6122$1573_Y + attribute \src "ls180.v:6123.107-6123.151" + wire $eq$ls180.v:6123$1577_Y + attribute \src "ls180.v:6125.104-6125.148" + wire $eq$ls180.v:6125$1580_Y + attribute \src "ls180.v:6126.107-6126.151" + wire $eq$ls180.v:6126$1584_Y + attribute \src "ls180.v:6128.104-6128.148" + wire $eq$ls180.v:6128$1587_Y + attribute \src "ls180.v:6129.107-6129.151" + wire $eq$ls180.v:6129$1591_Y + attribute \src "ls180.v:6131.104-6131.148" + wire $eq$ls180.v:6131$1594_Y + attribute \src "ls180.v:6132.107-6132.151" + wire $eq$ls180.v:6132$1598_Y + attribute \src "ls180.v:6134.103-6134.147" + wire $eq$ls180.v:6134$1601_Y + attribute \src "ls180.v:6135.106-6135.150" + wire $eq$ls180.v:6135$1605_Y + attribute \src "ls180.v:6137.103-6137.147" + wire $eq$ls180.v:6137$1608_Y + attribute \src "ls180.v:6138.106-6138.150" + wire $eq$ls180.v:6138$1612_Y + attribute \src "ls180.v:6140.103-6140.147" + wire $eq$ls180.v:6140$1615_Y + attribute \src "ls180.v:6141.106-6141.150" + wire $eq$ls180.v:6141$1619_Y + attribute \src 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"ls180.v:6294.105-6294.150" + wire $eq$ls180.v:6294$1893_Y + attribute \src "ls180.v:6296.99-6296.144" + wire $eq$ls180.v:6296$1896_Y + attribute \src "ls180.v:6297.102-6297.147" + wire $eq$ls180.v:6297$1900_Y + attribute \src "ls180.v:6299.100-6299.145" + wire $eq$ls180.v:6299$1903_Y + attribute \src "ls180.v:6300.103-6300.148" + wire $eq$ls180.v:6300$1907_Y + attribute \src "ls180.v:6302.102-6302.147" + wire $eq$ls180.v:6302$1910_Y + attribute \src "ls180.v:6303.105-6303.150" + wire $eq$ls180.v:6303$1914_Y + attribute \src "ls180.v:6305.102-6305.147" + wire $eq$ls180.v:6305$1917_Y + attribute \src "ls180.v:6306.105-6306.150" + wire $eq$ls180.v:6306$1921_Y + attribute \src "ls180.v:6308.102-6308.147" + wire $eq$ls180.v:6308$1924_Y + attribute \src "ls180.v:6309.105-6309.150" + wire $eq$ls180.v:6309$1928_Y attribute \src "ls180.v:6311.102-6311.147" - wire $eq$ls180.v:6311$1982_Y - attribute \src "ls180.v:6313.98-6313.143" - wire $eq$ls180.v:6313$1985_Y - attribute \src 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"ls180.v:6427.108-6427.153" - wire $eq$ls180.v:6427$2167_Y - attribute \src "ls180.v:6429.106-6429.151" - wire $eq$ls180.v:6429$2170_Y - attribute \src "ls180.v:6430.109-6430.154" - wire $eq$ls180.v:6430$2174_Y - attribute \src "ls180.v:6432.104-6432.149" - wire $eq$ls180.v:6432$2177_Y - attribute \src "ls180.v:6433.107-6433.152" - wire $eq$ls180.v:6433$2181_Y - attribute \src "ls180.v:6435.101-6435.146" - wire $eq$ls180.v:6435$2184_Y - attribute \src "ls180.v:6436.104-6436.149" - wire $eq$ls180.v:6436$2188_Y - attribute \src "ls180.v:6438.100-6438.145" - wire $eq$ls180.v:6438$2191_Y - attribute \src "ls180.v:6439.103-6439.148" - wire $eq$ls180.v:6439$2195_Y - attribute \src "ls180.v:6449.33-6449.79" - wire $eq$ls180.v:6449$2197_Y - attribute \src "ls180.v:6451.106-6451.151" - wire $eq$ls180.v:6451$2199_Y - attribute \src "ls180.v:6452.109-6452.154" - wire $eq$ls180.v:6452$2203_Y - attribute \src "ls180.v:6454.106-6454.151" - wire $eq$ls180.v:6454$2206_Y - attribute \src "ls180.v:6455.109-6455.154" - wire $eq$ls180.v:6455$2210_Y + wire $eq$ls180.v:6311$1931_Y + attribute \src "ls180.v:6312.105-6312.150" + wire $eq$ls180.v:6312$1935_Y + attribute \src "ls180.v:6334.32-6334.78" + wire $eq$ls180.v:6334$1937_Y + attribute \src "ls180.v:6336.102-6336.146" + wire $eq$ls180.v:6336$1939_Y + attribute \src "ls180.v:6337.105-6337.149" + wire $eq$ls180.v:6337$1943_Y + attribute \src "ls180.v:6339.107-6339.151" + wire $eq$ls180.v:6339$1946_Y + attribute \src "ls180.v:6340.110-6340.154" + wire $eq$ls180.v:6340$1950_Y + attribute \src "ls180.v:6342.107-6342.151" + wire $eq$ls180.v:6342$1953_Y + attribute \src "ls180.v:6343.110-6343.154" + wire $eq$ls180.v:6343$1957_Y + attribute \src "ls180.v:6345.100-6345.144" + wire $eq$ls180.v:6345$1960_Y + attribute \src "ls180.v:6346.103-6346.147" + wire $eq$ls180.v:6346$1964_Y + attribute \src "ls180.v:6351.32-6351.77" + wire $eq$ls180.v:6351$1966_Y + attribute \src "ls180.v:6353.104-6353.148" + wire $eq$ls180.v:6353$1968_Y + attribute \src "ls180.v:6354.107-6354.151" + wire $eq$ls180.v:6354$1972_Y + attribute \src "ls180.v:6356.108-6356.152" + wire $eq$ls180.v:6356$1975_Y + attribute \src "ls180.v:6357.111-6357.155" + wire $eq$ls180.v:6357$1979_Y + attribute \src "ls180.v:6359.98-6359.142" + wire $eq$ls180.v:6359$1982_Y + attribute \src "ls180.v:6360.101-6360.145" + wire $eq$ls180.v:6360$1986_Y + attribute \src "ls180.v:6362.108-6362.152" + wire $eq$ls180.v:6362$1989_Y + attribute \src "ls180.v:6363.111-6363.155" + wire $eq$ls180.v:6363$1993_Y + attribute \src "ls180.v:6365.108-6365.152" + wire $eq$ls180.v:6365$1996_Y + attribute \src "ls180.v:6366.111-6366.155" + wire $eq$ls180.v:6366$2000_Y + attribute \src "ls180.v:6368.109-6368.153" + wire $eq$ls180.v:6368$2003_Y + attribute \src "ls180.v:6369.112-6369.156" + wire $eq$ls180.v:6369$2007_Y + attribute \src "ls180.v:6371.107-6371.151" + wire $eq$ls180.v:6371$2010_Y + attribute \src "ls180.v:6372.110-6372.154" + wire $eq$ls180.v:6372$2014_Y + attribute \src "ls180.v:6374.107-6374.151" + wire $eq$ls180.v:6374$2017_Y + attribute \src "ls180.v:6375.110-6375.154" + wire $eq$ls180.v:6375$2021_Y + attribute \src "ls180.v:6377.107-6377.151" + wire $eq$ls180.v:6377$2024_Y + attribute \src "ls180.v:6378.110-6378.154" + wire $eq$ls180.v:6378$2028_Y + attribute \src "ls180.v:6380.107-6380.151" + wire $eq$ls180.v:6380$2031_Y + attribute \src "ls180.v:6381.110-6381.154" + wire $eq$ls180.v:6381$2035_Y + attribute \src "ls180.v:6396.33-6396.79" + wire $eq$ls180.v:6396$2037_Y + attribute \src "ls180.v:6398.102-6398.147" + wire $eq$ls180.v:6398$2039_Y + attribute \src "ls180.v:6399.105-6399.150" + wire $eq$ls180.v:6399$2043_Y + attribute \src "ls180.v:6401.102-6401.147" + wire $eq$ls180.v:6401$2046_Y + attribute \src "ls180.v:6402.105-6402.150" + wire $eq$ls180.v:6402$2050_Y + attribute \src "ls180.v:6404.100-6404.145" + wire $eq$ls180.v:6404$2053_Y + attribute \src "ls180.v:6405.103-6405.148" + wire $eq$ls180.v:6405$2057_Y + attribute \src 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attribute \src "ls180.v:8079.132-8079.165" + wire $eq$ls180.v:8079$2661_Y + attribute \src "ls180.v:8079.214-8079.247" + wire $eq$ls180.v:8079$2664_Y + attribute \src "ls180.v:8079.296-8079.329" + wire $eq$ls180.v:8079$2667_Y + attribute \src "ls180.v:8114.9-8114.42" + wire $eq$ls180.v:8114$2679_Y + attribute \src "ls180.v:8117.10-8117.43" + wire $eq$ls180.v:8117$2680_Y + attribute \src "ls180.v:8143.9-8143.42" + wire $eq$ls180.v:8143$2686_Y + attribute \src "ls180.v:8148.10-8148.43" + wire $eq$ls180.v:8148$2687_Y + attribute \src "ls180.v:8355.9-8355.53" + wire $eq$ls180.v:8355$2736_Y + attribute \src "ls180.v:8436.9-8436.54" + wire $eq$ls180.v:8436$2748_Y + attribute \src "ls180.v:8515.9-8515.55" + wire $eq$ls180.v:8515$2760_Y + attribute \src "ls180.v:8738.9-8738.49" + wire $eq$ls180.v:8738$2793_Y + attribute \src "ls180.v:8314.8-8314.54" + wire $ge$ls180.v:8314$2728_Y + attribute \src "ls180.v:8328.8-8328.54" + wire $ge$ls180.v:8328$2732_Y + attribute \src "ls180.v:5249.47-5249.83" + wire $gt$ls180.v:5249$1029_Y + attribute \src "ls180.v:5255.7-5255.43" + wire $lt$ls180.v:5255$1032_Y + attribute \src "ls180.v:8309.8-8309.43" + wire $lt$ls180.v:8309$2726_Y + attribute \src "ls180.v:8323.8-8323.43" + wire $lt$ls180.v:8323$2730_Y + attribute \src "ls180.v:10227.33-10227.36" + wire width 64 $memrd$\mem$ls180.v:10227$2847_DATA + attribute \src "ls180.v:10255.27-10255.32" + wire width 64 $memrd$\mem_1$ls180.v:10255$2873_DATA + attribute \src "ls180.v:10283.27-10283.32" + wire width 64 $memrd$\mem_2$ls180.v:10283$2899_DATA + attribute \src "ls180.v:10311.27-10311.32" + wire width 64 $memrd$\mem_3$ls180.v:10311$2925_DATA + attribute \src "ls180.v:10322.12-10322.19" + wire width 25 $memrd$\storage$ls180.v:10322$2930_DATA + attribute \src "ls180.v:10329.68-10329.75" + wire width 25 $memrd$\storage$ls180.v:10329$2932_DATA + attribute \src "ls180.v:10336.14-10336.23" + wire width 25 $memrd$\storage_1$ls180.v:10336$2937_DATA + attribute \src "ls180.v:10343.68-10343.77" + wire width 25 $memrd$\storage_1$ls180.v:10343$2939_DATA + attribute \src "ls180.v:10350.14-10350.23" + wire width 25 $memrd$\storage_2$ls180.v:10350$2944_DATA + attribute \src "ls180.v:10357.68-10357.77" + wire width 25 $memrd$\storage_2$ls180.v:10357$2946_DATA + attribute \src "ls180.v:10364.14-10364.23" + wire width 25 $memrd$\storage_3$ls180.v:10364$2951_DATA + attribute \src "ls180.v:10371.68-10371.77" + wire width 25 $memrd$\storage_3$ls180.v:10371$2953_DATA + attribute \src "ls180.v:10379.14-10379.23" + wire width 10 $memrd$\storage_4$ls180.v:10379$2958_DATA + attribute \src "ls180.v:10384.15-10384.24" + wire width 10 $memrd$\storage_4$ls180.v:10384$2960_DATA + attribute \src "ls180.v:10396.14-10396.23" + wire width 10 $memrd$\storage_5$ls180.v:10396$2965_DATA + attribute \src "ls180.v:10401.15-10401.24" + wire width 10 $memrd$\storage_5$ls180.v:10401$2967_DATA + attribute \src "ls180.v:10412.14-10412.23" + wire width 10 $memrd$\storage_6$ls180.v:10412$2972_DATA + attribute \src "ls180.v:10419.45-10419.54" + wire width 10 $memrd$\storage_6$ls180.v:10419$2974_DATA + attribute \src "ls180.v:10426.14-10426.23" + wire width 10 $memrd$\storage_7$ls180.v:10426$2979_DATA + attribute \src "ls180.v:10433.45-10433.54" + wire width 10 $memrd$\storage_7$ls180.v:10433$2981_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem$ls180.v:10209$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10209$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10209$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem$ls180.v:10211$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10211$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10211$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem$ls180.v:10213$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10213$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10213$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem$ls180.v:10215$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10215$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10215$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem$ls180.v:10217$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10217$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10217$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem$ls180.v:10219$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10219$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10219$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem$ls180.v:10221$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10221$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10221$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem$ls180.v:10223$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10223$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10223$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_1$ls180.v:10237$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10237$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10237$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_1$ls180.v:10239$10_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10239$10_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10239$10_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_1$ls180.v:10241$11_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10241$11_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10241$11_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_1$ls180.v:10243$12_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10243$12_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10243$12_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_1$ls180.v:10245$13_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10245$13_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10245$13_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_1$ls180.v:10247$14_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10247$14_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10247$14_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_1$ls180.v:10249$15_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10249$15_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10249$15_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_1$ls180.v:10251$16_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10251$16_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10251$16_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_2$ls180.v:10265$17_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10265$17_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10265$17_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_2$ls180.v:10267$18_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10267$18_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10267$18_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_2$ls180.v:10269$19_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10269$19_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10269$19_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_2$ls180.v:10271$20_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10271$20_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10271$20_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_2$ls180.v:10273$21_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10273$21_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10273$21_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_2$ls180.v:10275$22_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10275$22_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10275$22_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_2$ls180.v:10277$23_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10277$23_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10277$23_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_2$ls180.v:10279$24_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10279$24_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10279$24_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_3$ls180.v:10293$25_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10293$25_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10293$25_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_3$ls180.v:10295$26_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10295$26_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10295$26_EN + attribute \src "ls180.v:0.0-0.0" + wire width 9 $memwr$\mem_3$ls180.v:10297$27_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10045$1_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10297$27_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10045$1_DATA + wire width 64 $memwr$\mem_3$ls180.v:10297$27_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10045$1_EN + wire width 9 $memwr$\mem_3$ls180.v:10299$28_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10047$2_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10299$28_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10047$2_DATA + wire width 64 $memwr$\mem_3$ls180.v:10299$28_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10047$2_EN + wire width 9 $memwr$\mem_3$ls180.v:10301$29_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10049$3_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10301$29_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10049$3_DATA + wire width 64 $memwr$\mem_3$ls180.v:10301$29_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10049$3_EN + wire width 9 $memwr$\mem_3$ls180.v:10303$30_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10051$4_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10303$30_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10051$4_DATA + wire width 64 $memwr$\mem_3$ls180.v:10303$30_EN attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10051$4_EN + wire width 9 $memwr$\mem_3$ls180.v:10305$31_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage$ls180.v:10065$5_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10305$31_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10065$5_DATA + wire width 64 $memwr$\mem_3$ls180.v:10305$31_EN attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10065$5_EN + wire width 9 $memwr$\mem_3$ls180.v:10307$32_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_1$ls180.v:10079$6_ADDR + wire width 64 $memwr$\mem_3$ls180.v:10307$32_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10079$6_DATA + wire width 64 $memwr$\mem_3$ls180.v:10307$32_EN attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10079$6_EN + wire width 3 $memwr$\storage$ls180.v:10321$33_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_2$ls180.v:10093$7_ADDR + wire width 25 $memwr$\storage$ls180.v:10321$33_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10093$7_DATA + wire width 25 $memwr$\storage$ls180.v:10321$33_EN attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10093$7_EN + wire width 3 $memwr$\storage_1$ls180.v:10335$34_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_3$ls180.v:10107$8_ADDR + wire width 25 $memwr$\storage_1$ls180.v:10335$34_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10107$8_DATA + wire width 25 $memwr$\storage_1$ls180.v:10335$34_EN attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10107$8_EN + wire width 3 $memwr$\storage_2$ls180.v:10349$35_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_4$ls180.v:10122$9_ADDR + wire width 25 $memwr$\storage_2$ls180.v:10349$35_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10122$9_DATA + wire width 25 $memwr$\storage_2$ls180.v:10349$35_EN attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10122$9_EN + wire width 3 $memwr$\storage_3$ls180.v:10363$36_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_5$ls180.v:10139$10_ADDR + wire width 25 $memwr$\storage_3$ls180.v:10363$36_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10139$10_DATA + wire width 25 $memwr$\storage_3$ls180.v:10363$36_EN attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10139$10_EN + wire width 4 $memwr$\storage_4$ls180.v:10378$37_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_6$ls180.v:10155$11_ADDR + wire width 10 $memwr$\storage_4$ls180.v:10378$37_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10155$11_DATA + wire width 10 $memwr$\storage_4$ls180.v:10378$37_EN attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10155$11_EN + wire width 4 $memwr$\storage_5$ls180.v:10395$38_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_7$ls180.v:10169$12_ADDR + wire width 10 $memwr$\storage_5$ls180.v:10395$38_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10169$12_DATA + wire width 10 $memwr$\storage_5$ls180.v:10395$38_EN attribute \src "ls180.v:0.0-0.0" - wire width 10 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"ls180.v:4194.91-4194.111" + wire $not$ls180.v:4194$669_Y + attribute \src "ls180.v:4210.35-4210.64" + wire $not$ls180.v:4210$678_Y + attribute \src "ls180.v:4211.36-4211.67" + wire $not$ls180.v:4211$679_Y + attribute \src "ls180.v:4217.32-4217.61" + wire $not$ls180.v:4217$680_Y + attribute \src "ls180.v:4223.36-4223.67" + wire $not$ls180.v:4223$681_Y + attribute \src "ls180.v:4224.35-4224.64" + wire $not$ls180.v:4224$682_Y + attribute \src "ls180.v:4227.32-4227.63" + wire $not$ls180.v:4227$685_Y + attribute \src "ls180.v:4265.81-4265.108" + wire $not$ls180.v:4265$695_Y + attribute \src "ls180.v:4295.81-4295.108" + wire $not$ls180.v:4295$706_Y + attribute \src "ls180.v:4495.60-4495.85" + wire $not$ls180.v:4495$755_Y + attribute \src "ls180.v:4636.54-4636.96" + wire $not$ls180.v:4636$769_Y + attribute \src "ls180.v:4639.48-4639.86" + wire $not$ls180.v:4639$772_Y + attribute \src "ls180.v:4763.55-4763.98" + wire $not$ls180.v:4763$790_Y + attribute \src "ls180.v:4766.49-4766.88" + wire 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$xor$ls180.v:4926$723_Y - attribute \src "ls180.v:4926.160-4926.273" - wire $xor$ls180.v:4926$724_Y - attribute \src "ls180.v:4927.353-4927.425" - wire $xor$ls180.v:4927$725_Y - attribute \src "ls180.v:4927.200-4927.272" - wire $xor$ls180.v:4927$726_Y - attribute \src "ls180.v:4927.160-4927.273" - wire $xor$ls180.v:4927$727_Y - attribute \src "ls180.v:4928.353-4928.425" - wire $xor$ls180.v:4928$728_Y - attribute \src "ls180.v:4928.200-4928.272" - wire $xor$ls180.v:4928$729_Y - attribute \src "ls180.v:4928.160-4928.273" - wire $xor$ls180.v:4928$730_Y - attribute \src "ls180.v:4929.353-4929.425" - wire $xor$ls180.v:4929$731_Y - attribute \src "ls180.v:4929.200-4929.272" - wire $xor$ls180.v:4929$732_Y - attribute \src "ls180.v:4929.160-4929.273" - wire $xor$ls180.v:4929$733_Y - attribute \src "ls180.v:4930.353-4930.425" - wire $xor$ls180.v:4930$734_Y - attribute \src "ls180.v:4930.200-4930.272" - wire $xor$ls180.v:4930$735_Y - attribute \src "ls180.v:4930.160-4930.273" - wire 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$xor$ls180.v:4935$749_Y - attribute \src "ls180.v:4935.205-4935.278" - wire $xor$ls180.v:4935$750_Y - attribute \src "ls180.v:4935.164-4935.279" - wire $xor$ls180.v:4935$751_Y - attribute \src "ls180.v:4936.361-4936.434" - wire $xor$ls180.v:4936$752_Y - attribute \src "ls180.v:4936.205-4936.278" - wire $xor$ls180.v:4936$753_Y - attribute \src "ls180.v:4936.164-4936.279" - wire $xor$ls180.v:4936$754_Y - attribute \src "ls180.v:4937.361-4937.434" - wire $xor$ls180.v:4937$755_Y - attribute \src "ls180.v:4937.205-4937.278" - wire $xor$ls180.v:4937$756_Y - attribute \src "ls180.v:4937.164-4937.279" - wire $xor$ls180.v:4937$757_Y - attribute \src "ls180.v:4938.361-4938.434" - wire $xor$ls180.v:4938$758_Y - attribute \src "ls180.v:4938.205-4938.278" - wire $xor$ls180.v:4938$759_Y - attribute \src "ls180.v:4938.164-4938.279" - wire $xor$ls180.v:4938$760_Y - attribute \src "ls180.v:4939.361-4939.434" - wire $xor$ls180.v:4939$761_Y - attribute \src "ls180.v:4939.205-4939.278" - wire $xor$ls180.v:4939$762_Y - attribute \src "ls180.v:4939.164-4939.279" - wire $xor$ls180.v:4939$763_Y - attribute \src "ls180.v:4940.361-4940.434" - wire $xor$ls180.v:4940$764_Y - attribute \src "ls180.v:4940.205-4940.278" - wire $xor$ls180.v:4940$765_Y - attribute \src "ls180.v:4940.164-4940.279" - wire $xor$ls180.v:4940$766_Y - attribute \src "ls180.v:4941.361-4941.434" - wire $xor$ls180.v:4941$767_Y - attribute \src "ls180.v:4941.205-4941.278" - wire $xor$ls180.v:4941$768_Y - attribute \src "ls180.v:4941.164-4941.279" - wire $xor$ls180.v:4941$769_Y - attribute \src "ls180.v:4942.361-4942.434" - wire $xor$ls180.v:4942$770_Y - attribute \src "ls180.v:4942.205-4942.278" - wire $xor$ls180.v:4942$771_Y - attribute \src "ls180.v:4942.164-4942.279" - wire $xor$ls180.v:4942$772_Y - attribute \src "ls180.v:4943.361-4943.434" - wire $xor$ls180.v:4943$773_Y - attribute \src "ls180.v:4943.205-4943.278" - wire $xor$ls180.v:4943$774_Y - attribute \src "ls180.v:4943.164-4943.279" - wire $xor$ls180.v:4943$775_Y - attribute \src "ls180.v:4944.361-4944.434" - wire $xor$ls180.v:4944$776_Y - attribute \src "ls180.v:4944.205-4944.278" - wire $xor$ls180.v:4944$777_Y - attribute \src "ls180.v:4944.164-4944.279" - wire $xor$ls180.v:4944$778_Y - attribute \src "ls180.v:4945.361-4945.434" - wire $xor$ls180.v:4945$779_Y - attribute \src "ls180.v:4945.205-4945.278" - wire $xor$ls180.v:4945$780_Y - attribute \src "ls180.v:4945.164-4945.279" - wire $xor$ls180.v:4945$781_Y - attribute \src "ls180.v:4946.361-4946.434" - wire $xor$ls180.v:4946$782_Y - attribute \src "ls180.v:4946.205-4946.278" - wire $xor$ls180.v:4946$783_Y - attribute \src "ls180.v:4946.164-4946.279" - wire $xor$ls180.v:4946$784_Y - attribute \src "ls180.v:4947.361-4947.434" - wire $xor$ls180.v:4947$785_Y - attribute \src "ls180.v:4947.205-4947.278" - wire $xor$ls180.v:4947$786_Y - attribute \src "ls180.v:4947.164-4947.279" - wire $xor$ls180.v:4947$787_Y - attribute \src "ls180.v:4948.361-4948.434" - wire $xor$ls180.v:4948$788_Y - attribute \src "ls180.v:4948.205-4948.278" - wire $xor$ls180.v:4948$789_Y - attribute \src "ls180.v:4948.164-4948.279" - wire $xor$ls180.v:4948$790_Y - attribute \src "ls180.v:4949.361-4949.434" - wire $xor$ls180.v:4949$791_Y - attribute \src "ls180.v:4949.205-4949.278" - wire $xor$ls180.v:4949$792_Y - attribute \src "ls180.v:4949.164-4949.279" - wire $xor$ls180.v:4949$793_Y - attribute \src "ls180.v:4950.361-4950.434" - wire $xor$ls180.v:4950$794_Y - attribute \src "ls180.v:4950.205-4950.278" - wire $xor$ls180.v:4950$795_Y - attribute \src "ls180.v:4950.164-4950.279" - wire $xor$ls180.v:4950$796_Y - attribute \src "ls180.v:4951.361-4951.434" - wire $xor$ls180.v:4951$797_Y - attribute \src "ls180.v:4951.205-4951.278" - wire $xor$ls180.v:4951$798_Y - attribute \src "ls180.v:4951.164-4951.279" - wire $xor$ls180.v:4951$799_Y - attribute \src "ls180.v:4952.360-4952.432" - wire $xor$ls180.v:4952$800_Y - attribute \src "ls180.v:4952.205-4952.277" - wire $xor$ls180.v:4952$801_Y - attribute \src "ls180.v:4952.164-4952.278" - wire $xor$ls180.v:4952$802_Y - attribute \src "ls180.v:4953.360-4953.432" - wire $xor$ls180.v:4953$803_Y - attribute \src "ls180.v:4953.205-4953.277" - wire $xor$ls180.v:4953$804_Y - attribute \src "ls180.v:4953.164-4953.278" - wire $xor$ls180.v:4953$805_Y - attribute \src "ls180.v:4954.360-4954.432" - wire $xor$ls180.v:4954$806_Y - attribute \src "ls180.v:4954.205-4954.277" - wire $xor$ls180.v:4954$807_Y - attribute \src "ls180.v:4954.164-4954.278" - wire $xor$ls180.v:4954$808_Y - attribute \src "ls180.v:4955.360-4955.432" - wire $xor$ls180.v:4955$809_Y - attribute \src "ls180.v:4955.205-4955.277" - wire $xor$ls180.v:4955$810_Y - attribute \src "ls180.v:4955.164-4955.278" - wire $xor$ls180.v:4955$811_Y - attribute \src "ls180.v:4956.360-4956.432" - wire $xor$ls180.v:4956$812_Y - attribute \src "ls180.v:4956.205-4956.277" - wire $xor$ls180.v:4956$813_Y - attribute \src "ls180.v:4956.164-4956.278" - wire $xor$ls180.v:4956$814_Y - attribute \src "ls180.v:4957.360-4957.432" - wire $xor$ls180.v:4957$815_Y - attribute \src "ls180.v:4957.205-4957.277" - wire $xor$ls180.v:4957$816_Y - attribute \src "ls180.v:4957.164-4957.278" - wire $xor$ls180.v:4957$817_Y - attribute \src "ls180.v:4958.360-4958.432" - wire $xor$ls180.v:4958$818_Y - attribute \src "ls180.v:4958.205-4958.277" - wire $xor$ls180.v:4958$819_Y - attribute \src "ls180.v:4958.164-4958.278" - wire $xor$ls180.v:4958$820_Y - attribute \src "ls180.v:4959.360-4959.432" - wire $xor$ls180.v:4959$821_Y - attribute \src "ls180.v:4959.205-4959.277" - wire $xor$ls180.v:4959$822_Y - attribute \src "ls180.v:4959.164-4959.278" - wire $xor$ls180.v:4959$823_Y - attribute \src "ls180.v:4960.360-4960.432" - wire $xor$ls180.v:4960$824_Y - attribute \src "ls180.v:4960.205-4960.277" - wire $xor$ls180.v:4960$825_Y - attribute \src "ls180.v:4960.164-4960.278" - wire $xor$ls180.v:4960$826_Y - attribute \src "ls180.v:4961.360-4961.432" - wire $xor$ls180.v:4961$827_Y - attribute \src "ls180.v:4961.205-4961.277" - wire $xor$ls180.v:4961$828_Y - attribute \src "ls180.v:4961.164-4961.278" - wire $xor$ls180.v:4961$829_Y - attribute \src "ls180.v:4982.899-4982.983" - wire $xor$ls180.v:4982$843_Y - attribute \src "ls180.v:4982.634-4982.718" - wire $xor$ls180.v:4982$844_Y - attribute \src "ls180.v:4982.588-4982.719" - wire $xor$ls180.v:4982$845_Y - attribute \src "ls180.v:4982.234-4982.318" - wire $xor$ls180.v:4982$846_Y - attribute \src "ls180.v:4982.187-4982.319" - wire $xor$ls180.v:4982$847_Y - attribute \src "ls180.v:4983.899-4983.983" - wire $xor$ls180.v:4983$848_Y - attribute \src "ls180.v:4983.634-4983.718" - wire $xor$ls180.v:4983$849_Y - attribute \src "ls180.v:4983.588-4983.719" - wire $xor$ls180.v:4983$850_Y - attribute \src "ls180.v:4983.234-4983.318" - wire $xor$ls180.v:4983$851_Y - attribute \src "ls180.v:4983.187-4983.319" - wire $xor$ls180.v:4983$852_Y - attribute \src "ls180.v:4992.899-4992.983" - wire $xor$ls180.v:4992$854_Y - attribute \src "ls180.v:4992.634-4992.718" - wire $xor$ls180.v:4992$855_Y - attribute \src "ls180.v:4992.588-4992.719" - wire $xor$ls180.v:4992$856_Y - attribute \src "ls180.v:4992.234-4992.318" - wire $xor$ls180.v:4992$857_Y - attribute \src "ls180.v:4992.187-4992.319" - wire $xor$ls180.v:4992$858_Y - attribute \src "ls180.v:4993.899-4993.983" - wire $xor$ls180.v:4993$859_Y - attribute \src "ls180.v:4993.634-4993.718" - wire $xor$ls180.v:4993$860_Y - attribute \src "ls180.v:4993.588-4993.719" - wire $xor$ls180.v:4993$861_Y - attribute \src "ls180.v:4993.234-4993.318" - wire $xor$ls180.v:4993$862_Y - attribute \src "ls180.v:4993.187-4993.319" - wire $xor$ls180.v:4993$863_Y - attribute \src "ls180.v:5002.899-5002.983" - wire $xor$ls180.v:5002$865_Y - attribute \src "ls180.v:5002.634-5002.718" - wire $xor$ls180.v:5002$866_Y - attribute \src "ls180.v:5002.588-5002.719" - wire $xor$ls180.v:5002$867_Y - attribute \src "ls180.v:5002.234-5002.318" - wire $xor$ls180.v:5002$868_Y - attribute \src "ls180.v:5002.187-5002.319" - wire $xor$ls180.v:5002$869_Y - attribute \src "ls180.v:5003.899-5003.983" - wire $xor$ls180.v:5003$870_Y - attribute \src "ls180.v:5003.634-5003.718" - wire $xor$ls180.v:5003$871_Y - attribute \src "ls180.v:5003.588-5003.719" - wire $xor$ls180.v:5003$872_Y - attribute \src "ls180.v:5003.234-5003.318" - wire $xor$ls180.v:5003$873_Y - attribute \src "ls180.v:5003.187-5003.319" - wire $xor$ls180.v:5003$874_Y - attribute \src "ls180.v:5012.899-5012.983" - wire $xor$ls180.v:5012$876_Y - attribute \src "ls180.v:5012.634-5012.718" - wire $xor$ls180.v:5012$877_Y - attribute \src "ls180.v:5012.588-5012.719" - wire $xor$ls180.v:5012$878_Y - attribute \src "ls180.v:5012.234-5012.318" - wire $xor$ls180.v:5012$879_Y - attribute \src "ls180.v:5012.187-5012.319" - wire $xor$ls180.v:5012$880_Y - attribute \src "ls180.v:5013.899-5013.983" - wire $xor$ls180.v:5013$881_Y - attribute \src "ls180.v:5013.634-5013.718" - wire $xor$ls180.v:5013$882_Y - attribute \src "ls180.v:5013.588-5013.719" - wire $xor$ls180.v:5013$883_Y - attribute \src "ls180.v:5013.234-5013.318" - wire $xor$ls180.v:5013$884_Y - attribute \src "ls180.v:5013.187-5013.319" - wire $xor$ls180.v:5013$885_Y - attribute \src "ls180.v:5164.879-5164.961" - wire $xor$ls180.v:5164$918_Y - attribute \src "ls180.v:5164.620-5164.702" - wire $xor$ls180.v:5164$919_Y - attribute \src "ls180.v:5164.575-5164.703" - wire $xor$ls180.v:5164$920_Y - attribute \src "ls180.v:5164.229-5164.311" - wire $xor$ls180.v:5164$921_Y - attribute \src "ls180.v:5164.183-5164.312" - wire $xor$ls180.v:5164$922_Y - attribute \src "ls180.v:5165.879-5165.961" - wire $xor$ls180.v:5165$923_Y - attribute \src "ls180.v:5165.620-5165.702" - wire $xor$ls180.v:5165$924_Y - attribute \src "ls180.v:5165.575-5165.703" - wire $xor$ls180.v:5165$925_Y - attribute \src "ls180.v:5165.229-5165.311" - wire $xor$ls180.v:5165$926_Y - attribute \src "ls180.v:5165.183-5165.312" - wire $xor$ls180.v:5165$927_Y - attribute \src "ls180.v:5174.879-5174.961" - wire $xor$ls180.v:5174$929_Y - attribute \src "ls180.v:5174.620-5174.702" - wire $xor$ls180.v:5174$930_Y - attribute \src "ls180.v:5174.575-5174.703" - wire $xor$ls180.v:5174$931_Y - attribute \src "ls180.v:5174.229-5174.311" - wire $xor$ls180.v:5174$932_Y - attribute \src "ls180.v:5174.183-5174.312" - wire $xor$ls180.v:5174$933_Y - attribute \src "ls180.v:5175.879-5175.961" - wire $xor$ls180.v:5175$934_Y - attribute \src "ls180.v:5175.620-5175.702" - wire $xor$ls180.v:5175$935_Y - attribute \src "ls180.v:5175.575-5175.703" - wire $xor$ls180.v:5175$936_Y - attribute \src "ls180.v:5175.229-5175.311" - wire $xor$ls180.v:5175$937_Y - attribute \src "ls180.v:5175.183-5175.312" - wire $xor$ls180.v:5175$938_Y - attribute \src "ls180.v:5184.879-5184.961" - wire $xor$ls180.v:5184$940_Y - attribute \src "ls180.v:5184.620-5184.702" - wire $xor$ls180.v:5184$941_Y - attribute \src "ls180.v:5184.575-5184.703" - wire $xor$ls180.v:5184$942_Y - attribute \src "ls180.v:5184.229-5184.311" - wire $xor$ls180.v:5184$943_Y - attribute \src "ls180.v:5184.183-5184.312" - wire $xor$ls180.v:5184$944_Y - attribute \src "ls180.v:5185.879-5185.961" - wire $xor$ls180.v:5185$945_Y - attribute \src "ls180.v:5185.620-5185.702" - wire $xor$ls180.v:5185$946_Y - attribute \src "ls180.v:5185.575-5185.703" - wire $xor$ls180.v:5185$947_Y - attribute \src "ls180.v:5185.229-5185.311" - wire $xor$ls180.v:5185$948_Y - attribute \src "ls180.v:5185.183-5185.312" - wire $xor$ls180.v:5185$949_Y - attribute \src "ls180.v:5194.879-5194.961" - wire $xor$ls180.v:5194$951_Y - attribute \src "ls180.v:5194.620-5194.702" - wire $xor$ls180.v:5194$952_Y - attribute \src "ls180.v:5194.575-5194.703" - wire $xor$ls180.v:5194$953_Y - attribute \src "ls180.v:5194.229-5194.311" - wire $xor$ls180.v:5194$954_Y - attribute \src "ls180.v:5194.183-5194.312" - wire $xor$ls180.v:5194$955_Y - attribute \src "ls180.v:5195.879-5195.961" - wire $xor$ls180.v:5195$956_Y - attribute \src "ls180.v:5195.620-5195.702" - wire $xor$ls180.v:5195$957_Y - attribute \src "ls180.v:5195.575-5195.703" - wire $xor$ls180.v:5195$958_Y - attribute \src "ls180.v:5195.229-5195.311" - wire $xor$ls180.v:5195$959_Y - attribute \src "ls180.v:5195.183-5195.312" - wire $xor$ls180.v:5195$960_Y - attribute \src "ls180.v:1745.11-1745.42" + wire width 3 $sub$ls180.v:8071$2644_Y + attribute \src "ls180.v:8198.33-8198.64" + wire width 5 $sub$ls180.v:8198$2703_Y + attribute \src "ls180.v:8220.33-8220.64" + wire width 5 $sub$ls180.v:8220$2714_Y + attribute \src "ls180.v:8255.34-8255.66" + wire width 3 $sub$ls180.v:8255$2719_Y + attribute \src "ls180.v:8290.32-8290.62" + wire width 3 $sub$ls180.v:8290$2724_Y + attribute \src "ls180.v:8314.30-8314.53" + wire width 32 $sub$ls180.v:8314$2727_Y + attribute \src "ls180.v:8328.30-8328.53" + wire width 32 $sub$ls180.v:8328$2731_Y + attribute \src "ls180.v:8731.36-8731.70" + wire width 6 $sub$ls180.v:8731$2792_Y + attribute \src "ls180.v:8829.36-8829.70" + wire width 6 $sub$ls180.v:8829$2814_Y + attribute \src "ls180.v:8942.22-8942.42" + wire width 20 $sub$ls180.v:8942$2821_Y + attribute \src "ls180.v:5020.353-5020.425" + wire $xor$ls180.v:5020$825_Y + attribute \src "ls180.v:5020.200-5020.272" + wire $xor$ls180.v:5020$826_Y + attribute \src "ls180.v:5020.160-5020.273" + wire $xor$ls180.v:5020$827_Y + attribute \src "ls180.v:5021.353-5021.425" + wire $xor$ls180.v:5021$828_Y + attribute \src "ls180.v:5021.200-5021.272" + wire $xor$ls180.v:5021$829_Y + attribute \src "ls180.v:5021.160-5021.273" + wire $xor$ls180.v:5021$830_Y + attribute \src "ls180.v:5022.353-5022.425" + wire $xor$ls180.v:5022$831_Y + attribute \src "ls180.v:5022.200-5022.272" + wire $xor$ls180.v:5022$832_Y + attribute \src "ls180.v:5022.160-5022.273" + wire $xor$ls180.v:5022$833_Y + attribute \src "ls180.v:5023.353-5023.425" + wire $xor$ls180.v:5023$834_Y + attribute \src "ls180.v:5023.200-5023.272" + wire $xor$ls180.v:5023$835_Y + attribute \src "ls180.v:5023.160-5023.273" + wire $xor$ls180.v:5023$836_Y + attribute \src "ls180.v:5024.353-5024.425" + wire $xor$ls180.v:5024$837_Y + attribute \src "ls180.v:5024.200-5024.272" + wire $xor$ls180.v:5024$838_Y + attribute \src "ls180.v:5024.160-5024.273" + wire $xor$ls180.v:5024$839_Y + attribute \src "ls180.v:5025.353-5025.425" + wire $xor$ls180.v:5025$840_Y + attribute \src "ls180.v:5025.200-5025.272" + wire $xor$ls180.v:5025$841_Y + attribute \src "ls180.v:5025.160-5025.273" + wire $xor$ls180.v:5025$842_Y + attribute \src "ls180.v:5026.353-5026.425" + wire $xor$ls180.v:5026$843_Y + attribute \src "ls180.v:5026.200-5026.272" + wire $xor$ls180.v:5026$844_Y + attribute \src "ls180.v:5026.160-5026.273" + wire $xor$ls180.v:5026$845_Y + attribute \src "ls180.v:5027.353-5027.425" + wire $xor$ls180.v:5027$846_Y + attribute \src "ls180.v:5027.200-5027.272" + wire $xor$ls180.v:5027$847_Y + attribute \src "ls180.v:5027.160-5027.273" + wire $xor$ls180.v:5027$848_Y + attribute \src "ls180.v:5028.353-5028.425" + wire $xor$ls180.v:5028$849_Y + attribute \src "ls180.v:5028.200-5028.272" + wire $xor$ls180.v:5028$850_Y + attribute \src "ls180.v:5028.160-5028.273" + wire $xor$ls180.v:5028$851_Y + attribute \src "ls180.v:5029.354-5029.426" + wire $xor$ls180.v:5029$852_Y + attribute \src "ls180.v:5029.201-5029.273" + wire $xor$ls180.v:5029$853_Y + attribute \src "ls180.v:5029.161-5029.274" + wire $xor$ls180.v:5029$854_Y + attribute \src "ls180.v:5030.361-5030.434" + wire $xor$ls180.v:5030$855_Y + attribute \src "ls180.v:5030.205-5030.278" + wire $xor$ls180.v:5030$856_Y + attribute \src "ls180.v:5030.164-5030.279" + wire $xor$ls180.v:5030$857_Y + attribute \src "ls180.v:5031.361-5031.434" + wire $xor$ls180.v:5031$858_Y + attribute \src "ls180.v:5031.205-5031.278" + wire $xor$ls180.v:5031$859_Y + attribute \src "ls180.v:5031.164-5031.279" + wire $xor$ls180.v:5031$860_Y + attribute \src "ls180.v:5032.361-5032.434" + wire $xor$ls180.v:5032$861_Y + attribute \src "ls180.v:5032.205-5032.278" + wire $xor$ls180.v:5032$862_Y + attribute \src "ls180.v:5032.164-5032.279" + wire $xor$ls180.v:5032$863_Y + attribute \src "ls180.v:5033.361-5033.434" + wire $xor$ls180.v:5033$864_Y + attribute \src "ls180.v:5033.205-5033.278" + wire $xor$ls180.v:5033$865_Y + attribute \src "ls180.v:5033.164-5033.279" + wire $xor$ls180.v:5033$866_Y + attribute \src "ls180.v:5034.361-5034.434" + wire $xor$ls180.v:5034$867_Y + attribute \src "ls180.v:5034.205-5034.278" + wire $xor$ls180.v:5034$868_Y + attribute \src "ls180.v:5034.164-5034.279" + wire $xor$ls180.v:5034$869_Y + attribute \src "ls180.v:5035.361-5035.434" + wire $xor$ls180.v:5035$870_Y + attribute \src "ls180.v:5035.205-5035.278" + wire $xor$ls180.v:5035$871_Y + attribute \src "ls180.v:5035.164-5035.279" + wire $xor$ls180.v:5035$872_Y + attribute \src "ls180.v:5036.361-5036.434" + wire $xor$ls180.v:5036$873_Y + attribute \src "ls180.v:5036.205-5036.278" + wire $xor$ls180.v:5036$874_Y + attribute \src "ls180.v:5036.164-5036.279" + wire $xor$ls180.v:5036$875_Y + attribute \src "ls180.v:5037.361-5037.434" + wire $xor$ls180.v:5037$876_Y + attribute \src "ls180.v:5037.205-5037.278" + wire $xor$ls180.v:5037$877_Y + attribute \src "ls180.v:5037.164-5037.279" + wire $xor$ls180.v:5037$878_Y + attribute \src "ls180.v:5038.361-5038.434" + wire $xor$ls180.v:5038$879_Y + attribute \src "ls180.v:5038.205-5038.278" + wire $xor$ls180.v:5038$880_Y + attribute \src "ls180.v:5038.164-5038.279" + wire $xor$ls180.v:5038$881_Y + attribute \src "ls180.v:5039.361-5039.434" + wire $xor$ls180.v:5039$882_Y + attribute \src "ls180.v:5039.205-5039.278" + wire $xor$ls180.v:5039$883_Y + attribute \src "ls180.v:5039.164-5039.279" + wire $xor$ls180.v:5039$884_Y + attribute \src "ls180.v:5040.361-5040.434" + wire $xor$ls180.v:5040$885_Y + attribute \src "ls180.v:5040.205-5040.278" + wire $xor$ls180.v:5040$886_Y + attribute \src "ls180.v:5040.164-5040.279" + wire $xor$ls180.v:5040$887_Y + attribute \src "ls180.v:5041.361-5041.434" + wire $xor$ls180.v:5041$888_Y + attribute \src "ls180.v:5041.205-5041.278" + wire $xor$ls180.v:5041$889_Y + attribute \src "ls180.v:5041.164-5041.279" + wire $xor$ls180.v:5041$890_Y + attribute \src "ls180.v:5042.361-5042.434" + wire $xor$ls180.v:5042$891_Y + attribute \src "ls180.v:5042.205-5042.278" + wire $xor$ls180.v:5042$892_Y + attribute \src "ls180.v:5042.164-5042.279" + wire $xor$ls180.v:5042$893_Y + attribute \src "ls180.v:5043.361-5043.434" + wire $xor$ls180.v:5043$894_Y + attribute \src "ls180.v:5043.205-5043.278" + wire $xor$ls180.v:5043$895_Y + attribute \src "ls180.v:5043.164-5043.279" + wire $xor$ls180.v:5043$896_Y + attribute \src "ls180.v:5044.361-5044.434" + wire $xor$ls180.v:5044$897_Y + attribute \src "ls180.v:5044.205-5044.278" + wire $xor$ls180.v:5044$898_Y + attribute \src "ls180.v:5044.164-5044.279" + wire $xor$ls180.v:5044$899_Y + attribute \src "ls180.v:5045.361-5045.434" + wire $xor$ls180.v:5045$900_Y + attribute \src "ls180.v:5045.205-5045.278" + wire $xor$ls180.v:5045$901_Y + attribute \src "ls180.v:5045.164-5045.279" + wire $xor$ls180.v:5045$902_Y + attribute \src "ls180.v:5046.361-5046.434" + wire $xor$ls180.v:5046$903_Y + attribute \src "ls180.v:5046.205-5046.278" + wire $xor$ls180.v:5046$904_Y + attribute \src "ls180.v:5046.164-5046.279" + wire $xor$ls180.v:5046$905_Y + attribute \src "ls180.v:5047.361-5047.434" + wire $xor$ls180.v:5047$906_Y + attribute \src "ls180.v:5047.205-5047.278" + wire $xor$ls180.v:5047$907_Y + attribute \src "ls180.v:5047.164-5047.279" + wire $xor$ls180.v:5047$908_Y + attribute \src "ls180.v:5048.361-5048.434" + wire $xor$ls180.v:5048$909_Y + attribute \src "ls180.v:5048.205-5048.278" + wire $xor$ls180.v:5048$910_Y + attribute \src "ls180.v:5048.164-5048.279" + wire $xor$ls180.v:5048$911_Y + attribute \src "ls180.v:5049.361-5049.434" + wire $xor$ls180.v:5049$912_Y + attribute \src "ls180.v:5049.205-5049.278" + wire $xor$ls180.v:5049$913_Y + attribute \src "ls180.v:5049.164-5049.279" + wire $xor$ls180.v:5049$914_Y + attribute \src "ls180.v:5050.360-5050.432" + wire $xor$ls180.v:5050$915_Y + attribute \src "ls180.v:5050.205-5050.277" + wire $xor$ls180.v:5050$916_Y + attribute \src "ls180.v:5050.164-5050.278" + wire $xor$ls180.v:5050$917_Y + attribute \src "ls180.v:5051.360-5051.432" + wire $xor$ls180.v:5051$918_Y + attribute \src "ls180.v:5051.205-5051.277" + wire $xor$ls180.v:5051$919_Y + attribute \src "ls180.v:5051.164-5051.278" + wire $xor$ls180.v:5051$920_Y + attribute \src "ls180.v:5052.360-5052.432" + wire $xor$ls180.v:5052$921_Y + attribute \src "ls180.v:5052.205-5052.277" + wire $xor$ls180.v:5052$922_Y + attribute \src "ls180.v:5052.164-5052.278" + wire $xor$ls180.v:5052$923_Y + attribute \src "ls180.v:5053.360-5053.432" + wire $xor$ls180.v:5053$924_Y + attribute \src "ls180.v:5053.205-5053.277" + wire $xor$ls180.v:5053$925_Y + attribute \src "ls180.v:5053.164-5053.278" + wire $xor$ls180.v:5053$926_Y + attribute \src "ls180.v:5054.360-5054.432" + wire $xor$ls180.v:5054$927_Y + attribute \src "ls180.v:5054.205-5054.277" + wire $xor$ls180.v:5054$928_Y + attribute \src "ls180.v:5054.164-5054.278" + wire $xor$ls180.v:5054$929_Y + attribute \src "ls180.v:5055.360-5055.432" + wire $xor$ls180.v:5055$930_Y + attribute \src "ls180.v:5055.205-5055.277" + wire $xor$ls180.v:5055$931_Y + attribute \src "ls180.v:5055.164-5055.278" + wire $xor$ls180.v:5055$932_Y + attribute \src "ls180.v:5056.360-5056.432" + wire $xor$ls180.v:5056$933_Y + attribute \src "ls180.v:5056.205-5056.277" + wire $xor$ls180.v:5056$934_Y + attribute \src "ls180.v:5056.164-5056.278" + wire $xor$ls180.v:5056$935_Y + attribute \src "ls180.v:5057.360-5057.432" + wire $xor$ls180.v:5057$936_Y + attribute \src "ls180.v:5057.205-5057.277" + wire $xor$ls180.v:5057$937_Y + attribute \src "ls180.v:5057.164-5057.278" + wire $xor$ls180.v:5057$938_Y + attribute \src "ls180.v:5058.360-5058.432" + wire $xor$ls180.v:5058$939_Y + attribute \src "ls180.v:5058.205-5058.277" + wire $xor$ls180.v:5058$940_Y + attribute \src "ls180.v:5058.164-5058.278" + wire $xor$ls180.v:5058$941_Y + attribute \src "ls180.v:5059.360-5059.432" + wire $xor$ls180.v:5059$942_Y + attribute \src "ls180.v:5059.205-5059.277" + wire $xor$ls180.v:5059$943_Y + attribute \src "ls180.v:5059.164-5059.278" + wire $xor$ls180.v:5059$944_Y + attribute \src "ls180.v:5080.899-5080.983" + wire $xor$ls180.v:5080$958_Y + attribute \src "ls180.v:5080.634-5080.718" + wire $xor$ls180.v:5080$959_Y + attribute \src "ls180.v:5080.588-5080.719" + wire $xor$ls180.v:5080$960_Y + attribute \src "ls180.v:5080.234-5080.318" + wire $xor$ls180.v:5080$961_Y + attribute \src "ls180.v:5080.187-5080.319" + wire $xor$ls180.v:5080$962_Y + attribute \src "ls180.v:5081.899-5081.983" + wire $xor$ls180.v:5081$963_Y + attribute \src "ls180.v:5081.634-5081.718" + wire $xor$ls180.v:5081$964_Y + attribute \src "ls180.v:5081.588-5081.719" + wire $xor$ls180.v:5081$965_Y + attribute \src "ls180.v:5081.234-5081.318" + wire $xor$ls180.v:5081$966_Y + attribute \src "ls180.v:5081.187-5081.319" + wire $xor$ls180.v:5081$967_Y + attribute \src "ls180.v:5090.899-5090.983" + wire $xor$ls180.v:5090$969_Y + attribute \src "ls180.v:5090.634-5090.718" + wire $xor$ls180.v:5090$970_Y + attribute \src "ls180.v:5090.588-5090.719" + wire $xor$ls180.v:5090$971_Y + attribute \src "ls180.v:5090.234-5090.318" + wire $xor$ls180.v:5090$972_Y + attribute \src "ls180.v:5090.187-5090.319" + wire $xor$ls180.v:5090$973_Y + attribute \src "ls180.v:5091.899-5091.983" + wire $xor$ls180.v:5091$974_Y + attribute \src "ls180.v:5091.634-5091.718" + wire $xor$ls180.v:5091$975_Y + attribute \src "ls180.v:5091.588-5091.719" + wire $xor$ls180.v:5091$976_Y + attribute \src "ls180.v:5091.234-5091.318" + wire $xor$ls180.v:5091$977_Y + attribute \src "ls180.v:5091.187-5091.319" + wire $xor$ls180.v:5091$978_Y + attribute \src "ls180.v:5100.899-5100.983" + wire $xor$ls180.v:5100$980_Y + attribute \src "ls180.v:5100.634-5100.718" + wire $xor$ls180.v:5100$981_Y + attribute \src "ls180.v:5100.588-5100.719" + wire $xor$ls180.v:5100$982_Y + attribute \src "ls180.v:5100.234-5100.318" + wire $xor$ls180.v:5100$983_Y + attribute \src "ls180.v:5100.187-5100.319" + wire $xor$ls180.v:5100$984_Y + attribute \src "ls180.v:5101.899-5101.983" + wire $xor$ls180.v:5101$985_Y + attribute \src "ls180.v:5101.634-5101.718" + wire $xor$ls180.v:5101$986_Y + attribute \src "ls180.v:5101.588-5101.719" + wire $xor$ls180.v:5101$987_Y + attribute \src "ls180.v:5101.234-5101.318" + wire $xor$ls180.v:5101$988_Y + attribute \src "ls180.v:5101.187-5101.319" + wire $xor$ls180.v:5101$989_Y + attribute \src "ls180.v:5110.899-5110.983" + wire $xor$ls180.v:5110$991_Y + attribute \src "ls180.v:5110.634-5110.718" + wire $xor$ls180.v:5110$992_Y + attribute \src "ls180.v:5110.588-5110.719" + wire $xor$ls180.v:5110$993_Y + attribute \src "ls180.v:5110.234-5110.318" + wire $xor$ls180.v:5110$994_Y + attribute \src "ls180.v:5110.187-5110.319" + wire $xor$ls180.v:5110$995_Y + attribute \src "ls180.v:5111.187-5111.319" + wire $xor$ls180.v:5111$1000_Y + attribute \src "ls180.v:5111.899-5111.983" + wire $xor$ls180.v:5111$996_Y + attribute \src "ls180.v:5111.634-5111.718" + wire $xor$ls180.v:5111$997_Y + attribute \src "ls180.v:5111.588-5111.719" + wire $xor$ls180.v:5111$998_Y + attribute \src "ls180.v:5111.234-5111.318" + wire $xor$ls180.v:5111$999_Y + attribute \src "ls180.v:5262.879-5262.961" + wire $xor$ls180.v:5262$1033_Y + attribute \src "ls180.v:5262.620-5262.702" + wire $xor$ls180.v:5262$1034_Y + attribute \src "ls180.v:5262.575-5262.703" + wire $xor$ls180.v:5262$1035_Y + attribute \src "ls180.v:5262.229-5262.311" + wire $xor$ls180.v:5262$1036_Y + attribute \src "ls180.v:5262.183-5262.312" + wire $xor$ls180.v:5262$1037_Y + attribute \src "ls180.v:5263.879-5263.961" + wire $xor$ls180.v:5263$1038_Y + attribute \src "ls180.v:5263.620-5263.702" + wire $xor$ls180.v:5263$1039_Y + attribute \src "ls180.v:5263.575-5263.703" + wire $xor$ls180.v:5263$1040_Y + attribute \src "ls180.v:5263.229-5263.311" + wire $xor$ls180.v:5263$1041_Y + attribute \src "ls180.v:5263.183-5263.312" + wire $xor$ls180.v:5263$1042_Y + attribute \src "ls180.v:5272.879-5272.961" + wire $xor$ls180.v:5272$1044_Y + attribute \src "ls180.v:5272.620-5272.702" + wire $xor$ls180.v:5272$1045_Y + attribute \src "ls180.v:5272.575-5272.703" + wire $xor$ls180.v:5272$1046_Y + attribute \src "ls180.v:5272.229-5272.311" + wire $xor$ls180.v:5272$1047_Y + attribute \src "ls180.v:5272.183-5272.312" + wire $xor$ls180.v:5272$1048_Y + attribute \src "ls180.v:5273.879-5273.961" + wire $xor$ls180.v:5273$1049_Y + attribute \src "ls180.v:5273.620-5273.702" + wire $xor$ls180.v:5273$1050_Y + attribute \src "ls180.v:5273.575-5273.703" + wire $xor$ls180.v:5273$1051_Y + attribute \src "ls180.v:5273.229-5273.311" + wire $xor$ls180.v:5273$1052_Y + attribute \src "ls180.v:5273.183-5273.312" + wire $xor$ls180.v:5273$1053_Y + attribute \src "ls180.v:5282.879-5282.961" + wire $xor$ls180.v:5282$1055_Y + attribute \src "ls180.v:5282.620-5282.702" + wire $xor$ls180.v:5282$1056_Y + attribute \src "ls180.v:5282.575-5282.703" + wire $xor$ls180.v:5282$1057_Y + attribute \src "ls180.v:5282.229-5282.311" + wire $xor$ls180.v:5282$1058_Y + attribute \src "ls180.v:5282.183-5282.312" + wire $xor$ls180.v:5282$1059_Y + attribute \src "ls180.v:5283.879-5283.961" + wire $xor$ls180.v:5283$1060_Y + attribute \src "ls180.v:5283.620-5283.702" + wire $xor$ls180.v:5283$1061_Y + attribute \src "ls180.v:5283.575-5283.703" + wire $xor$ls180.v:5283$1062_Y + attribute \src "ls180.v:5283.229-5283.311" + wire $xor$ls180.v:5283$1063_Y + attribute \src "ls180.v:5283.183-5283.312" + wire $xor$ls180.v:5283$1064_Y + attribute \src "ls180.v:5292.879-5292.961" + wire $xor$ls180.v:5292$1066_Y + attribute \src "ls180.v:5292.620-5292.702" + wire $xor$ls180.v:5292$1067_Y + attribute \src "ls180.v:5292.575-5292.703" + wire $xor$ls180.v:5292$1068_Y + attribute \src "ls180.v:5292.229-5292.311" + wire $xor$ls180.v:5292$1069_Y + attribute \src "ls180.v:5292.183-5292.312" + wire $xor$ls180.v:5292$1070_Y + attribute \src "ls180.v:5293.879-5293.961" + wire $xor$ls180.v:5293$1071_Y + attribute \src "ls180.v:5293.620-5293.702" + wire $xor$ls180.v:5293$1072_Y + attribute \src "ls180.v:5293.575-5293.703" + wire $xor$ls180.v:5293$1073_Y + attribute \src "ls180.v:5293.229-5293.311" + wire $xor$ls180.v:5293$1074_Y + attribute \src "ls180.v:5293.183-5293.312" + wire $xor$ls180.v:5293$1075_Y + attribute \src "ls180.v:1789.11-1789.42" wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1744.11-1744.37" + attribute \src "ls180.v:1788.11-1788.37" wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1747.11-1747.42" + attribute \src "ls180.v:1791.11-1791.42" wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1746.11-1746.37" + attribute \src "ls180.v:1790.11-1790.37" wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1749.11-1749.42" + attribute \src "ls180.v:1793.11-1793.42" wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1748.11-1748.37" + attribute \src "ls180.v:1792.11-1792.37" wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1751.11-1751.42" + attribute \src "ls180.v:1795.11-1795.42" wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1750.11-1750.37" + attribute \src "ls180.v:1794.11-1794.37" wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2596.5-2596.34" + attribute \src "ls180.v:2648.5-2648.34" wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2597.12-2597.41" + attribute \src "ls180.v:2649.12-2649.41" wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2609.5-2609.35" + attribute \src "ls180.v:2661.5-2661.35" wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2610.5-2610.35" + attribute \src "ls180.v:2662.5-2662.35" wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2614.12-2614.42" + attribute \src "ls180.v:2666.12-2666.42" wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2615.5-2615.35" + attribute \src "ls180.v:2667.5-2667.35" wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2616.5-2616.35" + attribute \src "ls180.v:2668.5-2668.35" wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2617.12-2617.42" + attribute \src "ls180.v:2669.12-2669.42" wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2618.5-2618.35" + attribute \src "ls180.v:2670.5-2670.35" wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2619.5-2619.35" + attribute \src "ls180.v:2671.5-2671.35" wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2620.12-2620.42" + attribute \src "ls180.v:2672.12-2672.42" wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2621.5-2621.35" + attribute \src "ls180.v:2673.5-2673.35" wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2598.11-2598.40" + attribute \src "ls180.v:2650.11-2650.40" wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2622.5-2622.35" + attribute \src "ls180.v:2674.5-2674.35" wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2623.12-2623.42" + attribute \src "ls180.v:2675.12-2675.42" wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2624.5-2624.35" + attribute \src "ls180.v:2676.5-2676.35" wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2625.5-2625.35" + attribute \src "ls180.v:2677.5-2677.35" wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2626.12-2626.42" + attribute \src "ls180.v:2678.12-2678.42" wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2627.12-2627.42" - wire width 32 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2628.11-2628.41" - wire width 4 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2629.5-2629.35" + attribute \src "ls180.v:2679.12-2679.42" + wire width 64 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2680.11-2680.41" + wire width 8 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2681.5-2681.35" wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2630.5-2630.35" + attribute \src "ls180.v:2682.5-2682.35" wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2631.5-2631.35" + attribute \src "ls180.v:2683.5-2683.35" wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2599.5-2599.34" + attribute \src "ls180.v:2651.5-2651.34" wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2632.11-2632.41" + attribute \src "ls180.v:2684.11-2684.41" wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2633.11-2633.41" + attribute \src "ls180.v:2685.11-2685.41" wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2600.5-2600.34" + attribute \src "ls180.v:2652.5-2652.34" wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2601.5-2601.34" + attribute \src "ls180.v:2653.5-2653.34" wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2605.5-2605.34" + attribute \src "ls180.v:2657.5-2657.34" wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2606.12-2606.41" + attribute \src "ls180.v:2658.12-2658.41" wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2607.11-2607.40" + attribute \src "ls180.v:2659.11-2659.40" wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2608.5-2608.34" + attribute \src "ls180.v:2660.5-2660.34" wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2602.5-2602.32" + attribute \src "ls180.v:2654.5-2654.32" wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2603.5-2603.32" + attribute \src "ls180.v:2655.5-2655.32" wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2604.5-2604.32" + attribute \src "ls180.v:2656.5-2656.32" wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2611.5-2611.32" + attribute \src "ls180.v:2663.5-2663.32" wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2612.5-2612.32" + attribute \src "ls180.v:2664.5-2664.32" wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2613.5-2613.32" + attribute \src "ls180.v:2665.5-2665.32" wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1731.5-1731.34" + attribute \src "ls180.v:1775.5-1775.34" wire \builder_converter0_next_state - attribute \src "ls180.v:1730.5-1730.29" + attribute \src "ls180.v:1774.5-1774.29" wire \builder_converter0_state - attribute \src "ls180.v:1735.5-1735.34" + attribute \src "ls180.v:1779.5-1779.34" wire \builder_converter1_next_state - attribute \src "ls180.v:1734.5-1734.29" + attribute \src "ls180.v:1778.5-1778.29" wire \builder_converter1_state - attribute \src "ls180.v:1739.5-1739.34" + attribute \src "ls180.v:1783.5-1783.34" wire \builder_converter2_next_state - attribute \src "ls180.v:1738.5-1738.29" + attribute \src "ls180.v:1782.5-1782.29" wire \builder_converter2_state - attribute \src "ls180.v:1776.5-1776.33" + attribute \src "ls180.v:1820.5-1820.33" wire \builder_converter_next_state - attribute \src "ls180.v:1775.5-1775.28" + attribute \src "ls180.v:1819.5-1819.28" wire \builder_converter_state - attribute \src "ls180.v:1896.12-1896.25" + attribute \src "ls180.v:1948.12-1948.25" wire width 20 \builder_count - attribute \src "ls180.v:2584.13-2584.41" + attribute \src "ls180.v:2636.13-2636.41" wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2587.12-2587.42" + attribute \src "ls180.v:2639.12-2639.42" wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2586.12-2586.42" + attribute \src "ls180.v:2638.12-2638.42" wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2585.6-2585.33" + attribute \src "ls180.v:2637.6-2637.33" wire \builder_csr_interconnect_we - attribute \src "ls180.v:1934.12-1934.42" + attribute \src "ls180.v:1986.12-1986.42" wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1933.6-1933.37" + attribute \src "ls180.v:1985.6-1985.37" wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1936.12-1936.42" + attribute \src "ls180.v:1988.12-1988.42" wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1935.6-1935.37" + attribute \src "ls180.v:1987.6-1987.37" wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1930.12-1930.42" + attribute \src "ls180.v:1982.12-1982.42" wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1929.6-1929.37" + attribute \src "ls180.v:1981.6-1981.37" wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1932.12-1932.42" + attribute \src "ls180.v:1984.12-1984.42" wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1931.6-1931.37" + attribute \src "ls180.v:1983.6-1983.37" wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1926.12-1926.42" + attribute \src "ls180.v:1978.12-1978.42" wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1925.6-1925.37" + attribute \src "ls180.v:1977.6-1977.37" wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1928.12-1928.42" + attribute \src "ls180.v:1980.12-1980.42" wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1927.6-1927.37" + attribute \src "ls180.v:1979.6-1979.37" wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1922.12-1922.42" + attribute \src "ls180.v:1974.12-1974.42" wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1921.6-1921.37" + attribute \src "ls180.v:1973.6-1973.37" wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1924.12-1924.42" + attribute \src "ls180.v:1976.12-1976.42" wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1923.6-1923.37" + attribute \src "ls180.v:1975.6-1975.37" wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1902.6-1902.31" + attribute \src "ls180.v:1954.6-1954.31" wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1901.6-1901.32" + attribute \src "ls180.v:1953.6-1953.32" wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1904.6-1904.31" + attribute \src "ls180.v:1956.6-1956.31" wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1903.6-1903.32" + attribute \src "ls180.v:1955.6-1955.32" wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1918.12-1918.39" + attribute \src "ls180.v:1970.12-1970.39" wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1917.6-1917.34" + attribute \src "ls180.v:1969.6-1969.34" wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1920.12-1920.39" + attribute \src "ls180.v:1972.12-1972.39" wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1919.6-1919.34" + attribute \src "ls180.v:1971.6-1971.34" wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1914.12-1914.39" + attribute \src "ls180.v:1966.12-1966.39" wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1913.6-1913.34" + attribute \src "ls180.v:1965.6-1965.34" wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1916.12-1916.39" + attribute \src "ls180.v:1968.12-1968.39" wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1915.6-1915.34" + attribute \src "ls180.v:1967.6-1967.34" wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1910.12-1910.39" + attribute \src "ls180.v:1962.12-1962.39" wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1909.6-1909.34" + attribute \src "ls180.v:1961.6-1961.34" wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1912.12-1912.39" + attribute \src "ls180.v:1964.12-1964.39" wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1911.6-1911.34" + attribute \src "ls180.v:1963.6-1963.34" wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1906.12-1906.39" + attribute \src "ls180.v:1958.12-1958.39" wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1905.6-1905.34" + attribute \src "ls180.v:1957.6-1957.34" wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1908.12-1908.39" + attribute \src "ls180.v:1960.12-1960.39" wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1907.6-1907.34" + attribute \src "ls180.v:1959.6-1959.34" wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1937.6-1937.26" + attribute \src "ls180.v:1989.6-1989.26" wire \builder_csrbank0_sel - attribute \src "ls180.v:2408.12-2408.40" + attribute \src "ls180.v:2460.12-2460.40" wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2407.6-2407.35" + attribute \src "ls180.v:2459.6-2459.35" wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2410.12-2410.40" + attribute \src "ls180.v:2462.12-2462.40" wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2409.6-2409.35" + attribute \src "ls180.v:2461.6-2461.35" wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2404.12-2404.40" + attribute \src "ls180.v:2456.12-2456.40" wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2403.6-2403.35" + attribute \src "ls180.v:2455.6-2455.35" wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2406.12-2406.40" + attribute \src "ls180.v:2458.12-2458.40" wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2405.6-2405.35" + attribute \src "ls180.v:2457.6-2457.35" wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2424.6-2424.29" + attribute \src "ls180.v:2476.6-2476.29" wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2423.6-2423.30" + attribute \src "ls180.v:2475.6-2475.30" wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2426.6-2426.29" + attribute \src "ls180.v:2478.6-2478.29" wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2425.6-2425.30" + attribute \src "ls180.v:2477.6-2477.30" wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2428.6-2428.35" + attribute \src "ls180.v:2480.6-2480.35" wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2427.6-2427.36" + attribute \src "ls180.v:2479.6-2479.36" wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2430.6-2430.35" + attribute \src "ls180.v:2482.6-2482.35" wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2429.6-2429.36" + attribute \src "ls180.v:2481.6-2481.36" wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2420.12-2420.36" + attribute \src "ls180.v:2472.12-2472.36" wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2419.6-2419.31" + attribute \src "ls180.v:2471.6-2471.31" wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2422.12-2422.36" + attribute \src "ls180.v:2474.12-2474.36" wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2421.6-2421.31" + attribute \src "ls180.v:2473.6-2473.31" wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2416.12-2416.37" + attribute \src "ls180.v:2468.12-2468.37" wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2415.6-2415.32" + attribute \src "ls180.v:2467.6-2467.32" wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2418.12-2418.37" + attribute \src "ls180.v:2470.12-2470.37" wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2417.6-2417.32" + attribute \src "ls180.v:2469.6-2469.32" wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2431.6-2431.27" + attribute \src "ls180.v:2483.6-2483.27" wire \builder_csrbank10_sel - attribute \src "ls180.v:2412.6-2412.32" + attribute \src "ls180.v:2464.6-2464.32" wire \builder_csrbank10_status_r - attribute \src "ls180.v:2411.6-2411.33" + attribute \src "ls180.v:2463.6-2463.33" wire \builder_csrbank10_status_re - attribute \src "ls180.v:2414.6-2414.32" + attribute \src "ls180.v:2466.6-2466.32" wire \builder_csrbank10_status_w - attribute \src "ls180.v:2413.6-2413.33" + attribute \src "ls180.v:2465.6-2465.33" wire \builder_csrbank10_status_we - attribute \src "ls180.v:2469.12-2469.44" + attribute \src "ls180.v:2521.12-2521.44" wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2468.6-2468.39" + attribute \src "ls180.v:2520.6-2520.39" wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2471.12-2471.44" + attribute \src "ls180.v:2523.12-2523.44" wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2470.6-2470.39" + attribute \src "ls180.v:2522.6-2522.39" wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2465.12-2465.44" + attribute \src "ls180.v:2517.12-2517.44" wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2464.6-2464.39" + attribute \src "ls180.v:2516.6-2516.39" wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2467.12-2467.44" + attribute \src "ls180.v:2519.12-2519.44" wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2466.6-2466.39" + attribute \src "ls180.v:2518.6-2518.39" wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2441.12-2441.40" + attribute \src "ls180.v:2493.12-2493.40" wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2440.6-2440.35" + attribute \src "ls180.v:2492.6-2492.35" wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2443.12-2443.40" + attribute \src "ls180.v:2495.12-2495.40" wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2442.6-2442.35" + attribute \src "ls180.v:2494.6-2494.35" wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2437.12-2437.40" + attribute \src "ls180.v:2489.12-2489.40" wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2436.6-2436.35" + attribute \src "ls180.v:2488.6-2488.35" wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2439.12-2439.40" + attribute \src "ls180.v:2491.12-2491.40" wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2438.6-2438.35" + attribute \src "ls180.v:2490.6-2490.35" wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2457.6-2457.29" + attribute \src "ls180.v:2509.6-2509.29" wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2456.6-2456.30" + attribute \src "ls180.v:2508.6-2508.30" wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2459.6-2459.29" + attribute \src "ls180.v:2511.6-2511.29" wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2458.6-2458.30" + attribute \src "ls180.v:2510.6-2510.30" wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2461.6-2461.35" + attribute \src "ls180.v:2513.6-2513.35" wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2460.6-2460.36" + attribute \src "ls180.v:2512.6-2512.36" wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2463.6-2463.35" + attribute \src "ls180.v:2515.6-2515.35" wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2462.6-2462.36" + attribute \src "ls180.v:2514.6-2514.36" wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2453.12-2453.36" + attribute \src "ls180.v:2505.12-2505.36" wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2452.6-2452.31" + attribute \src "ls180.v:2504.6-2504.31" wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2455.12-2455.36" + attribute \src "ls180.v:2507.12-2507.36" wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2454.6-2454.31" + attribute \src "ls180.v:2506.6-2506.31" wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2449.12-2449.37" + attribute \src "ls180.v:2501.12-2501.37" wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2448.6-2448.32" + attribute \src "ls180.v:2500.6-2500.32" wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2451.12-2451.37" + attribute \src "ls180.v:2503.12-2503.37" wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2450.6-2450.32" + attribute \src "ls180.v:2502.6-2502.32" wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2472.6-2472.27" + attribute \src "ls180.v:2524.6-2524.27" wire \builder_csrbank11_sel - attribute \src "ls180.v:2445.6-2445.32" + attribute \src "ls180.v:2497.6-2497.32" wire \builder_csrbank11_status_r - attribute \src "ls180.v:2444.6-2444.33" + attribute \src "ls180.v:2496.6-2496.33" wire \builder_csrbank11_status_re - attribute \src "ls180.v:2447.6-2447.32" + attribute \src "ls180.v:2499.6-2499.32" wire \builder_csrbank11_status_w - attribute \src "ls180.v:2446.6-2446.33" + attribute \src "ls180.v:2498.6-2498.33" wire \builder_csrbank11_status_we - attribute \src "ls180.v:2510.6-2510.29" + attribute \src "ls180.v:2562.6-2562.29" wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2509.6-2509.30" + attribute \src "ls180.v:2561.6-2561.30" wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2512.6-2512.29" + attribute \src "ls180.v:2564.6-2564.29" wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2511.6-2511.30" + attribute \src "ls180.v:2563.6-2563.30" wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2534.6-2534.36" + attribute \src "ls180.v:2586.6-2586.36" wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2533.6-2533.37" + attribute \src "ls180.v:2585.6-2585.37" wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2536.6-2536.36" + attribute \src "ls180.v:2588.6-2588.36" wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2535.6-2535.37" + attribute \src "ls180.v:2587.6-2587.37" wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2490.12-2490.37" + attribute \src "ls180.v:2542.12-2542.37" wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2489.6-2489.32" + attribute \src "ls180.v:2541.6-2541.32" wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2492.12-2492.37" + attribute \src "ls180.v:2544.12-2544.37" wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2491.6-2491.32" + attribute \src "ls180.v:2543.6-2543.32" wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2486.12-2486.37" + attribute \src "ls180.v:2538.12-2538.37" wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2485.6-2485.32" + attribute \src "ls180.v:2537.6-2537.32" wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2488.12-2488.37" + attribute \src "ls180.v:2540.12-2540.37" wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2487.6-2487.32" + attribute \src "ls180.v:2539.6-2539.32" wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2482.12-2482.37" + attribute \src "ls180.v:2534.12-2534.37" wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2481.6-2481.32" + attribute \src "ls180.v:2533.6-2533.32" wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2484.12-2484.37" + attribute \src "ls180.v:2536.12-2536.37" wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2483.6-2483.32" + attribute \src "ls180.v:2535.6-2535.32" wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2478.12-2478.37" + attribute \src "ls180.v:2530.12-2530.37" wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2477.6-2477.32" + attribute \src "ls180.v:2529.6-2529.32" wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2480.12-2480.37" + attribute \src "ls180.v:2532.12-2532.37" wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2479.6-2479.32" + attribute \src "ls180.v:2531.6-2531.32" wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2506.12-2506.39" + attribute \src "ls180.v:2558.12-2558.39" wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2505.6-2505.34" + attribute \src "ls180.v:2557.6-2557.34" wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2508.12-2508.39" + attribute \src "ls180.v:2560.12-2560.39" wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2507.6-2507.34" + attribute \src "ls180.v:2559.6-2559.34" wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2502.12-2502.39" + attribute \src "ls180.v:2554.12-2554.39" wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2501.6-2501.34" + attribute \src "ls180.v:2553.6-2553.34" wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2504.12-2504.39" + attribute \src "ls180.v:2556.12-2556.39" wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2503.6-2503.34" + attribute \src "ls180.v:2555.6-2555.34" wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2498.12-2498.39" + attribute \src "ls180.v:2550.12-2550.39" wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2497.6-2497.34" + attribute \src "ls180.v:2549.6-2549.34" wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2500.12-2500.39" + attribute \src "ls180.v:2552.12-2552.39" wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2499.6-2499.34" + attribute \src "ls180.v:2551.6-2551.34" wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2494.12-2494.39" + attribute \src "ls180.v:2546.12-2546.39" wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2493.6-2493.34" + attribute \src "ls180.v:2545.6-2545.34" wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2496.12-2496.39" + attribute \src "ls180.v:2548.12-2548.39" wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2495.6-2495.34" + attribute \src "ls180.v:2547.6-2547.34" wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2537.6-2537.27" + attribute \src "ls180.v:2589.6-2589.27" wire \builder_csrbank12_sel - attribute \src "ls180.v:2514.6-2514.39" + attribute \src "ls180.v:2566.6-2566.39" wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2513.6-2513.40" + attribute \src "ls180.v:2565.6-2565.40" wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2516.6-2516.39" + attribute \src "ls180.v:2568.6-2568.39" wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2515.6-2515.40" + attribute \src "ls180.v:2567.6-2567.40" wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2530.12-2530.38" + attribute \src "ls180.v:2582.12-2582.38" wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2529.6-2529.33" + attribute \src "ls180.v:2581.6-2581.33" wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2532.12-2532.38" + attribute \src "ls180.v:2584.12-2584.38" wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2531.6-2531.33" + attribute \src "ls180.v:2583.6-2583.33" wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2526.12-2526.38" + attribute \src "ls180.v:2578.12-2578.38" wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2525.6-2525.33" + attribute \src "ls180.v:2577.6-2577.33" wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2528.12-2528.38" + attribute \src "ls180.v:2580.12-2580.38" wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2527.6-2527.33" + attribute \src "ls180.v:2579.6-2579.33" wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2522.12-2522.38" + attribute \src "ls180.v:2574.12-2574.38" wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2521.6-2521.33" + attribute \src "ls180.v:2573.6-2573.33" wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2524.12-2524.38" + attribute \src "ls180.v:2576.12-2576.38" wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2523.6-2523.33" + attribute \src "ls180.v:2575.6-2575.33" wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2518.12-2518.38" + attribute \src "ls180.v:2570.12-2570.38" wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2517.6-2517.33" + attribute \src "ls180.v:2569.6-2569.33" wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2520.12-2520.38" + attribute \src "ls180.v:2572.12-2572.38" wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2519.6-2519.33" + attribute \src "ls180.v:2571.6-2571.33" wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2551.12-2551.42" + attribute \src "ls180.v:2603.12-2603.42" wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2550.6-2550.37" + attribute \src "ls180.v:2602.6-2602.37" wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2553.12-2553.42" + attribute \src "ls180.v:2605.12-2605.42" wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2552.6-2552.37" + attribute \src "ls180.v:2604.6-2604.37" wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2547.6-2547.33" + attribute \src "ls180.v:2599.6-2599.33" wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2546.6-2546.34" + attribute \src "ls180.v:2598.6-2598.34" wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2549.6-2549.33" + attribute \src "ls180.v:2601.6-2601.33" wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2548.6-2548.34" + attribute \src "ls180.v:2600.6-2600.34" wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2559.6-2559.32" + attribute \src "ls180.v:2611.6-2611.32" wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2558.6-2558.33" + attribute \src "ls180.v:2610.6-2610.33" wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2561.6-2561.32" + attribute \src "ls180.v:2613.6-2613.32" wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2560.6-2560.33" + attribute \src "ls180.v:2612.6-2612.33" wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2562.6-2562.27" + attribute \src "ls180.v:2614.6-2614.27" wire \builder_csrbank13_sel - attribute \src "ls180.v:2555.6-2555.33" + attribute \src "ls180.v:2607.6-2607.33" wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2554.6-2554.34" + attribute \src "ls180.v:2606.6-2606.34" wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2557.6-2557.33" + attribute \src "ls180.v:2609.6-2609.33" wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2556.6-2556.34" + attribute \src "ls180.v:2608.6-2608.34" wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2543.6-2543.32" + attribute \src "ls180.v:2595.6-2595.32" wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2542.6-2542.33" + attribute \src "ls180.v:2594.6-2594.33" wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2545.6-2545.32" + attribute \src "ls180.v:2597.6-2597.32" wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2544.6-2544.33" + attribute \src "ls180.v:2596.6-2596.33" wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2583.6-2583.27" + attribute \src "ls180.v:2635.6-2635.27" wire \builder_csrbank14_sel - attribute \src "ls180.v:2580.12-2580.44" + attribute \src "ls180.v:2632.12-2632.44" wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2579.6-2579.39" + attribute \src "ls180.v:2631.6-2631.39" wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2582.12-2582.44" + attribute \src "ls180.v:2634.12-2634.44" wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2581.6-2581.39" + attribute \src "ls180.v:2633.6-2633.39" wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2576.12-2576.44" + attribute \src "ls180.v:2628.12-2628.44" wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2575.6-2575.39" + attribute \src "ls180.v:2627.6-2627.39" wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2578.12-2578.44" + attribute \src "ls180.v:2630.12-2630.44" wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2577.6-2577.39" + attribute \src "ls180.v:2629.6-2629.39" wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2572.12-2572.44" + attribute \src "ls180.v:2624.12-2624.44" wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2571.6-2571.39" + attribute \src "ls180.v:2623.6-2623.39" wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2574.12-2574.44" + attribute \src "ls180.v:2626.12-2626.44" wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2573.6-2573.39" + attribute \src "ls180.v:2625.6-2625.39" wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2568.12-2568.44" + attribute \src "ls180.v:2620.12-2620.44" wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2567.6-2567.39" + attribute \src "ls180.v:2619.6-2619.39" wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2570.12-2570.44" + attribute \src "ls180.v:2622.12-2622.44" wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2569.6-2569.39" + attribute \src "ls180.v:2621.6-2621.39" wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:1955.12-1955.34" + attribute \src "ls180.v:2007.12-2007.34" wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:1954.6-1954.29" + attribute \src "ls180.v:2006.6-2006.29" wire \builder_csrbank1_in0_re - attribute \src "ls180.v:1957.12-1957.34" + attribute \src "ls180.v:2009.12-2009.34" wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:1956.6-1956.29" + attribute \src "ls180.v:2008.6-2008.29" wire \builder_csrbank1_in0_we - attribute \src "ls180.v:1951.12-1951.34" + attribute \src "ls180.v:2003.12-2003.34" wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:1950.6-1950.29" + attribute \src "ls180.v:2002.6-2002.29" wire \builder_csrbank1_in1_re - attribute \src "ls180.v:1953.12-1953.34" + attribute \src "ls180.v:2005.12-2005.34" wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:1952.6-1952.29" + attribute \src "ls180.v:2004.6-2004.29" wire \builder_csrbank1_in1_we - attribute \src "ls180.v:1947.12-1947.34" + attribute \src "ls180.v:1999.12-1999.34" wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:1946.6-1946.29" + attribute \src "ls180.v:1998.6-1998.29" wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:1949.12-1949.34" + attribute \src "ls180.v:2001.12-2001.34" wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:1948.6-1948.29" + attribute \src "ls180.v:2000.6-2000.29" wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:1943.12-1943.34" + attribute \src "ls180.v:1995.12-1995.34" wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:1942.6-1942.29" + attribute \src "ls180.v:1994.6-1994.29" wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:1945.12-1945.34" + attribute \src "ls180.v:1997.12-1997.34" wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:1944.6-1944.29" + attribute \src "ls180.v:1996.6-1996.29" wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:1963.12-1963.35" + attribute \src "ls180.v:2015.12-2015.35" wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:1962.6-1962.30" + attribute \src "ls180.v:2014.6-2014.30" wire \builder_csrbank1_out0_re - attribute \src "ls180.v:1965.12-1965.35" + attribute \src "ls180.v:2017.12-2017.35" wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:1964.6-1964.30" + attribute \src "ls180.v:2016.6-2016.30" wire \builder_csrbank1_out0_we - attribute \src "ls180.v:1959.12-1959.35" + attribute \src "ls180.v:2011.12-2011.35" wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:1958.6-1958.30" + attribute \src "ls180.v:2010.6-2010.30" wire \builder_csrbank1_out1_re - attribute \src "ls180.v:1961.12-1961.35" + attribute \src "ls180.v:2013.12-2013.35" wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:1960.6-1960.30" + attribute \src "ls180.v:2012.6-2012.30" wire \builder_csrbank1_out1_we - attribute \src "ls180.v:1966.6-1966.26" + attribute \src "ls180.v:2018.6-2018.26" wire \builder_csrbank1_sel - attribute \src "ls180.v:1976.6-1976.26" + attribute \src "ls180.v:2028.6-2028.26" wire \builder_csrbank2_r_r - attribute \src "ls180.v:1975.6-1975.27" + attribute \src "ls180.v:2027.6-2027.27" wire \builder_csrbank2_r_re - attribute \src "ls180.v:1978.6-1978.26" + attribute \src "ls180.v:2030.6-2030.26" wire \builder_csrbank2_r_w - attribute \src "ls180.v:1977.6-1977.27" + attribute \src "ls180.v:2029.6-2029.27" wire \builder_csrbank2_r_we - attribute \src "ls180.v:1979.6-1979.26" + attribute \src "ls180.v:2031.6-2031.26" wire \builder_csrbank2_sel - attribute \src "ls180.v:1972.12-1972.33" + attribute \src "ls180.v:2024.12-2024.33" wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:1971.6-1971.28" + attribute \src "ls180.v:2023.6-2023.28" wire \builder_csrbank2_w0_re - attribute \src "ls180.v:1974.12-1974.33" + attribute \src "ls180.v:2026.12-2026.33" wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:1973.6-1973.28" + attribute \src "ls180.v:2025.6-2025.28" wire \builder_csrbank2_w0_we - attribute \src "ls180.v:1985.6-1985.32" + attribute \src "ls180.v:2037.6-2037.32" wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:1984.6-1984.33" + attribute \src "ls180.v:2036.6-2036.33" wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:1987.6-1987.32" + attribute \src "ls180.v:2039.6-2039.32" wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:1986.6-1986.33" + attribute \src "ls180.v:2038.6-2038.33" wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2017.12-2017.38" + attribute \src "ls180.v:2069.12-2069.38" wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2016.6-2016.33" + attribute \src "ls180.v:2068.6-2068.33" wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2019.12-2019.38" + attribute \src "ls180.v:2071.12-2071.38" wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2018.6-2018.33" + attribute \src "ls180.v:2070.6-2070.33" wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2013.12-2013.38" + attribute \src "ls180.v:2065.12-2065.38" wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2012.6-2012.33" + attribute \src "ls180.v:2064.6-2064.33" wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2015.12-2015.38" + attribute \src "ls180.v:2067.12-2067.38" wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2014.6-2014.33" + attribute \src "ls180.v:2066.6-2066.33" wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2009.12-2009.38" + attribute \src "ls180.v:2061.12-2061.38" wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2008.6-2008.33" + attribute \src "ls180.v:2060.6-2060.33" wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2011.12-2011.38" + attribute \src "ls180.v:2063.12-2063.38" wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2010.6-2010.33" + attribute \src "ls180.v:2062.6-2062.33" wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2005.12-2005.38" + attribute \src "ls180.v:2057.12-2057.38" wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2004.6-2004.33" + attribute \src "ls180.v:2056.6-2056.33" wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2007.12-2007.38" + attribute \src "ls180.v:2059.12-2059.38" wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2006.6-2006.33" + attribute \src "ls180.v:2058.6-2058.33" wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2020.6-2020.26" + attribute \src "ls180.v:2072.6-2072.26" wire \builder_csrbank3_sel - attribute \src "ls180.v:2001.12-2001.37" + attribute \src "ls180.v:2053.12-2053.37" wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2000.6-2000.32" + attribute \src "ls180.v:2052.6-2052.32" wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2003.12-2003.37" + attribute \src "ls180.v:2055.12-2055.37" wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2002.6-2002.32" + attribute \src "ls180.v:2054.6-2054.32" wire \builder_csrbank3_width0_we - attribute \src "ls180.v:1997.12-1997.37" + attribute \src "ls180.v:2049.12-2049.37" wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:1996.6-1996.32" + attribute \src "ls180.v:2048.6-2048.32" wire \builder_csrbank3_width1_re - attribute \src "ls180.v:1999.12-1999.37" + attribute \src "ls180.v:2051.12-2051.37" wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:1998.6-1998.32" + attribute \src "ls180.v:2050.6-2050.32" wire \builder_csrbank3_width1_we - attribute \src "ls180.v:1993.12-1993.37" + attribute \src "ls180.v:2045.12-2045.37" wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:1992.6-1992.32" + attribute \src "ls180.v:2044.6-2044.32" wire \builder_csrbank3_width2_re - attribute \src "ls180.v:1995.12-1995.37" + attribute \src "ls180.v:2047.12-2047.37" wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:1994.6-1994.32" + attribute \src "ls180.v:2046.6-2046.32" wire \builder_csrbank3_width2_we - attribute \src "ls180.v:1989.12-1989.37" + attribute \src "ls180.v:2041.12-2041.37" wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:1988.6-1988.32" + attribute \src "ls180.v:2040.6-2040.32" wire \builder_csrbank3_width3_re - attribute \src "ls180.v:1991.12-1991.37" + attribute \src "ls180.v:2043.12-2043.37" wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:1990.6-1990.32" + attribute \src "ls180.v:2042.6-2042.32" wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2026.6-2026.32" + attribute \src "ls180.v:2078.6-2078.32" wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2025.6-2025.33" + attribute \src "ls180.v:2077.6-2077.33" wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2028.6-2028.32" + attribute \src "ls180.v:2080.6-2080.32" wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2027.6-2027.33" + attribute \src "ls180.v:2079.6-2079.33" wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2058.12-2058.38" + attribute \src "ls180.v:2110.12-2110.38" wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2057.6-2057.33" + attribute \src "ls180.v:2109.6-2109.33" wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2060.12-2060.38" + attribute \src "ls180.v:2112.12-2112.38" wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2059.6-2059.33" + attribute \src "ls180.v:2111.6-2111.33" wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2054.12-2054.38" + attribute \src "ls180.v:2106.12-2106.38" wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2053.6-2053.33" + attribute \src "ls180.v:2105.6-2105.33" wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2056.12-2056.38" + attribute \src "ls180.v:2108.12-2108.38" wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2055.6-2055.33" + attribute \src "ls180.v:2107.6-2107.33" wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2050.12-2050.38" + attribute \src "ls180.v:2102.12-2102.38" wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2049.6-2049.33" + attribute \src "ls180.v:2101.6-2101.33" wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2052.12-2052.38" + attribute \src "ls180.v:2104.12-2104.38" wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2051.6-2051.33" + attribute \src "ls180.v:2103.6-2103.33" wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2046.12-2046.38" + attribute \src "ls180.v:2098.12-2098.38" wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2045.6-2045.33" + attribute \src "ls180.v:2097.6-2097.33" wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2048.12-2048.38" + attribute \src "ls180.v:2100.12-2100.38" wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2047.6-2047.33" + attribute \src "ls180.v:2099.6-2099.33" wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2061.6-2061.26" + attribute \src "ls180.v:2113.6-2113.26" wire \builder_csrbank4_sel - attribute \src "ls180.v:2042.12-2042.37" + attribute \src "ls180.v:2094.12-2094.37" wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2041.6-2041.32" + attribute \src "ls180.v:2093.6-2093.32" wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2044.12-2044.37" + attribute \src "ls180.v:2096.12-2096.37" wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2043.6-2043.32" + attribute \src "ls180.v:2095.6-2095.32" wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2038.12-2038.37" + attribute \src "ls180.v:2090.12-2090.37" wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2037.6-2037.32" + attribute \src "ls180.v:2089.6-2089.32" wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2040.12-2040.37" + attribute \src "ls180.v:2092.12-2092.37" wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2039.6-2039.32" + attribute \src "ls180.v:2091.6-2091.32" wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2034.12-2034.37" + attribute \src "ls180.v:2086.12-2086.37" wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2033.6-2033.32" + attribute \src "ls180.v:2085.6-2085.32" wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2036.12-2036.37" + attribute \src "ls180.v:2088.12-2088.37" wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2035.6-2035.32" + attribute \src "ls180.v:2087.6-2087.32" wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2030.12-2030.37" + attribute \src "ls180.v:2082.12-2082.37" wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2029.6-2029.32" + attribute \src "ls180.v:2081.6-2081.32" wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2032.12-2032.37" + attribute \src "ls180.v:2084.12-2084.37" wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2031.6-2031.32" + attribute \src "ls180.v:2083.6-2083.32" wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2095.12-2095.40" + attribute \src "ls180.v:2147.12-2147.40" wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2094.6-2094.35" + attribute \src "ls180.v:2146.6-2146.35" wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2097.12-2097.40" + attribute \src "ls180.v:2149.12-2149.40" wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2096.6-2096.35" + attribute \src "ls180.v:2148.6-2148.35" wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2091.12-2091.40" + attribute \src "ls180.v:2143.12-2143.40" wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2090.6-2090.35" + attribute \src "ls180.v:2142.6-2142.35" wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2093.12-2093.40" + attribute \src "ls180.v:2145.12-2145.40" wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2092.6-2092.35" + attribute \src "ls180.v:2144.6-2144.35" wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2087.12-2087.40" + attribute \src "ls180.v:2139.12-2139.40" wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2086.6-2086.35" + attribute \src "ls180.v:2138.6-2138.35" wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2089.12-2089.40" + attribute \src "ls180.v:2141.12-2141.40" wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2088.6-2088.35" + attribute \src "ls180.v:2140.6-2140.35" wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2083.12-2083.40" + attribute \src "ls180.v:2135.12-2135.40" wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2082.6-2082.35" + attribute \src "ls180.v:2134.6-2134.35" wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2085.12-2085.40" + attribute \src "ls180.v:2137.12-2137.40" wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2084.6-2084.35" + attribute \src "ls180.v:2136.6-2136.35" wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2079.12-2079.40" + attribute \src "ls180.v:2131.12-2131.40" wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2078.6-2078.35" + attribute \src "ls180.v:2130.6-2130.35" wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2081.12-2081.40" + attribute \src "ls180.v:2133.12-2133.40" wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2080.6-2080.35" + attribute \src "ls180.v:2132.6-2132.35" wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2075.12-2075.40" + attribute \src "ls180.v:2127.12-2127.40" wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2074.6-2074.35" + attribute \src "ls180.v:2126.6-2126.35" wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2077.12-2077.40" + attribute \src "ls180.v:2129.12-2129.40" wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2076.6-2076.35" + attribute \src "ls180.v:2128.6-2128.35" wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2071.12-2071.40" + attribute \src "ls180.v:2123.12-2123.40" wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2070.6-2070.35" + attribute \src "ls180.v:2122.6-2122.35" wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2073.12-2073.40" + attribute \src "ls180.v:2125.12-2125.40" wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2072.6-2072.35" + attribute \src "ls180.v:2124.6-2124.35" wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2067.12-2067.40" + attribute \src "ls180.v:2119.12-2119.40" wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2066.6-2066.35" + attribute \src "ls180.v:2118.6-2118.35" wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2069.12-2069.40" + attribute \src "ls180.v:2121.12-2121.40" wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2068.6-2068.35" + attribute \src "ls180.v:2120.6-2120.35" wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2119.6-2119.33" + attribute \src "ls180.v:2171.6-2171.33" wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2118.6-2118.34" + attribute \src "ls180.v:2170.6-2170.34" wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2121.6-2121.33" + attribute \src "ls180.v:2173.6-2173.33" wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2120.6-2120.34" + attribute \src "ls180.v:2172.6-2172.34" wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2115.6-2115.36" + attribute \src "ls180.v:2167.6-2167.36" wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2114.6-2114.37" + attribute \src "ls180.v:2166.6-2166.37" wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2117.6-2117.36" + attribute \src "ls180.v:2169.6-2169.36" wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2116.6-2116.37" + attribute \src "ls180.v:2168.6-2168.37" wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2111.12-2111.42" + attribute \src "ls180.v:2163.12-2163.42" wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2110.6-2110.37" + attribute \src "ls180.v:2162.6-2162.37" wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2113.12-2113.42" + attribute \src "ls180.v:2165.12-2165.42" wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2112.6-2112.37" + attribute \src "ls180.v:2164.6-2164.37" wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2107.12-2107.42" + attribute \src "ls180.v:2159.12-2159.42" wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2106.6-2106.37" + attribute \src "ls180.v:2158.6-2158.37" wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2109.12-2109.42" + attribute \src "ls180.v:2161.12-2161.42" wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2108.6-2108.37" + attribute \src "ls180.v:2160.6-2160.37" wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2103.12-2103.42" + attribute \src "ls180.v:2155.12-2155.42" wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2102.6-2102.37" + attribute \src "ls180.v:2154.6-2154.37" wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2105.12-2105.42" + attribute \src "ls180.v:2157.12-2157.42" wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2104.6-2104.37" + attribute \src "ls180.v:2156.6-2156.37" wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2099.12-2099.42" + attribute \src "ls180.v:2151.12-2151.42" wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2098.6-2098.37" + attribute \src "ls180.v:2150.6-2150.37" wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2101.12-2101.42" + attribute \src "ls180.v:2153.12-2153.42" wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2100.6-2100.37" + attribute \src "ls180.v:2152.6-2152.37" wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2123.6-2123.34" + attribute \src "ls180.v:2175.6-2175.34" wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2122.6-2122.35" + attribute \src "ls180.v:2174.6-2174.35" wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2125.6-2125.34" + attribute \src "ls180.v:2177.6-2177.34" wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2124.6-2124.35" + attribute \src "ls180.v:2176.6-2176.35" wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2126.6-2126.26" + attribute \src "ls180.v:2178.6-2178.26" wire \builder_csrbank5_sel - attribute \src "ls180.v:2256.12-2256.43" + attribute \src "ls180.v:2308.12-2308.43" wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2255.6-2255.38" + attribute \src "ls180.v:2307.6-2307.38" wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2258.12-2258.43" + attribute \src "ls180.v:2310.12-2310.43" wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2257.6-2257.38" + attribute \src "ls180.v:2309.6-2309.38" wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2252.12-2252.43" + attribute \src "ls180.v:2304.12-2304.43" wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2251.6-2251.38" + attribute \src "ls180.v:2303.6-2303.38" wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2254.12-2254.43" + attribute \src "ls180.v:2306.12-2306.43" wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2253.6-2253.38" + attribute \src "ls180.v:2305.6-2305.38" wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2248.12-2248.43" + attribute \src "ls180.v:2300.12-2300.43" wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2247.6-2247.38" + attribute \src "ls180.v:2299.6-2299.38" wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2250.12-2250.43" + attribute \src "ls180.v:2302.12-2302.43" wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2249.6-2249.38" + attribute \src "ls180.v:2301.6-2301.38" wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2244.12-2244.43" + attribute \src "ls180.v:2296.12-2296.43" wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2243.6-2243.38" + attribute \src "ls180.v:2295.6-2295.38" wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2246.12-2246.43" + attribute \src "ls180.v:2298.12-2298.43" wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2245.6-2245.38" + attribute \src "ls180.v:2297.6-2297.38" wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2240.12-2240.44" + attribute \src "ls180.v:2292.12-2292.44" wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2239.6-2239.39" + attribute \src "ls180.v:2291.6-2291.39" wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2242.12-2242.44" + attribute \src "ls180.v:2294.12-2294.44" wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2241.6-2241.39" + attribute \src "ls180.v:2293.6-2293.39" wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2236.12-2236.44" + attribute \src "ls180.v:2288.12-2288.44" wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2235.6-2235.39" + attribute \src "ls180.v:2287.6-2287.39" wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2238.12-2238.44" + attribute \src "ls180.v:2290.12-2290.44" wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2237.6-2237.39" + attribute \src "ls180.v:2289.6-2289.39" wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2144.12-2144.44" + attribute \src "ls180.v:2196.12-2196.44" wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2143.6-2143.39" + attribute \src "ls180.v:2195.6-2195.39" wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2146.12-2146.44" + attribute \src "ls180.v:2198.12-2198.44" wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2145.6-2145.39" + attribute \src "ls180.v:2197.6-2197.39" wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2140.12-2140.44" + attribute \src "ls180.v:2192.12-2192.44" wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2139.6-2139.39" + attribute \src "ls180.v:2191.6-2191.39" wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2142.12-2142.44" + attribute \src "ls180.v:2194.12-2194.44" wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2141.6-2141.39" + attribute \src "ls180.v:2193.6-2193.39" wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2136.12-2136.44" + attribute \src "ls180.v:2188.12-2188.44" wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2135.6-2135.39" + attribute \src "ls180.v:2187.6-2187.39" wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2138.12-2138.44" + attribute \src "ls180.v:2190.12-2190.44" wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2137.6-2137.39" + attribute \src "ls180.v:2189.6-2189.39" wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2132.12-2132.44" + attribute \src "ls180.v:2184.12-2184.44" wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2131.6-2131.39" + attribute \src "ls180.v:2183.6-2183.39" wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2134.12-2134.44" + attribute \src "ls180.v:2186.12-2186.44" wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2133.6-2133.39" + attribute \src "ls180.v:2185.6-2185.39" wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2160.12-2160.43" + attribute \src "ls180.v:2212.12-2212.43" wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2159.6-2159.38" + attribute \src "ls180.v:2211.6-2211.38" wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2162.12-2162.43" + attribute \src "ls180.v:2214.12-2214.43" wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2161.6-2161.38" + attribute \src "ls180.v:2213.6-2213.38" wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2156.12-2156.43" + attribute \src "ls180.v:2208.12-2208.43" wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2155.6-2155.38" + attribute \src "ls180.v:2207.6-2207.38" wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2158.12-2158.43" + attribute \src "ls180.v:2210.12-2210.43" wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2157.6-2157.38" + attribute \src "ls180.v:2209.6-2209.38" wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2152.12-2152.43" + attribute \src "ls180.v:2204.12-2204.43" wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2151.6-2151.38" + attribute \src "ls180.v:2203.6-2203.38" wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2154.12-2154.43" + attribute \src "ls180.v:2206.12-2206.43" wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2153.6-2153.38" + attribute \src "ls180.v:2205.6-2205.38" wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2148.12-2148.43" + attribute \src "ls180.v:2200.12-2200.43" wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2147.6-2147.38" + attribute \src "ls180.v:2199.6-2199.38" wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2150.12-2150.43" + attribute \src "ls180.v:2202.12-2202.43" wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2149.6-2149.38" + attribute \src "ls180.v:2201.6-2201.38" wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2228.12-2228.40" + attribute \src "ls180.v:2280.12-2280.40" wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2227.6-2227.35" + attribute \src "ls180.v:2279.6-2279.35" wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2230.12-2230.40" + attribute \src "ls180.v:2282.12-2282.40" wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2229.6-2229.35" + attribute \src "ls180.v:2281.6-2281.35" wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2224.12-2224.44" + attribute \src "ls180.v:2276.12-2276.44" wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2223.6-2223.39" + attribute \src "ls180.v:2275.6-2275.39" wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2226.12-2226.44" + attribute \src "ls180.v:2278.12-2278.44" wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2225.6-2225.39" + attribute \src "ls180.v:2277.6-2277.39" wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2184.12-2184.45" + attribute \src "ls180.v:2236.12-2236.45" wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2183.6-2183.40" + attribute \src "ls180.v:2235.6-2235.40" wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2186.12-2186.45" + attribute \src "ls180.v:2238.12-2238.45" wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2185.6-2185.40" + attribute \src "ls180.v:2237.6-2237.40" wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2180.12-2180.45" + attribute \src "ls180.v:2232.12-2232.45" wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2179.6-2179.40" + attribute \src "ls180.v:2231.6-2231.40" wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2182.12-2182.45" + attribute \src "ls180.v:2234.12-2234.45" wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2181.6-2181.40" + attribute \src "ls180.v:2233.6-2233.40" wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2176.12-2176.45" + attribute \src "ls180.v:2228.12-2228.45" wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2175.6-2175.40" + attribute \src "ls180.v:2227.6-2227.40" wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2178.12-2178.45" + attribute \src "ls180.v:2230.12-2230.45" wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2177.6-2177.40" + attribute \src "ls180.v:2229.6-2229.40" wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2172.12-2172.45" + attribute \src "ls180.v:2224.12-2224.45" wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2171.6-2171.40" + attribute \src "ls180.v:2223.6-2223.40" wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2174.12-2174.45" + attribute \src "ls180.v:2226.12-2226.45" wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2173.6-2173.40" + attribute \src "ls180.v:2225.6-2225.40" wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2168.12-2168.45" + attribute \src "ls180.v:2220.12-2220.45" wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2167.6-2167.40" + attribute \src "ls180.v:2219.6-2219.40" wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2170.12-2170.45" + attribute \src "ls180.v:2222.12-2222.45" wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2169.6-2169.40" + attribute \src "ls180.v:2221.6-2221.40" wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2164.12-2164.45" + attribute \src "ls180.v:2216.12-2216.45" wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2163.6-2163.40" + attribute \src "ls180.v:2215.6-2215.40" wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2166.12-2166.45" + attribute \src "ls180.v:2218.12-2218.45" wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2165.6-2165.40" + attribute \src "ls180.v:2217.6-2217.40" wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2220.12-2220.44" + attribute \src "ls180.v:2272.12-2272.44" wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2219.6-2219.39" + attribute \src "ls180.v:2271.6-2271.39" wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2222.12-2222.44" + attribute \src "ls180.v:2274.12-2274.44" wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2221.6-2221.39" + attribute \src "ls180.v:2273.6-2273.39" wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2216.12-2216.44" + attribute \src "ls180.v:2268.12-2268.44" wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2215.6-2215.39" + attribute \src "ls180.v:2267.6-2267.39" wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2218.12-2218.44" + attribute \src "ls180.v:2270.12-2270.44" wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2217.6-2217.39" + attribute \src "ls180.v:2269.6-2269.39" wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2212.12-2212.44" + attribute \src "ls180.v:2264.12-2264.44" wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2211.6-2211.39" + attribute \src "ls180.v:2263.6-2263.39" wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2214.12-2214.44" + attribute \src "ls180.v:2266.12-2266.44" wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2213.6-2213.39" + attribute \src "ls180.v:2265.6-2265.39" wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2208.12-2208.44" + attribute \src "ls180.v:2260.12-2260.44" wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2207.6-2207.39" + attribute \src "ls180.v:2259.6-2259.39" wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2210.12-2210.44" + attribute \src "ls180.v:2262.12-2262.44" wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2209.6-2209.39" + attribute \src "ls180.v:2261.6-2261.39" wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2204.12-2204.44" + attribute \src "ls180.v:2256.12-2256.44" wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2203.6-2203.39" + attribute \src "ls180.v:2255.6-2255.39" wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2206.12-2206.44" + attribute \src "ls180.v:2258.12-2258.44" wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2205.6-2205.39" + attribute \src "ls180.v:2257.6-2257.39" wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2200.12-2200.44" + attribute \src "ls180.v:2252.12-2252.44" wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2199.6-2199.39" + attribute \src "ls180.v:2251.6-2251.39" wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2202.12-2202.44" + attribute \src "ls180.v:2254.12-2254.44" wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2201.6-2201.39" + attribute \src "ls180.v:2253.6-2253.39" wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2196.12-2196.44" + attribute \src "ls180.v:2248.12-2248.44" wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2195.6-2195.39" + attribute \src "ls180.v:2247.6-2247.39" wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2198.12-2198.44" + attribute \src "ls180.v:2250.12-2250.44" wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2197.6-2197.39" + attribute \src "ls180.v:2249.6-2249.39" wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2192.12-2192.44" + attribute \src "ls180.v:2244.12-2244.44" wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2191.6-2191.39" + attribute \src "ls180.v:2243.6-2243.39" wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2194.12-2194.44" + attribute \src "ls180.v:2246.12-2246.44" wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2193.6-2193.39" + attribute \src "ls180.v:2245.6-2245.39" wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2188.12-2188.44" + attribute \src "ls180.v:2240.12-2240.44" wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2187.6-2187.39" + attribute \src "ls180.v:2239.6-2239.39" wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2190.12-2190.44" + attribute \src "ls180.v:2242.12-2242.44" wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2189.6-2189.39" + attribute \src "ls180.v:2241.6-2241.39" wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2232.12-2232.41" + attribute \src "ls180.v:2284.12-2284.41" wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2231.6-2231.36" + attribute \src "ls180.v:2283.6-2283.36" wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2234.12-2234.41" + attribute \src "ls180.v:2286.12-2286.41" wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2233.6-2233.36" + attribute \src "ls180.v:2285.6-2285.36" wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2259.6-2259.26" + attribute \src "ls180.v:2311.6-2311.26" wire \builder_csrbank6_sel - attribute \src "ls180.v:2293.12-2293.40" + attribute \src "ls180.v:2345.12-2345.40" wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2292.6-2292.35" + attribute \src "ls180.v:2344.6-2344.35" wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2295.12-2295.40" + attribute \src "ls180.v:2347.12-2347.40" wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2294.6-2294.35" + attribute \src "ls180.v:2346.6-2346.35" wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2289.12-2289.40" + attribute \src "ls180.v:2341.12-2341.40" wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2288.6-2288.35" + attribute \src "ls180.v:2340.6-2340.35" wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2291.12-2291.40" + attribute \src "ls180.v:2343.12-2343.40" wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2290.6-2290.35" + attribute \src "ls180.v:2342.6-2342.35" wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2285.12-2285.40" + attribute \src "ls180.v:2337.12-2337.40" wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2284.6-2284.35" + attribute \src "ls180.v:2336.6-2336.35" wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2287.12-2287.40" + attribute \src "ls180.v:2339.12-2339.40" wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2286.6-2286.35" + attribute \src "ls180.v:2338.6-2338.35" wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2281.12-2281.40" + attribute \src "ls180.v:2333.12-2333.40" wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2280.6-2280.35" + attribute \src "ls180.v:2332.6-2332.35" wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2283.12-2283.40" + attribute \src "ls180.v:2335.12-2335.40" wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2282.6-2282.35" + attribute \src "ls180.v:2334.6-2334.35" wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2277.12-2277.40" + attribute \src "ls180.v:2329.12-2329.40" wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2276.6-2276.35" + attribute \src "ls180.v:2328.6-2328.35" wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2279.12-2279.40" + attribute \src "ls180.v:2331.12-2331.40" wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2278.6-2278.35" + attribute \src "ls180.v:2330.6-2330.35" wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2273.12-2273.40" + attribute \src "ls180.v:2325.12-2325.40" wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2272.6-2272.35" + attribute \src "ls180.v:2324.6-2324.35" wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2275.12-2275.40" + attribute \src "ls180.v:2327.12-2327.40" wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2274.6-2274.35" + attribute \src "ls180.v:2326.6-2326.35" wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2269.12-2269.40" + attribute \src "ls180.v:2321.12-2321.40" wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2268.6-2268.35" + attribute \src "ls180.v:2320.6-2320.35" wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2271.12-2271.40" + attribute \src "ls180.v:2323.12-2323.40" wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2270.6-2270.35" + attribute \src "ls180.v:2322.6-2322.35" wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2265.12-2265.40" + attribute \src "ls180.v:2317.12-2317.40" wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2264.6-2264.35" + attribute \src "ls180.v:2316.6-2316.35" wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2267.12-2267.40" + attribute \src "ls180.v:2319.12-2319.40" wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2266.6-2266.35" + attribute \src "ls180.v:2318.6-2318.35" wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2317.6-2317.33" + attribute \src "ls180.v:2369.6-2369.33" wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2316.6-2316.34" + attribute \src "ls180.v:2368.6-2368.34" wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2319.6-2319.33" + attribute \src "ls180.v:2371.6-2371.33" wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2318.6-2318.34" + attribute \src "ls180.v:2370.6-2370.34" wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2313.6-2313.36" + attribute \src "ls180.v:2365.6-2365.36" wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2312.6-2312.37" + attribute \src "ls180.v:2364.6-2364.37" wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2315.6-2315.36" + attribute \src "ls180.v:2367.6-2367.36" wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2314.6-2314.37" + attribute \src "ls180.v:2366.6-2366.37" wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2309.12-2309.42" + attribute \src "ls180.v:2361.12-2361.42" wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2308.6-2308.37" + attribute \src "ls180.v:2360.6-2360.37" wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2311.12-2311.42" + attribute \src "ls180.v:2363.12-2363.42" wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2310.6-2310.37" + attribute \src "ls180.v:2362.6-2362.37" wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2305.12-2305.42" + attribute \src "ls180.v:2357.12-2357.42" wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2304.6-2304.37" + attribute \src "ls180.v:2356.6-2356.37" wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2307.12-2307.42" + attribute \src "ls180.v:2359.12-2359.42" wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2306.6-2306.37" + attribute \src "ls180.v:2358.6-2358.37" wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2301.12-2301.42" + attribute \src "ls180.v:2353.12-2353.42" wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2300.6-2300.37" + attribute \src "ls180.v:2352.6-2352.37" wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2303.12-2303.42" + attribute \src "ls180.v:2355.12-2355.42" wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2302.6-2302.37" + attribute \src "ls180.v:2354.6-2354.37" wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2297.12-2297.42" + attribute \src "ls180.v:2349.12-2349.42" wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2296.6-2296.37" + attribute \src "ls180.v:2348.6-2348.37" wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2299.12-2299.42" + attribute \src "ls180.v:2351.12-2351.42" wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2298.6-2298.37" + attribute \src "ls180.v:2350.6-2350.37" wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2321.6-2321.34" + attribute \src "ls180.v:2373.6-2373.34" wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2320.6-2320.35" + attribute \src "ls180.v:2372.6-2372.35" wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2323.6-2323.34" + attribute \src "ls180.v:2375.6-2375.34" wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2322.6-2322.35" + attribute \src "ls180.v:2374.6-2374.35" wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2337.12-2337.42" + attribute \src "ls180.v:2389.12-2389.42" wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2336.6-2336.37" + attribute \src "ls180.v:2388.6-2388.37" wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2339.12-2339.42" + attribute \src "ls180.v:2391.12-2391.42" wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2338.6-2338.37" + attribute \src "ls180.v:2390.6-2390.37" wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2333.12-2333.42" + attribute \src "ls180.v:2385.12-2385.42" wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2332.6-2332.37" + attribute \src "ls180.v:2384.6-2384.37" wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2335.12-2335.42" + attribute \src "ls180.v:2387.12-2387.42" wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2334.6-2334.37" + attribute \src "ls180.v:2386.6-2386.37" wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2329.12-2329.42" + attribute \src "ls180.v:2381.12-2381.42" wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2328.6-2328.37" + attribute \src "ls180.v:2380.6-2380.37" wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2331.12-2331.42" + attribute \src "ls180.v:2383.12-2383.42" wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2330.6-2330.37" + attribute \src "ls180.v:2382.6-2382.37" wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2325.12-2325.42" + attribute \src "ls180.v:2377.12-2377.42" wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2324.6-2324.37" + attribute \src "ls180.v:2376.6-2376.37" wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2327.12-2327.42" + attribute \src "ls180.v:2379.12-2379.42" wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2326.6-2326.37" + attribute \src "ls180.v:2378.6-2378.37" wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2340.6-2340.26" + attribute \src "ls180.v:2392.6-2392.26" wire \builder_csrbank7_sel - attribute \src "ls180.v:2346.6-2346.36" + attribute \src "ls180.v:2398.6-2398.36" wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2345.6-2345.37" + attribute \src "ls180.v:2397.6-2397.37" wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2348.6-2348.36" + attribute \src "ls180.v:2400.6-2400.36" wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2347.6-2347.37" + attribute \src "ls180.v:2399.6-2399.37" wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2354.12-2354.47" + attribute \src "ls180.v:2406.12-2406.47" wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2353.6-2353.42" + attribute \src "ls180.v:2405.6-2405.42" wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2356.12-2356.47" + attribute \src "ls180.v:2408.12-2408.47" wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2355.6-2355.42" + attribute \src "ls180.v:2407.6-2407.42" wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2350.6-2350.41" + attribute \src "ls180.v:2402.6-2402.41" wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2349.6-2349.42" + attribute \src "ls180.v:2401.6-2401.42" wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2352.6-2352.41" + attribute \src "ls180.v:2404.6-2404.41" wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2351.6-2351.42" + attribute \src "ls180.v:2403.6-2403.42" wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2357.6-2357.26" + attribute \src "ls180.v:2409.6-2409.26" wire \builder_csrbank8_sel - attribute \src "ls180.v:2363.12-2363.44" + attribute \src "ls180.v:2415.12-2415.44" wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2362.6-2362.39" + attribute \src "ls180.v:2414.6-2414.39" wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2365.12-2365.44" + attribute \src "ls180.v:2417.12-2417.44" wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2364.6-2364.39" + attribute \src "ls180.v:2416.6-2416.39" wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2375.12-2375.48" + attribute \src "ls180.v:2427.12-2427.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2374.6-2374.43" + attribute \src "ls180.v:2426.6-2426.43" wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2377.12-2377.48" + attribute \src "ls180.v:2429.12-2429.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2376.6-2376.43" + attribute \src "ls180.v:2428.6-2428.43" wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2371.12-2371.48" + attribute \src "ls180.v:2423.12-2423.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2370.6-2370.43" + attribute \src "ls180.v:2422.6-2422.43" wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2373.12-2373.48" + attribute \src "ls180.v:2425.12-2425.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2372.6-2372.43" + attribute \src "ls180.v:2424.6-2424.43" wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2379.12-2379.49" + attribute \src "ls180.v:2431.12-2431.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2378.6-2378.44" + attribute \src "ls180.v:2430.6-2430.44" wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2381.12-2381.49" + attribute \src "ls180.v:2433.12-2433.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2380.6-2380.44" + attribute \src "ls180.v:2432.6-2432.44" wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2367.12-2367.48" + attribute \src "ls180.v:2419.12-2419.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2366.6-2366.43" + attribute \src "ls180.v:2418.6-2418.43" wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2369.12-2369.48" + attribute \src "ls180.v:2421.12-2421.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2368.6-2368.43" + attribute \src "ls180.v:2420.6-2420.43" wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2395.12-2395.47" + attribute \src "ls180.v:2447.12-2447.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2394.6-2394.42" + attribute \src "ls180.v:2446.6-2446.42" wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2397.12-2397.47" + attribute \src "ls180.v:2449.12-2449.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2396.6-2396.42" + attribute \src "ls180.v:2448.6-2448.42" wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2391.12-2391.47" + attribute \src "ls180.v:2443.12-2443.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2390.6-2390.42" + attribute \src "ls180.v:2442.6-2442.42" wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2393.12-2393.47" + attribute \src "ls180.v:2445.12-2445.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2392.6-2392.42" + attribute \src "ls180.v:2444.6-2444.42" wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2387.12-2387.47" + attribute \src "ls180.v:2439.12-2439.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2386.6-2386.42" + attribute \src "ls180.v:2438.6-2438.42" wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2389.12-2389.47" + attribute \src "ls180.v:2441.12-2441.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2388.6-2388.42" + attribute \src "ls180.v:2440.6-2440.42" wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2383.12-2383.47" + attribute \src "ls180.v:2435.12-2435.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2382.6-2382.42" + attribute \src "ls180.v:2434.6-2434.42" wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2385.12-2385.47" + attribute \src "ls180.v:2437.12-2437.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2384.6-2384.42" + attribute \src "ls180.v:2436.6-2436.42" wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2398.6-2398.26" + attribute \src "ls180.v:2450.6-2450.26" wire \builder_csrbank9_sel - attribute \src "ls180.v:1895.6-1895.18" + attribute \src "ls180.v:1947.6-1947.18" wire \builder_done - attribute \src "ls180.v:1893.5-1893.18" + attribute \src "ls180.v:1945.5-1945.18" wire \builder_error - attribute \src "ls180.v:1890.11-1890.24" + attribute \src "ls180.v:1942.11-1942.24" wire width 3 \builder_grant - attribute \src "ls180.v:1897.13-1897.44" + attribute \src "ls180.v:1949.13-1949.44" wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1900.11-1900.44" + attribute \src "ls180.v:1952.11-1952.44" wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1899.12-1899.45" + attribute \src "ls180.v:1951.12-1951.45" wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1898.6-1898.36" + attribute \src "ls180.v:1950.6-1950.36" wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2399.13-2399.45" + attribute \src "ls180.v:2451.13-2451.45" wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2402.11-2402.45" + attribute \src "ls180.v:2454.11-2454.45" wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2401.12-2401.46" + attribute \src "ls180.v:2453.12-2453.46" wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2400.6-2400.37" + attribute \src "ls180.v:2452.6-2452.37" wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2432.13-2432.45" + attribute \src "ls180.v:2484.13-2484.45" wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2435.11-2435.45" + attribute \src "ls180.v:2487.11-2487.45" wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2434.12-2434.46" + attribute \src "ls180.v:2486.12-2486.46" wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2433.6-2433.37" + attribute \src "ls180.v:2485.6-2485.37" wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2473.13-2473.45" + attribute \src "ls180.v:2525.13-2525.45" wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2476.11-2476.45" + attribute \src "ls180.v:2528.11-2528.45" wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2475.12-2475.46" + attribute \src "ls180.v:2527.12-2527.46" wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2474.6-2474.37" + attribute \src "ls180.v:2526.6-2526.37" wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2538.13-2538.45" + attribute \src "ls180.v:2590.13-2590.45" wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2541.11-2541.45" + attribute \src "ls180.v:2593.11-2593.45" wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2540.12-2540.46" + attribute \src "ls180.v:2592.12-2592.46" wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2539.6-2539.37" + attribute \src "ls180.v:2591.6-2591.37" wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2563.13-2563.45" + attribute \src "ls180.v:2615.13-2615.45" wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2566.11-2566.45" + attribute \src "ls180.v:2618.11-2618.45" wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2565.12-2565.46" + attribute \src "ls180.v:2617.12-2617.46" wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2564.6-2564.37" + attribute \src "ls180.v:2616.6-2616.37" wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:1938.13-1938.44" + attribute \src "ls180.v:1990.13-1990.44" wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1941.11-1941.44" + attribute \src "ls180.v:1993.11-1993.44" wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1940.12-1940.45" + attribute \src "ls180.v:1992.12-1992.45" wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1939.6-1939.36" + attribute \src "ls180.v:1991.6-1991.36" wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:1967.13-1967.44" + attribute \src "ls180.v:2019.13-2019.44" wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:1970.11-1970.44" + attribute \src "ls180.v:2022.11-2022.44" wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:1969.12-1969.45" + attribute \src "ls180.v:2021.12-2021.45" wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:1968.6-1968.36" + attribute \src "ls180.v:2020.6-2020.36" wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:1980.13-1980.44" + attribute \src "ls180.v:2032.13-2032.44" wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:1983.11-1983.44" + attribute \src "ls180.v:2035.11-2035.44" wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:1982.12-1982.45" + attribute \src "ls180.v:2034.12-2034.45" wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:1981.6-1981.36" + attribute \src "ls180.v:2033.6-2033.36" wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2021.13-2021.44" + attribute \src "ls180.v:2073.13-2073.44" wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2024.11-2024.44" + attribute \src "ls180.v:2076.11-2076.44" wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2023.12-2023.45" + attribute \src "ls180.v:2075.12-2075.45" wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2022.6-2022.36" + attribute \src "ls180.v:2074.6-2074.36" wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2062.13-2062.44" + attribute \src "ls180.v:2114.13-2114.44" wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2065.11-2065.44" + attribute \src "ls180.v:2117.11-2117.44" wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2064.12-2064.45" + attribute \src "ls180.v:2116.12-2116.45" wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2063.6-2063.36" + attribute \src "ls180.v:2115.6-2115.36" wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2127.13-2127.44" + attribute \src "ls180.v:2179.13-2179.44" wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2130.11-2130.44" + attribute \src "ls180.v:2182.11-2182.44" wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2129.12-2129.45" + attribute \src "ls180.v:2181.12-2181.45" wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2128.6-2128.36" + attribute \src "ls180.v:2180.6-2180.36" wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2260.13-2260.44" + attribute \src "ls180.v:2312.13-2312.44" wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2263.11-2263.44" + attribute \src "ls180.v:2315.11-2315.44" wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2262.12-2262.45" + attribute \src "ls180.v:2314.12-2314.45" wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2261.6-2261.36" + attribute \src "ls180.v:2313.6-2313.36" wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2341.13-2341.44" + attribute \src "ls180.v:2393.13-2393.44" wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2344.11-2344.44" + attribute \src "ls180.v:2396.11-2396.44" wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2343.12-2343.45" + attribute \src "ls180.v:2395.12-2395.45" wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2342.6-2342.36" + attribute \src "ls180.v:2394.6-2394.36" wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2358.13-2358.44" + attribute \src "ls180.v:2410.13-2410.44" wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2361.11-2361.44" + attribute \src "ls180.v:2413.11-2413.44" wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2360.12-2360.45" + attribute \src "ls180.v:2412.12-2412.45" wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2359.6-2359.36" + attribute \src "ls180.v:2411.6-2411.36" wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1863.12-1863.35" + attribute \src "ls180.v:1907.12-1907.35" wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2592.12-2592.47" + attribute \src "ls180.v:2644.12-2644.47" wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2593.5-2593.43" + attribute \src "ls180.v:2645.5-2645.43" wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1866.12-1866.37" + attribute \src "ls180.v:1925.5-1925.48" + wire \builder_libresocsim_converted_interface_ack + attribute \src "ls180.v:1919.13-1919.56" + wire width 30 \builder_libresocsim_converted_interface_adr + attribute \src "ls180.v:1928.12-1928.55" + wire width 2 \builder_libresocsim_converted_interface_bte + attribute \src "ls180.v:1927.12-1927.55" + wire width 3 \builder_libresocsim_converted_interface_cti + attribute \src "ls180.v:1923.6-1923.49" + wire \builder_libresocsim_converted_interface_cyc + attribute \src "ls180.v:1921.12-1921.57" + wire width 64 \builder_libresocsim_converted_interface_dat_r + attribute \src "ls180.v:1920.13-1920.58" + wire width 64 \builder_libresocsim_converted_interface_dat_w + attribute \src "ls180.v:1929.5-1929.48" + wire \builder_libresocsim_converted_interface_err + attribute \src "ls180.v:1922.12-1922.55" + wire width 8 \builder_libresocsim_converted_interface_sel + attribute \src "ls180.v:1924.6-1924.49" + wire \builder_libresocsim_converted_interface_stb + attribute \src "ls180.v:1926.6-1926.48" + wire \builder_libresocsim_converted_interface_we + attribute \src "ls180.v:1910.12-1910.37" wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1865.11-1865.36" + attribute \src "ls180.v:1909.11-1909.36" wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2590.11-2590.48" + attribute \src "ls180.v:2642.11-2642.48" wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2591.5-2591.45" + attribute \src "ls180.v:2643.5-2643.45" wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1864.5-1864.27" + attribute \src "ls180.v:1908.5-1908.27" wire \builder_libresocsim_we - attribute \src "ls180.v:2594.5-2594.39" + attribute \src "ls180.v:2646.5-2646.39" wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2595.5-2595.42" + attribute \src "ls180.v:2647.5-2647.42" wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1873.5-1873.37" + attribute \src "ls180.v:1917.5-1917.37" wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1867.13-1867.45" + attribute \src "ls180.v:1911.12-1911.44" wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1876.12-1876.44" - wire width 2 \builder_libresocsim_wishbone_bte - attribute \src "ls180.v:1875.12-1875.44" - wire width 3 \builder_libresocsim_wishbone_cti - attribute \src "ls180.v:1871.6-1871.38" + attribute \src "ls180.v:1915.5-1915.37" wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1869.12-1869.46" + attribute \src "ls180.v:1913.12-1913.46" wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1868.13-1868.47" + attribute \src "ls180.v:1912.12-1912.46" wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1877.5-1877.37" - wire \builder_libresocsim_wishbone_err - attribute \src "ls180.v:1870.12-1870.44" + attribute \src "ls180.v:1914.11-1914.43" wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1872.6-1872.38" + attribute \src "ls180.v:1916.5-1916.37" wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1874.6-1874.37" + attribute \src "ls180.v:1918.5-1918.36" wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1766.5-1766.20" + attribute \src "ls180.v:1810.5-1810.20" wire \builder_locked0 - attribute \src "ls180.v:1767.5-1767.20" + attribute \src "ls180.v:1811.5-1811.20" wire \builder_locked1 - attribute \src "ls180.v:1768.5-1768.20" + attribute \src "ls180.v:1812.5-1812.20" wire \builder_locked2 - attribute \src "ls180.v:1769.5-1769.20" + attribute \src "ls180.v:1813.5-1813.20" wire \builder_locked3 - attribute \src "ls180.v:1753.11-1753.41" + attribute \src "ls180.v:1797.11-1797.41" wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1752.11-1752.36" + attribute \src "ls180.v:1796.11-1796.36" wire width 3 \builder_multiplexer_state attribute \no_retiming "true" - attribute \src "ls180.v:2699.32-2699.59" + attribute \src "ls180.v:2751.32-2751.59" wire \builder_multiregimpl0_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2700.32-2700.59" + attribute \src "ls180.v:2752.32-2752.59" wire \builder_multiregimpl0_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2719.32-2719.60" + attribute \src "ls180.v:2771.32-2771.60" wire \builder_multiregimpl10_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2720.32-2720.60" + attribute \src "ls180.v:2772.32-2772.60" wire \builder_multiregimpl10_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2721.32-2721.60" + attribute \src "ls180.v:2773.32-2773.60" wire \builder_multiregimpl11_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2722.32-2722.60" + attribute \src "ls180.v:2774.32-2774.60" wire \builder_multiregimpl11_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2723.32-2723.60" + attribute \src "ls180.v:2775.32-2775.60" wire \builder_multiregimpl12_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2724.32-2724.60" + attribute \src "ls180.v:2776.32-2776.60" wire \builder_multiregimpl12_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2725.32-2725.60" + attribute \src "ls180.v:2777.32-2777.60" wire \builder_multiregimpl13_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2726.32-2726.60" + attribute \src "ls180.v:2778.32-2778.60" wire \builder_multiregimpl13_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2727.32-2727.60" + attribute \src "ls180.v:2779.32-2779.60" wire \builder_multiregimpl14_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2728.32-2728.60" + attribute \src "ls180.v:2780.32-2780.60" wire \builder_multiregimpl14_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2729.32-2729.60" + attribute \src "ls180.v:2781.32-2781.60" wire \builder_multiregimpl15_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2730.32-2730.60" + attribute \src "ls180.v:2782.32-2782.60" wire \builder_multiregimpl15_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2731.32-2731.60" + attribute \src "ls180.v:2783.32-2783.60" wire \builder_multiregimpl16_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2732.32-2732.60" + attribute \src "ls180.v:2784.32-2784.60" wire \builder_multiregimpl16_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2701.32-2701.59" + attribute \src "ls180.v:2753.32-2753.59" wire \builder_multiregimpl1_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2702.32-2702.59" + attribute \src "ls180.v:2754.32-2754.59" wire \builder_multiregimpl1_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2703.32-2703.59" + attribute \src "ls180.v:2755.32-2755.59" wire \builder_multiregimpl2_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2704.32-2704.59" + attribute \src "ls180.v:2756.32-2756.59" wire \builder_multiregimpl2_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2705.32-2705.59" + attribute \src "ls180.v:2757.32-2757.59" wire \builder_multiregimpl3_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2706.32-2706.59" + attribute \src "ls180.v:2758.32-2758.59" wire \builder_multiregimpl3_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2707.32-2707.59" + attribute \src "ls180.v:2759.32-2759.59" wire \builder_multiregimpl4_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2708.32-2708.59" + attribute \src "ls180.v:2760.32-2760.59" wire \builder_multiregimpl4_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2709.32-2709.59" + attribute \src "ls180.v:2761.32-2761.59" wire \builder_multiregimpl5_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2710.32-2710.59" + attribute \src "ls180.v:2762.32-2762.59" wire \builder_multiregimpl5_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2711.32-2711.59" + attribute \src "ls180.v:2763.32-2763.59" wire \builder_multiregimpl6_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2712.32-2712.59" + attribute \src "ls180.v:2764.32-2764.59" wire \builder_multiregimpl6_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2713.32-2713.59" + attribute \src "ls180.v:2765.32-2765.59" wire \builder_multiregimpl7_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2714.32-2714.59" + attribute \src "ls180.v:2766.32-2766.59" wire \builder_multiregimpl7_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2715.32-2715.59" + attribute \src "ls180.v:2767.32-2767.59" wire \builder_multiregimpl8_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2716.32-2716.59" + attribute \src "ls180.v:2768.32-2768.59" wire \builder_multiregimpl8_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2717.32-2717.59" + attribute \src "ls180.v:2769.32-2769.59" wire \builder_multiregimpl9_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2718.32-2718.59" + attribute \src "ls180.v:2770.32-2770.59" wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1771.5-1771.36" + attribute \src "ls180.v:1815.5-1815.36" wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1772.5-1772.36" + attribute \src "ls180.v:1816.5-1816.36" wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1773.5-1773.36" + attribute \src "ls180.v:1817.5-1817.36" wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1774.5-1774.36" + attribute \src "ls180.v:1818.5-1818.36" wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1770.5-1770.35" + attribute \src "ls180.v:1814.5-1814.35" wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2589.11-2589.29" + attribute \src "ls180.v:2641.11-2641.29" wire width 2 \builder_next_state - attribute \src "ls180.v:1743.11-1743.39" + attribute \src "ls180.v:1787.11-1787.39" wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1742.11-1742.34" + attribute \src "ls180.v:1786.11-1786.34" wire width 2 \builder_refresher_state - attribute \src "ls180.v:1889.12-1889.27" + attribute \src "ls180.v:1941.12-1941.27" wire width 5 \builder_request - attribute \src "ls180.v:1756.6-1756.28" + attribute \src "ls180.v:1800.6-1800.28" wire \builder_roundrobin0_ce - attribute \src "ls180.v:1755.6-1755.31" + attribute \src "ls180.v:1799.6-1799.31" wire \builder_roundrobin0_grant - attribute \src "ls180.v:1754.6-1754.33" + attribute \src "ls180.v:1798.6-1798.33" wire \builder_roundrobin0_request - attribute \src "ls180.v:1759.6-1759.28" + attribute \src "ls180.v:1803.6-1803.28" wire \builder_roundrobin1_ce - attribute \src "ls180.v:1758.6-1758.31" + attribute \src "ls180.v:1802.6-1802.31" wire \builder_roundrobin1_grant - attribute \src "ls180.v:1757.6-1757.33" + attribute \src "ls180.v:1801.6-1801.33" wire \builder_roundrobin1_request - attribute \src "ls180.v:1762.6-1762.28" + attribute \src "ls180.v:1806.6-1806.28" wire \builder_roundrobin2_ce - attribute \src "ls180.v:1761.6-1761.31" + attribute \src "ls180.v:1805.6-1805.31" wire \builder_roundrobin2_grant - attribute \src "ls180.v:1760.6-1760.33" + attribute \src "ls180.v:1804.6-1804.33" wire \builder_roundrobin2_request - attribute \src "ls180.v:1765.6-1765.28" + attribute \src "ls180.v:1809.6-1809.28" wire \builder_roundrobin3_ce - attribute \src "ls180.v:1764.6-1764.31" + attribute \src "ls180.v:1808.6-1808.31" wire \builder_roundrobin3_grant - attribute \src "ls180.v:1763.6-1763.33" + attribute \src "ls180.v:1807.6-1807.33" wire \builder_roundrobin3_request - attribute \src "ls180.v:1852.11-1852.44" + attribute \src "ls180.v:1896.11-1896.44" wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1851.11-1851.39" + attribute \src "ls180.v:1895.11-1895.39" wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1820.5-1820.50" + attribute \src "ls180.v:1864.5-1864.50" wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1819.5-1819.45" + attribute \src "ls180.v:1863.5-1863.45" wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1832.11-1832.40" + attribute \src "ls180.v:1876.11-1876.40" wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1831.11-1831.35" + attribute \src "ls180.v:1875.11-1875.35" wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1856.5-1856.42" + attribute \src "ls180.v:1900.5-1900.42" wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1855.5-1855.37" + attribute \src "ls180.v:1899.5-1899.37" wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1860.11-1860.58" + attribute \src "ls180.v:1904.11-1904.58" wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1859.11-1859.53" + attribute \src "ls180.v:1903.11-1903.53" wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1808.11-1808.39" + attribute \src "ls180.v:1852.11-1852.39" wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1807.11-1807.34" + attribute \src "ls180.v:1851.11-1851.34" wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1796.11-1796.45" + attribute \src "ls180.v:1840.11-1840.45" wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1795.11-1795.40" + attribute \src "ls180.v:1839.11-1839.40" wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1792.11-1792.45" + attribute \src "ls180.v:1836.11-1836.45" wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1791.11-1791.40" + attribute \src "ls180.v:1835.11-1835.40" wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1804.5-1804.39" + attribute \src "ls180.v:1848.5-1848.39" wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1803.5-1803.34" + attribute \src "ls180.v:1847.5-1847.34" wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1812.11-1812.46" + attribute \src "ls180.v:1856.11-1856.46" wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1811.11-1811.41" + attribute \src "ls180.v:1855.11-1855.41" wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1788.5-1788.39" + attribute \src "ls180.v:1832.5-1832.39" wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1787.5-1787.34" + attribute \src "ls180.v:1831.5-1831.34" wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1884.5-1884.23" + attribute \src "ls180.v:1936.5-1936.23" wire \builder_shared_ack - attribute \src "ls180.v:1878.13-1878.31" + attribute \src "ls180.v:1930.13-1930.31" wire width 30 \builder_shared_adr - attribute \src "ls180.v:1887.12-1887.30" + attribute \src "ls180.v:1939.12-1939.30" wire width 2 \builder_shared_bte - attribute \src "ls180.v:1886.12-1886.30" + attribute \src "ls180.v:1938.12-1938.30" wire width 3 \builder_shared_cti - attribute \src "ls180.v:1882.6-1882.24" + attribute \src "ls180.v:1934.6-1934.24" wire \builder_shared_cyc - attribute \src "ls180.v:1880.12-1880.32" + attribute \src "ls180.v:1932.12-1932.32" wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1879.13-1879.33" + attribute \src "ls180.v:1931.13-1931.33" wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1888.6-1888.24" + attribute \src "ls180.v:1940.6-1940.24" wire \builder_shared_err - attribute \src "ls180.v:1881.12-1881.30" + attribute \src "ls180.v:1933.12-1933.30" wire width 4 \builder_shared_sel - attribute \src "ls180.v:1883.6-1883.24" + attribute \src "ls180.v:1935.6-1935.24" wire \builder_shared_stb - attribute \src "ls180.v:1885.6-1885.23" + attribute \src "ls180.v:1937.6-1937.23" wire \builder_shared_we - attribute \src "ls180.v:1891.11-1891.28" - wire width 5 \builder_slave_sel - attribute \src "ls180.v:1892.11-1892.30" - wire width 5 \builder_slave_sel_r - attribute \src "ls180.v:1780.11-1780.40" + attribute \src "ls180.v:1943.11-1943.28" + wire width 8 \builder_slave_sel + attribute \src "ls180.v:1944.11-1944.30" + wire width 8 \builder_slave_sel_r + attribute \src "ls180.v:1824.11-1824.40" wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1779.11-1779.35" + attribute \src "ls180.v:1823.11-1823.35" wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1784.11-1784.40" + attribute \src "ls180.v:1828.11-1828.40" wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1783.11-1783.35" + attribute \src "ls180.v:1827.11-1827.35" wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2588.11-2588.24" + attribute \src "ls180.v:2640.11-2640.24" wire width 2 \builder_state - attribute \src "ls180.v:2641.5-2641.32" + attribute \src "ls180.v:2693.5-2693.32" wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2642.5-2642.32" + attribute \src "ls180.v:2694.5-2694.32" wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2634.11-2634.40" + attribute \src "ls180.v:2686.11-2686.40" wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2635.12-2635.41" + attribute \src "ls180.v:2687.12-2687.41" wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2636.5-2636.34" + attribute \src "ls180.v:2688.5-2688.34" wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2637.5-2637.34" + attribute \src "ls180.v:2689.5-2689.34" wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2638.5-2638.34" + attribute \src "ls180.v:2690.5-2690.34" wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2639.5-2639.34" + attribute \src "ls180.v:2691.5-2691.34" wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2640.5-2640.34" + attribute \src "ls180.v:2692.5-2692.34" wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1894.6-1894.18" + attribute \src "ls180.v:1946.6-1946.18" wire \builder_wait - attribute \src "ls180.v:36.19-36.23" - wire width 3 input 32 \eint - attribute \src "ls180.v:153.12-153.18" + attribute \src "ls180.v:33.19-33.23" + wire width 3 input 29 \eint + attribute \src "ls180.v:150.12-150.18" wire width 3 \eint_1 - attribute \src "ls180.v:33.20-33.26" - wire width 16 input 29 \gpio_i - attribute \src "ls180.v:34.21-34.27" - wire width 16 output 30 \gpio_o - attribute \src "ls180.v:35.21-35.28" - wire width 16 output 31 \gpio_oe - attribute \src "ls180.v:29.14-29.21" - wire output 25 \i2c_scl - attribute \src "ls180.v:30.13-30.22" - wire input 26 \i2c_sda_i - attribute \src "ls180.v:31.14-31.23" - wire output 27 \i2c_sda_o - attribute \src "ls180.v:32.14-32.24" - wire output 28 \i2c_sda_oe + attribute \src "ls180.v:11.20-11.26" + wire width 16 input 7 \gpio_i + attribute \src "ls180.v:12.21-12.27" + wire width 16 output 8 \gpio_o + attribute \src "ls180.v:13.21-13.28" + wire width 16 output 9 \gpio_oe + attribute \src "ls180.v:35.14-35.21" + wire output 31 \i2c_scl + attribute \src "ls180.v:36.13-36.22" + wire input 32 \i2c_sda_i + attribute \src "ls180.v:37.14-37.23" + wire output 33 \i2c_sda_o + attribute \src "ls180.v:38.14-38.24" + wire output 34 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -231361,142 +231991,276 @@ module \ls180 wire output 47 \jtag_tdo attribute \src "ls180.v:48.13-48.21" wire input 44 \jtag_tms - attribute \src "ls180.v:834.6-834.18" + attribute \src "ls180.v:878.6-878.18" wire \main_ack_cmd - attribute \src "ls180.v:836.6-836.20" + attribute \src "ls180.v:880.6-880.20" wire \main_ack_rdata - attribute \src "ls180.v:835.6-835.20" + attribute \src "ls180.v:879.6-879.20" wire \main_ack_wdata - attribute \src "ls180.v:832.5-832.22" + attribute \src "ls180.v:876.5-876.22" wire \main_cmd_consumed - attribute \src "ls180.v:829.5-829.27" + attribute \src "ls180.v:259.5-259.28" + wire \main_converter0_counter + attribute \src "ls180.v:1776.5-1776.50" + wire \main_converter0_counter_converter0_next_value + attribute \src "ls180.v:1777.5-1777.53" + wire \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:261.12-261.33" + wire width 64 \main_converter0_dat_r + attribute \src "ls180.v:260.6-260.27" + wire \main_converter0_reset + attribute \src "ls180.v:258.5-258.25" + wire \main_converter0_skip + attribute \src "ls180.v:274.5-274.28" + wire \main_converter1_counter + attribute \src "ls180.v:1780.5-1780.50" + wire \main_converter1_counter_converter1_next_value + attribute \src "ls180.v:1781.5-1781.53" + wire \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:276.12-276.33" + wire width 64 \main_converter1_dat_r + attribute \src "ls180.v:275.6-275.27" + wire \main_converter1_reset + attribute \src "ls180.v:273.5-273.25" + wire \main_converter1_skip + attribute \src "ls180.v:873.5-873.27" wire \main_converter_counter - attribute \src "ls180.v:1777.5-1777.48" + attribute \src "ls180.v:1821.5-1821.48" wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1778.5-1778.51" + attribute \src "ls180.v:1822.5-1822.51" wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:831.12-831.32" + attribute \src "ls180.v:875.12-875.32" wire width 32 \main_converter_dat_r - attribute \src "ls180.v:830.6-830.26" + attribute \src "ls180.v:874.6-874.26" wire \main_converter_reset - attribute \src "ls180.v:828.5-828.24" + attribute \src "ls180.v:872.5-872.24" wire \main_converter_skip - attribute \src "ls180.v:258.6-258.23" + attribute \src "ls180.v:290.6-290.23" wire \main_dfi_p0_act_n - attribute \src "ls180.v:249.13-249.32" + attribute \src "ls180.v:281.13-281.32" wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:250.12-250.28" + attribute \src "ls180.v:282.12-282.28" wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:251.6-251.23" + attribute \src "ls180.v:283.6-283.23" wire \main_dfi_p0_cas_n - attribute \src "ls180.v:255.6-255.21" + attribute \src "ls180.v:287.6-287.21" wire \main_dfi_p0_cke - attribute \src "ls180.v:252.6-252.22" + attribute \src "ls180.v:284.6-284.22" wire \main_dfi_p0_cs_n - attribute \src "ls180.v:256.6-256.21" + attribute \src "ls180.v:288.6-288.21" wire \main_dfi_p0_odt - attribute \src "ls180.v:253.6-253.23" + attribute \src "ls180.v:285.6-285.23" wire \main_dfi_p0_ras_n - attribute \src "ls180.v:263.12-263.30" + attribute \src "ls180.v:295.12-295.30" wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:262.6-262.27" + attribute \src "ls180.v:294.6-294.27" wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:264.5-264.29" + attribute \src "ls180.v:296.5-296.29" wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:257.6-257.25" + attribute \src "ls180.v:289.6-289.25" wire \main_dfi_p0_reset_n - attribute \src "ls180.v:254.6-254.22" + attribute \src "ls180.v:286.6-286.22" wire \main_dfi_p0_we_n - attribute \src "ls180.v:259.13-259.31" + attribute \src "ls180.v:291.13-291.31" wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:260.6-260.27" + attribute \src "ls180.v:292.6-292.27" wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:261.12-261.35" + attribute \src "ls180.v:293.12-293.35" wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1063.12-1063.22" + attribute \src "ls180.v:1107.12-1107.22" wire width 24 \main_dummy - attribute \src "ls180.v:980.5-980.20" + attribute \src "ls180.v:1024.5-1024.20" wire \main_gpio_oe_re - attribute \src "ls180.v:979.12-979.32" + attribute \src "ls180.v:1023.12-1023.32" wire width 16 \main_gpio_oe_storage - attribute \src "ls180.v:984.5-984.21" + attribute \src "ls180.v:1028.5-1028.21" wire \main_gpio_out_re - attribute \src "ls180.v:983.12-983.33" + attribute \src "ls180.v:1027.12-1027.33" wire width 16 \main_gpio_out_storage - attribute \src "ls180.v:985.13-985.29" + attribute \src "ls180.v:1029.13-1029.29" wire width 16 \main_gpio_pads_i - attribute \src "ls180.v:986.13-986.29" + attribute \src "ls180.v:1030.13-1030.29" wire width 16 \main_gpio_pads_o - attribute \src "ls180.v:987.13-987.30" + attribute \src "ls180.v:1031.13-1031.30" wire width 16 \main_gpio_pads_oe - attribute \src "ls180.v:981.12-981.28" + attribute \src "ls180.v:1025.12-1025.28" wire width 16 \main_gpio_status - attribute \src "ls180.v:982.6-982.18" + attribute \src "ls180.v:1026.6-1026.18" wire \main_gpio_we - attribute \src "ls180.v:1085.6-1085.17" + attribute \src "ls180.v:1129.6-1129.17" wire \main_i2c_oe - attribute \src "ls180.v:1088.5-1088.16" + attribute \src "ls180.v:1132.5-1132.16" wire \main_i2c_re - attribute \src "ls180.v:1084.6-1084.18" + attribute \src "ls180.v:1128.6-1128.18" wire \main_i2c_scl - attribute \src "ls180.v:1086.6-1086.19" + attribute \src "ls180.v:1130.6-1130.19" wire \main_i2c_sda0 - attribute \src "ls180.v:1089.6-1089.19" + attribute \src "ls180.v:1133.6-1133.19" wire \main_i2c_sda1 - attribute \src "ls180.v:1090.6-1090.21" + attribute \src "ls180.v:1134.6-1134.21" wire \main_i2c_status - attribute \src "ls180.v:1087.11-1087.27" + attribute \src "ls180.v:1131.11-1131.27" wire width 3 \main_i2c_storage - attribute \src "ls180.v:1091.6-1091.17" + attribute \src "ls180.v:1135.6-1135.17" wire \main_i2c_we - attribute \src "ls180.v:248.5-248.17" + attribute \src "ls180.v:280.5-280.17" wire \main_int_rst - attribute \src "ls180.v:1551.6-1551.29" + attribute \src "ls180.v:1595.6-1595.29" wire \main_interface0_bus_ack - attribute \src "ls180.v:1545.13-1545.36" + attribute \src "ls180.v:1589.13-1589.36" wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1554.11-1554.34" + attribute \src "ls180.v:1598.11-1598.34" wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1553.11-1553.34" + attribute \src "ls180.v:1597.11-1597.34" wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1549.6-1549.29" + attribute \src "ls180.v:1593.6-1593.29" wire \main_interface0_bus_cyc - attribute \src "ls180.v:1547.13-1547.38" - wire width 32 \main_interface0_bus_dat_r - attribute \src "ls180.v:1546.13-1546.38" - wire width 32 \main_interface0_bus_dat_w - attribute \src "ls180.v:1555.6-1555.29" + attribute \src "ls180.v:1591.13-1591.38" + wire width 64 \main_interface0_bus_dat_r + attribute \src "ls180.v:1590.13-1590.38" + wire width 64 \main_interface0_bus_dat_w + attribute \src "ls180.v:1599.6-1599.29" wire \main_interface0_bus_err - attribute \src "ls180.v:1548.12-1548.35" - wire width 4 \main_interface0_bus_sel - attribute \src "ls180.v:1550.6-1550.29" + attribute \src "ls180.v:1592.12-1592.35" + wire width 8 \main_interface0_bus_sel + attribute \src "ls180.v:1594.6-1594.29" wire \main_interface0_bus_stb - attribute \src "ls180.v:1552.6-1552.28" + attribute \src "ls180.v:1596.6-1596.28" wire \main_interface0_bus_we - attribute \src "ls180.v:1642.6-1642.29" + attribute \src "ls180.v:253.5-253.44" + wire \main_interface0_converted_interface_ack + attribute \src "ls180.v:247.13-247.52" + wire width 30 \main_interface0_converted_interface_adr + attribute \src "ls180.v:256.12-256.51" + wire width 2 \main_interface0_converted_interface_bte + attribute \src "ls180.v:255.12-255.51" + wire width 3 \main_interface0_converted_interface_cti + attribute \src "ls180.v:251.6-251.45" + wire \main_interface0_converted_interface_cyc + attribute \src "ls180.v:249.13-249.54" + wire width 64 \main_interface0_converted_interface_dat_r + attribute \src "ls180.v:248.13-248.54" + wire width 64 \main_interface0_converted_interface_dat_w + attribute \src "ls180.v:257.5-257.44" + wire \main_interface0_converted_interface_err + attribute \src "ls180.v:250.12-250.51" + wire width 8 \main_interface0_converted_interface_sel + attribute \src "ls180.v:252.6-252.45" + wire \main_interface0_converted_interface_stb + attribute \src "ls180.v:254.6-254.44" + wire \main_interface0_converted_interface_we + attribute \src "ls180.v:208.5-208.32" + wire \main_interface0_ram_bus_ack + attribute \src "ls180.v:202.13-202.40" + wire width 30 \main_interface0_ram_bus_adr + attribute \src "ls180.v:211.12-211.39" + wire width 2 \main_interface0_ram_bus_bte + attribute \src "ls180.v:210.12-210.39" + wire width 3 \main_interface0_ram_bus_cti + attribute \src "ls180.v:206.6-206.33" + wire \main_interface0_ram_bus_cyc + attribute \src "ls180.v:204.13-204.42" + wire width 64 \main_interface0_ram_bus_dat_r + attribute \src "ls180.v:203.13-203.42" + wire width 64 \main_interface0_ram_bus_dat_w + attribute \src "ls180.v:212.5-212.32" + wire \main_interface0_ram_bus_err + attribute \src "ls180.v:205.12-205.39" + wire width 8 \main_interface0_ram_bus_sel + attribute \src "ls180.v:207.6-207.33" + wire \main_interface0_ram_bus_stb + attribute \src "ls180.v:209.6-209.32" + wire \main_interface0_ram_bus_we + attribute \src "ls180.v:1686.6-1686.29" wire \main_interface1_bus_ack - attribute \src "ls180.v:1636.12-1636.35" + attribute \src "ls180.v:1680.12-1680.35" wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1645.11-1645.34" + attribute \src "ls180.v:1689.11-1689.34" wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1644.11-1644.34" + attribute \src "ls180.v:1688.11-1688.34" wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1640.5-1640.28" + attribute \src "ls180.v:1684.5-1684.28" wire \main_interface1_bus_cyc - attribute \src "ls180.v:1638.13-1638.38" - wire width 32 \main_interface1_bus_dat_r - attribute \src "ls180.v:1637.12-1637.37" - wire width 32 \main_interface1_bus_dat_w - attribute \src "ls180.v:1646.6-1646.29" + attribute \src "ls180.v:1682.13-1682.38" + wire width 64 \main_interface1_bus_dat_r + attribute \src "ls180.v:1681.12-1681.37" + wire width 64 \main_interface1_bus_dat_w + attribute \src "ls180.v:1690.6-1690.29" wire \main_interface1_bus_err - attribute \src "ls180.v:1639.11-1639.34" - wire width 4 \main_interface1_bus_sel - attribute \src "ls180.v:1641.5-1641.28" + attribute \src "ls180.v:1683.11-1683.34" + wire width 8 \main_interface1_bus_sel + attribute \src "ls180.v:1685.5-1685.28" wire \main_interface1_bus_stb - attribute \src "ls180.v:1643.5-1643.27" + attribute \src "ls180.v:1687.5-1687.27" wire \main_interface1_bus_we - attribute \src "ls180.v:214.12-214.32" - wire width 7 \main_libresocsim_adr + attribute \src "ls180.v:268.5-268.44" + wire \main_interface1_converted_interface_ack + attribute \src "ls180.v:262.13-262.52" + wire width 30 \main_interface1_converted_interface_adr + attribute \src "ls180.v:271.12-271.51" + wire width 2 \main_interface1_converted_interface_bte + attribute \src "ls180.v:270.12-270.51" + wire width 3 \main_interface1_converted_interface_cti + attribute \src "ls180.v:266.6-266.45" + wire \main_interface1_converted_interface_cyc + attribute \src "ls180.v:264.13-264.54" + wire width 64 \main_interface1_converted_interface_dat_r + attribute \src "ls180.v:263.13-263.54" + wire width 64 \main_interface1_converted_interface_dat_w + attribute \src "ls180.v:272.5-272.44" + wire \main_interface1_converted_interface_err + attribute \src "ls180.v:265.12-265.51" + wire width 8 \main_interface1_converted_interface_sel + attribute \src "ls180.v:267.6-267.45" + wire \main_interface1_converted_interface_stb + attribute \src "ls180.v:269.6-269.44" + wire \main_interface1_converted_interface_we + attribute \src "ls180.v:223.5-223.32" + wire \main_interface1_ram_bus_ack + attribute \src "ls180.v:217.13-217.40" + wire width 30 \main_interface1_ram_bus_adr + attribute \src "ls180.v:226.12-226.39" + wire width 2 \main_interface1_ram_bus_bte + attribute \src "ls180.v:225.12-225.39" + wire width 3 \main_interface1_ram_bus_cti + attribute \src "ls180.v:221.6-221.33" + wire \main_interface1_ram_bus_cyc + attribute \src "ls180.v:219.13-219.42" + wire width 64 \main_interface1_ram_bus_dat_r + attribute \src "ls180.v:218.13-218.42" + wire width 64 \main_interface1_ram_bus_dat_w + attribute \src "ls180.v:227.5-227.32" + wire \main_interface1_ram_bus_err + attribute \src "ls180.v:220.12-220.39" + wire width 8 \main_interface1_ram_bus_sel + attribute \src "ls180.v:222.6-222.33" + wire \main_interface1_ram_bus_stb + attribute \src "ls180.v:224.6-224.32" + wire \main_interface1_ram_bus_we + attribute \src "ls180.v:238.5-238.32" + wire \main_interface2_ram_bus_ack + attribute \src "ls180.v:232.13-232.40" + wire width 30 \main_interface2_ram_bus_adr + attribute \src "ls180.v:241.12-241.39" + wire width 2 \main_interface2_ram_bus_bte + attribute \src "ls180.v:240.12-240.39" + wire width 3 \main_interface2_ram_bus_cti + attribute \src "ls180.v:236.6-236.33" + wire \main_interface2_ram_bus_cyc + attribute \src "ls180.v:234.13-234.42" + wire width 64 \main_interface2_ram_bus_dat_r + attribute \src "ls180.v:233.13-233.42" + wire width 64 \main_interface2_ram_bus_dat_w + attribute \src "ls180.v:242.5-242.32" + wire \main_interface2_ram_bus_err + attribute \src "ls180.v:235.12-235.39" + wire width 8 \main_interface2_ram_bus_sel + attribute \src "ls180.v:237.6-237.33" + wire \main_interface2_ram_bus_stb + attribute \src "ls180.v:239.6-239.32" + wire \main_interface2_ram_bus_we + attribute \src "ls180.v:171.12-171.32" + wire width 9 \main_libresocsim_adr attribute \src "ls180.v:62.6-62.32" wire \main_libresocsim_bus_error attribute \src "ls180.v:63.12-63.39" @@ -231505,217 +232269,119 @@ module \ls180 wire width 32 \main_libresocsim_bus_errors_status attribute \src "ls180.v:60.6-60.36" wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:170.5-170.40" - wire \main_libresocsim_converter0_counter - attribute \src "ls180.v:1732.5-1732.62" - wire \main_libresocsim_converter0_counter_converter0_next_value - attribute \src "ls180.v:1733.5-1733.65" - wire \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:172.12-172.45" - wire width 64 \main_libresocsim_converter0_dat_r - attribute \src "ls180.v:171.6-171.39" - wire \main_libresocsim_converter0_reset - attribute \src "ls180.v:169.5-169.37" - wire \main_libresocsim_converter0_skip - attribute \src "ls180.v:185.5-185.40" - wire \main_libresocsim_converter1_counter - attribute \src "ls180.v:1736.5-1736.62" - wire \main_libresocsim_converter1_counter_converter1_next_value - attribute \src "ls180.v:1737.5-1737.65" - wire \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:187.12-187.45" - wire width 64 \main_libresocsim_converter1_dat_r - attribute \src "ls180.v:186.6-186.39" - wire \main_libresocsim_converter1_reset - attribute \src "ls180.v:184.5-184.37" - wire \main_libresocsim_converter1_skip - attribute \src "ls180.v:200.5-200.40" - wire \main_libresocsim_converter2_counter - attribute \src "ls180.v:1740.5-1740.62" - wire \main_libresocsim_converter2_counter_converter2_next_value - attribute \src "ls180.v:1741.5-1741.65" - wire \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:202.12-202.45" - wire width 64 \main_libresocsim_converter2_dat_r - attribute \src "ls180.v:201.6-201.39" - wire \main_libresocsim_converter2_reset - attribute \src "ls180.v:199.5-199.37" - wire \main_libresocsim_converter2_skip - attribute \src "ls180.v:215.13-215.35" - wire width 32 \main_libresocsim_dat_r - attribute \src "ls180.v:217.13-217.35" - wire width 32 \main_libresocsim_dat_w - attribute \src "ls180.v:223.5-223.27" + attribute \src "ls180.v:172.13-172.35" + wire width 64 \main_libresocsim_dat_r + attribute \src "ls180.v:174.13-174.35" + wire width 64 \main_libresocsim_dat_w + attribute \src "ls180.v:180.5-180.27" wire \main_libresocsim_en_re - attribute \src "ls180.v:222.5-222.32" + attribute \src "ls180.v:179.5-179.32" wire \main_libresocsim_en_storage - attribute \src "ls180.v:239.6-239.45" + attribute \src "ls180.v:196.6-196.45" wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:238.6-238.46" + attribute \src "ls180.v:195.6-195.46" wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:241.6-241.45" + attribute \src "ls180.v:198.6-198.45" wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:240.6-240.46" + attribute \src "ls180.v:197.6-197.46" wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:243.5-243.37" + attribute \src "ls180.v:200.5-200.37" wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:235.6-235.44" + attribute \src "ls180.v:192.6-192.44" wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:234.6-234.45" + attribute \src "ls180.v:191.6-191.45" wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:237.6-237.44" + attribute \src "ls180.v:194.6-194.44" wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:236.6-236.45" + attribute \src "ls180.v:193.6-193.45" wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:242.5-242.42" + attribute \src "ls180.v:199.5-199.42" wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:164.6-164.57" - wire \main_libresocsim_interface0_converted_interface_ack - attribute \src "ls180.v:158.12-158.63" - wire width 30 \main_libresocsim_interface0_converted_interface_adr - attribute \src "ls180.v:167.11-167.62" - wire width 2 \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:166.11-166.62" - wire width 3 \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:162.5-162.56" - wire \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:160.13-160.66" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_r - attribute \src "ls180.v:159.12-159.65" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:168.6-168.57" - wire \main_libresocsim_interface0_converted_interface_err - attribute \src "ls180.v:161.11-161.62" - wire width 4 \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:163.5-163.56" - wire \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:165.5-165.55" - wire \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:179.6-179.57" - wire \main_libresocsim_interface1_converted_interface_ack - attribute \src "ls180.v:173.12-173.63" - wire width 30 \main_libresocsim_interface1_converted_interface_adr - attribute \src "ls180.v:182.11-182.62" - wire width 2 \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:181.11-181.62" - wire width 3 \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:177.5-177.56" - wire \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:175.13-175.66" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_r - attribute \src "ls180.v:174.12-174.65" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:183.6-183.57" - wire \main_libresocsim_interface1_converted_interface_err - attribute \src "ls180.v:176.11-176.62" - wire width 4 \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:178.5-178.56" - wire \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:180.5-180.55" - wire \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:194.6-194.57" - wire \main_libresocsim_interface2_converted_interface_ack - attribute \src "ls180.v:188.12-188.63" - wire width 30 \main_libresocsim_interface2_converted_interface_adr - attribute \src "ls180.v:197.11-197.62" - wire width 2 \main_libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:196.11-196.62" - wire width 3 \main_libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:192.5-192.56" - wire \main_libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:190.13-190.66" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_r - attribute \src "ls180.v:189.12-189.65" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:198.6-198.57" - wire \main_libresocsim_interface2_converted_interface_err - attribute \src "ls180.v:191.11-191.62" - wire width 4 \main_libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:193.5-193.56" - wire \main_libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:195.5-195.55" - wire \main_libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:228.6-228.26" + attribute \src "ls180.v:185.6-185.26" wire \main_libresocsim_irq - attribute \src "ls180.v:119.6-119.32" + attribute \src "ls180.v:121.6-121.32" wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:120.6-120.32" + attribute \src "ls180.v:122.6-122.32" wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:121.13-121.39" + attribute \src "ls180.v:123.13-123.39" wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:123.12-123.45" + attribute \src "ls180.v:125.12-125.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:150.13-150.67" + attribute \src "ls180.v:131.13-131.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:151.13-151.67" + attribute \src "ls180.v:132.13-132.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:152.13-152.68" + attribute \src "ls180.v:133.13-133.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:146.6-146.61" + attribute \src "ls180.v:152.6-152.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:147.6-147.63" + attribute \src "ls180.v:153.6-153.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:148.6-148.63" + attribute \src "ls180.v:154.6-154.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:149.6-149.64" + attribute \src "ls180.v:155.6-155.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:137.6-137.64" + attribute \src "ls180.v:134.6-134.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:138.6-138.66" + attribute \src "ls180.v:135.6-135.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:139.6-139.66" + attribute \src "ls180.v:136.6-136.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:140.6-140.67" + attribute \src "ls180.v:137.6-137.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:125.13-125.68" + attribute \src "ls180.v:138.13-138.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:134.12-134.68" + attribute \src "ls180.v:147.12-147.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:131.6-131.65" + attribute \src "ls180.v:144.6-144.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:133.6-133.63" + attribute \src "ls180.v:146.6-146.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:132.6-132.64" + attribute \src "ls180.v:145.6-145.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:135.12-135.68" + attribute \src "ls180.v:148.12-148.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:126.13-126.71" + attribute \src "ls180.v:139.13-139.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:127.13-127.71" + attribute \src "ls180.v:140.13-140.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:128.6-128.65" + attribute \src "ls180.v:141.6-141.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:130.6-130.65" + attribute \src "ls180.v:143.6-143.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:129.6-129.64" + attribute \src "ls180.v:142.6-142.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:142.6-142.67" + attribute \src "ls180.v:156.6-156.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:144.6-144.68" + attribute \src "ls180.v:158.6-158.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:145.6-145.68" + attribute \src "ls180.v:159.6-159.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:143.6-143.68" + attribute \src "ls180.v:157.6-157.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:154.6-154.67" + attribute \src "ls180.v:127.6-127.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:156.6-156.68" + attribute \src "ls180.v:129.6-129.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:157.6-157.68" + attribute \src "ls180.v:130.6-130.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:155.6-155.68" + attribute \src "ls180.v:128.6-128.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - attribute \src "ls180.v:72.5-72.39" + attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack attribute \src "ls180.v:66.13-66.47" wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:75.11-75.45" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:74.11-74.45" + wire width 3 \main_libresocsim_libresoc_dbus_cti attribute \src "ls180.v:70.6-70.40" wire \main_libresocsim_libresoc_dbus_cyc attribute \src "ls180.v:68.13-68.49" wire width 64 \main_libresocsim_libresoc_dbus_dat_r attribute \src "ls180.v:67.13-67.49" wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:74.5-74.39" + attribute \src "ls180.v:76.6-76.40" wire \main_libresocsim_libresoc_dbus_err attribute \src "ls180.v:69.12-69.46" wire width 8 \main_libresocsim_libresoc_dbus_sel @@ -231723,45 +232389,53 @@ module \ls180 wire \main_libresocsim_libresoc_dbus_stb attribute \src "ls180.v:73.6-73.39" wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:81.5-81.39" + attribute \src "ls180.v:83.6-83.40" wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:75.13-75.47" + attribute \src "ls180.v:77.13-77.47" wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:79.6-79.40" + attribute \src "ls180.v:86.11-86.45" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:85.11-85.45" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:81.6-81.40" wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:77.13-77.49" + attribute \src "ls180.v:79.13-79.49" wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:76.13-76.49" + attribute \src "ls180.v:78.13-78.49" wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:83.5-83.39" + attribute \src "ls180.v:87.6-87.40" wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:78.12-78.46" + attribute \src "ls180.v:80.12-80.46" wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:80.6-80.40" + attribute \src "ls180.v:82.6-82.40" wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:82.6-82.39" + attribute \src "ls180.v:84.6-84.39" wire \main_libresocsim_libresoc_ibus_we attribute \src "ls180.v:65.12-65.47" wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:115.6-115.40" - wire \main_libresocsim_libresoc_jtag_tck attribute \src "ls180.v:117.6-117.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:119.6-119.40" wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:118.6-118.40" + attribute \src "ls180.v:120.6-120.40" wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:116.6-116.40" + attribute \src "ls180.v:118.6-118.40" wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:112.5-112.42" + attribute \src "ls180.v:112.6-112.43" wire \main_libresocsim_libresoc_jtag_wb_ack attribute \src "ls180.v:106.13-106.50" wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:115.11-115.48" + wire width 2 \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:114.11-114.48" + wire width 3 \main_libresocsim_libresoc_jtag_wb_cti attribute \src "ls180.v:110.6-110.43" wire \main_libresocsim_libresoc_jtag_wb_cyc attribute \src "ls180.v:108.13-108.52" wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r attribute \src "ls180.v:107.13-107.52" wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:114.5-114.42" + attribute \src "ls180.v:116.6-116.43" wire \main_libresocsim_libresoc_jtag_wb_err attribute \src "ls180.v:109.12-109.49" wire width 8 \main_libresocsim_libresoc_jtag_wb_sel @@ -231769,85 +232443,77 @@ module \ls180 wire \main_libresocsim_libresoc_jtag_wb_stb attribute \src "ls180.v:113.6-113.42" wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:122.6-122.40" + attribute \src "ls180.v:124.6-124.40" wire \main_libresocsim_libresoc_pll_18_o - attribute \src "ls180.v:124.6-124.41" + attribute \src "ls180.v:126.6-126.41" wire \main_libresocsim_libresoc_pll_lck_o attribute \src "ls180.v:64.6-64.37" wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:90.6-90.44" + attribute \src "ls180.v:94.6-94.44" wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:84.13-84.51" + attribute \src "ls180.v:88.12-88.50" wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:93.12-93.50" - wire width 2 \main_libresocsim_libresoc_xics_icp_bte - attribute \src "ls180.v:92.12-92.50" - wire width 3 \main_libresocsim_libresoc_xics_icp_cti - attribute \src "ls180.v:88.6-88.44" + attribute \src "ls180.v:92.5-92.43" wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:86.13-86.53" + attribute \src "ls180.v:90.13-90.53" wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:85.13-85.53" + attribute \src "ls180.v:89.12-89.52" wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:94.6-94.44" + attribute \src "ls180.v:96.6-96.44" wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:87.12-87.50" + attribute \src "ls180.v:91.11-91.49" wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:89.6-89.44" + attribute \src "ls180.v:93.5-93.43" wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:91.6-91.43" + attribute \src "ls180.v:95.5-95.42" wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:101.6-101.44" + attribute \src "ls180.v:103.6-103.44" wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:95.13-95.51" + attribute \src "ls180.v:97.12-97.50" wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:104.12-104.50" - wire width 2 \main_libresocsim_libresoc_xics_ics_bte - attribute \src "ls180.v:103.12-103.50" - wire width 3 \main_libresocsim_libresoc_xics_ics_cti - attribute \src "ls180.v:99.6-99.44" + attribute \src "ls180.v:101.5-101.43" wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:97.13-97.53" + attribute \src "ls180.v:99.13-99.53" wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:96.13-96.53" + attribute \src "ls180.v:98.12-98.52" wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w attribute \src "ls180.v:105.6-105.44" wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:98.12-98.50" + attribute \src "ls180.v:100.11-100.49" wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:100.6-100.44" + attribute \src "ls180.v:102.5-102.43" wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:102.6-102.43" + attribute \src "ls180.v:104.5-104.42" wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:219.5-219.29" + attribute \src "ls180.v:176.5-176.29" wire \main_libresocsim_load_re - attribute \src "ls180.v:218.12-218.41" + attribute \src "ls180.v:175.12-175.41" wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:209.5-209.33" + attribute \src "ls180.v:166.5-166.33" wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:203.13-203.41" + attribute \src "ls180.v:160.13-160.41" wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:212.12-212.40" + attribute \src "ls180.v:169.12-169.40" wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:211.12-211.40" + attribute \src "ls180.v:168.12-168.40" wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:207.6-207.34" + attribute \src "ls180.v:164.6-164.34" wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:205.13-205.43" - wire width 32 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:204.13-204.43" - wire width 32 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:213.5-213.33" + attribute \src "ls180.v:162.13-162.43" + wire width 64 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:161.13-161.43" + wire width 64 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:170.5-170.33" wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:206.12-206.40" - wire width 4 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:208.6-208.34" + attribute \src "ls180.v:163.12-163.40" + wire width 8 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:165.6-165.34" wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:210.6-210.33" + attribute \src "ls180.v:167.6-167.33" wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:221.5-221.31" + attribute \src "ls180.v:178.5-178.31" wire \main_libresocsim_reload_re - attribute \src "ls180.v:220.12-220.43" + attribute \src "ls180.v:177.12-177.43" wire width 32 \main_libresocsim_reload_storage attribute \src "ls180.v:61.6-61.28" wire \main_libresocsim_reset @@ -231859,3221 +232525,3279 @@ module \ls180 wire \main_libresocsim_scratch_re attribute \src "ls180.v:57.12-57.44" wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:225.5-225.37" + attribute \src "ls180.v:182.5-182.37" wire \main_libresocsim_update_value_re - attribute \src "ls180.v:224.5-224.42" + attribute \src "ls180.v:181.5-181.42" wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:244.12-244.34" + attribute \src "ls180.v:201.12-201.34" wire width 32 \main_libresocsim_value - attribute \src "ls180.v:226.12-226.41" + attribute \src "ls180.v:183.12-183.41" wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:227.6-227.31" + attribute \src "ls180.v:184.6-184.31" wire \main_libresocsim_value_we - attribute \src "ls180.v:216.11-216.30" - wire width 4 \main_libresocsim_we - attribute \src "ls180.v:232.5-232.32" + attribute \src "ls180.v:173.11-173.30" + wire width 8 \main_libresocsim_we + attribute \src "ls180.v:189.5-189.32" wire \main_libresocsim_zero_clear - attribute \src "ls180.v:233.5-233.38" + attribute \src "ls180.v:190.5-190.38" wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:230.5-230.34" + attribute \src "ls180.v:187.5-187.34" wire \main_libresocsim_zero_pending - attribute \src "ls180.v:229.6-229.34" + attribute \src "ls180.v:186.6-186.34" wire \main_libresocsim_zero_status - attribute \src "ls180.v:231.6-231.35" + attribute \src "ls180.v:188.6-188.35" wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:826.6-826.26" + attribute \src "ls180.v:870.6-870.26" wire \main_litedram_wb_ack - attribute \src "ls180.v:820.12-820.32" + attribute \src "ls180.v:864.12-864.32" wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:824.5-824.25" + attribute \src "ls180.v:868.5-868.25" wire \main_litedram_wb_cyc - attribute \src "ls180.v:822.13-822.35" + attribute \src "ls180.v:866.13-866.35" wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:821.12-821.34" + attribute \src "ls180.v:865.12-865.34" wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:823.11-823.31" + attribute \src "ls180.v:867.11-867.31" wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:825.5-825.25" + attribute \src "ls180.v:869.5-869.25" wire \main_litedram_wb_stb - attribute \src "ls180.v:827.5-827.24" + attribute \src "ls180.v:871.5-871.24" wire \main_litedram_wb_we - attribute \src "ls180.v:1062.13-1062.20" + attribute \src "ls180.v:1106.13-1106.20" wire width 24 \main_nc - attribute \src "ls180.v:799.6-799.24" + attribute \src "ls180.v:831.6-831.24" wire \main_port_cmd_last - attribute \src "ls180.v:801.13-801.39" + attribute \src "ls180.v:833.13-833.39" wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:800.6-800.30" + attribute \src "ls180.v:832.6-832.30" wire \main_port_cmd_payload_we - attribute \src "ls180.v:798.6-798.25" + attribute \src "ls180.v:830.6-830.25" wire \main_port_cmd_ready - attribute \src "ls180.v:797.6-797.25" + attribute \src "ls180.v:829.6-829.25" wire \main_port_cmd_valid - attribute \src "ls180.v:796.6-796.21" + attribute \src "ls180.v:828.6-828.21" wire \main_port_flush - attribute \src "ls180.v:808.13-808.41" + attribute \src "ls180.v:840.13-840.41" wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:807.6-807.27" + attribute \src "ls180.v:839.6-839.27" wire \main_port_rdata_ready - attribute \src "ls180.v:806.6-806.27" + attribute \src "ls180.v:838.6-838.27" wire \main_port_rdata_valid - attribute \src "ls180.v:804.13-804.41" + attribute \src "ls180.v:836.13-836.41" wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:805.12-805.38" + attribute \src "ls180.v:837.12-837.38" wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:803.6-803.27" + attribute \src "ls180.v:835.6-835.27" wire \main_port_wdata_ready - attribute \src "ls180.v:802.6-802.27" + attribute \src "ls180.v:834.6-834.27" wire \main_port_wdata_valid - attribute \src "ls180.v:1067.12-1067.29" + attribute \src "ls180.v:1111.12-1111.29" wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1064.6-1064.22" + attribute \src "ls180.v:1108.6-1108.22" wire \main_pwm0_enable - attribute \src "ls180.v:1069.5-1069.24" + attribute \src "ls180.v:1113.5-1113.24" wire \main_pwm0_enable_re - attribute \src "ls180.v:1068.5-1068.29" + attribute \src "ls180.v:1112.5-1112.29" wire \main_pwm0_enable_storage - attribute \src "ls180.v:1066.13-1066.29" + attribute \src "ls180.v:1110.13-1110.29" wire width 32 \main_pwm0_period - attribute \src "ls180.v:1073.5-1073.24" + attribute \src "ls180.v:1117.5-1117.24" wire \main_pwm0_period_re - attribute \src "ls180.v:1072.12-1072.36" + attribute \src "ls180.v:1116.12-1116.36" wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1065.13-1065.28" + attribute \src "ls180.v:1109.13-1109.28" wire width 32 \main_pwm0_width - attribute \src "ls180.v:1071.5-1071.23" + attribute \src "ls180.v:1115.5-1115.23" wire \main_pwm0_width_re - attribute \src "ls180.v:1070.12-1070.35" + attribute \src "ls180.v:1114.12-1114.35" wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1077.12-1077.29" + attribute \src "ls180.v:1121.12-1121.29" wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1074.6-1074.22" + attribute \src "ls180.v:1118.6-1118.22" wire \main_pwm1_enable - attribute \src "ls180.v:1079.5-1079.24" + attribute \src "ls180.v:1123.5-1123.24" wire \main_pwm1_enable_re - attribute \src "ls180.v:1078.5-1078.29" + attribute \src "ls180.v:1122.5-1122.29" wire \main_pwm1_enable_storage - attribute \src "ls180.v:1076.13-1076.29" + attribute \src "ls180.v:1120.13-1120.29" wire width 32 \main_pwm1_period - attribute \src "ls180.v:1083.5-1083.24" + attribute \src "ls180.v:1127.5-1127.24" wire \main_pwm1_period_re - attribute \src "ls180.v:1082.12-1082.36" + attribute \src "ls180.v:1126.12-1126.36" wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1075.13-1075.28" + attribute \src "ls180.v:1119.13-1119.28" wire width 32 \main_pwm1_width - attribute \src "ls180.v:1081.5-1081.23" + attribute \src "ls180.v:1125.5-1125.23" wire \main_pwm1_width_re - attribute \src "ls180.v:1080.12-1080.35" + attribute \src "ls180.v:1124.12-1124.35" wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:265.11-265.25" + attribute \src "ls180.v:297.11-297.25" wire width 3 \main_rddata_en - attribute \src "ls180.v:1605.11-1605.43" - wire width 2 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1606.6-1606.42" + attribute \src "ls180.v:1649.11-1649.43" + wire width 3 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1650.6-1650.42" wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1596.6-1596.43" + attribute \src "ls180.v:1640.6-1640.43" wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1597.6-1597.42" + attribute \src "ls180.v:1641.6-1641.42" wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1598.12-1598.56" + attribute \src "ls180.v:1642.12-1642.56" wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1595.6-1595.43" + attribute \src "ls180.v:1639.6-1639.43" wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1594.6-1594.43" + attribute \src "ls180.v:1638.6-1638.43" wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1601.5-1601.44" + attribute \src "ls180.v:1645.5-1645.44" wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1602.5-1602.43" + attribute \src "ls180.v:1646.5-1646.43" wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1603.12-1603.58" - wire width 32 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1604.11-1604.70" - wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1600.6-1600.45" + attribute \src "ls180.v:1647.12-1647.58" + wire width 64 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1648.11-1648.70" + wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1644.6-1644.45" wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1599.6-1599.45" + attribute \src "ls180.v:1643.6-1643.45" wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1607.5-1607.42" + attribute \src "ls180.v:1651.5-1651.42" wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1580.11-1580.40" + attribute \src "ls180.v:1624.11-1624.40" wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1585.6-1585.35" + attribute \src "ls180.v:1629.6-1629.35" wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1589.6-1589.41" + attribute \src "ls180.v:1633.6-1633.41" wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1590.6-1590.40" + attribute \src "ls180.v:1634.6-1634.40" wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1588.12-1588.54" + attribute \src "ls180.v:1632.12-1632.54" wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1592.6-1592.42" + attribute \src "ls180.v:1636.6-1636.42" wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1593.6-1593.41" + attribute \src "ls180.v:1637.6-1637.41" wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1591.12-1591.55" + attribute \src "ls180.v:1635.12-1635.55" wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1577.11-1577.38" + attribute \src "ls180.v:1621.11-1621.38" wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1579.11-1579.40" + attribute \src "ls180.v:1623.11-1623.40" wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1586.12-1586.44" + attribute \src "ls180.v:1630.12-1630.44" wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1587.12-1587.46" + attribute \src "ls180.v:1631.12-1631.46" wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1578.5-1578.34" + attribute \src "ls180.v:1622.5-1622.34" wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1563.6-1563.38" + attribute \src "ls180.v:1607.6-1607.38" wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1564.6-1564.37" + attribute \src "ls180.v:1608.6-1608.37" wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1565.12-1565.51" + attribute \src "ls180.v:1609.12-1609.51" wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1562.6-1562.38" + attribute \src "ls180.v:1606.6-1606.38" wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1561.6-1561.38" + attribute \src "ls180.v:1605.6-1605.38" wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1568.6-1568.40" + attribute \src "ls180.v:1612.6-1612.40" wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1569.6-1569.39" + attribute \src "ls180.v:1613.6-1613.39" wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1570.12-1570.53" + attribute \src "ls180.v:1614.12-1614.53" wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1567.6-1567.40" + attribute \src "ls180.v:1611.6-1611.40" wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1566.6-1566.40" + attribute \src "ls180.v:1610.6-1610.40" wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1575.12-1575.46" + attribute \src "ls180.v:1619.12-1619.46" wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1576.12-1576.47" + attribute \src "ls180.v:1620.12-1620.47" wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1573.6-1573.39" + attribute \src "ls180.v:1617.6-1617.39" wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1574.6-1574.45" + attribute \src "ls180.v:1618.6-1618.45" wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1571.6-1571.39" + attribute \src "ls180.v:1615.6-1615.39" wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1572.6-1572.45" + attribute \src "ls180.v:1616.6-1616.45" wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1581.11-1581.43" + attribute \src "ls180.v:1625.11-1625.43" wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1582.12-1582.46" + attribute \src "ls180.v:1626.12-1626.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1584.12-1584.46" + attribute \src "ls180.v:1628.12-1628.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1583.6-1583.37" + attribute \src "ls180.v:1627.6-1627.37" wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1558.6-1558.38" + attribute \src "ls180.v:1602.6-1602.38" wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1559.6-1559.37" + attribute \src "ls180.v:1603.6-1603.37" wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1615.12-1615.54" + attribute \src "ls180.v:1659.12-1659.54" wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1560.12-1560.52" + attribute \src "ls180.v:1604.12-1604.52" wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1616.12-1616.52" - wire width 32 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1557.6-1557.39" + attribute \src "ls180.v:1660.12-1660.52" + wire width 64 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1601.6-1601.39" wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1614.6-1614.39" + attribute \src "ls180.v:1658.6-1658.39" wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1556.6-1556.39" + attribute \src "ls180.v:1600.6-1600.39" wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1613.5-1613.38" + attribute \src "ls180.v:1657.5-1657.38" wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1610.6-1610.42" + attribute \src "ls180.v:1654.6-1654.42" wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1611.6-1611.41" + attribute \src "ls180.v:1655.6-1655.41" wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1612.13-1612.56" - wire width 32 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1609.6-1609.42" + attribute \src "ls180.v:1656.13-1656.56" + wire width 64 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1653.6-1653.42" wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1608.6-1608.42" + attribute \src "ls180.v:1652.6-1652.42" wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1632.13-1632.52" + attribute \src "ls180.v:1676.13-1676.52" wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1623.5-1623.47" + attribute \src "ls180.v:1667.5-1667.47" wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1622.12-1622.59" + attribute \src "ls180.v:1666.12-1666.59" wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1627.5-1627.49" + attribute \src "ls180.v:1671.5-1671.49" wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1626.5-1626.54" + attribute \src "ls180.v:1670.5-1670.54" wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1634.13-1634.54" + attribute \src "ls180.v:1678.13-1678.54" wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1625.5-1625.49" + attribute \src "ls180.v:1669.5-1669.49" wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1624.12-1624.61" + attribute \src "ls180.v:1668.12-1668.61" wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1631.5-1631.47" + attribute \src "ls180.v:1675.5-1675.47" wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1630.5-1630.52" + attribute \src "ls180.v:1674.5-1674.52" wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1633.12-1633.53" + attribute \src "ls180.v:1677.12-1677.53" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1853.12-1853.79" + attribute \src "ls180.v:1897.12-1897.79" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1854.5-1854.75" + attribute \src "ls180.v:1898.5-1898.75" wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1635.6-1635.46" + attribute \src "ls180.v:1679.6-1679.46" wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1619.6-1619.51" + attribute \src "ls180.v:1663.6-1663.51" wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1620.6-1620.50" + attribute \src "ls180.v:1664.6-1664.50" wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1621.13-1621.65" - wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1618.5-1618.50" + attribute \src "ls180.v:1665.13-1665.65" + wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1662.5-1662.50" wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1617.6-1617.51" + attribute \src "ls180.v:1661.6-1661.51" wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1628.5-1628.46" + attribute \src "ls180.v:1672.5-1672.46" wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1629.6-1629.43" + attribute \src "ls180.v:1673.6-1673.43" wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1397.5-1397.31" + attribute \src "ls180.v:1441.5-1441.31" wire \main_sdcore_block_count_re - attribute \src "ls180.v:1396.12-1396.43" + attribute \src "ls180.v:1440.12-1440.43" wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1395.5-1395.32" + attribute \src "ls180.v:1439.5-1439.32" wire \main_sdcore_block_length_re - attribute \src "ls180.v:1394.11-1394.43" + attribute \src "ls180.v:1438.11-1438.43" wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1381.5-1381.32" + attribute \src "ls180.v:1425.5-1425.32" wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1380.12-1380.44" + attribute \src "ls180.v:1424.12-1424.44" wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1383.5-1383.31" + attribute \src "ls180.v:1427.5-1427.31" wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1382.12-1382.43" + attribute \src "ls180.v:1426.12-1426.43" wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1536.11-1536.32" + attribute \src "ls180.v:1580.11-1580.32" wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1837.11-1837.55" + attribute \src "ls180.v:1881.11-1881.55" wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1838.5-1838.52" + attribute \src "ls180.v:1882.5-1882.52" wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1537.5-1537.25" + attribute \src "ls180.v:1581.5-1581.25" wire \main_sdcore_cmd_done - attribute \src "ls180.v:1833.5-1833.48" + attribute \src "ls180.v:1877.5-1877.48" wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1834.5-1834.51" + attribute \src "ls180.v:1878.5-1878.51" wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1538.5-1538.26" + attribute \src "ls180.v:1582.5-1582.26" wire \main_sdcore_cmd_error - attribute \src "ls180.v:1841.5-1841.49" + attribute \src "ls180.v:1885.5-1885.49" wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1842.5-1842.52" + attribute \src "ls180.v:1886.5-1886.52" wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1390.12-1390.40" + attribute \src "ls180.v:1434.12-1434.40" wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1391.6-1391.30" + attribute \src "ls180.v:1435.6-1435.30" wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1388.13-1388.44" + attribute \src "ls180.v:1432.13-1432.44" wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1849.13-1849.67" + attribute \src "ls180.v:1893.13-1893.67" wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1850.5-1850.62" + attribute \src "ls180.v:1894.5-1894.62" wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1389.6-1389.33" + attribute \src "ls180.v:1433.6-1433.33" wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1385.6-1385.28" + attribute \src "ls180.v:1429.6-1429.28" wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1384.6-1384.29" + attribute \src "ls180.v:1428.6-1428.29" wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1387.5-1387.27" + attribute \src "ls180.v:1431.5-1431.27" wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1386.6-1386.29" + attribute \src "ls180.v:1430.6-1430.29" wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1539.5-1539.28" + attribute \src "ls180.v:1583.5-1583.28" wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1843.5-1843.51" + attribute \src "ls180.v:1887.5-1887.51" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1844.5-1844.54" + attribute \src "ls180.v:1888.5-1888.54" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1535.12-1535.32" + attribute \src "ls180.v:1579.12-1579.32" wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1497.11-1497.40" + attribute \src "ls180.v:1541.11-1541.40" wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1503.5-1503.39" + attribute \src "ls180.v:1547.5-1547.39" wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1502.12-1502.46" + attribute \src "ls180.v:1546.12-1546.46" wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1498.12-1498.50" + attribute \src "ls180.v:1542.12-1542.50" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1499.13-1499.51" + attribute \src "ls180.v:1543.13-1543.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1500.13-1500.51" + attribute \src "ls180.v:1544.13-1544.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1504.6-1504.43" + attribute \src "ls180.v:1548.6-1548.43" wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1501.12-1501.46" + attribute \src "ls180.v:1545.12-1545.46" wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1510.5-1510.39" + attribute \src "ls180.v:1554.5-1554.39" wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1509.12-1509.46" + attribute \src "ls180.v:1553.12-1553.46" wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1505.12-1505.50" + attribute \src "ls180.v:1549.12-1549.50" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1506.13-1506.51" + attribute \src "ls180.v:1550.13-1550.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1507.13-1507.51" + attribute \src "ls180.v:1551.13-1551.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1511.6-1511.43" + attribute \src "ls180.v:1555.6-1555.43" wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1508.12-1508.46" + attribute \src "ls180.v:1552.12-1552.46" wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1517.5-1517.39" + attribute \src "ls180.v:1561.5-1561.39" wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1516.12-1516.46" + attribute \src "ls180.v:1560.12-1560.46" wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1512.12-1512.50" + attribute \src "ls180.v:1556.12-1556.50" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1513.13-1513.51" + attribute \src "ls180.v:1557.13-1557.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1514.13-1514.51" + attribute \src "ls180.v:1558.13-1558.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1518.6-1518.43" + attribute \src "ls180.v:1562.6-1562.43" wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1515.12-1515.46" + attribute \src "ls180.v:1559.12-1559.46" wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1524.5-1524.39" + attribute \src "ls180.v:1568.5-1568.39" wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1523.12-1523.46" + attribute \src "ls180.v:1567.12-1567.46" wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1519.12-1519.50" + attribute \src "ls180.v:1563.12-1563.50" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1520.13-1520.51" + attribute \src "ls180.v:1564.13-1564.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1521.13-1521.51" + attribute \src "ls180.v:1565.13-1565.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1525.6-1525.43" + attribute \src "ls180.v:1569.6-1569.43" wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1522.12-1522.46" + attribute \src "ls180.v:1566.12-1566.46" wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1526.12-1526.45" + attribute \src "ls180.v:1570.12-1570.45" wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1527.12-1527.45" + attribute \src "ls180.v:1571.12-1571.45" wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1528.12-1528.45" + attribute \src "ls180.v:1572.12-1572.45" wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1529.12-1529.45" + attribute \src "ls180.v:1573.12-1573.45" wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1531.12-1531.43" + attribute \src "ls180.v:1575.12-1575.43" wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1532.12-1532.43" + attribute \src "ls180.v:1576.12-1576.43" wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1533.12-1533.43" + attribute \src "ls180.v:1577.12-1577.43" wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1534.12-1534.43" + attribute \src "ls180.v:1578.12-1578.43" wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1488.5-1488.41" + attribute \src "ls180.v:1532.5-1532.41" wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1489.5-1489.40" + attribute \src "ls180.v:1533.5-1533.40" wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1490.11-1490.54" + attribute \src "ls180.v:1534.11-1534.54" wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1487.5-1487.41" + attribute \src "ls180.v:1531.5-1531.41" wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1486.5-1486.41" + attribute \src "ls180.v:1530.5-1530.41" wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1493.5-1493.43" + attribute \src "ls180.v:1537.5-1537.43" wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1494.6-1494.43" + attribute \src "ls180.v:1538.6-1538.43" wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1495.12-1495.57" + attribute \src "ls180.v:1539.12-1539.57" wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1492.6-1492.44" + attribute \src "ls180.v:1536.6-1536.44" wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1491.5-1491.43" + attribute \src "ls180.v:1535.5-1535.43" wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1496.11-1496.40" + attribute \src "ls180.v:1540.11-1540.40" wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1530.5-1530.36" + attribute \src "ls180.v:1574.5-1574.36" wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1453.11-1453.41" + attribute \src "ls180.v:1497.11-1497.41" wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1829.11-1829.80" + attribute \src "ls180.v:1873.11-1873.80" wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1830.5-1830.77" + attribute \src "ls180.v:1874.5-1874.77" wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1459.6-1459.41" + attribute \src "ls180.v:1503.6-1503.41" wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1458.12-1458.47" + attribute \src "ls180.v:1502.12-1502.47" wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1454.12-1454.51" + attribute \src "ls180.v:1498.12-1498.51" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1455.13-1455.52" + attribute \src "ls180.v:1499.13-1499.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1456.13-1456.52" + attribute \src "ls180.v:1500.13-1500.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1460.6-1460.44" + attribute \src "ls180.v:1504.6-1504.44" wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1457.12-1457.47" + attribute \src "ls180.v:1501.12-1501.47" wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1466.6-1466.41" + attribute \src "ls180.v:1510.6-1510.41" wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1465.12-1465.47" + attribute \src "ls180.v:1509.12-1509.47" wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1461.12-1461.51" + attribute \src "ls180.v:1505.12-1505.51" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1462.13-1462.52" + attribute \src "ls180.v:1506.13-1506.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1463.13-1463.52" + attribute \src "ls180.v:1507.13-1507.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1467.6-1467.44" + attribute \src "ls180.v:1511.6-1511.44" wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1464.12-1464.47" + attribute \src "ls180.v:1508.12-1508.47" wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1473.6-1473.41" + attribute \src "ls180.v:1517.6-1517.41" wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1472.12-1472.47" + attribute \src "ls180.v:1516.12-1516.47" wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1468.12-1468.51" + attribute \src "ls180.v:1512.12-1512.51" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1469.13-1469.52" + attribute \src "ls180.v:1513.13-1513.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1470.13-1470.52" + attribute \src "ls180.v:1514.13-1514.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1474.6-1474.44" + attribute \src "ls180.v:1518.6-1518.44" wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1471.12-1471.47" + attribute \src "ls180.v:1515.12-1515.47" wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1480.6-1480.41" + attribute \src "ls180.v:1524.6-1524.41" wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1479.12-1479.47" + attribute \src "ls180.v:1523.12-1523.47" wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1475.12-1475.51" + attribute \src "ls180.v:1519.12-1519.51" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1476.13-1476.52" + attribute \src "ls180.v:1520.13-1520.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1477.13-1477.52" + attribute \src "ls180.v:1521.13-1521.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1481.6-1481.44" + attribute \src "ls180.v:1525.6-1525.44" wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1478.12-1478.47" + attribute \src "ls180.v:1522.12-1522.47" wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1482.12-1482.46" + attribute \src "ls180.v:1526.12-1526.46" wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1821.12-1821.85" + attribute \src "ls180.v:1865.12-1865.85" wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1822.5-1822.81" + attribute \src "ls180.v:1866.5-1866.81" wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1483.12-1483.46" + attribute \src "ls180.v:1527.12-1527.46" wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1823.12-1823.85" + attribute \src "ls180.v:1867.12-1867.85" wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1824.5-1824.81" + attribute \src "ls180.v:1868.5-1868.81" wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1484.12-1484.46" + attribute \src "ls180.v:1528.12-1528.46" wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1825.12-1825.85" + attribute \src "ls180.v:1869.12-1869.85" wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1826.5-1826.81" + attribute \src "ls180.v:1870.5-1870.81" wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1485.12-1485.46" + attribute \src "ls180.v:1529.12-1529.46" wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1827.12-1827.85" + attribute \src "ls180.v:1871.12-1871.85" wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1828.5-1828.81" + attribute \src "ls180.v:1872.5-1872.81" wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1445.6-1445.43" + attribute \src "ls180.v:1489.6-1489.43" wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1446.6-1446.42" + attribute \src "ls180.v:1490.6-1490.42" wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1447.12-1447.56" + attribute \src "ls180.v:1491.12-1491.56" wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1444.5-1444.42" + attribute \src "ls180.v:1488.5-1488.42" wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1443.6-1443.43" + attribute \src "ls180.v:1487.6-1487.43" wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1450.5-1450.44" + attribute \src "ls180.v:1494.5-1494.44" wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1451.5-1451.43" + attribute \src "ls180.v:1495.5-1495.43" wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1452.11-1452.57" + attribute \src "ls180.v:1496.11-1496.57" wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1449.5-1449.44" + attribute \src "ls180.v:1493.5-1493.44" wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1448.5-1448.44" + attribute \src "ls180.v:1492.5-1492.44" wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1441.6-1441.35" + attribute \src "ls180.v:1485.6-1485.35" wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1440.11-1440.40" + attribute \src "ls180.v:1484.11-1484.40" wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1398.11-1398.44" + attribute \src "ls180.v:1442.11-1442.44" wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1399.12-1399.45" + attribute \src "ls180.v:1443.12-1443.45" wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1408.12-1408.46" + attribute \src "ls180.v:1452.12-1452.46" wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1409.12-1409.46" + attribute \src "ls180.v:1453.12-1453.46" wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1410.12-1410.46" + attribute \src "ls180.v:1454.12-1454.46" wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1411.12-1411.46" + attribute \src "ls180.v:1455.12-1455.46" wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1412.12-1412.46" + attribute \src "ls180.v:1456.12-1456.46" wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1413.12-1413.46" + attribute \src "ls180.v:1457.12-1457.46" wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1414.12-1414.46" + attribute \src "ls180.v:1458.12-1458.46" wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1415.12-1415.46" + attribute \src "ls180.v:1459.12-1459.46" wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1416.12-1416.46" + attribute \src "ls180.v:1460.12-1460.46" wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1417.12-1417.46" + attribute \src "ls180.v:1461.12-1461.46" wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1400.12-1400.45" + attribute \src "ls180.v:1444.12-1444.45" wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1418.12-1418.46" + attribute \src "ls180.v:1462.12-1462.46" wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1419.12-1419.46" + attribute \src "ls180.v:1463.12-1463.46" wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1420.12-1420.46" + attribute \src "ls180.v:1464.12-1464.46" wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1421.12-1421.46" + attribute \src "ls180.v:1465.12-1465.46" wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1422.12-1422.46" + attribute \src "ls180.v:1466.12-1466.46" wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1423.12-1423.46" + attribute \src "ls180.v:1467.12-1467.46" wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1424.12-1424.46" + attribute \src "ls180.v:1468.12-1468.46" wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1425.12-1425.46" + attribute \src "ls180.v:1469.12-1469.46" wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1426.12-1426.46" + attribute \src "ls180.v:1470.12-1470.46" wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1427.12-1427.46" + attribute \src "ls180.v:1471.12-1471.46" wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1401.12-1401.45" + attribute \src "ls180.v:1445.12-1445.45" wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1428.12-1428.46" + attribute \src "ls180.v:1472.12-1472.46" wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1429.12-1429.46" + attribute \src "ls180.v:1473.12-1473.46" wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1430.12-1430.46" + attribute \src "ls180.v:1474.12-1474.46" wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1431.12-1431.46" + attribute \src "ls180.v:1475.12-1475.46" wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1432.12-1432.46" + attribute \src "ls180.v:1476.12-1476.46" wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1433.12-1433.46" + attribute \src "ls180.v:1477.12-1477.46" wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1434.12-1434.46" + attribute \src "ls180.v:1478.12-1478.46" wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1435.12-1435.46" + attribute \src "ls180.v:1479.12-1479.46" wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1436.12-1436.46" + attribute \src "ls180.v:1480.12-1480.46" wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1437.12-1437.46" + attribute \src "ls180.v:1481.12-1481.46" wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1402.12-1402.45" + attribute \src "ls180.v:1446.12-1446.45" wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1438.12-1438.46" + attribute \src "ls180.v:1482.12-1482.46" wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1403.12-1403.45" + attribute \src "ls180.v:1447.12-1447.45" wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1404.12-1404.45" + attribute \src "ls180.v:1448.12-1448.45" wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1405.12-1405.45" + attribute \src "ls180.v:1449.12-1449.45" wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1406.12-1406.45" + attribute \src "ls180.v:1450.12-1450.45" wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1407.12-1407.45" + attribute \src "ls180.v:1451.12-1451.45" wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1442.6-1442.38" + attribute \src "ls180.v:1486.6-1486.38" wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1439.13-1439.42" + attribute \src "ls180.v:1483.13-1483.42" wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1541.12-1541.34" + attribute \src "ls180.v:1585.12-1585.34" wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1839.12-1839.57" + attribute \src "ls180.v:1883.12-1883.57" wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1840.5-1840.53" + attribute \src "ls180.v:1884.5-1884.53" wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1542.5-1542.26" + attribute \src "ls180.v:1586.5-1586.26" wire \main_sdcore_data_done - attribute \src "ls180.v:1835.5-1835.49" + attribute \src "ls180.v:1879.5-1879.49" wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1836.5-1836.52" + attribute \src "ls180.v:1880.5-1880.52" wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1543.5-1543.27" + attribute \src "ls180.v:1587.5-1587.27" wire \main_sdcore_data_error - attribute \src "ls180.v:1845.5-1845.50" + attribute \src "ls180.v:1889.5-1889.50" wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1846.5-1846.53" + attribute \src "ls180.v:1890.5-1890.53" wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1392.12-1392.41" + attribute \src "ls180.v:1436.12-1436.41" wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1393.6-1393.31" + attribute \src "ls180.v:1437.6-1437.31" wire \main_sdcore_data_event_we - attribute \src "ls180.v:1544.5-1544.29" + attribute \src "ls180.v:1588.5-1588.29" wire \main_sdcore_data_timeout - attribute \src "ls180.v:1847.5-1847.52" + attribute \src "ls180.v:1891.5-1891.52" wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1848.5-1848.55" + attribute \src "ls180.v:1892.5-1892.55" wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1540.12-1540.33" + attribute \src "ls180.v:1584.12-1584.33" wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1372.6-1372.33" + attribute \src "ls180.v:1416.6-1416.33" wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1373.6-1373.32" + attribute \src "ls180.v:1417.6-1417.32" wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1374.12-1374.46" + attribute \src "ls180.v:1418.12-1418.46" wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1371.6-1371.33" + attribute \src "ls180.v:1415.6-1415.33" wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1370.6-1370.33" + attribute \src "ls180.v:1414.6-1414.33" wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1377.6-1377.37" + attribute \src "ls180.v:1421.6-1421.37" wire \main_sdcore_source_source_first - attribute \src "ls180.v:1378.6-1378.36" + attribute \src "ls180.v:1422.6-1422.36" wire \main_sdcore_source_source_last - attribute \src "ls180.v:1379.12-1379.50" + attribute \src "ls180.v:1423.12-1423.50" wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1376.6-1376.37" + attribute \src "ls180.v:1420.6-1420.37" wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1375.6-1375.37" + attribute \src "ls180.v:1419.6-1419.37" wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1690.6-1690.38" + attribute \src "ls180.v:1734.6-1734.38" wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1691.6-1691.37" + attribute \src "ls180.v:1735.6-1735.37" wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1689.11-1689.41" - wire width 2 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1680.6-1680.43" + attribute \src "ls180.v:1733.11-1733.41" + wire width 3 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1724.6-1724.43" wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1681.6-1681.42" + attribute \src "ls180.v:1725.6-1725.42" wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1682.13-1682.57" - wire width 32 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1679.6-1679.43" + attribute \src "ls180.v:1726.13-1726.57" + wire width 64 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1723.6-1723.43" wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1678.6-1678.43" + attribute \src "ls180.v:1722.6-1722.43" wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1685.6-1685.45" + attribute \src "ls180.v:1729.6-1729.45" wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1686.6-1686.44" + attribute \src "ls180.v:1730.6-1730.44" wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1687.11-1687.57" + attribute \src "ls180.v:1731.11-1731.57" wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1688.6-1688.65" + attribute \src "ls180.v:1732.6-1732.65" wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1684.6-1684.45" + attribute \src "ls180.v:1728.6-1728.45" wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1683.6-1683.45" + attribute \src "ls180.v:1727.6-1727.45" wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1674.13-1674.38" + attribute \src "ls180.v:1718.13-1718.38" wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1663.5-1663.33" + attribute \src "ls180.v:1707.5-1707.33" wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1662.12-1662.45" + attribute \src "ls180.v:1706.12-1706.45" wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1661.12-1661.37" - wire width 32 \main_sdmem2block_dma_data - attribute \src "ls180.v:1857.12-1857.67" - wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1858.5-1858.63" + attribute \src "ls180.v:1705.12-1705.37" + wire width 64 \main_sdmem2block_dma_data + attribute \src "ls180.v:1901.12-1901.67" + wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1902.5-1902.63" wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1668.5-1668.37" + attribute \src "ls180.v:1712.5-1712.37" wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1669.6-1669.34" + attribute \src "ls180.v:1713.6-1713.34" wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1667.5-1667.35" + attribute \src "ls180.v:1711.5-1711.35" wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1666.5-1666.40" + attribute \src "ls180.v:1710.5-1710.40" wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1676.13-1676.40" + attribute \src "ls180.v:1720.13-1720.40" wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1665.5-1665.35" + attribute \src "ls180.v:1709.5-1709.35" wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1664.12-1664.47" + attribute \src "ls180.v:1708.12-1708.47" wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1671.5-1671.33" + attribute \src "ls180.v:1715.5-1715.33" wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1670.5-1670.38" + attribute \src "ls180.v:1714.5-1714.38" wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1675.12-1675.39" + attribute \src "ls180.v:1719.12-1719.39" wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1861.12-1861.79" + attribute \src "ls180.v:1905.12-1905.79" wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1862.5-1862.75" + attribute \src "ls180.v:1906.5-1906.75" wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1672.13-1672.47" + attribute \src "ls180.v:1716.13-1716.47" wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1673.6-1673.36" + attribute \src "ls180.v:1717.6-1717.36" wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1677.6-1677.32" + attribute \src "ls180.v:1721.6-1721.32" wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1654.5-1654.35" + attribute \src "ls180.v:1698.5-1698.35" wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1655.12-1655.53" + attribute \src "ls180.v:1699.12-1699.53" wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1653.5-1653.36" + attribute \src "ls180.v:1697.5-1697.36" wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1652.5-1652.36" + attribute \src "ls180.v:1696.5-1696.36" wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1658.5-1658.38" + attribute \src "ls180.v:1702.5-1702.38" wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1659.5-1659.37" + attribute \src "ls180.v:1703.5-1703.37" wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1660.12-1660.52" - wire width 32 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1657.6-1657.39" + attribute \src "ls180.v:1704.12-1704.52" + wire width 64 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1701.6-1701.39" wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1656.5-1656.38" + attribute \src "ls180.v:1700.5-1700.38" wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1716.11-1716.40" + attribute \src "ls180.v:1760.11-1760.40" wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1721.6-1721.35" + attribute \src "ls180.v:1765.6-1765.35" wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1725.6-1725.41" + attribute \src "ls180.v:1769.6-1769.41" wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1726.6-1726.40" + attribute \src "ls180.v:1770.6-1770.40" wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1724.12-1724.54" + attribute \src "ls180.v:1768.12-1768.54" wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1728.6-1728.42" + attribute \src "ls180.v:1772.6-1772.42" wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1729.6-1729.41" + attribute \src "ls180.v:1773.6-1773.41" wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1727.12-1727.55" + attribute \src "ls180.v:1771.12-1771.55" wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1713.11-1713.38" + attribute \src "ls180.v:1757.11-1757.38" wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1715.11-1715.40" + attribute \src "ls180.v:1759.11-1759.40" wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1722.12-1722.44" + attribute \src "ls180.v:1766.12-1766.44" wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1723.12-1723.46" + attribute \src "ls180.v:1767.12-1767.46" wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1714.5-1714.34" + attribute \src "ls180.v:1758.5-1758.34" wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1699.6-1699.38" + attribute \src "ls180.v:1743.6-1743.38" wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1700.6-1700.37" + attribute \src "ls180.v:1744.6-1744.37" wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1701.12-1701.51" + attribute \src "ls180.v:1745.12-1745.51" wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1698.6-1698.38" + attribute \src "ls180.v:1742.6-1742.38" wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1697.6-1697.38" + attribute \src "ls180.v:1741.6-1741.38" wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1704.6-1704.40" + attribute \src "ls180.v:1748.6-1748.40" wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1705.6-1705.39" + attribute \src "ls180.v:1749.6-1749.39" wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1706.12-1706.53" + attribute \src "ls180.v:1750.12-1750.53" wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1703.6-1703.40" + attribute \src "ls180.v:1747.6-1747.40" wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1702.6-1702.40" + attribute \src "ls180.v:1746.6-1746.40" wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1711.12-1711.46" + attribute \src "ls180.v:1755.12-1755.46" wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1712.12-1712.47" + attribute \src "ls180.v:1756.12-1756.47" wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1709.6-1709.39" + attribute \src "ls180.v:1753.6-1753.39" wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1710.6-1710.45" + attribute \src "ls180.v:1754.6-1754.45" wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1707.6-1707.39" + attribute \src "ls180.v:1751.6-1751.39" wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1708.6-1708.45" + attribute \src "ls180.v:1752.6-1752.45" wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1717.11-1717.43" + attribute \src "ls180.v:1761.11-1761.43" wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1718.12-1718.46" + attribute \src "ls180.v:1762.12-1762.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1720.12-1720.46" + attribute \src "ls180.v:1764.12-1764.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1719.6-1719.37" + attribute \src "ls180.v:1763.6-1763.37" wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1649.6-1649.43" + attribute \src "ls180.v:1693.6-1693.43" wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1694.6-1694.43" + attribute \src "ls180.v:1738.6-1738.43" wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1650.6-1650.42" + attribute \src "ls180.v:1694.6-1694.42" wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1695.6-1695.42" + attribute \src "ls180.v:1739.6-1739.42" wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1651.12-1651.56" + attribute \src "ls180.v:1695.12-1695.56" wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1696.12-1696.56" + attribute \src "ls180.v:1740.12-1740.56" wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1648.6-1648.43" + attribute \src "ls180.v:1692.6-1692.43" wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1693.6-1693.43" + attribute \src "ls180.v:1737.6-1737.43" wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1647.6-1647.43" + attribute \src "ls180.v:1691.6-1691.43" wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1692.6-1692.43" + attribute \src "ls180.v:1736.6-1736.43" wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1098.6-1098.27" + attribute \src "ls180.v:1142.6-1142.27" wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1097.5-1097.28" + attribute \src "ls180.v:1141.5-1141.28" wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1100.5-1100.28" + attribute \src "ls180.v:1144.5-1144.28" wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1101.5-1101.29" + attribute \src "ls180.v:1145.5-1145.29" wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1099.11-1099.34" + attribute \src "ls180.v:1143.11-1143.34" wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1095.5-1095.26" + attribute \src "ls180.v:1139.5-1139.26" wire \main_sdphy_clocker_re - attribute \src "ls180.v:1096.6-1096.29" + attribute \src "ls180.v:1140.6-1140.29" wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1094.11-1094.37" + attribute \src "ls180.v:1138.11-1138.37" wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1198.6-1198.41" + attribute \src "ls180.v:1242.6-1242.41" wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1199.6-1199.40" + attribute \src "ls180.v:1243.6-1243.40" wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1200.12-1200.54" + attribute \src "ls180.v:1244.12-1244.54" wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1197.6-1197.41" + attribute \src "ls180.v:1241.6-1241.41" wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1196.6-1196.41" + attribute \src "ls180.v:1240.6-1240.41" wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1203.5-1203.42" + attribute \src "ls180.v:1247.5-1247.42" wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1204.5-1204.41" + attribute \src "ls180.v:1248.5-1248.41" wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1205.11-1205.55" + attribute \src "ls180.v:1249.11-1249.55" wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1202.6-1202.43" + attribute \src "ls180.v:1246.6-1246.43" wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1201.5-1201.42" + attribute \src "ls180.v:1245.5-1245.42" wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1188.11-1188.47" + attribute \src "ls180.v:1232.11-1232.47" wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1189.6-1189.46" + attribute \src "ls180.v:1233.6-1233.46" wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1179.5-1179.46" + attribute \src "ls180.v:1223.5-1223.46" wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1180.5-1180.45" + attribute \src "ls180.v:1224.5-1224.45" wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1181.6-1181.54" + attribute \src "ls180.v:1225.6-1225.54" wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1178.6-1178.47" + attribute \src "ls180.v:1222.6-1222.47" wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1177.6-1177.47" + attribute \src "ls180.v:1221.6-1221.47" wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1184.5-1184.48" + attribute \src "ls180.v:1228.5-1228.48" wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1185.5-1185.47" + attribute \src "ls180.v:1229.5-1229.47" wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1186.11-1186.61" + attribute \src "ls180.v:1230.11-1230.61" wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1187.11-1187.74" + attribute \src "ls180.v:1231.11-1231.74" wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1183.6-1183.49" + attribute \src "ls180.v:1227.6-1227.49" wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1182.6-1182.49" + attribute \src "ls180.v:1226.6-1226.49" wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1190.5-1190.46" + attribute \src "ls180.v:1234.5-1234.46" wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1161.6-1161.40" + attribute \src "ls180.v:1205.6-1205.40" wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1162.6-1162.39" + attribute \src "ls180.v:1206.6-1206.39" wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1163.6-1163.46" + attribute \src "ls180.v:1207.6-1207.46" wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1164.6-1164.48" + attribute \src "ls180.v:1208.6-1208.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1165.6-1165.48" + attribute \src "ls180.v:1209.6-1209.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1166.6-1166.49" + attribute \src "ls180.v:1210.6-1210.49" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1167.12-1167.55" + attribute \src "ls180.v:1211.12-1211.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1168.12-1168.55" + attribute \src "ls180.v:1212.12-1212.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1169.6-1169.50" + attribute \src "ls180.v:1213.6-1213.50" wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1160.5-1160.39" + attribute \src "ls180.v:1204.5-1204.39" wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1159.6-1159.40" + attribute \src "ls180.v:1203.6-1203.40" wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1206.5-1206.31" + attribute \src "ls180.v:1250.5-1250.31" wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1801.5-1801.59" + attribute \src "ls180.v:1845.5-1845.59" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1802.5-1802.62" + attribute \src "ls180.v:1846.5-1846.62" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1176.5-1176.29" + attribute \src "ls180.v:1220.5-1220.29" wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1172.6-1172.47" + attribute \src "ls180.v:1216.6-1216.47" wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1193.6-1193.47" + attribute \src "ls180.v:1237.6-1237.47" wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1173.6-1173.46" + attribute \src "ls180.v:1217.6-1217.46" wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1194.6-1194.46" + attribute \src "ls180.v:1238.6-1238.46" wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1174.12-1174.60" + attribute \src "ls180.v:1218.12-1218.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1195.12-1195.60" + attribute \src "ls180.v:1239.12-1239.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1171.5-1171.46" + attribute \src "ls180.v:1215.5-1215.46" wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1192.6-1192.47" + attribute \src "ls180.v:1236.6-1236.47" wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1170.6-1170.47" + attribute \src "ls180.v:1214.6-1214.47" wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1191.6-1191.47" + attribute \src "ls180.v:1235.6-1235.47" wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1175.6-1175.32" + attribute \src "ls180.v:1219.6-1219.32" wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1158.11-1158.32" + attribute \src "ls180.v:1202.11-1202.32" wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1797.11-1797.60" + attribute \src "ls180.v:1841.11-1841.60" wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1798.5-1798.57" + attribute \src "ls180.v:1842.5-1842.57" wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1133.5-1133.42" + attribute \src "ls180.v:1177.5-1177.42" wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1134.5-1134.41" + attribute \src "ls180.v:1178.5-1178.41" wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1135.5-1135.48" + attribute \src "ls180.v:1179.5-1179.48" wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1136.6-1136.51" + attribute \src "ls180.v:1180.6-1180.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1137.5-1137.50" + attribute \src "ls180.v:1181.5-1181.50" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1138.5-1138.51" + attribute \src "ls180.v:1182.5-1182.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1139.12-1139.58" + attribute \src "ls180.v:1183.12-1183.58" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1140.11-1140.57" + attribute \src "ls180.v:1184.11-1184.57" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1141.5-1141.52" + attribute \src "ls180.v:1185.5-1185.52" wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1132.6-1132.43" + attribute \src "ls180.v:1176.6-1176.43" wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1131.6-1131.43" + attribute \src "ls180.v:1175.6-1175.43" wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1143.5-1143.41" + attribute \src "ls180.v:1187.5-1187.41" wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1144.5-1144.43" + attribute \src "ls180.v:1188.5-1188.43" wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1145.5-1145.44" + attribute \src "ls180.v:1189.5-1189.44" wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1146.11-1146.50" + attribute \src "ls180.v:1190.11-1190.50" wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1147.5-1147.45" + attribute \src "ls180.v:1191.5-1191.45" wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1142.6-1142.36" + attribute \src "ls180.v:1186.6-1186.36" wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1150.5-1150.30" + attribute \src "ls180.v:1194.5-1194.30" wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1151.11-1151.46" + attribute \src "ls180.v:1195.11-1195.46" wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1149.5-1149.31" + attribute \src "ls180.v:1193.5-1193.31" wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1148.5-1148.31" + attribute \src "ls180.v:1192.5-1192.31" wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1154.5-1154.32" + attribute \src "ls180.v:1198.5-1198.32" wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1155.11-1155.46" + attribute \src "ls180.v:1199.11-1199.46" wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1156.11-1156.48" + attribute \src "ls180.v:1200.11-1200.48" wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1153.5-1153.33" + attribute \src "ls180.v:1197.5-1197.33" wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1152.5-1152.33" + attribute \src "ls180.v:1196.5-1196.33" wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1157.12-1157.35" + attribute \src "ls180.v:1201.12-1201.35" wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1799.12-1799.63" + attribute \src "ls180.v:1843.12-1843.63" wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1800.5-1800.59" + attribute \src "ls180.v:1844.5-1844.59" wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1130.11-1130.32" + attribute \src "ls180.v:1174.11-1174.32" wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1793.11-1793.59" + attribute \src "ls180.v:1837.11-1837.59" wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1794.5-1794.56" + attribute \src "ls180.v:1838.5-1838.56" wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1129.5-1129.25" + attribute \src "ls180.v:1173.5-1173.25" wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1117.6-1117.43" + attribute \src "ls180.v:1161.6-1161.43" wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1118.12-1118.50" + attribute \src "ls180.v:1162.12-1162.50" wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1116.6-1116.35" + attribute \src "ls180.v:1160.6-1160.35" wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1120.5-1120.41" + attribute \src "ls180.v:1164.5-1164.41" wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1121.5-1121.43" + attribute \src "ls180.v:1165.5-1165.43" wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1122.5-1122.44" + attribute \src "ls180.v:1166.5-1166.44" wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1123.11-1123.50" + attribute \src "ls180.v:1167.11-1167.50" wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1124.5-1124.45" + attribute \src "ls180.v:1168.5-1168.45" wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1119.6-1119.36" + attribute \src "ls180.v:1163.6-1163.36" wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1127.5-1127.30" + attribute \src "ls180.v:1171.5-1171.30" wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1128.11-1128.44" + attribute \src "ls180.v:1172.11-1172.44" wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1126.5-1126.31" + attribute \src "ls180.v:1170.5-1170.31" wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1125.5-1125.31" + attribute \src "ls180.v:1169.5-1169.31" wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1314.11-1314.33" + attribute \src "ls180.v:1358.11-1358.33" wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1813.11-1813.62" + attribute \src "ls180.v:1857.11-1857.62" wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1814.5-1814.59" + attribute \src "ls180.v:1858.5-1858.59" wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1354.6-1354.43" + attribute \src "ls180.v:1398.6-1398.43" wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1355.6-1355.42" + attribute \src "ls180.v:1399.6-1399.42" wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1356.12-1356.56" + attribute \src "ls180.v:1400.12-1400.56" wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1353.6-1353.43" + attribute \src "ls180.v:1397.6-1397.43" wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1352.6-1352.43" + attribute \src "ls180.v:1396.6-1396.43" wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1359.5-1359.44" + attribute \src "ls180.v:1403.5-1403.44" wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1360.5-1360.43" + attribute \src "ls180.v:1404.5-1404.43" wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1361.11-1361.57" + attribute \src "ls180.v:1405.11-1405.57" wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1358.6-1358.45" + attribute \src "ls180.v:1402.6-1402.45" wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1357.5-1357.44" + attribute \src "ls180.v:1401.5-1401.44" wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1344.5-1344.43" + attribute \src "ls180.v:1388.5-1388.43" wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1345.6-1345.48" + attribute \src "ls180.v:1389.6-1389.48" wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1335.5-1335.48" + attribute \src "ls180.v:1379.5-1379.48" wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1336.5-1336.47" + attribute \src "ls180.v:1380.5-1380.47" wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1337.12-1337.62" + attribute \src "ls180.v:1381.12-1381.62" wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1334.6-1334.49" + attribute \src "ls180.v:1378.6-1378.49" wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1333.6-1333.49" + attribute \src "ls180.v:1377.6-1377.49" wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1340.5-1340.50" + attribute \src "ls180.v:1384.5-1384.50" wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1341.5-1341.49" + attribute \src "ls180.v:1385.5-1385.49" wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1342.11-1342.63" + attribute \src "ls180.v:1386.11-1386.63" wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1343.11-1343.76" + attribute \src "ls180.v:1387.11-1387.76" wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1339.6-1339.51" + attribute \src "ls180.v:1383.6-1383.51" wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1338.6-1338.51" + attribute \src "ls180.v:1382.6-1382.51" wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1346.5-1346.48" + attribute \src "ls180.v:1390.5-1390.48" wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1317.6-1317.42" + attribute \src "ls180.v:1361.6-1361.42" wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1318.6-1318.41" + attribute \src "ls180.v:1362.6-1362.41" wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1319.6-1319.48" + attribute \src "ls180.v:1363.6-1363.48" wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1320.6-1320.50" + attribute \src "ls180.v:1364.6-1364.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1321.6-1321.50" + attribute \src "ls180.v:1365.6-1365.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1322.6-1322.51" + attribute \src "ls180.v:1366.6-1366.51" wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1323.12-1323.57" + attribute \src "ls180.v:1367.12-1367.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1324.12-1324.57" + attribute \src "ls180.v:1368.12-1368.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1325.6-1325.52" + attribute \src "ls180.v:1369.6-1369.52" wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1316.5-1316.41" + attribute \src "ls180.v:1360.5-1360.41" wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1315.6-1315.42" + attribute \src "ls180.v:1359.6-1359.42" wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1362.5-1362.33" + attribute \src "ls180.v:1406.5-1406.33" wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1817.5-1817.62" + attribute \src "ls180.v:1861.5-1861.62" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1818.5-1818.65" + attribute \src "ls180.v:1862.5-1862.65" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1332.5-1332.31" + attribute \src "ls180.v:1376.5-1376.31" wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1328.6-1328.49" + attribute \src "ls180.v:1372.6-1372.49" wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1349.6-1349.49" + attribute \src "ls180.v:1393.6-1393.49" wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1329.6-1329.48" + attribute \src "ls180.v:1373.6-1373.48" wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1350.6-1350.48" + attribute \src "ls180.v:1394.6-1394.48" wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1330.12-1330.62" + attribute \src "ls180.v:1374.12-1374.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1351.12-1351.62" + attribute \src "ls180.v:1395.12-1395.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1327.5-1327.48" + attribute \src "ls180.v:1371.5-1371.48" wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1348.6-1348.49" + attribute \src "ls180.v:1392.6-1392.49" wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1326.6-1326.49" + attribute \src "ls180.v:1370.6-1370.49" wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1347.6-1347.49" + attribute \src "ls180.v:1391.6-1391.49" wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1331.6-1331.34" + attribute \src "ls180.v:1375.6-1375.34" wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1287.5-1287.43" + attribute \src "ls180.v:1331.5-1331.43" wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1288.5-1288.42" + attribute \src "ls180.v:1332.5-1332.42" wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1289.5-1289.49" + attribute \src "ls180.v:1333.5-1333.49" wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1290.6-1290.52" + attribute \src "ls180.v:1334.6-1334.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1291.5-1291.51" + attribute \src "ls180.v:1335.5-1335.51" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1292.5-1292.52" + attribute \src "ls180.v:1336.5-1336.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1293.12-1293.59" + attribute \src "ls180.v:1337.12-1337.59" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1294.11-1294.58" + attribute \src "ls180.v:1338.11-1338.58" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1295.5-1295.53" + attribute \src "ls180.v:1339.5-1339.53" wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1286.6-1286.44" + attribute \src "ls180.v:1330.6-1330.44" wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1285.6-1285.44" + attribute \src "ls180.v:1329.6-1329.44" wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1297.5-1297.42" + attribute \src "ls180.v:1341.5-1341.42" wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1298.5-1298.44" + attribute \src "ls180.v:1342.5-1342.44" wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1299.5-1299.45" + attribute \src "ls180.v:1343.5-1343.45" wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1300.11-1300.51" + attribute \src "ls180.v:1344.11-1344.51" wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1301.5-1301.46" + attribute \src "ls180.v:1345.5-1345.46" wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1296.6-1296.37" + attribute \src "ls180.v:1340.6-1340.37" wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1304.5-1304.31" + attribute \src "ls180.v:1348.5-1348.31" wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1305.11-1305.53" + attribute \src "ls180.v:1349.11-1349.53" wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1303.5-1303.32" + attribute \src "ls180.v:1347.5-1347.32" wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1302.5-1302.32" + attribute \src "ls180.v:1346.5-1346.32" wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1308.5-1308.34" + attribute \src "ls180.v:1352.5-1352.34" wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1309.5-1309.33" + attribute \src "ls180.v:1353.5-1353.33" wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1310.11-1310.47" + attribute \src "ls180.v:1354.11-1354.47" wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1311.11-1311.49" + attribute \src "ls180.v:1355.11-1355.49" wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1307.5-1307.34" + attribute \src "ls180.v:1351.5-1351.34" wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1306.5-1306.34" + attribute \src "ls180.v:1350.5-1350.34" wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1312.5-1312.26" + attribute \src "ls180.v:1356.5-1356.26" wire \main_sdphy_datar_stop - attribute \src "ls180.v:1313.12-1313.36" + attribute \src "ls180.v:1357.12-1357.36" wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1815.12-1815.65" + attribute \src "ls180.v:1859.12-1859.65" wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1816.5-1816.61" + attribute \src "ls180.v:1860.5-1860.61" wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1222.11-1222.33" + attribute \src "ls180.v:1266.11-1266.33" wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1809.11-1809.54" + attribute \src "ls180.v:1853.11-1853.54" wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1810.5-1810.51" + attribute \src "ls180.v:1854.5-1854.51" wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1276.6-1276.42" + attribute \src "ls180.v:1320.6-1320.42" wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1277.6-1277.41" + attribute \src "ls180.v:1321.6-1321.41" wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1278.12-1278.55" + attribute \src "ls180.v:1322.12-1322.55" wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1275.6-1275.42" + attribute \src "ls180.v:1319.6-1319.42" wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1274.6-1274.42" + attribute \src "ls180.v:1318.6-1318.42" wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1281.5-1281.43" + attribute \src "ls180.v:1325.5-1325.43" wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1282.5-1282.42" + attribute \src "ls180.v:1326.5-1326.42" wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1283.11-1283.56" + attribute \src "ls180.v:1327.11-1327.56" wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1280.6-1280.44" + attribute \src "ls180.v:1324.6-1324.44" wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1279.5-1279.43" + attribute \src "ls180.v:1323.5-1323.43" wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1266.11-1266.48" + attribute \src "ls180.v:1310.11-1310.48" wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1267.6-1267.47" + attribute \src "ls180.v:1311.6-1311.47" wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1257.5-1257.47" + attribute \src "ls180.v:1301.5-1301.47" wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1258.5-1258.46" + attribute \src "ls180.v:1302.5-1302.46" wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1259.6-1259.55" + attribute \src "ls180.v:1303.6-1303.55" wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1256.6-1256.48" + attribute \src "ls180.v:1300.6-1300.48" wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1255.6-1255.48" + attribute \src "ls180.v:1299.6-1299.48" wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1262.5-1262.49" + attribute \src "ls180.v:1306.5-1306.49" wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1263.5-1263.48" + attribute \src "ls180.v:1307.5-1307.48" wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1264.11-1264.62" + attribute \src "ls180.v:1308.11-1308.62" wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1265.11-1265.75" + attribute \src "ls180.v:1309.11-1309.75" wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1261.6-1261.50" + attribute \src "ls180.v:1305.6-1305.50" wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1260.6-1260.50" + attribute \src "ls180.v:1304.6-1304.50" wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1268.5-1268.47" + attribute \src "ls180.v:1312.5-1312.47" wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1239.6-1239.41" + attribute \src "ls180.v:1283.6-1283.41" wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1240.6-1240.40" + attribute \src "ls180.v:1284.6-1284.40" wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1241.6-1241.47" + attribute \src "ls180.v:1285.6-1285.47" wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1242.6-1242.49" + attribute \src "ls180.v:1286.6-1286.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1243.6-1243.49" + attribute \src "ls180.v:1287.6-1287.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1244.6-1244.50" + attribute \src "ls180.v:1288.6-1288.50" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1245.12-1245.56" + attribute \src "ls180.v:1289.12-1289.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1246.12-1246.56" + attribute \src "ls180.v:1290.12-1290.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1247.6-1247.51" + attribute \src "ls180.v:1291.6-1291.51" wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1238.5-1238.40" + attribute \src "ls180.v:1282.5-1282.40" wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1237.6-1237.41" + attribute \src "ls180.v:1281.6-1281.41" wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1284.5-1284.32" + attribute \src "ls180.v:1328.5-1328.32" wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1805.5-1805.59" + attribute \src "ls180.v:1849.5-1849.59" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1806.5-1806.62" + attribute \src "ls180.v:1850.5-1850.62" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1254.5-1254.30" + attribute \src "ls180.v:1298.5-1298.30" wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1250.6-1250.48" + attribute \src "ls180.v:1294.6-1294.48" wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1271.6-1271.48" + attribute \src "ls180.v:1315.6-1315.48" wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1251.6-1251.47" + attribute \src "ls180.v:1295.6-1295.47" wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1272.6-1272.47" + attribute \src "ls180.v:1316.6-1316.47" wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1252.12-1252.61" + attribute \src "ls180.v:1296.12-1296.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1273.12-1273.61" + attribute \src "ls180.v:1317.12-1317.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1249.5-1249.47" + attribute \src "ls180.v:1293.5-1293.47" wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1270.6-1270.48" + attribute \src "ls180.v:1314.6-1314.48" wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1248.6-1248.48" + attribute \src "ls180.v:1292.6-1292.48" wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1269.6-1269.48" + attribute \src "ls180.v:1313.6-1313.48" wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1253.6-1253.33" + attribute \src "ls180.v:1297.6-1297.33" wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1236.5-1236.27" + attribute \src "ls180.v:1280.5-1280.27" wire \main_sdphy_dataw_error - attribute \src "ls180.v:1225.5-1225.43" + attribute \src "ls180.v:1269.5-1269.43" wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1226.5-1226.42" + attribute \src "ls180.v:1270.5-1270.42" wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1227.5-1227.49" + attribute \src "ls180.v:1271.5-1271.49" wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1228.5-1228.51" + attribute \src "ls180.v:1272.5-1272.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1229.5-1229.51" + attribute \src "ls180.v:1273.5-1273.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1230.5-1230.52" + attribute \src "ls180.v:1274.5-1274.52" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1231.11-1231.58" + attribute \src "ls180.v:1275.11-1275.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1232.11-1232.58" + attribute \src "ls180.v:1276.11-1276.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1233.5-1233.53" + attribute \src "ls180.v:1277.5-1277.53" wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1224.6-1224.44" + attribute \src "ls180.v:1268.6-1268.44" wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1223.5-1223.43" + attribute \src "ls180.v:1267.5-1267.43" wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1208.6-1208.44" + attribute \src "ls180.v:1252.6-1252.44" wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1209.12-1209.51" + attribute \src "ls180.v:1253.12-1253.51" wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1207.6-1207.36" + attribute \src "ls180.v:1251.6-1251.36" wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1211.5-1211.42" + attribute \src "ls180.v:1255.5-1255.42" wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1212.5-1212.44" + attribute \src "ls180.v:1256.5-1256.44" wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1213.5-1213.45" + attribute \src "ls180.v:1257.5-1257.45" wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1214.11-1214.51" + attribute \src "ls180.v:1258.11-1258.51" wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1215.5-1215.46" + attribute \src "ls180.v:1259.5-1259.46" wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1210.6-1210.37" + attribute \src "ls180.v:1254.6-1254.37" wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1218.5-1218.32" + attribute \src "ls180.v:1262.5-1262.32" wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1219.5-1219.31" + attribute \src "ls180.v:1263.5-1263.31" wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1220.11-1220.45" + attribute \src "ls180.v:1264.11-1264.45" wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1217.5-1217.32" + attribute \src "ls180.v:1261.5-1261.32" wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1216.5-1216.32" + attribute \src "ls180.v:1260.5-1260.32" wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1234.5-1234.27" + attribute \src "ls180.v:1278.5-1278.27" wire \main_sdphy_dataw_start - attribute \src "ls180.v:1221.5-1221.26" + attribute \src "ls180.v:1265.5-1265.26" wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1235.5-1235.27" + attribute \src "ls180.v:1279.5-1279.27" wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1115.11-1115.32" + attribute \src "ls180.v:1159.11-1159.32" wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1789.11-1789.59" + attribute \src "ls180.v:1833.11-1833.59" wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1790.5-1790.56" + attribute \src "ls180.v:1834.5-1834.56" wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1103.6-1103.34" + attribute \src "ls180.v:1147.6-1147.34" wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1102.6-1102.35" + attribute \src "ls180.v:1146.6-1146.35" wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1105.5-1105.33" + attribute \src "ls180.v:1149.5-1149.33" wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1104.6-1104.35" + attribute \src "ls180.v:1148.6-1148.35" wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1107.6-1107.43" + attribute \src "ls180.v:1151.6-1151.43" wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1108.12-1108.50" + attribute \src "ls180.v:1152.12-1152.50" wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1106.6-1106.35" + attribute \src "ls180.v:1150.6-1150.35" wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1110.5-1110.41" + attribute \src "ls180.v:1154.5-1154.41" wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1111.5-1111.43" + attribute \src "ls180.v:1155.5-1155.43" wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1112.5-1112.44" + attribute \src "ls180.v:1156.5-1156.44" wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1113.11-1113.50" + attribute \src "ls180.v:1157.11-1157.50" wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1114.5-1114.45" + attribute \src "ls180.v:1158.5-1158.45" wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1109.6-1109.36" + attribute \src "ls180.v:1153.6-1153.36" wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1363.6-1363.27" + attribute \src "ls180.v:1407.6-1407.27" wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1364.5-1364.28" + attribute \src "ls180.v:1408.5-1408.28" wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1365.6-1365.29" + attribute \src "ls180.v:1409.6-1409.29" wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1366.6-1366.30" + attribute \src "ls180.v:1410.6-1410.30" wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1367.11-1367.35" + attribute \src "ls180.v:1411.11-1411.35" wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1368.12-1368.36" + attribute \src "ls180.v:1412.12-1412.36" wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1369.6-1369.31" + attribute \src "ls180.v:1413.6-1413.31" wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1092.6-1092.23" + attribute \src "ls180.v:1136.6-1136.23" wire \main_sdphy_status - attribute \src "ls180.v:1093.6-1093.19" + attribute \src "ls180.v:1137.6-1137.19" wire \main_sdphy_we - attribute \src "ls180.v:327.5-327.26" + attribute \src "ls180.v:359.5-359.26" wire \main_sdram_address_re - attribute \src "ls180.v:326.12-326.38" + attribute \src "ls180.v:358.12-358.38" wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:329.5-329.27" + attribute \src "ls180.v:361.5-361.27" wire \main_sdram_baddress_re - attribute \src "ls180.v:328.11-328.38" + attribute \src "ls180.v:360.11-360.38" wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:425.5-425.43" + attribute \src "ls180.v:457.5-457.43" wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:447.11-447.63" + attribute \src "ls180.v:479.11-479.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:452.6-452.58" + attribute \src "ls180.v:484.6-484.58" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:457.6-457.64" + attribute \src "ls180.v:489.6-489.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:458.6-458.63" + attribute \src "ls180.v:490.6-490.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:456.13-456.78" + attribute \src "ls180.v:488.13-488.78" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:455.6-455.69" + attribute \src "ls180.v:487.6-487.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:461.6-461.65" + attribute \src "ls180.v:493.6-493.65" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:462.6-462.64" + attribute \src "ls180.v:494.6-494.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:460.13-460.79" + attribute \src "ls180.v:492.13-492.79" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:459.6-459.70" + attribute \src "ls180.v:491.6-491.70" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:444.11-444.61" + attribute \src "ls180.v:476.11-476.61" wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:446.11-446.63" + attribute \src "ls180.v:478.11-478.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:453.12-453.67" + attribute \src "ls180.v:485.12-485.67" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:454.13-454.70" + attribute \src "ls180.v:486.13-486.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:445.5-445.57" + attribute \src "ls180.v:477.5-477.57" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:428.5-428.60" + attribute \src "ls180.v:460.5-460.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:429.5-429.59" + attribute \src "ls180.v:461.5-461.59" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:431.13-431.75" + attribute \src "ls180.v:463.13-463.75" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:430.6-430.66" + attribute \src "ls180.v:462.6-462.66" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:427.6-427.61" + attribute \src "ls180.v:459.6-459.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:426.6-426.61" + attribute \src "ls180.v:458.6-458.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:434.6-434.63" + attribute \src "ls180.v:466.6-466.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:435.6-435.62" + attribute \src "ls180.v:467.6-467.62" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:437.13-437.77" + attribute \src "ls180.v:469.13-469.77" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:436.6-436.68" + attribute \src "ls180.v:468.6-468.68" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:433.6-433.63" + attribute \src "ls180.v:465.6-465.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:432.6-432.63" + attribute \src "ls180.v:464.6-464.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:442.13-442.71" + attribute \src "ls180.v:474.13-474.71" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:443.13-443.72" + attribute \src "ls180.v:475.13-475.72" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:440.6-440.63" + attribute \src "ls180.v:472.6-472.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:441.6-441.69" + attribute \src "ls180.v:473.6-473.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:438.6-438.63" + attribute \src "ls180.v:470.6-470.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:439.6-439.69" + attribute \src "ls180.v:471.6-471.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:448.11-448.66" + attribute \src "ls180.v:480.11-480.66" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:449.13-449.70" + attribute \src "ls180.v:481.13-481.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:451.13-451.70" + attribute \src "ls180.v:483.13-483.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:450.6-450.60" + attribute \src "ls180.v:482.6-482.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:465.6-465.51" + attribute \src "ls180.v:497.6-497.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:466.6-466.50" + attribute \src "ls180.v:498.6-498.50" wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:468.13-468.65" + attribute \src "ls180.v:500.13-500.65" wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:467.6-467.56" + attribute \src "ls180.v:499.6-499.56" wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:464.6-464.51" + attribute \src "ls180.v:496.6-496.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:463.6-463.51" + attribute \src "ls180.v:495.6-495.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:471.5-471.52" + attribute \src "ls180.v:503.5-503.52" wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:472.5-472.51" + attribute \src "ls180.v:504.5-504.51" wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:474.12-474.66" + attribute \src "ls180.v:506.12-506.66" wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:473.5-473.57" + attribute \src "ls180.v:505.5-505.57" wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:470.6-470.53" + attribute \src "ls180.v:502.6-502.53" wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:469.5-469.52" + attribute \src "ls180.v:501.5-501.52" wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:417.12-417.49" + attribute \src "ls180.v:449.12-449.49" wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:418.12-418.50" + attribute \src "ls180.v:450.12-450.50" wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:419.5-419.44" + attribute \src "ls180.v:451.5-451.44" wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:422.5-422.47" + attribute \src "ls180.v:454.5-454.47" wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:423.5-423.48" + attribute \src "ls180.v:455.5-455.48" wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:424.5-424.49" + attribute \src "ls180.v:456.5-456.49" wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:420.5-420.44" + attribute \src "ls180.v:452.5-452.44" wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:421.5-421.43" + attribute \src "ls180.v:453.5-453.43" wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:416.5-416.38" + attribute \src "ls180.v:448.5-448.38" wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:415.5-415.38" + attribute \src "ls180.v:447.5-447.38" wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:414.5-414.40" + attribute \src "ls180.v:446.5-446.40" wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:413.6-413.41" + attribute \src "ls180.v:445.6-445.41" wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:409.13-409.45" + attribute \src "ls180.v:441.13-441.45" wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:410.6-410.38" + attribute \src "ls180.v:442.6-442.38" wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:412.5-412.44" + attribute \src "ls180.v:444.5-444.44" wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:407.6-407.39" + attribute \src "ls180.v:439.6-439.39" wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:406.6-406.39" + attribute \src "ls180.v:438.6-438.39" wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:411.5-411.44" + attribute \src "ls180.v:443.5-443.44" wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:408.6-408.36" + attribute \src "ls180.v:440.6-440.36" wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:475.12-475.39" + attribute \src "ls180.v:507.12-507.39" wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:479.5-479.38" + attribute \src "ls180.v:511.5-511.38" wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:480.5-480.47" + attribute \src "ls180.v:512.5-512.47" wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:477.6-477.37" + attribute \src "ls180.v:509.6-509.37" wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:478.5-478.37" + attribute \src "ls180.v:510.5-510.37" wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:476.5-476.39" + attribute \src "ls180.v:508.5-508.39" wire \main_sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:487.32-487.69" + attribute \src "ls180.v:519.32-519.69" wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:486.6-486.43" + attribute \src "ls180.v:518.6-518.43" wire \main_sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:485.32-485.68" + attribute \src "ls180.v:517.32-517.68" wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:484.6-484.42" + attribute \src "ls180.v:516.6-516.42" wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:483.11-483.48" + attribute \src "ls180.v:515.11-515.48" wire width 3 \main_sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:482.32-482.69" + attribute \src "ls180.v:514.32-514.69" wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:481.6-481.43" + attribute \src "ls180.v:513.6-513.43" wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:507.5-507.43" + attribute \src "ls180.v:539.5-539.43" wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:529.11-529.63" + attribute \src "ls180.v:561.11-561.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:534.6-534.58" + attribute \src "ls180.v:566.6-566.58" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:539.6-539.64" + attribute \src "ls180.v:571.6-571.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:540.6-540.63" + attribute \src "ls180.v:572.6-572.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:538.13-538.78" + attribute \src "ls180.v:570.13-570.78" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:537.6-537.69" + attribute \src "ls180.v:569.6-569.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:543.6-543.65" + attribute \src "ls180.v:575.6-575.65" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:544.6-544.64" + attribute \src "ls180.v:576.6-576.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:542.13-542.79" + attribute \src "ls180.v:574.13-574.79" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:541.6-541.70" + attribute \src "ls180.v:573.6-573.70" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:526.11-526.61" + attribute \src "ls180.v:558.11-558.61" wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:528.11-528.63" + attribute \src "ls180.v:560.11-560.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:535.12-535.67" + attribute \src "ls180.v:567.12-567.67" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:536.13-536.70" + attribute \src "ls180.v:568.13-568.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:527.5-527.57" + attribute \src "ls180.v:559.5-559.57" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:510.5-510.60" + attribute \src "ls180.v:542.5-542.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:511.5-511.59" + attribute \src "ls180.v:543.5-543.59" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:513.13-513.75" + attribute \src "ls180.v:545.13-545.75" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:512.6-512.66" + attribute \src "ls180.v:544.6-544.66" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:509.6-509.61" + attribute \src "ls180.v:541.6-541.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:508.6-508.61" + attribute \src "ls180.v:540.6-540.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:516.6-516.63" + attribute \src "ls180.v:548.6-548.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:517.6-517.62" + attribute \src "ls180.v:549.6-549.62" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:519.13-519.77" + attribute \src "ls180.v:551.13-551.77" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:518.6-518.68" + attribute \src "ls180.v:550.6-550.68" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:515.6-515.63" + attribute \src "ls180.v:547.6-547.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:514.6-514.63" + attribute \src "ls180.v:546.6-546.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:524.13-524.71" + attribute \src "ls180.v:556.13-556.71" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:525.13-525.72" + attribute \src "ls180.v:557.13-557.72" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:522.6-522.63" + attribute \src "ls180.v:554.6-554.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:523.6-523.69" + attribute \src "ls180.v:555.6-555.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:520.6-520.63" + attribute \src "ls180.v:552.6-552.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:521.6-521.69" + attribute \src "ls180.v:553.6-553.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:530.11-530.66" + attribute \src "ls180.v:562.11-562.66" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:531.13-531.70" + attribute \src "ls180.v:563.13-563.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:533.13-533.70" + attribute \src "ls180.v:565.13-565.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:532.6-532.60" + attribute \src "ls180.v:564.6-564.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:547.6-547.51" + attribute \src "ls180.v:579.6-579.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:548.6-548.50" + attribute \src "ls180.v:580.6-580.50" wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:550.13-550.65" + attribute \src "ls180.v:582.13-582.65" wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:549.6-549.56" + attribute \src "ls180.v:581.6-581.56" wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:546.6-546.51" + attribute \src "ls180.v:578.6-578.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:545.6-545.51" + attribute \src "ls180.v:577.6-577.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:553.5-553.52" + attribute \src "ls180.v:585.5-585.52" wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:554.5-554.51" + attribute \src "ls180.v:586.5-586.51" wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:556.12-556.66" + attribute \src "ls180.v:588.12-588.66" wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:555.5-555.57" + attribute \src "ls180.v:587.5-587.57" wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:552.6-552.53" + attribute \src "ls180.v:584.6-584.53" wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:551.5-551.52" + attribute \src "ls180.v:583.5-583.52" wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:499.12-499.49" + attribute \src "ls180.v:531.12-531.49" wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:500.12-500.50" + attribute \src "ls180.v:532.12-532.50" wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:501.5-501.44" + attribute \src "ls180.v:533.5-533.44" wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:504.5-504.47" + attribute \src "ls180.v:536.5-536.47" wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:505.5-505.48" + attribute \src "ls180.v:537.5-537.48" wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:506.5-506.49" + attribute \src "ls180.v:538.5-538.49" wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:502.5-502.44" + attribute \src "ls180.v:534.5-534.44" wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:503.5-503.43" + attribute \src "ls180.v:535.5-535.43" wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:498.5-498.38" + attribute \src "ls180.v:530.5-530.38" wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:497.5-497.38" + attribute \src "ls180.v:529.5-529.38" wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:496.5-496.40" + attribute \src "ls180.v:528.5-528.40" wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:495.6-495.41" + attribute \src "ls180.v:527.6-527.41" wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:491.13-491.45" + attribute \src "ls180.v:523.13-523.45" wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:492.6-492.38" + attribute \src "ls180.v:524.6-524.38" wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:494.5-494.44" + attribute \src "ls180.v:526.5-526.44" wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:489.6-489.39" + attribute \src "ls180.v:521.6-521.39" wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:488.6-488.39" + attribute \src "ls180.v:520.6-520.39" wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:493.5-493.44" + attribute \src "ls180.v:525.5-525.44" wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:490.6-490.36" + attribute \src "ls180.v:522.6-522.36" wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:557.12-557.39" + attribute \src "ls180.v:589.12-589.39" wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:561.5-561.38" + attribute \src "ls180.v:593.5-593.38" wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:562.5-562.47" + attribute \src "ls180.v:594.5-594.47" wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:559.6-559.37" + attribute \src "ls180.v:591.6-591.37" wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:560.5-560.37" + attribute \src "ls180.v:592.5-592.37" wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:558.5-558.39" + attribute \src "ls180.v:590.5-590.39" wire \main_sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:569.32-569.69" + attribute \src "ls180.v:601.32-601.69" wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:568.6-568.43" + attribute \src "ls180.v:600.6-600.43" wire \main_sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:567.32-567.68" + attribute \src "ls180.v:599.32-599.68" wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:566.6-566.42" + attribute \src "ls180.v:598.6-598.42" wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:565.11-565.48" + attribute \src "ls180.v:597.11-597.48" wire width 3 \main_sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:564.32-564.69" + attribute \src "ls180.v:596.32-596.69" wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:563.6-563.43" + attribute \src "ls180.v:595.6-595.43" wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:589.5-589.43" + attribute \src "ls180.v:621.5-621.43" wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:611.11-611.63" + attribute \src "ls180.v:643.11-643.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:616.6-616.58" + attribute \src "ls180.v:648.6-648.58" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:621.6-621.64" + attribute \src "ls180.v:653.6-653.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:622.6-622.63" + attribute \src "ls180.v:654.6-654.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:620.13-620.78" + attribute \src "ls180.v:652.13-652.78" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:619.6-619.69" + attribute \src "ls180.v:651.6-651.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:625.6-625.65" + attribute \src "ls180.v:657.6-657.65" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:626.6-626.64" + attribute \src "ls180.v:658.6-658.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:624.13-624.79" + attribute \src "ls180.v:656.13-656.79" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:623.6-623.70" + attribute \src "ls180.v:655.6-655.70" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:608.11-608.61" + attribute \src "ls180.v:640.11-640.61" wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:610.11-610.63" + attribute \src "ls180.v:642.11-642.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:617.12-617.67" + attribute \src "ls180.v:649.12-649.67" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:618.13-618.70" + attribute \src "ls180.v:650.13-650.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:609.5-609.57" + attribute \src "ls180.v:641.5-641.57" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:592.5-592.60" + attribute \src "ls180.v:624.5-624.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:593.5-593.59" + attribute \src "ls180.v:625.5-625.59" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:595.13-595.75" + attribute \src "ls180.v:627.13-627.75" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:594.6-594.66" + attribute \src "ls180.v:626.6-626.66" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:591.6-591.61" + attribute \src "ls180.v:623.6-623.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:590.6-590.61" + attribute \src "ls180.v:622.6-622.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:598.6-598.63" + attribute \src "ls180.v:630.6-630.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:599.6-599.62" + attribute \src "ls180.v:631.6-631.62" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:601.13-601.77" + attribute \src "ls180.v:633.13-633.77" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:600.6-600.68" + attribute \src "ls180.v:632.6-632.68" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:597.6-597.63" + attribute \src "ls180.v:629.6-629.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:596.6-596.63" + attribute \src "ls180.v:628.6-628.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:606.13-606.71" + attribute \src "ls180.v:638.13-638.71" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:607.13-607.72" + attribute \src "ls180.v:639.13-639.72" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:604.6-604.63" + attribute \src "ls180.v:636.6-636.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:605.6-605.69" + attribute \src "ls180.v:637.6-637.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:602.6-602.63" + attribute \src "ls180.v:634.6-634.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:603.6-603.69" + attribute \src "ls180.v:635.6-635.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:612.11-612.66" + attribute \src "ls180.v:644.11-644.66" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:613.13-613.70" + attribute \src "ls180.v:645.13-645.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:615.13-615.70" + attribute \src "ls180.v:647.13-647.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:614.6-614.60" + attribute \src "ls180.v:646.6-646.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:629.6-629.51" + attribute \src "ls180.v:661.6-661.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:630.6-630.50" + attribute \src "ls180.v:662.6-662.50" wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:632.13-632.65" + attribute \src "ls180.v:664.13-664.65" wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:631.6-631.56" + attribute \src "ls180.v:663.6-663.56" wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:628.6-628.51" + attribute \src "ls180.v:660.6-660.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:627.6-627.51" + attribute \src "ls180.v:659.6-659.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:635.5-635.52" + attribute \src "ls180.v:667.5-667.52" wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:636.5-636.51" + attribute \src "ls180.v:668.5-668.51" wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:638.12-638.66" + attribute \src "ls180.v:670.12-670.66" wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:637.5-637.57" + attribute \src "ls180.v:669.5-669.57" wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:634.6-634.53" + attribute \src "ls180.v:666.6-666.53" wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:633.5-633.52" + attribute \src "ls180.v:665.5-665.52" wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:581.12-581.49" + attribute \src "ls180.v:613.12-613.49" wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:582.12-582.50" + attribute \src "ls180.v:614.12-614.50" wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:583.5-583.44" + attribute \src "ls180.v:615.5-615.44" wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:586.5-586.47" + attribute \src "ls180.v:618.5-618.47" wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:587.5-587.48" + attribute \src "ls180.v:619.5-619.48" wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:588.5-588.49" + attribute \src "ls180.v:620.5-620.49" wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:584.5-584.44" + attribute \src "ls180.v:616.5-616.44" wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:585.5-585.43" + attribute \src "ls180.v:617.5-617.43" wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:580.5-580.38" + attribute \src "ls180.v:612.5-612.38" wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:579.5-579.38" + attribute \src "ls180.v:611.5-611.38" wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:578.5-578.40" + attribute \src "ls180.v:610.5-610.40" wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:577.6-577.41" + attribute \src "ls180.v:609.6-609.41" wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:573.13-573.45" + attribute \src "ls180.v:605.13-605.45" wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:574.6-574.38" + attribute \src "ls180.v:606.6-606.38" wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:576.5-576.44" + attribute \src "ls180.v:608.5-608.44" wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:571.6-571.39" + attribute \src "ls180.v:603.6-603.39" wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:570.6-570.39" + attribute \src "ls180.v:602.6-602.39" wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:575.5-575.44" + attribute \src "ls180.v:607.5-607.44" wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:572.6-572.36" + attribute \src "ls180.v:604.6-604.36" wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:639.12-639.39" + attribute \src "ls180.v:671.12-671.39" wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:643.5-643.38" + attribute \src "ls180.v:675.5-675.38" wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:644.5-644.47" + attribute \src "ls180.v:676.5-676.47" wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:641.6-641.37" + attribute \src "ls180.v:673.6-673.37" wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:642.5-642.37" + attribute \src "ls180.v:674.5-674.37" wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:640.5-640.39" + attribute \src "ls180.v:672.5-672.39" wire \main_sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:651.32-651.69" + attribute \src "ls180.v:683.32-683.69" wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:650.6-650.43" + attribute \src "ls180.v:682.6-682.43" wire \main_sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:649.32-649.68" + attribute \src "ls180.v:681.32-681.68" wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:648.6-648.42" + attribute \src "ls180.v:680.6-680.42" wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:647.11-647.48" + attribute \src "ls180.v:679.11-679.48" wire width 3 \main_sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:646.32-646.69" + attribute \src "ls180.v:678.32-678.69" wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:645.6-645.43" + attribute \src "ls180.v:677.6-677.43" wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:671.5-671.43" + attribute \src "ls180.v:703.5-703.43" wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:693.11-693.63" + attribute \src "ls180.v:725.11-725.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:698.6-698.58" + attribute \src "ls180.v:730.6-730.58" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:703.6-703.64" + attribute \src "ls180.v:735.6-735.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:704.6-704.63" + attribute \src "ls180.v:736.6-736.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:702.13-702.78" + attribute \src "ls180.v:734.13-734.78" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:701.6-701.69" + attribute \src "ls180.v:733.6-733.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:707.6-707.65" + attribute \src "ls180.v:739.6-739.65" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:708.6-708.64" + attribute \src "ls180.v:740.6-740.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:706.13-706.79" + attribute \src "ls180.v:738.13-738.79" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:705.6-705.70" + attribute \src "ls180.v:737.6-737.70" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:690.11-690.61" + attribute \src "ls180.v:722.11-722.61" wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:692.11-692.63" + attribute \src "ls180.v:724.11-724.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:699.12-699.67" + attribute \src "ls180.v:731.12-731.67" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:700.13-700.70" + attribute \src "ls180.v:732.13-732.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:691.5-691.57" + attribute \src "ls180.v:723.5-723.57" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:674.5-674.60" + attribute \src "ls180.v:706.5-706.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:675.5-675.59" + attribute \src "ls180.v:707.5-707.59" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:677.13-677.75" + attribute \src "ls180.v:709.13-709.75" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:676.6-676.66" + attribute \src "ls180.v:708.6-708.66" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:673.6-673.61" + attribute \src "ls180.v:705.6-705.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:672.6-672.61" + attribute \src "ls180.v:704.6-704.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:680.6-680.63" + attribute \src "ls180.v:712.6-712.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:681.6-681.62" + attribute \src "ls180.v:713.6-713.62" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:683.13-683.77" + attribute \src "ls180.v:715.13-715.77" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:682.6-682.68" + attribute \src "ls180.v:714.6-714.68" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:679.6-679.63" + attribute \src "ls180.v:711.6-711.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:678.6-678.63" + attribute \src "ls180.v:710.6-710.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:688.13-688.71" + attribute \src "ls180.v:720.13-720.71" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:689.13-689.72" + attribute \src "ls180.v:721.13-721.72" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:686.6-686.63" + attribute \src "ls180.v:718.6-718.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:687.6-687.69" + attribute \src "ls180.v:719.6-719.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:684.6-684.63" + attribute \src "ls180.v:716.6-716.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:685.6-685.69" + attribute \src "ls180.v:717.6-717.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:694.11-694.66" + attribute \src "ls180.v:726.11-726.66" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:695.13-695.70" + attribute \src "ls180.v:727.13-727.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:697.13-697.70" + attribute \src "ls180.v:729.13-729.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:696.6-696.60" + attribute \src "ls180.v:728.6-728.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:711.6-711.51" + attribute \src "ls180.v:743.6-743.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:712.6-712.50" + attribute \src "ls180.v:744.6-744.50" wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:714.13-714.65" + attribute \src "ls180.v:746.13-746.65" wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:713.6-713.56" + attribute \src "ls180.v:745.6-745.56" wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:710.6-710.51" + attribute \src "ls180.v:742.6-742.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:709.6-709.51" + attribute \src "ls180.v:741.6-741.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:717.5-717.52" + attribute \src "ls180.v:749.5-749.52" wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:718.5-718.51" + attribute \src "ls180.v:750.5-750.51" wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:720.12-720.66" + attribute \src "ls180.v:752.12-752.66" wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:719.5-719.57" + attribute \src "ls180.v:751.5-751.57" wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:716.6-716.53" + attribute \src "ls180.v:748.6-748.53" wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:715.5-715.52" + attribute \src "ls180.v:747.5-747.52" wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:663.12-663.49" + attribute \src "ls180.v:695.12-695.49" wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:664.12-664.50" + attribute \src "ls180.v:696.12-696.50" wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:665.5-665.44" + attribute \src "ls180.v:697.5-697.44" wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:668.5-668.47" + attribute \src "ls180.v:700.5-700.47" wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:669.5-669.48" + attribute \src "ls180.v:701.5-701.48" wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:670.5-670.49" + attribute \src "ls180.v:702.5-702.49" wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:666.5-666.44" + attribute \src "ls180.v:698.5-698.44" wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:667.5-667.43" + attribute \src "ls180.v:699.5-699.43" wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:662.5-662.38" + attribute \src "ls180.v:694.5-694.38" wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:661.5-661.38" + attribute \src "ls180.v:693.5-693.38" wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:660.5-660.40" + attribute \src "ls180.v:692.5-692.40" wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:659.6-659.41" + attribute \src "ls180.v:691.6-691.41" wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:655.13-655.45" + attribute \src "ls180.v:687.13-687.45" wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:656.6-656.38" + attribute \src "ls180.v:688.6-688.38" wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:658.5-658.44" + attribute \src "ls180.v:690.5-690.44" wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:653.6-653.39" + attribute \src "ls180.v:685.6-685.39" wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:652.6-652.39" + attribute \src "ls180.v:684.6-684.39" wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:657.5-657.44" + attribute \src "ls180.v:689.5-689.44" wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:654.6-654.36" + attribute \src "ls180.v:686.6-686.36" wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:721.12-721.39" + attribute \src "ls180.v:753.12-753.39" wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:725.5-725.38" + attribute \src "ls180.v:757.5-757.38" wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:726.5-726.47" + attribute \src "ls180.v:758.5-758.47" wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:723.6-723.37" + attribute \src "ls180.v:755.6-755.37" wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:724.5-724.37" + attribute \src "ls180.v:756.5-756.37" wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:722.5-722.39" + attribute \src "ls180.v:754.5-754.39" wire \main_sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:733.32-733.69" + attribute \src "ls180.v:765.32-765.69" wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:732.6-732.43" + attribute \src "ls180.v:764.6-764.43" wire \main_sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:731.32-731.68" + attribute \src "ls180.v:763.32-763.68" wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:730.6-730.42" + attribute \src "ls180.v:762.6-762.42" wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:729.11-729.48" + attribute \src "ls180.v:761.11-761.48" wire width 3 \main_sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:728.32-728.69" + attribute \src "ls180.v:760.32-760.69" wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:727.6-727.43" + attribute \src "ls180.v:759.6-759.43" wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:735.6-735.28" + attribute \src "ls180.v:767.6-767.28" wire \main_sdram_cas_allowed - attribute \src "ls180.v:753.6-753.30" + attribute \src "ls180.v:785.6-785.30" wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:742.13-742.48" + attribute \src "ls180.v:774.13-774.48" wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:743.12-743.48" + attribute \src "ls180.v:775.12-775.48" wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:744.5-744.42" + attribute \src "ls180.v:776.5-776.42" wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:747.6-747.46" + attribute \src "ls180.v:779.6-779.46" wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:748.6-748.47" + attribute \src "ls180.v:780.6-780.47" wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:749.6-749.48" + attribute \src "ls180.v:781.6-781.48" wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:745.5-745.42" + attribute \src "ls180.v:777.5-777.42" wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:746.5-746.41" + attribute \src "ls180.v:778.5-778.41" wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:741.5-741.36" + attribute \src "ls180.v:773.5-773.36" wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:740.6-740.37" + attribute \src "ls180.v:772.6-772.37" wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:752.11-752.38" + attribute \src "ls180.v:784.11-784.38" wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:751.12-751.41" + attribute \src "ls180.v:783.12-783.41" wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:750.11-750.39" + attribute \src "ls180.v:782.11-782.39" wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:739.5-739.41" + attribute \src "ls180.v:771.5-771.41" wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:738.5-738.36" + attribute \src "ls180.v:770.5-770.36" wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:736.5-736.37" + attribute \src "ls180.v:768.5-768.37" wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:737.5-737.38" + attribute \src "ls180.v:769.5-769.38" wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:771.6-771.30" + attribute \src "ls180.v:803.6-803.30" wire \main_sdram_choose_req_ce - attribute \src "ls180.v:760.13-760.48" + attribute \src "ls180.v:792.13-792.48" wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:761.12-761.48" + attribute \src "ls180.v:793.12-793.48" wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:762.5-762.42" + attribute \src "ls180.v:794.5-794.42" wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:765.6-765.46" + attribute \src "ls180.v:797.6-797.46" wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:766.6-766.47" + attribute \src "ls180.v:798.6-798.47" wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:767.6-767.48" + attribute \src "ls180.v:799.6-799.48" wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:763.5-763.42" + attribute \src "ls180.v:795.5-795.42" wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:764.5-764.41" + attribute \src "ls180.v:796.5-796.41" wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:759.5-759.36" + attribute \src "ls180.v:791.5-791.36" wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:758.6-758.37" + attribute \src "ls180.v:790.6-790.37" wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:770.11-770.38" + attribute \src "ls180.v:802.11-802.38" wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:769.12-769.41" + attribute \src "ls180.v:801.12-801.41" wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:768.11-768.39" + attribute \src "ls180.v:800.11-800.39" wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:757.5-757.41" + attribute \src "ls180.v:789.5-789.41" wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:756.6-756.37" + attribute \src "ls180.v:788.6-788.37" wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:754.5-754.37" + attribute \src "ls180.v:786.5-786.37" wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:755.5-755.38" + attribute \src "ls180.v:787.5-787.38" wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:315.6-315.20" + attribute \src "ls180.v:347.6-347.20" wire \main_sdram_cke - attribute \src "ls180.v:383.5-383.24" + attribute \src "ls180.v:415.5-415.24" wire \main_sdram_cmd_last - attribute \src "ls180.v:384.12-384.36" + attribute \src "ls180.v:416.12-416.36" wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:385.11-385.36" + attribute \src "ls180.v:417.11-417.36" wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:386.5-386.31" + attribute \src "ls180.v:418.5-418.31" wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:389.5-389.35" + attribute \src "ls180.v:421.5-421.35" wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:390.5-390.36" + attribute \src "ls180.v:422.5-422.36" wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:387.5-387.31" + attribute \src "ls180.v:419.5-419.31" wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:388.5-388.30" + attribute \src "ls180.v:420.5-420.30" wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:382.5-382.25" + attribute \src "ls180.v:414.5-414.25" wire \main_sdram_cmd_ready - attribute \src "ls180.v:381.5-381.25" + attribute \src "ls180.v:413.5-413.25" wire \main_sdram_cmd_valid - attribute \src "ls180.v:323.6-323.32" + attribute \src "ls180.v:355.6-355.32" wire \main_sdram_command_issue_r - attribute \src "ls180.v:322.6-322.33" + attribute \src "ls180.v:354.6-354.33" wire \main_sdram_command_issue_re - attribute \src "ls180.v:325.5-325.31" + attribute \src "ls180.v:357.5-357.31" wire \main_sdram_command_issue_w - attribute \src "ls180.v:324.6-324.33" + attribute \src "ls180.v:356.6-356.33" wire \main_sdram_command_issue_we - attribute \src "ls180.v:321.5-321.26" + attribute \src "ls180.v:353.5-353.26" wire \main_sdram_command_re - attribute \src "ls180.v:320.11-320.37" + attribute \src "ls180.v:352.11-352.37" wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:374.5-374.28" + attribute \src "ls180.v:406.5-406.28" wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:365.12-365.37" + attribute \src "ls180.v:397.12-397.37" wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:366.11-366.33" + attribute \src "ls180.v:398.11-398.33" wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:367.5-367.28" + attribute \src "ls180.v:399.5-399.28" wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:371.6-371.27" + attribute \src "ls180.v:403.6-403.27" wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:368.5-368.27" + attribute \src "ls180.v:400.5-400.27" wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:372.6-372.27" + attribute \src "ls180.v:404.6-404.27" wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:369.5-369.28" + attribute \src "ls180.v:401.5-401.28" wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:379.13-379.37" + attribute \src "ls180.v:411.13-411.37" wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:378.5-378.32" + attribute \src "ls180.v:410.5-410.32" wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:380.6-380.36" + attribute \src "ls180.v:412.6-412.36" wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:373.6-373.31" + attribute \src "ls180.v:405.6-405.31" wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:370.5-370.27" + attribute \src "ls180.v:402.5-402.27" wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:375.13-375.37" + attribute \src "ls180.v:407.13-407.37" wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:376.5-376.32" + attribute \src "ls180.v:408.5-408.32" wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:377.12-377.41" + attribute \src "ls180.v:409.12-409.41" wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:789.5-789.19" + attribute \src "ls180.v:821.5-821.19" wire \main_sdram_en0 - attribute \src "ls180.v:792.5-792.19" + attribute \src "ls180.v:824.5-824.19" wire \main_sdram_en1 - attribute \src "ls180.v:795.6-795.30" + attribute \src "ls180.v:827.6-827.30" wire \main_sdram_go_to_refresh - attribute \src "ls180.v:337.13-337.44" + attribute \src "ls180.v:369.13-369.44" wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:338.6-338.37" + attribute \src "ls180.v:370.6-370.37" wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:340.6-340.44" + attribute \src "ls180.v:372.6-372.44" wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:335.6-335.38" + attribute \src "ls180.v:367.6-367.38" wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:334.6-334.38" + attribute \src "ls180.v:366.6-366.38" wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:339.6-339.44" + attribute \src "ls180.v:371.6-371.44" wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:336.6-336.35" + attribute \src "ls180.v:368.6-368.35" wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:344.13-344.44" + attribute \src "ls180.v:376.13-376.44" wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:345.6-345.37" + attribute \src "ls180.v:377.6-377.37" wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:347.6-347.44" + attribute \src "ls180.v:379.6-379.44" wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:342.6-342.38" + attribute \src "ls180.v:374.6-374.38" wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:341.6-341.38" + attribute \src "ls180.v:373.6-373.38" wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:346.6-346.44" + attribute \src "ls180.v:378.6-378.44" wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:343.6-343.35" + attribute \src "ls180.v:375.6-375.35" wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:351.13-351.44" + attribute \src "ls180.v:383.13-383.44" wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:352.6-352.37" + attribute \src "ls180.v:384.6-384.37" wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:354.6-354.44" + attribute \src "ls180.v:386.6-386.44" wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:349.6-349.38" + attribute \src "ls180.v:381.6-381.38" wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:348.6-348.38" + attribute \src "ls180.v:380.6-380.38" wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:353.6-353.44" + attribute \src "ls180.v:385.6-385.44" wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:350.6-350.35" + attribute \src "ls180.v:382.6-382.35" wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:358.13-358.44" + attribute \src "ls180.v:390.13-390.44" wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:359.6-359.37" + attribute \src "ls180.v:391.6-391.37" wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:361.6-361.44" + attribute \src "ls180.v:393.6-393.44" wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:356.6-356.38" + attribute \src "ls180.v:388.6-388.38" wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:355.6-355.38" + attribute \src "ls180.v:387.6-387.38" wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:360.6-360.44" + attribute \src "ls180.v:392.6-392.44" wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:357.6-357.35" + attribute \src "ls180.v:389.6-389.35" wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:364.13-364.39" + attribute \src "ls180.v:396.13-396.39" wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:362.12-362.38" + attribute \src "ls180.v:394.12-394.38" wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:363.11-363.40" + attribute \src "ls180.v:395.11-395.40" wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:275.5-275.29" + attribute \src "ls180.v:307.5-307.29" wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:266.13-266.39" + attribute \src "ls180.v:298.13-298.39" wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:267.12-267.35" + attribute \src "ls180.v:299.12-299.35" wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:268.5-268.29" + attribute \src "ls180.v:300.5-300.29" wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:272.6-272.28" + attribute \src "ls180.v:304.6-304.28" wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:269.5-269.28" + attribute \src "ls180.v:301.5-301.28" wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:273.6-273.28" + attribute \src "ls180.v:305.6-305.28" wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:270.5-270.29" + attribute \src "ls180.v:302.5-302.29" wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:280.12-280.37" + attribute \src "ls180.v:312.12-312.37" wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:279.6-279.34" + attribute \src "ls180.v:311.6-311.34" wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:281.5-281.36" + attribute \src "ls180.v:313.5-313.36" wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:274.6-274.32" + attribute \src "ls180.v:306.6-306.32" wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:271.5-271.28" + attribute \src "ls180.v:303.5-303.28" wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:276.13-276.38" + attribute \src "ls180.v:308.13-308.38" wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:277.6-277.34" + attribute \src "ls180.v:309.6-309.34" wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:278.12-278.42" + attribute \src "ls180.v:310.12-310.42" wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:307.5-307.31" + attribute \src "ls180.v:339.5-339.31" wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:298.12-298.40" + attribute \src "ls180.v:330.12-330.40" wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:299.11-299.36" + attribute \src "ls180.v:331.11-331.36" wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:300.5-300.31" + attribute \src "ls180.v:332.5-332.31" wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:304.5-304.29" + attribute \src "ls180.v:336.5-336.29" wire \main_sdram_master_p0_cke - attribute \src "ls180.v:301.5-301.30" + attribute \src "ls180.v:333.5-333.30" wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:305.5-305.29" + attribute \src "ls180.v:337.5-337.29" wire \main_sdram_master_p0_odt - attribute \src "ls180.v:302.5-302.31" + attribute \src "ls180.v:334.5-334.31" wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:312.13-312.40" + attribute \src "ls180.v:344.13-344.40" wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:311.5-311.35" + attribute \src "ls180.v:343.5-343.35" wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:313.6-313.39" + attribute \src "ls180.v:345.6-345.39" wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:306.5-306.33" + attribute \src "ls180.v:338.5-338.33" wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:303.5-303.30" + attribute \src "ls180.v:335.5-335.30" wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:308.12-308.39" + attribute \src "ls180.v:340.12-340.39" wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:309.5-309.35" + attribute \src "ls180.v:341.5-341.35" wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:310.11-310.43" + attribute \src "ls180.v:342.11-342.43" wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:790.6-790.26" + attribute \src "ls180.v:822.6-822.26" wire \main_sdram_max_time0 - attribute \src "ls180.v:793.6-793.26" + attribute \src "ls180.v:825.6-825.26" wire \main_sdram_max_time1 - attribute \src "ls180.v:772.12-772.28" + attribute \src "ls180.v:804.12-804.28" wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:773.11-773.28" + attribute \src "ls180.v:805.11-805.28" wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:316.6-316.20" + attribute \src "ls180.v:348.6-348.20" wire \main_sdram_odt - attribute \src "ls180.v:399.5-399.31" + attribute \src "ls180.v:431.5-431.31" wire \main_sdram_postponer_count - attribute \src "ls180.v:397.6-397.32" + attribute \src "ls180.v:429.6-429.32" wire \main_sdram_postponer_req_i - attribute \src "ls180.v:398.5-398.31" + attribute \src "ls180.v:430.5-430.31" wire \main_sdram_postponer_req_o - attribute \src "ls180.v:734.6-734.28" + attribute \src "ls180.v:766.6-766.28" wire \main_sdram_ras_allowed - attribute \src "ls180.v:319.5-319.18" + attribute \src "ls180.v:351.5-351.18" wire \main_sdram_re - attribute \src "ls180.v:787.6-787.31" + attribute \src "ls180.v:819.6-819.31" wire \main_sdram_read_available - attribute \src "ls180.v:317.6-317.24" + attribute \src "ls180.v:349.6-349.24" wire \main_sdram_reset_n - attribute \src "ls180.v:314.6-314.20" + attribute \src "ls180.v:346.6-346.20" wire \main_sdram_sel - attribute \src "ls180.v:405.5-405.31" + attribute \src "ls180.v:437.5-437.31" wire \main_sdram_sequencer_count - attribute \src "ls180.v:404.11-404.39" + attribute \src "ls180.v:436.11-436.39" wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:401.6-401.32" + attribute \src "ls180.v:433.6-433.32" wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:403.5-403.31" + attribute \src "ls180.v:435.5-435.31" wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:400.5-400.32" + attribute \src "ls180.v:432.5-432.32" wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:402.6-402.33" + attribute \src "ls180.v:434.6-434.33" wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:291.6-291.31" + attribute \src "ls180.v:323.6-323.31" wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:282.13-282.40" + attribute \src "ls180.v:314.13-314.40" wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:283.12-283.36" + attribute \src "ls180.v:315.12-315.36" wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:284.6-284.31" + attribute \src "ls180.v:316.6-316.31" wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:288.6-288.29" + attribute \src "ls180.v:320.6-320.29" wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:285.6-285.30" + attribute \src "ls180.v:317.6-317.30" wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:289.6-289.29" + attribute \src "ls180.v:321.6-321.29" wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:286.6-286.31" + attribute \src "ls180.v:318.6-318.31" wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:296.12-296.38" + attribute \src "ls180.v:328.12-328.38" wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:295.6-295.35" + attribute \src "ls180.v:327.6-327.35" wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:297.5-297.37" + attribute \src "ls180.v:329.5-329.37" wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:290.6-290.33" + attribute \src "ls180.v:322.6-322.33" wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:287.6-287.30" + attribute \src "ls180.v:319.6-319.30" wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:292.13-292.39" + attribute \src "ls180.v:324.13-324.39" wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:293.6-293.35" + attribute \src "ls180.v:325.6-325.35" wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:294.12-294.43" + attribute \src "ls180.v:326.12-326.43" wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:332.12-332.29" + attribute \src "ls180.v:364.12-364.29" wire width 16 \main_sdram_status - attribute \src "ls180.v:775.5-775.24" + attribute \src "ls180.v:807.5-807.24" wire \main_sdram_steerer0 - attribute \src "ls180.v:776.5-776.24" + attribute \src "ls180.v:808.5-808.24" wire \main_sdram_steerer1 - attribute \src "ls180.v:774.11-774.33" + attribute \src "ls180.v:806.11-806.33" wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:318.11-318.29" + attribute \src "ls180.v:350.11-350.29" wire width 4 \main_sdram_storage - attribute \src "ls180.v:783.5-783.29" + attribute \src "ls180.v:815.5-815.29" wire \main_sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:782.32-782.56" + attribute \src "ls180.v:814.32-814.56" wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:781.6-781.30" + attribute \src "ls180.v:813.6-813.30" wire \main_sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:780.32-780.56" + attribute \src "ls180.v:812.32-812.56" wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:779.6-779.30" + attribute \src "ls180.v:811.6-811.30" wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:791.11-791.27" + attribute \src "ls180.v:823.11-823.27" wire width 5 \main_sdram_time0 - attribute \src "ls180.v:794.11-794.27" + attribute \src "ls180.v:826.11-826.27" wire width 4 \main_sdram_time1 - attribute \src "ls180.v:394.12-394.35" + attribute \src "ls180.v:426.12-426.35" wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:396.11-396.34" + attribute \src "ls180.v:428.11-428.34" wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:393.6-393.28" + attribute \src "ls180.v:425.6-425.28" wire \main_sdram_timer_done0 - attribute \src "ls180.v:395.6-395.28" + attribute \src "ls180.v:427.6-427.28" wire \main_sdram_timer_done1 - attribute \src "ls180.v:392.6-392.27" + attribute \src "ls180.v:424.6-424.27" wire \main_sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:778.32-778.56" + attribute \src "ls180.v:810.32-810.56" wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:777.6-777.30" + attribute \src "ls180.v:809.6-809.30" wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:786.11-786.35" + attribute \src "ls180.v:818.11-818.35" wire width 3 \main_sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:785.32-785.56" + attribute \src "ls180.v:817.32-817.56" wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:784.6-784.30" + attribute \src "ls180.v:816.6-816.30" wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:391.6-391.30" + attribute \src "ls180.v:423.6-423.30" wire \main_sdram_wants_refresh - attribute \src "ls180.v:333.6-333.19" + attribute \src "ls180.v:365.6-365.19" wire \main_sdram_we - attribute \src "ls180.v:331.5-331.25" + attribute \src "ls180.v:363.5-363.25" wire \main_sdram_wrdata_re - attribute \src "ls180.v:330.12-330.37" + attribute \src "ls180.v:362.12-362.37" wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:788.6-788.32" + attribute \src "ls180.v:820.6-820.32" wire \main_sdram_write_available - attribute \src "ls180.v:988.6-988.27" + attribute \src "ls180.v:855.5-855.47" + wire \main_socbushandler_converted_interface_ack + attribute \src "ls180.v:849.13-849.55" + wire width 30 \main_socbushandler_converted_interface_adr + attribute \src "ls180.v:858.12-858.54" + wire width 2 \main_socbushandler_converted_interface_bte + attribute \src "ls180.v:857.12-857.54" + wire width 3 \main_socbushandler_converted_interface_cti + attribute \src "ls180.v:853.6-853.48" + wire \main_socbushandler_converted_interface_cyc + attribute \src "ls180.v:851.13-851.57" + wire width 64 \main_socbushandler_converted_interface_dat_r + attribute \src "ls180.v:850.13-850.57" + wire width 64 \main_socbushandler_converted_interface_dat_w + attribute \src "ls180.v:859.5-859.47" + wire \main_socbushandler_converted_interface_err + attribute \src "ls180.v:852.12-852.54" + wire width 8 \main_socbushandler_converted_interface_sel + attribute \src "ls180.v:854.6-854.48" + wire \main_socbushandler_converted_interface_stb + attribute \src "ls180.v:856.6-856.47" + wire \main_socbushandler_converted_interface_we + attribute \src "ls180.v:861.5-861.31" + wire \main_socbushandler_counter + attribute \src "ls180.v:1784.5-1784.53" + wire \main_socbushandler_counter_converter2_next_value + attribute \src "ls180.v:1785.5-1785.56" + wire \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:863.12-863.36" + wire width 64 \main_socbushandler_dat_r + attribute \src "ls180.v:862.6-862.30" + wire \main_socbushandler_reset + attribute \src "ls180.v:860.5-860.28" + wire \main_socbushandler_skip + attribute \src "ls180.v:1032.6-1032.27" wire \main_spimaster0_start - attribute \src "ls180.v:998.12-998.35" + attribute \src "ls180.v:1042.12-1042.35" wire width 8 \main_spimaster10_length - attribute \src "ls180.v:999.12-999.36" + attribute \src "ls180.v:1043.12-1043.36" wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1000.5-1000.24" + attribute \src "ls180.v:1044.5-1044.24" wire \main_spimaster12_re - attribute \src "ls180.v:1001.6-1001.27" + attribute \src "ls180.v:1045.6-1045.27" wire \main_spimaster13_done - attribute \src "ls180.v:1002.6-1002.29" + attribute \src "ls180.v:1046.6-1046.29" wire \main_spimaster14_status - attribute \src "ls180.v:1003.6-1003.25" + attribute \src "ls180.v:1047.6-1047.25" wire \main_spimaster15_we - attribute \src "ls180.v:1004.11-1004.35" + attribute \src "ls180.v:1048.11-1048.35" wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1005.5-1005.24" + attribute \src "ls180.v:1049.5-1049.24" wire \main_spimaster17_re - attribute \src "ls180.v:1006.12-1006.35" + attribute \src "ls180.v:1050.12-1050.35" wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1007.6-1007.25" + attribute \src "ls180.v:1051.6-1051.25" wire \main_spimaster19_we - attribute \src "ls180.v:989.12-989.34" + attribute \src "ls180.v:1033.12-1033.34" wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1061.5-1061.23" + attribute \src "ls180.v:1105.5-1105.23" wire \main_spimaster1_re - attribute \src "ls180.v:1060.12-1060.35" + attribute \src "ls180.v:1104.12-1104.35" wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1008.6-1008.26" + attribute \src "ls180.v:1052.6-1052.26" wire \main_spimaster20_sel - attribute \src "ls180.v:1009.5-1009.29" + attribute \src "ls180.v:1053.5-1053.29" wire \main_spimaster21_storage - attribute \src "ls180.v:1010.5-1010.24" + attribute \src "ls180.v:1054.5-1054.24" wire \main_spimaster22_re - attribute \src "ls180.v:1011.5-1011.29" + attribute \src "ls180.v:1055.5-1055.29" wire \main_spimaster23_storage - attribute \src "ls180.v:1012.5-1012.24" + attribute \src "ls180.v:1056.5-1056.24" wire \main_spimaster24_re - attribute \src "ls180.v:1013.5-1013.32" + attribute \src "ls180.v:1057.5-1057.32" wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1014.5-1014.31" + attribute \src "ls180.v:1058.5-1058.31" wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1015.11-1015.33" + attribute \src "ls180.v:1059.11-1059.33" wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1781.11-1781.55" + attribute \src "ls180.v:1825.11-1825.55" wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1782.5-1782.52" + attribute \src "ls180.v:1826.5-1826.52" wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1016.5-1016.32" + attribute \src "ls180.v:1060.5-1060.32" wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1017.5-1017.32" + attribute \src "ls180.v:1061.5-1061.32" wire \main_spimaster29_miso_latch - attribute \src "ls180.v:990.5-990.25" + attribute \src "ls180.v:1034.5-1034.25" wire \main_spimaster2_done - attribute \src "ls180.v:1018.12-1018.40" + attribute \src "ls180.v:1062.12-1062.40" wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1019.6-1019.31" + attribute \src "ls180.v:1063.6-1063.31" wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1020.6-1020.31" + attribute \src "ls180.v:1064.6-1064.31" wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1021.11-1021.37" + attribute \src "ls180.v:1065.11-1065.37" wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1022.11-1022.36" + attribute \src "ls180.v:1066.11-1066.36" wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1023.11-1023.37" + attribute \src "ls180.v:1067.11-1067.37" wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:991.5-991.24" + attribute \src "ls180.v:1035.5-1035.24" wire \main_spimaster3_irq - attribute \src "ls180.v:992.12-992.32" + attribute \src "ls180.v:1036.12-1036.32" wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:993.11-993.31" + attribute \src "ls180.v:1037.11-1037.31" wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:994.6-994.24" + attribute \src "ls180.v:1038.6-1038.24" wire \main_spimaster6_cs - attribute \src "ls180.v:995.6-995.30" + attribute \src "ls180.v:1039.6-1039.30" wire \main_spimaster7_loopback - attribute \src "ls180.v:996.12-996.39" + attribute \src "ls180.v:1040.12-1040.39" wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:997.5-997.26" + attribute \src "ls180.v:1041.5-1041.26" wire \main_spimaster9_start - attribute \src "ls180.v:1032.13-1032.40" + attribute \src "ls180.v:1076.13-1076.40" wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1054.12-1054.39" + attribute \src "ls180.v:1098.12-1098.39" wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1049.5-1049.30" + attribute \src "ls180.v:1093.5-1093.30" wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1056.6-1056.29" + attribute \src "ls180.v:1100.6-1100.29" wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1055.6-1055.29" + attribute \src "ls180.v:1099.6-1099.29" wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1036.5-1036.30" + attribute \src "ls180.v:1080.5-1080.30" wire \main_spisdcard_control_re - attribute \src "ls180.v:1035.12-1035.42" + attribute \src "ls180.v:1079.12-1079.42" wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1051.11-1051.31" + attribute \src "ls180.v:1095.11-1095.31" wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1785.11-1785.53" + attribute \src "ls180.v:1829.11-1829.53" wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1786.5-1786.50" + attribute \src "ls180.v:1830.5-1830.50" wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1030.6-1030.23" + attribute \src "ls180.v:1074.6-1074.23" wire \main_spisdcard_cs - attribute \src "ls180.v:1050.5-1050.29" + attribute \src "ls180.v:1094.5-1094.29" wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1046.5-1046.25" + attribute \src "ls180.v:1090.5-1090.25" wire \main_spisdcard_cs_re - attribute \src "ls180.v:1045.5-1045.30" + attribute \src "ls180.v:1089.5-1089.30" wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1026.5-1026.25" + attribute \src "ls180.v:1070.5-1070.25" wire \main_spisdcard_done0 - attribute \src "ls180.v:1037.6-1037.26" + attribute \src "ls180.v:1081.6-1081.26" wire \main_spisdcard_done1 - attribute \src "ls180.v:1027.5-1027.23" + attribute \src "ls180.v:1071.5-1071.23" wire \main_spisdcard_irq - attribute \src "ls180.v:1025.12-1025.34" + attribute \src "ls180.v:1069.12-1069.34" wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1034.12-1034.34" + attribute \src "ls180.v:1078.12-1078.34" wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1031.6-1031.29" + attribute \src "ls180.v:1075.6-1075.29" wire \main_spisdcard_loopback - attribute \src "ls180.v:1048.5-1048.31" + attribute \src "ls180.v:1092.5-1092.31" wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1047.5-1047.36" + attribute \src "ls180.v:1091.5-1091.36" wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1029.11-1029.30" + attribute \src "ls180.v:1073.11-1073.30" wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1059.11-1059.35" + attribute \src "ls180.v:1103.11-1103.35" wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1053.5-1053.30" + attribute \src "ls180.v:1097.5-1097.30" wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1042.12-1042.38" + attribute \src "ls180.v:1086.12-1086.38" wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1043.6-1043.28" + attribute \src "ls180.v:1087.6-1087.28" wire \main_spisdcard_miso_we - attribute \src "ls180.v:1028.12-1028.31" + attribute \src "ls180.v:1072.12-1072.31" wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1057.11-1057.35" + attribute \src "ls180.v:1101.11-1101.35" wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1052.5-1052.30" + attribute \src "ls180.v:1096.5-1096.30" wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1041.5-1041.27" + attribute \src "ls180.v:1085.5-1085.27" wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1058.11-1058.34" + attribute \src "ls180.v:1102.11-1102.34" wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1040.11-1040.38" + attribute \src "ls180.v:1084.11-1084.38" wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1044.6-1044.24" + attribute \src "ls180.v:1088.6-1088.24" wire \main_spisdcard_sel - attribute \src "ls180.v:1024.6-1024.27" + attribute \src "ls180.v:1068.6-1068.27" wire \main_spisdcard_start0 - attribute \src "ls180.v:1033.5-1033.26" + attribute \src "ls180.v:1077.5-1077.26" wire \main_spisdcard_start1 - attribute \src "ls180.v:1038.6-1038.34" + attribute \src "ls180.v:1082.6-1082.34" wire \main_spisdcard_status_status - attribute \src "ls180.v:1039.6-1039.30" + attribute \src "ls180.v:1083.6-1083.30" wire \main_spisdcard_status_we - attribute \src "ls180.v:885.12-885.44" + attribute \src "ls180.v:213.12-213.26" + wire width 9 \main_sram0_adr + attribute \src "ls180.v:214.13-214.29" + wire width 64 \main_sram0_dat_r + attribute \src "ls180.v:216.13-216.29" + wire width 64 \main_sram0_dat_w + attribute \src "ls180.v:215.11-215.24" + wire width 8 \main_sram0_we + attribute \src "ls180.v:228.12-228.26" + wire width 9 \main_sram1_adr + attribute \src "ls180.v:229.13-229.29" + wire width 64 \main_sram1_dat_r + attribute \src "ls180.v:231.13-231.29" + wire width 64 \main_sram1_dat_w + attribute \src "ls180.v:230.11-230.24" + wire width 8 \main_sram1_we + attribute \src "ls180.v:243.12-243.26" + wire width 9 \main_sram2_adr + attribute \src "ls180.v:244.13-244.29" + wire width 64 \main_sram2_dat_r + attribute \src "ls180.v:246.13-246.29" + wire width 64 \main_sram2_dat_w + attribute \src "ls180.v:245.11-245.24" + wire width 8 \main_sram2_we + attribute \src "ls180.v:929.12-929.44" wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:884.6-884.39" + attribute \src "ls180.v:928.6-928.39" wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:887.11-887.43" + attribute \src "ls180.v:931.11-931.43" wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:886.6-886.39" + attribute \src "ls180.v:930.6-930.39" wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:889.5-889.30" + attribute \src "ls180.v:933.5-933.30" wire \main_uart_eventmanager_re - attribute \src "ls180.v:881.12-881.43" + attribute \src "ls180.v:925.12-925.43" wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:880.6-880.38" + attribute \src "ls180.v:924.6-924.38" wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:883.11-883.42" + attribute \src "ls180.v:927.11-927.42" wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:882.6-882.38" + attribute \src "ls180.v:926.6-926.38" wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:888.11-888.41" + attribute \src "ls180.v:932.11-932.41" wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:869.6-869.19" + attribute \src "ls180.v:913.6-913.19" wire \main_uart_irq - attribute \src "ls180.v:855.12-855.46" + attribute \src "ls180.v:899.12-899.46" wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:845.12-845.46" + attribute \src "ls180.v:889.12-889.46" wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:838.5-838.21" + attribute \src "ls180.v:882.5-882.21" wire \main_uart_phy_re - attribute \src "ls180.v:856.6-856.22" + attribute \src "ls180.v:900.6-900.22" wire \main_uart_phy_rx - attribute \src "ls180.v:859.11-859.36" + attribute \src "ls180.v:903.11-903.36" wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:860.5-860.26" + attribute \src "ls180.v:904.5-904.26" wire \main_uart_phy_rx_busy - attribute \src "ls180.v:857.5-857.23" + attribute \src "ls180.v:901.5-901.23" wire \main_uart_phy_rx_r - attribute \src "ls180.v:858.11-858.31" + attribute \src "ls180.v:902.11-902.31" wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:841.6-841.30" + attribute \src "ls180.v:885.6-885.30" wire \main_uart_phy_sink_first - attribute \src "ls180.v:842.6-842.29" + attribute \src "ls180.v:886.6-886.29" wire \main_uart_phy_sink_last - attribute \src "ls180.v:843.12-843.43" + attribute \src "ls180.v:887.12-887.43" wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:840.5-840.29" + attribute \src "ls180.v:884.5-884.29" wire \main_uart_phy_sink_ready - attribute \src "ls180.v:839.6-839.30" + attribute \src "ls180.v:883.6-883.30" wire \main_uart_phy_sink_valid - attribute \src "ls180.v:851.5-851.31" + attribute \src "ls180.v:895.5-895.31" wire \main_uart_phy_source_first - attribute \src "ls180.v:852.5-852.30" + attribute \src "ls180.v:896.5-896.30" wire \main_uart_phy_source_last - attribute \src "ls180.v:853.11-853.44" + attribute \src "ls180.v:897.11-897.44" wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:850.6-850.32" + attribute \src "ls180.v:894.6-894.32" wire \main_uart_phy_source_ready - attribute \src "ls180.v:849.5-849.31" + attribute \src "ls180.v:893.5-893.31" wire \main_uart_phy_source_valid - attribute \src "ls180.v:837.12-837.33" + attribute \src "ls180.v:881.12-881.33" wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:847.11-847.36" + attribute \src "ls180.v:891.11-891.36" wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:848.5-848.26" + attribute \src "ls180.v:892.5-892.26" wire \main_uart_phy_tx_busy - attribute \src "ls180.v:846.11-846.31" + attribute \src "ls180.v:890.11-890.31" wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:854.5-854.32" + attribute \src "ls180.v:898.5-898.32" wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:844.5-844.32" + attribute \src "ls180.v:888.5-888.32" wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:978.5-978.20" + attribute \src "ls180.v:1022.5-1022.20" wire \main_uart_reset - attribute \src "ls180.v:878.5-878.23" + attribute \src "ls180.v:922.5-922.23" wire \main_uart_rx_clear - attribute \src "ls180.v:962.11-962.36" + attribute \src "ls180.v:1006.11-1006.36" wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:967.6-967.31" + attribute \src "ls180.v:1011.6-1011.31" wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:973.6-973.37" + attribute \src "ls180.v:1017.6-1017.37" wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:974.6-974.36" + attribute \src "ls180.v:1018.6-1018.36" wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:972.12-972.50" + attribute \src "ls180.v:1016.12-1016.50" wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:976.6-976.38" + attribute \src "ls180.v:1020.6-1020.38" wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:977.6-977.37" + attribute \src "ls180.v:1021.6-1021.37" wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:975.12-975.51" + attribute \src "ls180.v:1019.12-1019.51" wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:959.11-959.35" + attribute \src "ls180.v:1003.11-1003.35" wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:971.12-971.36" + attribute \src "ls180.v:1015.12-1015.36" wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:961.11-961.36" + attribute \src "ls180.v:1005.11-1005.36" wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:968.12-968.40" + attribute \src "ls180.v:1012.12-1012.40" wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:969.12-969.42" + attribute \src "ls180.v:1013.12-1013.42" wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:970.6-970.33" + attribute \src "ls180.v:1014.6-1014.33" wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:951.6-951.26" + attribute \src "ls180.v:995.6-995.26" wire \main_uart_rx_fifo_re - attribute \src "ls180.v:952.5-952.31" + attribute \src "ls180.v:996.5-996.31" wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:960.5-960.30" + attribute \src "ls180.v:1004.5-1004.30" wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:943.6-943.34" + attribute \src "ls180.v:987.6-987.34" wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:944.6-944.33" + attribute \src "ls180.v:988.6-988.33" wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:945.12-945.47" + attribute \src "ls180.v:989.12-989.47" wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:942.6-942.34" + attribute \src "ls180.v:986.6-986.34" wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:941.6-941.34" + attribute \src "ls180.v:985.6-985.34" wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:948.6-948.36" + attribute \src "ls180.v:992.6-992.36" wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:949.6-949.35" + attribute \src "ls180.v:993.6-993.35" wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:950.12-950.49" + attribute \src "ls180.v:994.12-994.49" wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:947.6-947.36" + attribute \src "ls180.v:991.6-991.36" wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:946.6-946.36" + attribute \src "ls180.v:990.6-990.36" wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:957.12-957.42" + attribute \src "ls180.v:1001.12-1001.42" wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:958.12-958.43" + attribute \src "ls180.v:1002.12-1002.43" wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:955.6-955.35" + attribute \src "ls180.v:999.6-999.35" wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:956.6-956.41" + attribute \src "ls180.v:1000.6-1000.41" wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:953.6-953.35" + attribute \src "ls180.v:997.6-997.35" wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:954.6-954.41" + attribute \src "ls180.v:998.6-998.41" wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:963.11-963.39" + attribute \src "ls180.v:1007.11-1007.39" wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:964.12-964.42" + attribute \src "ls180.v:1008.12-1008.42" wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:966.12-966.42" + attribute \src "ls180.v:1010.12-1010.42" wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:965.6-965.33" + attribute \src "ls180.v:1009.6-1009.33" wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:879.5-879.29" + attribute \src "ls180.v:923.5-923.29" wire \main_uart_rx_old_trigger - attribute \src "ls180.v:876.5-876.25" + attribute \src "ls180.v:920.5-920.25" wire \main_uart_rx_pending - attribute \src "ls180.v:875.6-875.25" + attribute \src "ls180.v:919.6-919.25" wire \main_uart_rx_status - attribute \src "ls180.v:877.6-877.26" + attribute \src "ls180.v:921.6-921.26" wire \main_uart_rx_trigger - attribute \src "ls180.v:867.6-867.30" + attribute \src "ls180.v:911.6-911.30" wire \main_uart_rxempty_status - attribute \src "ls180.v:868.6-868.26" + attribute \src "ls180.v:912.6-912.26" wire \main_uart_rxempty_we - attribute \src "ls180.v:892.6-892.29" + attribute \src "ls180.v:936.6-936.29" wire \main_uart_rxfull_status - attribute \src "ls180.v:893.6-893.25" + attribute \src "ls180.v:937.6-937.25" wire \main_uart_rxfull_we - attribute \src "ls180.v:862.12-862.28" + attribute \src "ls180.v:906.12-906.28" wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:861.6-861.23" + attribute \src "ls180.v:905.6-905.23" wire \main_uart_rxtx_re - attribute \src "ls180.v:864.12-864.28" + attribute \src "ls180.v:908.12-908.28" wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:863.6-863.23" + attribute \src "ls180.v:907.6-907.23" wire \main_uart_rxtx_we - attribute \src "ls180.v:873.5-873.23" + attribute \src "ls180.v:917.5-917.23" wire \main_uart_tx_clear - attribute \src "ls180.v:925.11-925.36" + attribute \src "ls180.v:969.11-969.36" wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:930.6-930.31" + attribute \src "ls180.v:974.6-974.31" wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:936.6-936.37" + attribute \src "ls180.v:980.6-980.37" wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:937.6-937.36" + attribute \src "ls180.v:981.6-981.36" wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:935.12-935.50" + attribute \src "ls180.v:979.12-979.50" wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:939.6-939.38" + attribute \src "ls180.v:983.6-983.38" wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:940.6-940.37" + attribute \src "ls180.v:984.6-984.37" wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:938.12-938.51" + attribute \src "ls180.v:982.12-982.51" wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:922.11-922.35" + attribute \src "ls180.v:966.11-966.35" wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:934.12-934.36" + attribute \src "ls180.v:978.12-978.36" wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:924.11-924.36" + attribute \src "ls180.v:968.11-968.36" wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:931.12-931.40" + attribute \src "ls180.v:975.12-975.40" wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:932.12-932.42" + attribute \src "ls180.v:976.12-976.42" wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:933.6-933.33" + attribute \src "ls180.v:977.6-977.33" wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:914.6-914.26" + attribute \src "ls180.v:958.6-958.26" wire \main_uart_tx_fifo_re - attribute \src "ls180.v:915.5-915.31" + attribute \src "ls180.v:959.5-959.31" wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:923.5-923.30" + attribute \src "ls180.v:967.5-967.30" wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:906.5-906.33" + attribute \src "ls180.v:950.5-950.33" wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:907.5-907.32" + attribute \src "ls180.v:951.5-951.32" wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:908.12-908.47" + attribute \src "ls180.v:952.12-952.47" wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:905.6-905.34" + attribute \src "ls180.v:949.6-949.34" wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:904.6-904.34" + attribute \src "ls180.v:948.6-948.34" wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:911.6-911.36" + attribute \src "ls180.v:955.6-955.36" wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:912.6-912.35" + attribute \src "ls180.v:956.6-956.35" wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:913.12-913.49" + attribute \src "ls180.v:957.12-957.49" wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:910.6-910.36" + attribute \src "ls180.v:954.6-954.36" wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:909.6-909.36" + attribute \src "ls180.v:953.6-953.36" wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:920.12-920.42" + attribute \src "ls180.v:964.12-964.42" wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:921.12-921.43" + attribute \src "ls180.v:965.12-965.43" wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:918.6-918.35" + attribute \src "ls180.v:962.6-962.35" wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:919.6-919.41" + attribute \src "ls180.v:963.6-963.41" wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:916.6-916.35" + attribute \src "ls180.v:960.6-960.35" wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:917.6-917.41" + attribute \src "ls180.v:961.6-961.41" wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:926.11-926.39" + attribute \src "ls180.v:970.11-970.39" wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:927.12-927.42" + attribute \src "ls180.v:971.12-971.42" wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:929.12-929.42" + attribute \src "ls180.v:973.12-973.42" wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:928.6-928.33" + attribute \src "ls180.v:972.6-972.33" wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:874.5-874.29" + attribute \src "ls180.v:918.5-918.29" wire \main_uart_tx_old_trigger - attribute \src "ls180.v:871.5-871.25" + attribute \src "ls180.v:915.5-915.25" wire \main_uart_tx_pending - attribute \src "ls180.v:870.6-870.25" + attribute \src "ls180.v:914.6-914.25" wire \main_uart_tx_status - attribute \src "ls180.v:872.6-872.26" + attribute \src "ls180.v:916.6-916.26" wire \main_uart_tx_trigger - attribute \src "ls180.v:890.6-890.30" + attribute \src "ls180.v:934.6-934.30" wire \main_uart_txempty_status - attribute \src "ls180.v:891.6-891.26" + attribute \src "ls180.v:935.6-935.26" wire \main_uart_txempty_we - attribute \src "ls180.v:865.6-865.29" + attribute \src "ls180.v:909.6-909.29" wire \main_uart_txfull_status - attribute \src "ls180.v:866.6-866.25" + attribute \src "ls180.v:910.6-910.25" wire \main_uart_txfull_we - attribute \src "ls180.v:896.6-896.31" + attribute \src "ls180.v:940.6-940.31" wire \main_uart_uart_sink_first - attribute \src "ls180.v:897.6-897.30" + attribute \src "ls180.v:941.6-941.30" wire \main_uart_uart_sink_last - attribute \src "ls180.v:898.12-898.44" + attribute \src "ls180.v:942.12-942.44" wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:895.6-895.31" + attribute \src "ls180.v:939.6-939.31" wire \main_uart_uart_sink_ready - attribute \src "ls180.v:894.6-894.31" + attribute \src "ls180.v:938.6-938.31" wire \main_uart_uart_sink_valid - attribute \src "ls180.v:901.6-901.33" + attribute \src "ls180.v:945.6-945.33" wire \main_uart_uart_source_first - attribute \src "ls180.v:902.6-902.32" + attribute \src "ls180.v:946.6-946.32" wire \main_uart_uart_source_last - attribute \src "ls180.v:903.12-903.46" + attribute \src "ls180.v:947.12-947.46" wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:900.6-900.33" + attribute \src "ls180.v:944.6-944.33" wire \main_uart_uart_source_ready - attribute \src "ls180.v:899.6-899.33" + attribute \src "ls180.v:943.6-943.33" wire \main_uart_uart_source_valid - attribute \src "ls180.v:815.5-815.22" + attribute \src "ls180.v:847.5-847.22" wire \main_wb_sdram_ack - attribute \src "ls180.v:809.13-809.30" + attribute \src "ls180.v:841.12-841.29" wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:818.12-818.29" - wire width 2 \main_wb_sdram_bte - attribute \src "ls180.v:817.12-817.29" - wire width 3 \main_wb_sdram_cti - attribute \src "ls180.v:813.6-813.23" + attribute \src "ls180.v:845.5-845.22" wire \main_wb_sdram_cyc - attribute \src "ls180.v:811.13-811.32" + attribute \src "ls180.v:843.13-843.32" wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:810.13-810.32" + attribute \src "ls180.v:842.12-842.31" wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:819.5-819.22" - wire \main_wb_sdram_err - attribute \src "ls180.v:812.12-812.29" + attribute \src "ls180.v:844.11-844.28" wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:814.6-814.23" + attribute \src "ls180.v:846.5-846.22" wire \main_wb_sdram_stb - attribute \src "ls180.v:816.6-816.22" + attribute \src "ls180.v:848.5-848.21" wire \main_wb_sdram_we - attribute \src "ls180.v:833.5-833.24" + attribute \src "ls180.v:877.5-877.24" wire \main_wdata_consumed - attribute \src "ls180.v:10042.11-10042.17" - wire width 7 \memadr - attribute \src "ls180.v:10062.12-10062.18" + attribute \src "ls180.v:10206.11-10206.17" + wire width 9 \memadr + attribute \src "ls180.v:10234.11-10234.19" + wire width 9 \memadr_1 + attribute \src "ls180.v:10262.11-10262.19" + wire width 9 \memadr_2 + attribute \src "ls180.v:10290.11-10290.19" + wire width 9 \memadr_3 + attribute \src "ls180.v:10318.12-10318.18" wire width 25 \memdat - attribute \src "ls180.v:10076.12-10076.20" + attribute \src "ls180.v:10332.12-10332.20" wire width 25 \memdat_1 - attribute \src "ls180.v:10090.12-10090.20" + attribute \src "ls180.v:10346.12-10346.20" wire width 25 \memdat_2 - attribute \src "ls180.v:10104.12-10104.20" + attribute \src "ls180.v:10360.12-10360.20" wire width 25 \memdat_3 - attribute \src "ls180.v:10118.11-10118.19" + attribute \src "ls180.v:10374.11-10374.19" wire width 10 \memdat_4 - attribute \src "ls180.v:10119.11-10119.19" + attribute \src "ls180.v:10375.11-10375.19" wire width 10 \memdat_5 - attribute \src "ls180.v:10135.11-10135.19" + attribute \src "ls180.v:10391.11-10391.19" wire width 10 \memdat_6 - attribute \src "ls180.v:10136.11-10136.19" + attribute \src "ls180.v:10392.11-10392.19" wire width 10 \memdat_7 - attribute \src "ls180.v:10152.11-10152.19" + attribute \src "ls180.v:10408.11-10408.19" wire width 10 \memdat_8 - attribute \src "ls180.v:10166.11-10166.19" + attribute \src "ls180.v:10422.11-10422.19" wire width 10 \memdat_9 attribute \src "ls180.v:52.20-52.22" wire width 24 input 48 \nc - attribute \src "ls180.v:247.6-247.13" + attribute \src "ls180.v:279.6-279.13" wire \por_clk - attribute \src "ls180.v:24.19-24.22" - wire width 2 output 20 \pwm - attribute \src "ls180.v:141.12-141.17" + attribute \src "ls180.v:34.19-34.22" + wire width 2 output 30 \pwm + attribute \src "ls180.v:151.12-151.17" wire width 2 \pwm_1 - attribute \src "ls180.v:17.13-17.23" - wire output 13 \sdcard_clk - attribute \src "ls180.v:18.13-18.25" - wire input 14 \sdcard_cmd_i - attribute \src "ls180.v:19.13-19.25" - wire output 15 \sdcard_cmd_o - attribute \src "ls180.v:20.13-20.26" - wire output 16 \sdcard_cmd_oe - attribute \src "ls180.v:21.19-21.32" - wire width 4 input 17 \sdcard_data_i - attribute \src "ls180.v:22.19-22.32" - wire width 4 output 18 \sdcard_data_o - attribute \src "ls180.v:23.13-23.27" - wire output 19 \sdcard_data_oe - attribute \src "ls180.v:5.20-5.27" - wire width 13 output 1 \sdram_a - attribute \src "ls180.v:14.19-14.27" - wire width 2 output 10 \sdram_ba - attribute \src "ls180.v:11.13-11.24" - wire output 7 \sdram_cas_n - attribute \src "ls180.v:13.13-13.22" - wire output 9 \sdram_cke - attribute \src "ls180.v:16.13-16.24" - wire output 12 \sdram_clock - attribute \src "ls180.v:136.6-136.19" + attribute \src "ls180.v:14.13-14.23" + wire output 10 \sdcard_clk + attribute \src "ls180.v:15.13-15.25" + wire input 11 \sdcard_cmd_i + attribute \src "ls180.v:16.13-16.25" + wire output 12 \sdcard_cmd_o + attribute \src "ls180.v:17.13-17.26" + wire output 13 \sdcard_cmd_oe + attribute \src "ls180.v:18.19-18.32" + wire width 4 input 14 \sdcard_data_i + attribute \src "ls180.v:19.19-19.32" + wire width 4 output 15 \sdcard_data_o + attribute \src "ls180.v:20.13-20.27" + wire output 16 \sdcard_data_oe + attribute \src "ls180.v:21.20-21.27" + wire width 13 output 17 \sdram_a + attribute \src "ls180.v:30.19-30.27" + wire width 2 output 26 \sdram_ba + attribute \src "ls180.v:27.13-27.24" + wire output 23 \sdram_cas_n + attribute \src "ls180.v:29.13-29.22" + wire output 25 \sdram_cke + attribute \src "ls180.v:32.13-32.24" + wire output 28 \sdram_clock + attribute \src "ls180.v:149.6-149.19" wire \sdram_clock_1 - attribute \src "ls180.v:12.13-12.23" - wire output 8 \sdram_cs_n - attribute \src "ls180.v:15.19-15.27" - wire width 2 output 11 \sdram_dm - attribute \src "ls180.v:6.20-6.30" - wire width 16 input 2 \sdram_dq_i - attribute \src "ls180.v:7.20-7.30" - wire width 16 output 3 \sdram_dq_o - attribute \src "ls180.v:8.13-8.24" - wire output 4 \sdram_dq_oe - attribute \src "ls180.v:10.13-10.24" - wire output 6 \sdram_ras_n - attribute \src "ls180.v:9.13-9.23" - wire output 5 \sdram_we_n - attribute \src "ls180.v:2643.6-2643.15" + attribute \src "ls180.v:28.13-28.23" + wire output 24 \sdram_cs_n + attribute \src "ls180.v:31.19-31.27" + wire width 2 output 27 \sdram_dm + attribute \src "ls180.v:22.20-22.30" + wire width 16 input 18 \sdram_dq_i + attribute \src "ls180.v:23.20-23.30" + wire width 16 output 19 \sdram_dq_o + attribute \src "ls180.v:24.13-24.24" + wire output 20 \sdram_dq_oe + attribute \src "ls180.v:26.13-26.24" + wire output 22 \sdram_ras_n + attribute \src "ls180.v:25.13-25.23" + wire output 21 \sdram_we_n + attribute \src "ls180.v:2695.6-2695.15" wire \sdrio_clk - attribute \src "ls180.v:2644.6-2644.17" + attribute \src "ls180.v:2696.6-2696.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2653.6-2653.18" + attribute \src "ls180.v:2705.6-2705.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2654.6-2654.18" + attribute \src "ls180.v:2706.6-2706.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2655.6-2655.18" + attribute \src "ls180.v:2707.6-2707.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2656.6-2656.18" + attribute \src "ls180.v:2708.6-2708.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2657.6-2657.18" + attribute \src "ls180.v:2709.6-2709.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2658.6-2658.18" + attribute \src "ls180.v:2710.6-2710.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2659.6-2659.18" + attribute \src "ls180.v:2711.6-2711.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2660.6-2660.18" + attribute \src "ls180.v:2712.6-2712.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2661.6-2661.18" + attribute \src "ls180.v:2713.6-2713.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2662.6-2662.18" + attribute \src "ls180.v:2714.6-2714.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2645.6-2645.17" + attribute \src "ls180.v:2697.6-2697.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2663.6-2663.18" + attribute \src "ls180.v:2715.6-2715.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2664.6-2664.18" + attribute \src "ls180.v:2716.6-2716.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2665.6-2665.18" + attribute \src "ls180.v:2717.6-2717.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2666.6-2666.18" + attribute \src "ls180.v:2718.6-2718.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2667.6-2667.18" + attribute \src "ls180.v:2719.6-2719.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2668.6-2668.18" + attribute \src "ls180.v:2720.6-2720.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2669.6-2669.18" + attribute \src "ls180.v:2721.6-2721.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2670.6-2670.18" + attribute \src "ls180.v:2722.6-2722.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2671.6-2671.18" + attribute \src "ls180.v:2723.6-2723.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2672.6-2672.18" + attribute \src "ls180.v:2724.6-2724.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2646.6-2646.17" + attribute \src "ls180.v:2698.6-2698.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2673.6-2673.18" + attribute \src "ls180.v:2725.6-2725.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2674.6-2674.18" + attribute \src "ls180.v:2726.6-2726.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2675.6-2675.18" + attribute \src "ls180.v:2727.6-2727.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2676.6-2676.18" + attribute \src "ls180.v:2728.6-2728.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2677.6-2677.18" + attribute \src "ls180.v:2729.6-2729.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2678.6-2678.18" + attribute \src "ls180.v:2730.6-2730.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2679.6-2679.18" + attribute \src "ls180.v:2731.6-2731.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2680.6-2680.18" + attribute \src "ls180.v:2732.6-2732.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2681.6-2681.18" + attribute \src "ls180.v:2733.6-2733.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2682.6-2682.18" + attribute \src "ls180.v:2734.6-2734.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2647.6-2647.17" + attribute \src "ls180.v:2699.6-2699.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2683.6-2683.18" + attribute \src "ls180.v:2735.6-2735.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2684.6-2684.18" + attribute \src "ls180.v:2736.6-2736.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2685.6-2685.18" + attribute \src "ls180.v:2737.6-2737.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2686.6-2686.18" + attribute \src "ls180.v:2738.6-2738.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2687.6-2687.18" + attribute \src "ls180.v:2739.6-2739.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2688.6-2688.18" + attribute \src "ls180.v:2740.6-2740.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2689.6-2689.18" + attribute \src "ls180.v:2741.6-2741.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2690.6-2690.18" + attribute \src "ls180.v:2742.6-2742.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2691.6-2691.18" + attribute \src "ls180.v:2743.6-2743.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2692.6-2692.18" + attribute \src "ls180.v:2744.6-2744.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2648.6-2648.17" + attribute \src "ls180.v:2700.6-2700.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2693.6-2693.18" + attribute \src "ls180.v:2745.6-2745.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2694.6-2694.18" + attribute \src "ls180.v:2746.6-2746.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2695.6-2695.18" + attribute \src "ls180.v:2747.6-2747.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2696.6-2696.18" + attribute \src "ls180.v:2748.6-2748.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2697.6-2697.18" + attribute \src "ls180.v:2749.6-2749.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2698.6-2698.18" + attribute \src "ls180.v:2750.6-2750.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2733.6-2733.18" + attribute \src "ls180.v:2785.6-2785.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2734.6-2734.18" + attribute \src "ls180.v:2786.6-2786.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2735.6-2735.18" + attribute \src "ls180.v:2787.6-2787.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2736.6-2736.18" + attribute \src "ls180.v:2788.6-2788.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2649.6-2649.17" + attribute \src "ls180.v:2701.6-2701.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2737.6-2737.18" + attribute \src "ls180.v:2789.6-2789.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2738.6-2738.18" + attribute \src "ls180.v:2790.6-2790.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2739.6-2739.18" + attribute \src "ls180.v:2791.6-2791.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2740.6-2740.18" + attribute \src "ls180.v:2792.6-2792.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2741.6-2741.18" + attribute \src "ls180.v:2793.6-2793.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2742.6-2742.18" + attribute \src "ls180.v:2794.6-2794.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2743.6-2743.18" + attribute \src "ls180.v:2795.6-2795.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2744.6-2744.18" + attribute \src "ls180.v:2796.6-2796.18" wire \sdrio_clk_67 - attribute \src "ls180.v:2745.6-2745.18" + attribute \src "ls180.v:2797.6-2797.18" wire \sdrio_clk_68 - attribute \src "ls180.v:2650.6-2650.17" + attribute \src "ls180.v:2702.6-2702.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2651.6-2651.17" + attribute \src "ls180.v:2703.6-2703.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2652.6-2652.17" + attribute \src "ls180.v:2704.6-2704.17" wire \sdrio_clk_9 - attribute \src "ls180.v:25.13-25.26" - wire output 21 \spimaster_clk - attribute \src "ls180.v:27.13-27.27" - wire output 23 \spimaster_cs_n - attribute \src "ls180.v:28.13-28.27" - wire input 24 \spimaster_miso - attribute \src "ls180.v:26.13-26.27" - wire output 22 \spimaster_mosi - attribute \src "ls180.v:37.13-37.26" - wire output 33 \spisdcard_clk - attribute \src "ls180.v:39.13-39.27" - wire output 35 \spisdcard_cs_n + attribute \src "ls180.v:39.13-39.26" + wire output 35 \spimaster_clk + attribute \src "ls180.v:41.13-41.27" + wire output 37 \spimaster_cs_n + attribute \src "ls180.v:42.13-42.27" + wire input 38 \spimaster_miso attribute \src "ls180.v:40.13-40.27" - wire input 36 \spisdcard_miso - attribute \src "ls180.v:38.13-38.27" - wire output 34 \spisdcard_mosi + wire output 36 \spimaster_mosi + attribute \src "ls180.v:5.13-5.26" + wire output 1 \spisdcard_clk + attribute \src "ls180.v:7.13-7.27" + wire output 3 \spisdcard_cs_n + attribute \src "ls180.v:8.13-8.27" + wire input 4 \spisdcard_miso + attribute \src "ls180.v:6.13-6.27" + wire output 2 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk - attribute \src "ls180.v:245.6-245.15" + attribute \src "ls180.v:277.6-277.15" wire \sys_clk_1 attribute \src "ls180.v:45.19-45.31" wire width 2 input 41 \sys_clksel_i @@ -235083,65 +235807,71 @@ module \ls180 wire output 43 \sys_pll_lck_o attribute \src "ls180.v:44.13-44.20" wire input 40 \sys_rst - attribute \src "ls180.v:246.6-246.15" + attribute \src "ls180.v:278.6-278.15" wire \sys_rst_1 - attribute \src "ls180.v:42.13-42.20" - wire input 38 \uart_rx - attribute \src "ls180.v:41.13-41.20" - wire output 37 \uart_tx - attribute \src "ls180.v:10041.12-10041.15" - memory width 32 size 128 \mem - attribute \src "ls180.v:10061.12-10061.19" + attribute \src "ls180.v:10.13-10.20" + wire input 6 \uart_rx + attribute \src "ls180.v:9.13-9.20" + wire output 5 \uart_tx + attribute \src "ls180.v:10205.12-10205.15" + memory width 64 size 512 \mem + attribute \src "ls180.v:10233.12-10233.17" + memory width 64 size 512 \mem_1 + attribute \src "ls180.v:10261.12-10261.17" + memory width 64 size 512 \mem_2 + attribute \src "ls180.v:10289.12-10289.17" + memory width 64 size 512 \mem_3 + attribute \src "ls180.v:10317.12-10317.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10075.12-10075.21" + attribute \src "ls180.v:10331.12-10331.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10089.12-10089.21" + attribute \src "ls180.v:10345.12-10345.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10103.12-10103.21" + attribute \src "ls180.v:10359.12-10359.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10117.11-10117.20" + attribute \src "ls180.v:10373.11-10373.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10134.11-10134.20" + attribute \src "ls180.v:10390.11-10390.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10151.11-10151.20" + attribute \src "ls180.v:10407.11-10407.20" memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10165.11-10165.20" + attribute \src "ls180.v:10421.11-10421.20" memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2815.68-2815.110" - cell $add $add$ls180.v:2815$22 + attribute \src "ls180.v:2867.56-2867.86" + cell $add $add$ls180.v:2867$50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter + connect \A \main_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2815$22_Y + connect \Y $add$ls180.v:2867$50_Y end - attribute \src "ls180.v:2875.68-2875.110" - cell $add $add$ls180.v:2875$33 + attribute \src "ls180.v:2927.56-2927.86" + cell $add $add$ls180.v:2927$61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter + connect \A \main_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2875$33_Y + connect \Y $add$ls180.v:2927$61_Y end - attribute \src "ls180.v:2935.68-2935.110" - cell $add $add$ls180.v:2935$44 + attribute \src "ls180.v:2987.59-2987.92" + cell $add $add$ls180.v:2987$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter + connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $add$ls180.v:2935$44_Y + connect \Y $add$ls180.v:2987$72_Y end - attribute \src "ls180.v:4068.54-4068.83" - cell $add $add$ls180.v:4068$537 + attribute \src "ls180.v:4166.54-4166.83" + cell $add $add$ls180.v:4166$652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235149,10 +235879,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4068$537_Y + connect \Y $add$ls180.v:4166$652_Y end - attribute \src "ls180.v:4168.36-4168.89" - cell $add $add$ls180.v:4168$583 + attribute \src "ls180.v:4266.36-4266.89" + cell $add $add$ls180.v:4266$698 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235160,10 +235890,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4168$583_Y + connect \Y $add$ls180.v:4266$698_Y end - attribute \src "ls180.v:4198.36-4198.89" - cell $add $add$ls180.v:4198$594 + attribute \src "ls180.v:4296.36-4296.89" + cell $add $add$ls180.v:4296$709 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235171,10 +235901,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4198$594_Y + connect \Y $add$ls180.v:4296$709_Y end - attribute \src "ls180.v:4253.54-4253.83" - cell $add $add$ls180.v:4253$607 + attribute \src "ls180.v:4351.54-4351.83" + cell $add $add$ls180.v:4351$722 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235182,10 +235912,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster27_count connect \B 1'1 - connect \Y $add$ls180.v:4253$607_Y + connect \Y $add$ls180.v:4351$722_Y end - attribute \src "ls180.v:4312.52-4312.79" - cell $add $add$ls180.v:4312$615 + attribute \src "ls180.v:4410.52-4410.79" + cell $add $add$ls180.v:4410$730 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235193,10 +235923,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_count connect \B 1'1 - connect \Y $add$ls180.v:4312$615_Y + connect \Y $add$ls180.v:4410$730_Y end - attribute \src "ls180.v:4416.58-4416.86" - cell $add $add$ls180.v:4416$643 + attribute \src "ls180.v:4514.58-4514.86" + cell $add $add$ls180.v:4514$758 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235204,10 +235934,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_init_count connect \B 1'1 - connect \Y $add$ls180.v:4416$643_Y + connect \Y $add$ls180.v:4514$758_Y end - attribute \src "ls180.v:4473.58-4473.86" - cell $add $add$ls180.v:4473$646 + attribute \src "ls180.v:4571.58-4571.86" + cell $add $add$ls180.v:4571$761 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235215,10 +235945,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4473$646_Y + connect \Y $add$ls180.v:4571$761_Y end - attribute \src "ls180.v:4490.58-4490.86" - cell $add $add$ls180.v:4490$648 + attribute \src "ls180.v:4588.58-4588.86" + cell $add $add$ls180.v:4588$763 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235226,10 +235956,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4490$648_Y + connect \Y $add$ls180.v:4588$763_Y end - attribute \src "ls180.v:4583.59-4583.87" - cell $add $add$ls180.v:4583$665 + attribute \src "ls180.v:4681.59-4681.87" + cell $add $add$ls180.v:4681$780 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235237,10 +235967,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4583$665_Y + connect \Y $add$ls180.v:4681$780_Y end - attribute \src "ls180.v:4608.59-4608.87" - cell $add $add$ls180.v:4608$668 + attribute \src "ls180.v:4706.59-4706.87" + cell $add $add$ls180.v:4706$783 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235248,10 +235978,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4608$668_Y + connect \Y $add$ls180.v:4706$783_Y end - attribute \src "ls180.v:4730.53-4730.82" - cell $add $add$ls180.v:4730$685 + attribute \src "ls180.v:4828.53-4828.82" + cell $add $add$ls180.v:4828$800 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235259,10 +235989,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $add$ls180.v:4730$685_Y + connect \Y $add$ls180.v:4828$800_Y end - attribute \src "ls180.v:4841.65-4841.114" - cell $add $add$ls180.v:4841$699 + attribute \src "ls180.v:4939.65-4939.114" + cell $add $add$ls180.v:4939$814 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235270,10 +236000,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_sink_payload_block_length connect \B 4'1000 - connect \Y $add$ls180.v:4841$699_Y + connect \Y $add$ls180.v:4939$814_Y end - attribute \src "ls180.v:4846.62-4846.91" - cell $add $add$ls180.v:4846$702 + attribute \src "ls180.v:4944.62-4944.91" + cell $add $add$ls180.v:4944$817 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235281,10 +236011,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4846$702_Y + connect \Y $add$ls180.v:4944$817_Y end - attribute \src "ls180.v:4872.61-4872.90" - cell $add $add$ls180.v:4872$705 + attribute \src "ls180.v:4970.61-4970.90" + cell $add $add$ls180.v:4970$820 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235292,10 +236022,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4872$705_Y + connect \Y $add$ls180.v:4970$820_Y end - attribute \src "ls180.v:5076.80-5076.117" - cell $add $add$ls180.v:5076$890 + attribute \src "ls180.v:5174.80-5174.117" + cell $add $add$ls180.v:5174$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235303,10 +236033,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_crc16_inserter_cnt connect \B 1'1 - connect \Y $add$ls180.v:5076$890_Y + connect \Y $add$ls180.v:5174$1005_Y end - attribute \src "ls180.v:5270.54-5270.82" - cell $add $add$ls180.v:5270$965 + attribute \src "ls180.v:5368.54-5368.82" + cell $add $add$ls180.v:5368$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235314,10 +236044,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_cmd_count connect \B 1'1 - connect \Y $add$ls180.v:5270$965_Y + connect \Y $add$ls180.v:5368$1080_Y end - attribute \src "ls180.v:5322.55-5322.84" - cell $add $add$ls180.v:5322$975 + attribute \src "ls180.v:5420.55-5420.84" + cell $add $add$ls180.v:5420$1090 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235325,10 +236055,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5322$975_Y + connect \Y $add$ls180.v:5420$1090_Y end - attribute \src "ls180.v:5348.57-5348.86" - cell $add $add$ls180.v:5348$983 + attribute \src "ls180.v:5446.57-5446.86" + cell $add $add$ls180.v:5446$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235336,10 +236066,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5348$983_Y + connect \Y $add$ls180.v:5446$1098_Y end - attribute \src "ls180.v:5469.51-5469.134" - cell $add $add$ls180.v:5469$999 + attribute \src "ls180.v:5567.51-5567.134" + cell $add $add$ls180.v:5567$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235347,10 +236077,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_base connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5469$999_Y + connect \Y $add$ls180.v:5567$1114_Y end - attribute \src "ls180.v:5472.77-5472.125" - cell $add $add$ls180.v:5472$1001 + attribute \src "ls180.v:5570.77-5570.125" + cell $add $add$ls180.v:5570$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235358,10 +236088,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_offset connect \B 1'1 - connect \Y $add$ls180.v:5472$1001_Y + connect \Y $add$ls180.v:5570$1116_Y end - attribute \src "ls180.v:5565.50-5565.105" - cell $add $add$ls180.v:5565$1010 + attribute \src "ls180.v:5663.50-5663.105" + cell $add $add$ls180.v:5663$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235369,10 +236099,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_base connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5565$1010_Y + connect \Y $add$ls180.v:5663$1125_Y end - attribute \src "ls180.v:5567.77-5567.111" - cell $add $add$ls180.v:5567$1011 + attribute \src "ls180.v:5665.77-5665.111" + cell $add $add$ls180.v:5665$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235380,10 +236110,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_offset connect \B 1'1 - connect \Y $add$ls180.v:5567$1011_Y + connect \Y $add$ls180.v:5665$1126_Y end - attribute \src "ls180.v:7487.36-7487.70" - cell $add $add$ls180.v:7487$2403 + attribute \src "ls180.v:7624.36-7624.70" + cell $add $add$ls180.v:7624$2536 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235391,10 +236121,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7487$2403_Y + connect \Y $add$ls180.v:7624$2536_Y end - attribute \src "ls180.v:7572.37-7572.72" - cell $add $add$ls180.v:7572$2424 + attribute \src "ls180.v:7721.37-7721.72" + cell $add $add$ls180.v:7721$2566 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235402,10 +236132,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7572$2424_Y + connect \Y $add$ls180.v:7721$2566_Y end - attribute \src "ls180.v:7589.60-7589.119" - cell $add $add$ls180.v:7589$2428 + attribute \src "ls180.v:7738.60-7738.119" + cell $add $add$ls180.v:7738$2570 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235413,10 +236143,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7589$2428_Y + connect \Y $add$ls180.v:7738$2570_Y end - attribute \src "ls180.v:7592.60-7592.119" - cell $add $add$ls180.v:7592$2429 + attribute \src "ls180.v:7741.60-7741.119" + cell $add $add$ls180.v:7741$2571 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235424,10 +236154,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7592$2429_Y + connect \Y $add$ls180.v:7741$2571_Y end - attribute \src "ls180.v:7596.59-7596.116" - cell $add $add$ls180.v:7596$2434 + attribute \src "ls180.v:7745.59-7745.116" + cell $add $add$ls180.v:7745$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235435,10 +236165,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7596$2434_Y + connect \Y $add$ls180.v:7745$2576_Y end - attribute \src "ls180.v:7635.60-7635.119" - cell $add $add$ls180.v:7635$2444 + attribute \src "ls180.v:7784.60-7784.119" + cell $add $add$ls180.v:7784$2586 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235446,10 +236176,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7635$2444_Y + connect \Y $add$ls180.v:7784$2586_Y end - attribute \src "ls180.v:7638.60-7638.119" - cell $add $add$ls180.v:7638$2445 + attribute \src "ls180.v:7787.60-7787.119" + cell $add $add$ls180.v:7787$2587 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235457,10 +236187,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7638$2445_Y + connect \Y $add$ls180.v:7787$2587_Y end - attribute \src "ls180.v:7642.59-7642.116" - cell $add $add$ls180.v:7642$2450 + attribute \src "ls180.v:7791.59-7791.116" + cell $add $add$ls180.v:7791$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235468,10 +236198,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7642$2450_Y + connect \Y $add$ls180.v:7791$2592_Y end - attribute \src "ls180.v:7681.60-7681.119" - cell $add $add$ls180.v:7681$2460 + attribute \src "ls180.v:7830.60-7830.119" + cell $add $add$ls180.v:7830$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235479,10 +236209,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7681$2460_Y + connect \Y $add$ls180.v:7830$2602_Y end - attribute \src "ls180.v:7684.60-7684.119" - cell $add $add$ls180.v:7684$2461 + attribute \src "ls180.v:7833.60-7833.119" + cell $add $add$ls180.v:7833$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235490,10 +236220,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7684$2461_Y + connect \Y $add$ls180.v:7833$2603_Y end - attribute \src "ls180.v:7688.59-7688.116" - cell $add $add$ls180.v:7688$2466 + attribute \src "ls180.v:7837.59-7837.116" + cell $add $add$ls180.v:7837$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235501,10 +236231,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7688$2466_Y + connect \Y $add$ls180.v:7837$2608_Y end - attribute \src "ls180.v:7727.60-7727.119" - cell $add $add$ls180.v:7727$2476 + attribute \src "ls180.v:7876.60-7876.119" + cell $add $add$ls180.v:7876$2618 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235512,10 +236242,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7727$2476_Y + connect \Y $add$ls180.v:7876$2618_Y end - attribute \src "ls180.v:7730.60-7730.119" - cell $add $add$ls180.v:7730$2477 + attribute \src "ls180.v:7879.60-7879.119" + cell $add $add$ls180.v:7879$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235523,10 +236253,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7730$2477_Y + connect \Y $add$ls180.v:7879$2619_Y end - attribute \src "ls180.v:7734.59-7734.116" - cell $add $add$ls180.v:7734$2482 + attribute \src "ls180.v:7883.59-7883.116" + cell $add $add$ls180.v:7883$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235534,10 +236264,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7734$2482_Y + connect \Y $add$ls180.v:7883$2624_Y end - attribute \src "ls180.v:7964.34-7964.66" - cell $add $add$ls180.v:7964$2536 + attribute \src "ls180.v:8113.34-8113.66" + cell $add $add$ls180.v:8113$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235545,10 +236275,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:7964$2536_Y + connect \Y $add$ls180.v:8113$2678_Y end - attribute \src "ls180.v:7980.73-7980.131" - cell $add $add$ls180.v:7980$2539 + attribute \src "ls180.v:8129.73-8129.131" + cell $add $add$ls180.v:8129$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235556,10 +236286,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_tx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:7980$2539_Y + connect \Y $add$ls180.v:8129$2681_Y end - attribute \src "ls180.v:7993.34-7993.66" - cell $add $add$ls180.v:7993$2543 + attribute \src "ls180.v:8142.34-8142.66" + cell $add $add$ls180.v:8142$2685 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235567,10 +236297,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:7993$2543_Y + connect \Y $add$ls180.v:8142$2685_Y end - attribute \src "ls180.v:8012.73-8012.131" - cell $add $add$ls180.v:8012$2546 + attribute \src "ls180.v:8161.73-8161.131" + cell $add $add$ls180.v:8161$2688 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235578,10 +236308,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_rx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8012$2546_Y + connect \Y $add$ls180.v:8161$2688_Y end - attribute \src "ls180.v:8038.33-8038.65" - cell $add $add$ls180.v:8038$2554 + attribute \src "ls180.v:8187.33-8187.65" + cell $add $add$ls180.v:8187$2696 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235589,10 +236319,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8038$2554_Y + connect \Y $add$ls180.v:8187$2696_Y end - attribute \src "ls180.v:8041.33-8041.65" - cell $add $add$ls180.v:8041$2555 + attribute \src "ls180.v:8190.33-8190.65" + cell $add $add$ls180.v:8190$2697 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235600,10 +236330,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8041$2555_Y + connect \Y $add$ls180.v:8190$2697_Y end - attribute \src "ls180.v:8045.33-8045.64" - cell $add $add$ls180.v:8045$2560 + attribute \src "ls180.v:8194.33-8194.64" + cell $add $add$ls180.v:8194$2702 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235611,10 +236341,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8045$2560_Y + connect \Y $add$ls180.v:8194$2702_Y end - attribute \src "ls180.v:8060.33-8060.65" - cell $add $add$ls180.v:8060$2565 + attribute \src "ls180.v:8209.33-8209.65" + cell $add $add$ls180.v:8209$2707 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235622,10 +236352,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8060$2565_Y + connect \Y $add$ls180.v:8209$2707_Y end - attribute \src "ls180.v:8063.33-8063.65" - cell $add $add$ls180.v:8063$2566 + attribute \src "ls180.v:8212.33-8212.65" + cell $add $add$ls180.v:8212$2708 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235633,10 +236363,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8063$2566_Y + connect \Y $add$ls180.v:8212$2708_Y end - attribute \src "ls180.v:8067.33-8067.64" - cell $add $add$ls180.v:8067$2571 + attribute \src "ls180.v:8216.33-8216.64" + cell $add $add$ls180.v:8216$2713 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235644,10 +236374,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8067$2571_Y + connect \Y $add$ls180.v:8216$2713_Y end - attribute \src "ls180.v:8088.35-8088.70" - cell $add $add$ls180.v:8088$2573 + attribute \src "ls180.v:8237.35-8237.70" + cell $add $add$ls180.v:8237$2715 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -235655,10 +236385,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster30_clk_divider connect \B 1'1 - connect \Y $add$ls180.v:8088$2573_Y + connect \Y $add$ls180.v:8237$2715_Y end - attribute \src "ls180.v:8123.34-8123.68" - cell $add $add$ls180.v:8123$2578 + attribute \src "ls180.v:8272.34-8272.68" + cell $add $add$ls180.v:8272$2720 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -235666,10 +236396,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8123$2578_Y + connect \Y $add$ls180.v:8272$2720_Y end - attribute \src "ls180.v:8159.25-8159.49" - cell $add $add$ls180.v:8159$2583 + attribute \src "ls180.v:8308.25-8308.49" + cell $add $add$ls180.v:8308$2725 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235677,10 +236407,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8159$2583_Y + connect \Y $add$ls180.v:8308$2725_Y end - attribute \src "ls180.v:8173.25-8173.49" - cell $add $add$ls180.v:8173$2587 + attribute \src "ls180.v:8322.25-8322.49" + cell $add $add$ls180.v:8322$2729 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235688,10 +236418,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8173$2587_Y + connect \Y $add$ls180.v:8322$2729_Y end - attribute \src "ls180.v:8187.31-8187.61" - cell $add $add$ls180.v:8187$2592 + attribute \src "ls180.v:8336.31-8336.61" + cell $add $add$ls180.v:8336$2734 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -235699,10 +236429,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8187$2592_Y + connect \Y $add$ls180.v:8336$2734_Y end - attribute \src "ls180.v:8210.45-8210.88" - cell $add $add$ls180.v:8210$2596 + attribute \src "ls180.v:8359.45-8359.88" + cell $add $add$ls180.v:8359$2738 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235710,10 +236440,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8210$2596_Y + connect \Y $add$ls180.v:8359$2738_Y end - attribute \src "ls180.v:8256.71-8256.114" - cell $add $add$ls180.v:8256$2602 + attribute \src "ls180.v:8405.71-8405.114" + cell $add $add$ls180.v:8405$2744 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235721,10 +236451,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8256$2602_Y + connect \Y $add$ls180.v:8405$2744_Y end - attribute \src "ls180.v:8291.46-8291.90" - cell $add $add$ls180.v:8291$2608 + attribute \src "ls180.v:8440.46-8440.90" + cell $add $add$ls180.v:8440$2750 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235732,10 +236462,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8291$2608_Y + connect \Y $add$ls180.v:8440$2750_Y end - attribute \src "ls180.v:8337.72-8337.116" - cell $add $add$ls180.v:8337$2614 + attribute \src "ls180.v:8486.72-8486.116" + cell $add $add$ls180.v:8486$2756 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235743,10 +236473,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8337$2614_Y + connect \Y $add$ls180.v:8486$2756_Y end - attribute \src "ls180.v:8370.47-8370.92" - cell $add $add$ls180.v:8370$2620 + attribute \src "ls180.v:8519.47-8519.92" + cell $add $add$ls180.v:8519$2762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235754,10 +236484,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8370$2620_Y + connect \Y $add$ls180.v:8519$2762_Y end - attribute \src "ls180.v:8398.73-8398.118" - cell $add $add$ls180.v:8398$2626 + attribute \src "ls180.v:8547.73-8547.118" + cell $add $add$ls180.v:8547$2768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235765,10 +236495,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8398$2626_Y + connect \Y $add$ls180.v:8547$2768_Y end - attribute \src "ls180.v:8510.39-8510.75" - cell $add $add$ls180.v:8510$2639 + attribute \src "ls180.v:8659.39-8659.75" + cell $add $add$ls180.v:8659$2781 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235776,10 +236506,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8510$2639_Y + connect \Y $add$ls180.v:8659$2781_Y end - attribute \src "ls180.v:8571.37-8571.73" - cell $add $add$ls180.v:8571$2643 + attribute \src "ls180.v:8720.37-8720.73" + cell $add $add$ls180.v:8720$2785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235787,10 +236517,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8571$2643_Y + connect \Y $add$ls180.v:8720$2785_Y end - attribute \src "ls180.v:8574.37-8574.73" - cell $add $add$ls180.v:8574$2644 + attribute \src "ls180.v:8723.37-8723.73" + cell $add $add$ls180.v:8723$2786 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235798,10 +236528,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8574$2644_Y + connect \Y $add$ls180.v:8723$2786_Y end - attribute \src "ls180.v:8578.36-8578.70" - cell $add $add$ls180.v:8578$2649 + attribute \src "ls180.v:8727.36-8727.70" + cell $add $add$ls180.v:8727$2791 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -235809,43 +236539,43 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8578$2649_Y + connect \Y $add$ls180.v:8727$2791_Y end - attribute \src "ls180.v:8593.41-8593.80" - cell $add $add$ls180.v:8593$2653 + attribute \src "ls180.v:8742.41-8742.80" + cell $add $add$ls180.v:8742$2795 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 + parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8593$2653_Y + connect \Y $add$ls180.v:8742$2795_Y end - attribute \src "ls180.v:8627.67-8627.106" - cell $add $add$ls180.v:8627$2659 + attribute \src "ls180.v:8788.67-8788.106" + cell $add $add$ls180.v:8788$2801 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 + parameter \Y_WIDTH 4 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8627$2659_Y + connect \Y $add$ls180.v:8788$2801_Y end - attribute \src "ls180.v:8653.39-8653.76" - cell $add $add$ls180.v:8653$2661 + attribute \src "ls180.v:8814.39-8814.76" + cell $add $add$ls180.v:8814$2803 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 + parameter \Y_WIDTH 3 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8653$2661_Y + connect \Y $add$ls180.v:8814$2803_Y end - attribute \src "ls180.v:8657.37-8657.73" - cell $add $add$ls180.v:8657$2665 + attribute \src "ls180.v:8818.37-8818.73" + cell $add $add$ls180.v:8818$2807 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235853,10 +236583,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8657$2665_Y + connect \Y $add$ls180.v:8818$2807_Y end - attribute \src "ls180.v:8660.37-8660.73" - cell $add $add$ls180.v:8660$2666 + attribute \src "ls180.v:8821.37-8821.73" + cell $add $add$ls180.v:8821$2808 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235864,10 +236594,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8660$2666_Y + connect \Y $add$ls180.v:8821$2808_Y end - attribute \src "ls180.v:8664.36-8664.70" - cell $add $add$ls180.v:8664$2671 + attribute \src "ls180.v:8825.36-8825.70" + cell $add $add$ls180.v:8825$2813 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -235875,76 +236605,76 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8664$2671_Y + connect \Y $add$ls180.v:8825$2813_Y end - attribute \src "ls180.v:2809.9-2809.80" - cell $and $and$ls180.v:2809$17 + attribute \src "ls180.v:2861.9-2861.90" + cell $and $and$ls180.v:2861$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2809$17_Y + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2861$45_Y end - attribute \src "ls180.v:2827.9-2827.80" - cell $and $and$ls180.v:2827$24 + attribute \src "ls180.v:2879.9-2879.90" + cell $and $and$ls180.v:2879$52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2827$24_Y + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2879$52_Y end - attribute \src "ls180.v:2869.9-2869.80" - cell $and $and$ls180.v:2869$28 + attribute \src "ls180.v:2921.9-2921.90" + cell $and $and$ls180.v:2921$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2869$28_Y + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2921$56_Y end - attribute \src "ls180.v:2887.9-2887.80" - cell $and $and$ls180.v:2887$35 + attribute \src "ls180.v:2939.9-2939.90" + cell $and $and$ls180.v:2939$63 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2887$35_Y + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2939$63_Y end - attribute \src "ls180.v:2929.9-2929.86" - cell $and $and$ls180.v:2929$39 + attribute \src "ls180.v:2981.9-2981.96" + cell $and $and$ls180.v:2981$67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2929$39_Y + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:2981$67_Y end - attribute \src "ls180.v:2947.9-2947.86" - cell $and $and$ls180.v:2947$46 + attribute \src "ls180.v:2999.9-2999.96" + cell $and $and$ls180.v:2999$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2947$46_Y + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:2999$74_Y end - attribute \src "ls180.v:2957.31-2957.90" - cell $and $and$ls180.v:2957$48 + attribute \src "ls180.v:3009.31-3009.90" + cell $and $and$ls180.v:3009$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235952,32 +236682,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2957$48_Y + connect \Y $and$ls180.v:3009$76_Y end - attribute \src "ls180.v:2957.30-2957.121" - cell $and $and$ls180.v:2957$49 + attribute \src "ls180.v:3009.30-3009.121" + cell $and $and$ls180.v:3009$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2957$48_Y + connect \A $and$ls180.v:3009$76_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2957$49_Y + connect \Y $and$ls180.v:3009$77_Y end - attribute \src "ls180.v:2957.29-2957.156" - cell $and $and$ls180.v:2957$50 + attribute \src "ls180.v:3009.29-3009.156" + cell $and $and$ls180.v:3009$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2957$49_Y + connect \A $and$ls180.v:3009$77_Y connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:2957$50_Y + connect \Y $and$ls180.v:3009$78_Y end - attribute \src "ls180.v:2958.31-2958.90" - cell $and $and$ls180.v:2958$51 + attribute \src "ls180.v:3010.31-3010.90" + cell $and $and$ls180.v:3010$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235985,32 +236715,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2958$51_Y + connect \Y $and$ls180.v:3010$79_Y end - attribute \src "ls180.v:2958.30-2958.121" - cell $and $and$ls180.v:2958$52 + attribute \src "ls180.v:3010.30-3010.121" + cell $and $and$ls180.v:3010$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2958$51_Y + connect \A $and$ls180.v:3010$79_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2958$52_Y + connect \Y $and$ls180.v:3010$80_Y end - attribute \src "ls180.v:2958.29-2958.156" - cell $and $and$ls180.v:2958$53 + attribute \src "ls180.v:3010.29-3010.156" + cell $and $and$ls180.v:3010$81 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2958$52_Y + connect \A $and$ls180.v:3010$80_Y connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:2958$53_Y + connect \Y $and$ls180.v:3010$81_Y end - attribute \src "ls180.v:2959.31-2959.90" - cell $and $and$ls180.v:2959$54 + attribute \src "ls180.v:3011.31-3011.90" + cell $and $and$ls180.v:3011$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236018,32 +236748,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2959$54_Y + connect \Y $and$ls180.v:3011$82_Y end - attribute \src "ls180.v:2959.30-2959.121" - cell $and $and$ls180.v:2959$55 + attribute \src "ls180.v:3011.30-3011.121" + cell $and $and$ls180.v:3011$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2959$54_Y + connect \A $and$ls180.v:3011$82_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2959$55_Y + connect \Y $and$ls180.v:3011$83_Y end - attribute \src "ls180.v:2959.29-2959.156" - cell $and $and$ls180.v:2959$56 + attribute \src "ls180.v:3011.29-3011.156" + cell $and $and$ls180.v:3011$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2959$55_Y + connect \A $and$ls180.v:3011$83_Y connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:2959$56_Y + connect \Y $and$ls180.v:3011$84_Y end - attribute \src "ls180.v:2960.31-2960.90" - cell $and $and$ls180.v:2960$57 + attribute \src "ls180.v:3012.31-3012.90" + cell $and $and$ls180.v:3012$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236051,945 +236781,1869 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2960$57_Y + connect \Y $and$ls180.v:3012$85_Y end - attribute \src "ls180.v:2960.30-2960.121" - cell $and $and$ls180.v:2960$58 + attribute \src "ls180.v:3012.30-3012.121" + cell $and $and$ls180.v:3012$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2960$57_Y + connect \A $and$ls180.v:3012$85_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2960$58_Y + connect \Y $and$ls180.v:3012$86_Y end - attribute \src "ls180.v:2960.29-2960.156" - cell $and $and$ls180.v:2960$59 + attribute \src "ls180.v:3012.29-3012.156" + cell $and $and$ls180.v:3012$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2960$58_Y + connect \A $and$ls180.v:3012$86_Y connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:2960$59_Y + connect \Y $and$ls180.v:3012$87_Y end - attribute \src "ls180.v:2969.7-2969.89" - cell $and $and$ls180.v:2969$62 + attribute \src "ls180.v:3013.31-3013.90" + cell $and $and$ls180.v:3013$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_re - connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:2969$62_Y + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3013$88_Y end - attribute \src "ls180.v:2974.32-2974.111" - cell $and $and$ls180.v:2974$63 + attribute \src "ls180.v:3013.30-3013.121" + cell $and $and$ls180.v:3013$89 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_w - connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:2974$63_Y + connect \A $and$ls180.v:3013$88_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3013$89_Y end - attribute \src "ls180.v:3088.40-3088.99" - cell $and $and$ls180.v:3088$70 + attribute \src "ls180.v:3013.29-3013.156" + cell $and $and$ls180.v:3013$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3088$70_Y + connect \A $and$ls180.v:3013$89_Y + connect \B \main_libresocsim_ram_bus_sel [4] + connect \Y $and$ls180.v:3013$90_Y end - attribute \src "ls180.v:3089.40-3089.99" - cell $and $and$ls180.v:3089$71 + attribute \src "ls180.v:3014.31-3014.90" + cell $and $and$ls180.v:3014$91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3089$71_Y + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3014$91_Y end - attribute \src "ls180.v:3127.38-3127.103" - cell $and $and$ls180.v:3127$77 + attribute \src "ls180.v:3014.30-3014.121" + cell $and $and$ls180.v:3014$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3127$76_Y - connect \Y $and$ls180.v:3127$77_Y + connect \A $and$ls180.v:3014$91_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3014$92_Y end - attribute \src "ls180.v:3181.50-3181.119" - cell $and $and$ls180.v:3181$85 + attribute \src "ls180.v:3014.29-3014.156" + cell $and $and$ls180.v:3014$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3181$85_Y + connect \A $and$ls180.v:3014$92_Y + connect \B \main_libresocsim_ram_bus_sel [5] + connect \Y $and$ls180.v:3014$93_Y end - attribute \src "ls180.v:3181.49-3181.167" - cell $and $and$ls180.v:3181$86 + attribute \src "ls180.v:3015.31-3015.90" + cell $and $and$ls180.v:3015$94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3181$85_Y - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3181$86_Y + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3015$94_Y end - attribute \src "ls180.v:3182.49-3182.118" - cell $and $and$ls180.v:3182$87 + attribute \src "ls180.v:3015.30-3015.121" + cell $and $and$ls180.v:3015$95 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3182$87_Y + connect \A $and$ls180.v:3015$94_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3015$95_Y end - attribute \src "ls180.v:3182.48-3182.154" - cell $and $and$ls180.v:3182$88 + attribute \src "ls180.v:3015.29-3015.156" + cell $and $and$ls180.v:3015$96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3182$87_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3182$88_Y + connect \A $and$ls180.v:3015$95_Y + connect \B \main_libresocsim_ram_bus_sel [6] + connect \Y $and$ls180.v:3015$96_Y end - attribute \src "ls180.v:3183.50-3183.119" - cell $and $and$ls180.v:3183$89 + attribute \src "ls180.v:3016.31-3016.90" + cell $and $and$ls180.v:3016$97 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3183$89_Y + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3016$97_Y end - attribute \src "ls180.v:3183.49-3183.155" - cell $and $and$ls180.v:3183$90 + attribute \src "ls180.v:3016.30-3016.121" + cell $and $and$ls180.v:3016$98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3183$89_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3183$90_Y + connect \A $and$ls180.v:3016$97_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3016$98_Y end - attribute \src "ls180.v:3186.7-3186.114" - cell $and $and$ls180.v:3186$92 + attribute \src "ls180.v:3016.29-3016.156" + cell $and $and$ls180.v:3016$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3186$92_Y + connect \A $and$ls180.v:3016$98_Y + connect \B \main_libresocsim_ram_bus_sel [7] + connect \Y $and$ls180.v:3016$99_Y end - attribute \src "ls180.v:3215.66-3215.246" - cell $and $and$ls180.v:3215$98 + attribute \src "ls180.v:3025.7-3025.89" + cell $and $and$ls180.v:3025$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3215$97_Y - connect \Y $and$ls180.v:3215$98_Y + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:3025$102_Y end - attribute \src "ls180.v:3216.64-3216.187" - cell $and $and$ls180.v:3216$99 + attribute \src "ls180.v:3030.32-3030.111" + cell $and $and$ls180.v:3030$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3216$99_Y + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:3030$103_Y end - attribute \src "ls180.v:3240.9-3240.86" - cell $and $and$ls180.v:3240$105 + attribute \src "ls180.v:3034.25-3034.82" + cell $and $and$ls180.v:3034$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3240$105_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3034$105_Y end - attribute \src "ls180.v:3252.9-3252.86" - cell $and $and$ls180.v:3252$106 + attribute \src "ls180.v:3034.24-3034.112" + cell $and $and$ls180.v:3034$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3252$106_Y + connect \A $and$ls180.v:3034$105_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3034$106_Y end - attribute \src "ls180.v:3302.13-3302.87" - cell $and $and$ls180.v:3302$108 + attribute \src "ls180.v:3034.23-3034.146" + cell $and $and$ls180.v:3034$107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_ready - connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3302$108_Y + connect \A $and$ls180.v:3034$106_Y + connect \B \main_interface0_ram_bus_sel [0] + connect \Y $and$ls180.v:3034$107_Y end - attribute \src "ls180.v:3338.50-3338.119" - cell $and $and$ls180.v:3338$115 + attribute \src "ls180.v:3035.25-3035.82" + cell $and $and$ls180.v:3035$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3338$115_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3035$108_Y end - attribute \src "ls180.v:3338.49-3338.167" - cell $and $and$ls180.v:3338$116 + attribute \src "ls180.v:3035.24-3035.112" + cell $and $and$ls180.v:3035$109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3338$115_Y - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3338$116_Y + connect \A $and$ls180.v:3035$108_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3035$109_Y end - attribute \src "ls180.v:3339.49-3339.118" - cell $and $and$ls180.v:3339$117 + attribute \src "ls180.v:3035.23-3035.146" + cell $and $and$ls180.v:3035$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3339$117_Y + connect \A $and$ls180.v:3035$109_Y + connect \B \main_interface0_ram_bus_sel [1] + connect \Y $and$ls180.v:3035$110_Y end - attribute \src "ls180.v:3339.48-3339.154" - cell $and $and$ls180.v:3339$118 + attribute \src "ls180.v:3036.25-3036.82" + cell $and $and$ls180.v:3036$111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3339$117_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3339$118_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3036$111_Y end - attribute \src "ls180.v:3340.50-3340.119" - cell $and $and$ls180.v:3340$119 + attribute \src "ls180.v:3036.24-3036.112" + cell $and $and$ls180.v:3036$112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3340$119_Y + connect \A $and$ls180.v:3036$111_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3036$112_Y end - attribute \src "ls180.v:3340.49-3340.155" - cell $and $and$ls180.v:3340$120 + attribute \src "ls180.v:3036.23-3036.146" + cell $and $and$ls180.v:3036$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3340$119_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3340$120_Y + connect \A $and$ls180.v:3036$112_Y + connect \B \main_interface0_ram_bus_sel [2] + connect \Y $and$ls180.v:3036$113_Y end - attribute \src "ls180.v:3343.7-3343.114" - cell $and $and$ls180.v:3343$122 + attribute \src "ls180.v:3037.25-3037.82" + cell $and $and$ls180.v:3037$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3343$122_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3037$114_Y end - attribute \src "ls180.v:3372.66-3372.246" - cell $and $and$ls180.v:3372$128 + attribute \src "ls180.v:3037.24-3037.112" + cell $and $and$ls180.v:3037$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3372$127_Y - connect \Y $and$ls180.v:3372$128_Y + connect \A $and$ls180.v:3037$114_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3037$115_Y end - attribute \src "ls180.v:3373.64-3373.187" - cell $and $and$ls180.v:3373$129 + attribute \src "ls180.v:3037.23-3037.146" + cell $and $and$ls180.v:3037$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3373$129_Y + connect \A $and$ls180.v:3037$115_Y + connect \B \main_interface0_ram_bus_sel [3] + connect \Y $and$ls180.v:3037$116_Y end - attribute \src "ls180.v:3397.9-3397.86" - cell $and $and$ls180.v:3397$135 + attribute \src "ls180.v:3038.25-3038.82" + cell $and $and$ls180.v:3038$117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3397$135_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3038$117_Y end - attribute \src "ls180.v:3409.9-3409.86" - cell $and $and$ls180.v:3409$136 + attribute \src "ls180.v:3038.24-3038.112" + cell $and $and$ls180.v:3038$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3409$136_Y + connect \A $and$ls180.v:3038$117_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3038$118_Y end - attribute \src "ls180.v:3459.13-3459.87" - cell $and $and$ls180.v:3459$138 + attribute \src "ls180.v:3038.23-3038.146" + cell $and $and$ls180.v:3038$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_ready - connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3459$138_Y + connect \A $and$ls180.v:3038$118_Y + connect \B \main_interface0_ram_bus_sel [4] + connect \Y $and$ls180.v:3038$119_Y end - attribute \src "ls180.v:3495.50-3495.119" - cell $and $and$ls180.v:3495$145 + attribute \src "ls180.v:3039.25-3039.82" + cell $and $and$ls180.v:3039$120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3495$145_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3039$120_Y end - attribute \src "ls180.v:3495.49-3495.167" - cell $and $and$ls180.v:3495$146 + attribute \src "ls180.v:3039.24-3039.112" + cell $and $and$ls180.v:3039$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3495$145_Y - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3495$146_Y + connect \A $and$ls180.v:3039$120_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3039$121_Y end - attribute \src "ls180.v:3496.49-3496.118" - cell $and $and$ls180.v:3496$147 + attribute \src "ls180.v:3039.23-3039.146" + cell $and $and$ls180.v:3039$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3496$147_Y + connect \A $and$ls180.v:3039$121_Y + connect \B \main_interface0_ram_bus_sel [5] + connect \Y $and$ls180.v:3039$122_Y end - attribute \src "ls180.v:3496.48-3496.154" - cell $and $and$ls180.v:3496$148 + attribute \src "ls180.v:3040.25-3040.82" + cell $and $and$ls180.v:3040$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3496$147_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3496$148_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3040$123_Y end - attribute \src "ls180.v:3497.50-3497.119" - cell $and $and$ls180.v:3497$149 + attribute \src "ls180.v:3040.24-3040.112" + cell $and $and$ls180.v:3040$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3497$149_Y + connect \A $and$ls180.v:3040$123_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3040$124_Y end - attribute \src "ls180.v:3497.49-3497.155" - cell $and $and$ls180.v:3497$150 + attribute \src "ls180.v:3040.23-3040.146" + cell $and $and$ls180.v:3040$125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3497$149_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3497$150_Y + connect \A $and$ls180.v:3040$124_Y + connect \B \main_interface0_ram_bus_sel [6] + connect \Y $and$ls180.v:3040$125_Y end - attribute \src "ls180.v:3500.7-3500.114" - cell $and $and$ls180.v:3500$152 + attribute \src "ls180.v:3041.25-3041.82" + cell $and $and$ls180.v:3041$126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3500$152_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3041$126_Y end - attribute \src "ls180.v:3529.66-3529.246" - cell $and $and$ls180.v:3529$158 + attribute \src "ls180.v:3041.24-3041.112" + cell $and $and$ls180.v:3041$127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3529$157_Y - connect \Y $and$ls180.v:3529$158_Y + connect \A $and$ls180.v:3041$126_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3041$127_Y end - attribute \src "ls180.v:3530.64-3530.187" - cell $and $and$ls180.v:3530$159 + attribute \src "ls180.v:3041.23-3041.146" + cell $and $and$ls180.v:3041$128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3530$159_Y + connect \A $and$ls180.v:3041$127_Y + connect \B \main_interface0_ram_bus_sel [7] + connect \Y $and$ls180.v:3041$128_Y end - attribute \src "ls180.v:3554.9-3554.86" - cell $and $and$ls180.v:3554$165 + attribute \src "ls180.v:3048.25-3048.82" + cell $and $and$ls180.v:3048$130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3554$165_Y + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3048$130_Y end - attribute \src "ls180.v:3566.9-3566.86" - cell $and $and$ls180.v:3566$166 + attribute \src "ls180.v:3048.24-3048.112" + cell $and $and$ls180.v:3048$131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3566$166_Y + connect \A $and$ls180.v:3048$130_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3048$131_Y end - attribute \src "ls180.v:3616.13-3616.87" - cell $and $and$ls180.v:3616$168 + attribute \src "ls180.v:3048.23-3048.146" + cell $and $and$ls180.v:3048$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_ready - connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3616$168_Y + connect \A $and$ls180.v:3048$131_Y + connect \B \main_interface1_ram_bus_sel [0] + connect \Y $and$ls180.v:3048$132_Y end - attribute \src "ls180.v:3652.50-3652.119" - cell $and $and$ls180.v:3652$175 + attribute \src "ls180.v:3049.25-3049.82" + cell $and $and$ls180.v:3049$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3652$175_Y + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3049$133_Y end - attribute \src "ls180.v:3652.49-3652.167" - cell $and $and$ls180.v:3652$176 + attribute \src "ls180.v:3049.24-3049.112" + cell $and $and$ls180.v:3049$134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3652$175_Y - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3652$176_Y + connect \A $and$ls180.v:3049$133_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3049$134_Y end - attribute \src "ls180.v:3653.49-3653.118" - cell $and $and$ls180.v:3653$177 + attribute \src "ls180.v:3049.23-3049.146" + cell $and $and$ls180.v:3049$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3653$177_Y + connect \A $and$ls180.v:3049$134_Y + connect \B \main_interface1_ram_bus_sel [1] + connect \Y $and$ls180.v:3049$135_Y end - attribute \src "ls180.v:3653.48-3653.154" - cell $and $and$ls180.v:3653$178 + attribute \src "ls180.v:3050.25-3050.82" + cell $and $and$ls180.v:3050$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3653$177_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3653$178_Y + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3050$136_Y end - attribute \src "ls180.v:3654.50-3654.119" - cell $and $and$ls180.v:3654$179 + attribute \src "ls180.v:3050.24-3050.112" + cell $and $and$ls180.v:3050$137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3654$179_Y + connect \A $and$ls180.v:3050$136_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3050$137_Y end - attribute \src "ls180.v:3654.49-3654.155" - cell $and $and$ls180.v:3654$180 + attribute \src "ls180.v:3050.23-3050.146" + cell $and $and$ls180.v:3050$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3654$179_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3654$180_Y + connect \A $and$ls180.v:3050$137_Y + connect \B \main_interface1_ram_bus_sel [2] + connect \Y $and$ls180.v:3050$138_Y end - attribute \src "ls180.v:3657.7-3657.114" - cell $and $and$ls180.v:3657$182 + attribute \src "ls180.v:3051.25-3051.82" + cell $and $and$ls180.v:3051$139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3657$182_Y + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3051$139_Y end - attribute \src "ls180.v:3686.66-3686.246" - cell $and $and$ls180.v:3686$188 + attribute \src "ls180.v:3051.24-3051.112" + cell $and $and$ls180.v:3051$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3686$187_Y - connect \Y $and$ls180.v:3686$188_Y + connect \A $and$ls180.v:3051$139_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3051$140_Y end - attribute \src "ls180.v:3687.64-3687.187" - cell $and $and$ls180.v:3687$189 + attribute \src "ls180.v:3051.23-3051.146" + cell $and $and$ls180.v:3051$141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3687$189_Y + connect \A $and$ls180.v:3051$140_Y + connect \B \main_interface1_ram_bus_sel [3] + connect \Y $and$ls180.v:3051$141_Y end - attribute \src "ls180.v:3711.9-3711.86" - cell $and $and$ls180.v:3711$195 + attribute \src "ls180.v:3052.25-3052.82" + cell $and $and$ls180.v:3052$142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3711$195_Y + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3052$142_Y end - attribute \src "ls180.v:3723.9-3723.86" - cell $and $and$ls180.v:3723$196 + attribute \src "ls180.v:3052.24-3052.112" + cell $and $and$ls180.v:3052$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3723$196_Y + connect \A $and$ls180.v:3052$142_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3052$143_Y end - attribute \src "ls180.v:3773.13-3773.87" - cell $and $and$ls180.v:3773$198 + attribute \src "ls180.v:3052.23-3052.146" + cell $and $and$ls180.v:3052$144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_ready - connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3773$198_Y + connect \A $and$ls180.v:3052$143_Y + connect \B \main_interface1_ram_bus_sel [4] + connect \Y $and$ls180.v:3052$144_Y end - attribute \src "ls180.v:3788.37-3788.102" - cell $and $and$ls180.v:3788$199 + attribute \src "ls180.v:3053.25-3053.82" + cell $and $and$ls180.v:3053$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3788$199_Y + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3053$145_Y end - attribute \src "ls180.v:3788.108-3788.188" - cell $and $and$ls180.v:3788$201 + attribute \src "ls180.v:3053.24-3053.112" + cell $and $and$ls180.v:3053$146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3788$200_Y - connect \Y $and$ls180.v:3788$201_Y + connect \A $and$ls180.v:3053$145_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3053$146_Y end - attribute \src "ls180.v:3788.107-3788.231" - cell $and $and$ls180.v:3788$203 + attribute \src "ls180.v:3053.23-3053.146" + cell $and $and$ls180.v:3053$147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3788$201_Y - connect \B $not$ls180.v:3788$202_Y - connect \Y $and$ls180.v:3788$203_Y + connect \A $and$ls180.v:3053$146_Y + connect \B \main_interface1_ram_bus_sel [5] + connect \Y $and$ls180.v:3053$147_Y end - attribute \src "ls180.v:3788.36-3788.232" - cell $and $and$ls180.v:3788$204 + attribute \src "ls180.v:3054.25-3054.82" + cell $and $and$ls180.v:3054$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3788$199_Y - connect \B $and$ls180.v:3788$203_Y - connect \Y $and$ls180.v:3788$204_Y + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3054$148_Y end - attribute \src "ls180.v:3789.37-3789.102" - cell $and $and$ls180.v:3789$205 + attribute \src "ls180.v:3054.24-3054.112" + cell $and $and$ls180.v:3054$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3789$205_Y + connect \A $and$ls180.v:3054$148_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3054$149_Y end - attribute \src "ls180.v:3789.108-3789.188" - cell $and $and$ls180.v:3789$207 + attribute \src "ls180.v:3054.23-3054.146" + cell $and $and$ls180.v:3054$150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3789$206_Y - connect \Y $and$ls180.v:3789$207_Y + connect \A $and$ls180.v:3054$149_Y + connect \B \main_interface1_ram_bus_sel [6] + connect \Y $and$ls180.v:3054$150_Y end - attribute \src "ls180.v:3789.107-3789.231" - cell $and $and$ls180.v:3789$209 + attribute \src "ls180.v:3055.25-3055.82" + cell $and $and$ls180.v:3055$151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3789$207_Y - connect \B $not$ls180.v:3789$208_Y - connect \Y $and$ls180.v:3789$209_Y + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3055$151_Y end - attribute \src "ls180.v:3789.36-3789.232" - cell $and $and$ls180.v:3789$210 + attribute \src "ls180.v:3055.24-3055.112" + cell $and $and$ls180.v:3055$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3789$205_Y - connect \B $and$ls180.v:3789$209_Y - connect \Y $and$ls180.v:3789$210_Y + connect \A $and$ls180.v:3055$151_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3055$152_Y end - attribute \src "ls180.v:3790.34-3790.85" - cell $and $and$ls180.v:3790$211 + attribute \src "ls180.v:3055.23-3055.146" + cell $and $and$ls180.v:3055$153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_trrdcon_ready - connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3790$211_Y + connect \A $and$ls180.v:3055$152_Y + connect \B \main_interface1_ram_bus_sel [7] + connect \Y $and$ls180.v:3055$153_Y end - attribute \src "ls180.v:3791.37-3791.102" - cell $and $and$ls180.v:3791$212 + attribute \src "ls180.v:3062.25-3062.82" + cell $and $and$ls180.v:3062$155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3791$212_Y + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3062$155_Y end - attribute \src "ls180.v:3791.36-3791.194" - cell $and $and$ls180.v:3791$214 + attribute \src "ls180.v:3062.24-3062.112" + cell $and $and$ls180.v:3062$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3791$212_Y - connect \B $or$ls180.v:3791$213_Y - connect \Y $and$ls180.v:3791$214_Y + connect \A $and$ls180.v:3062$155_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3062$156_Y end - attribute \src "ls180.v:3793.37-3793.102" - cell $and $and$ls180.v:3793$215 + attribute \src "ls180.v:3062.23-3062.146" + cell $and $and$ls180.v:3062$157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3793$215_Y + connect \A $and$ls180.v:3062$156_Y + connect \B \main_interface2_ram_bus_sel [0] + connect \Y $and$ls180.v:3062$157_Y end - attribute \src "ls180.v:3793.36-3793.148" - cell $and $and$ls180.v:3793$216 + attribute \src "ls180.v:3063.25-3063.82" + cell $and $and$ls180.v:3063$158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3793$215_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3793$216_Y + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3063$158_Y end - attribute \src "ls180.v:3794.40-3794.119" - cell $and $and$ls180.v:3794$217 + attribute \src "ls180.v:3063.24-3063.112" + cell $and $and$ls180.v:3063$159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3794$217_Y + connect \A $and$ls180.v:3063$158_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3063$159_Y end - attribute \src "ls180.v:3794.124-3794.203" - cell $and $and$ls180.v:3794$218 + attribute \src "ls180.v:3063.23-3063.146" + cell $and $and$ls180.v:3063$160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3794$218_Y + connect \A $and$ls180.v:3063$159_Y + connect \B \main_interface2_ram_bus_sel [1] + connect \Y $and$ls180.v:3063$160_Y end - attribute \src "ls180.v:3794.209-3794.288" - cell $and $and$ls180.v:3794$220 + attribute \src "ls180.v:3064.25-3064.82" + cell $and $and$ls180.v:3064$161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3794$220_Y + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3064$161_Y end - attribute \src "ls180.v:3794.294-3794.373" - cell $and $and$ls180.v:3794$222 + attribute \src "ls180.v:3064.24-3064.112" + cell $and $and$ls180.v:3064$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3794$222_Y + connect \A $and$ls180.v:3064$161_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3064$162_Y end - attribute \src "ls180.v:3795.41-3795.121" - cell $and $and$ls180.v:3795$224 + attribute \src "ls180.v:3064.23-3064.146" + cell $and $and$ls180.v:3064$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3795$224_Y + connect \A $and$ls180.v:3064$162_Y + connect \B \main_interface2_ram_bus_sel [2] + connect \Y $and$ls180.v:3064$163_Y end - attribute \src "ls180.v:3795.126-3795.206" - cell $and $and$ls180.v:3795$225 + attribute \src "ls180.v:3065.25-3065.82" + cell $and $and$ls180.v:3065$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3795$225_Y + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3065$164_Y end - attribute \src "ls180.v:3795.212-3795.292" - cell $and $and$ls180.v:3795$227 + attribute \src "ls180.v:3065.24-3065.112" + cell $and $and$ls180.v:3065$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3795$227_Y + connect \A $and$ls180.v:3065$164_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3065$165_Y end - attribute \src "ls180.v:3795.298-3795.378" - cell $and $and$ls180.v:3795$229 + attribute \src "ls180.v:3065.23-3065.146" + cell $and $and$ls180.v:3065$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3795$229_Y + connect \A $and$ls180.v:3065$165_Y + connect \B \main_interface2_ram_bus_sel [3] + connect \Y $and$ls180.v:3065$166_Y end - attribute \src "ls180.v:3802.38-3802.111" - cell $and $and$ls180.v:3802$233 + attribute \src "ls180.v:3066.25-3066.82" + cell $and $and$ls180.v:3066$167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_gnt - connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3802$233_Y + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3066$167_Y end - attribute \src "ls180.v:3802.37-3802.150" - cell $and $and$ls180.v:3802$234 + attribute \src "ls180.v:3066.24-3066.112" + cell $and $and$ls180.v:3066$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3802$233_Y - connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3802$234_Y + connect \A $and$ls180.v:3066$167_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3066$168_Y end - attribute \src "ls180.v:3802.36-3802.189" - cell $and $and$ls180.v:3802$235 + attribute \src "ls180.v:3066.23-3066.146" + cell $and $and$ls180.v:3066$169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3802$234_Y - connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3802$235_Y + connect \A $and$ls180.v:3066$168_Y + connect \B \main_interface2_ram_bus_sel [4] + connect \Y $and$ls180.v:3066$169_Y end - attribute \src "ls180.v:3808.77-3808.153" - cell $and $and$ls180.v:3808$238 + attribute \src "ls180.v:3067.25-3067.82" + cell $and $and$ls180.v:3067$170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3808$238_Y + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3067$170_Y end - attribute \src "ls180.v:3808.162-3808.246" - cell $and $and$ls180.v:3808$240 + attribute \src "ls180.v:3067.24-3067.112" + cell $and $and$ls180.v:3067$171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3808$239_Y - connect \Y $and$ls180.v:3808$240_Y + connect \A $and$ls180.v:3067$170_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3067$171_Y end - attribute \src "ls180.v:3808.161-3808.291" - cell $and $and$ls180.v:3808$242 + attribute \src "ls180.v:3067.23-3067.146" + cell $and $and$ls180.v:3067$172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3808$240_Y - connect \B $not$ls180.v:3808$241_Y - connect \Y $and$ls180.v:3808$242_Y + connect \A $and$ls180.v:3067$171_Y + connect \B \main_interface2_ram_bus_sel [5] + connect \Y $and$ls180.v:3067$172_Y end - attribute \src "ls180.v:3808.76-3808.333" - cell $and $and$ls180.v:3808$245 + attribute \src "ls180.v:3068.25-3068.82" + cell $and $and$ls180.v:3068$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3808$238_Y - connect \B $or$ls180.v:3808$244_Y - connect \Y $and$ls180.v:3808$245_Y + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3068$173_Y end - attribute \src "ls180.v:3808.338-3808.505" - cell $and $and$ls180.v:3808$248 + attribute \src "ls180.v:3068.24-3068.112" + cell $and $and$ls180.v:3068$174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3808$246_Y - connect \B $eq$ls180.v:3808$247_Y - connect \Y $and$ls180.v:3808$248_Y + connect \A $and$ls180.v:3068$173_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3068$174_Y end - attribute \src "ls180.v:3808.38-3808.507" - cell $and $and$ls180.v:3808$250 + attribute \src "ls180.v:3068.23-3068.146" + cell $and $and$ls180.v:3068$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3068$174_Y + connect \B \main_interface2_ram_bus_sel [6] + connect \Y $and$ls180.v:3068$175_Y + end + attribute \src "ls180.v:3069.25-3069.82" + cell $and $and$ls180.v:3069$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3069$176_Y + end + attribute \src "ls180.v:3069.24-3069.112" + cell $and $and$ls180.v:3069$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3069$176_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3069$177_Y + end + attribute \src "ls180.v:3069.23-3069.146" + cell $and $and$ls180.v:3069$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3069$177_Y + connect \B \main_interface2_ram_bus_sel [7] + connect \Y $and$ls180.v:3069$178_Y + end + attribute \src "ls180.v:3186.40-3186.99" + cell $and $and$ls180.v:3186$185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3186$185_Y + end + attribute \src "ls180.v:3187.40-3187.99" + cell $and $and$ls180.v:3187$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3187$186_Y + end + attribute \src "ls180.v:3225.38-3225.103" + cell $and $and$ls180.v:3225$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3225$191_Y + connect \Y $and$ls180.v:3225$192_Y + end + attribute \src "ls180.v:3279.50-3279.119" + cell $and $and$ls180.v:3279$200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3808$249_Y - connect \Y $and$ls180.v:3808$250_Y + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3279$200_Y end - attribute \src "ls180.v:3809.77-3809.153" - cell $and $and$ls180.v:3809$251 + attribute \src "ls180.v:3279.49-3279.167" + cell $and $and$ls180.v:3279$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3279$200_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3279$201_Y + end + attribute \src "ls180.v:3280.49-3280.118" + cell $and $and$ls180.v:3280$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3280$202_Y + end + attribute \src "ls180.v:3280.48-3280.154" + cell $and $and$ls180.v:3280$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3280$202_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3280$203_Y + end + attribute \src "ls180.v:3281.50-3281.119" + cell $and $and$ls180.v:3281$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3281$204_Y + end + attribute \src "ls180.v:3281.49-3281.155" + cell $and $and$ls180.v:3281$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3281$204_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3281$205_Y + end + attribute \src "ls180.v:3284.7-3284.114" + cell $and $and$ls180.v:3284$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3284$207_Y + end + attribute \src "ls180.v:3313.66-3313.246" + cell $and $and$ls180.v:3313$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3313$212_Y + connect \Y $and$ls180.v:3313$213_Y + end + attribute \src "ls180.v:3314.64-3314.187" + cell $and $and$ls180.v:3314$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3314$214_Y + end + attribute \src "ls180.v:3338.9-3338.86" + cell $and $and$ls180.v:3338$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3338$220_Y + end + attribute \src "ls180.v:3350.9-3350.86" + cell $and $and$ls180.v:3350$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3350$221_Y + end + attribute \src "ls180.v:3400.13-3400.87" + cell $and $and$ls180.v:3400$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3400$223_Y + end + attribute \src "ls180.v:3436.50-3436.119" + cell $and $and$ls180.v:3436$230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3436$230_Y + end + attribute \src "ls180.v:3436.49-3436.167" + cell $and $and$ls180.v:3436$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3436$230_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3436$231_Y + end + attribute \src "ls180.v:3437.49-3437.118" + cell $and $and$ls180.v:3437$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3437$232_Y + end + attribute \src "ls180.v:3437.48-3437.154" + cell $and $and$ls180.v:3437$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3437$232_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3437$233_Y + end + attribute \src "ls180.v:3438.50-3438.119" + cell $and $and$ls180.v:3438$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3438$234_Y + end + attribute \src "ls180.v:3438.49-3438.155" + cell $and $and$ls180.v:3438$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3438$234_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3438$235_Y + end + attribute \src "ls180.v:3441.7-3441.114" + cell $and $and$ls180.v:3441$237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3441$237_Y + end + attribute \src "ls180.v:3470.66-3470.246" + cell $and $and$ls180.v:3470$243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3470$242_Y + connect \Y $and$ls180.v:3470$243_Y + end + attribute \src "ls180.v:3471.64-3471.187" + cell $and $and$ls180.v:3471$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3471$244_Y + end + attribute \src "ls180.v:3495.9-3495.86" + cell $and $and$ls180.v:3495$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3495$250_Y + end + attribute \src "ls180.v:3507.9-3507.86" + cell $and $and$ls180.v:3507$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3507$251_Y + end + attribute \src "ls180.v:3557.13-3557.87" + cell $and $and$ls180.v:3557$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3557$253_Y + end + attribute \src "ls180.v:3593.50-3593.119" + cell $and $and$ls180.v:3593$260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3593$260_Y + end + attribute \src "ls180.v:3593.49-3593.167" + cell $and $and$ls180.v:3593$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3593$260_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3593$261_Y + end + attribute \src "ls180.v:3594.49-3594.118" + cell $and $and$ls180.v:3594$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3594$262_Y + end + attribute \src "ls180.v:3594.48-3594.154" + cell $and $and$ls180.v:3594$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3594$262_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3594$263_Y + end + attribute \src "ls180.v:3595.50-3595.119" + cell $and $and$ls180.v:3595$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3595$264_Y + end + attribute \src "ls180.v:3595.49-3595.155" + cell $and $and$ls180.v:3595$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3595$264_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3595$265_Y + end + attribute \src "ls180.v:3598.7-3598.114" + cell $and $and$ls180.v:3598$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3598$267_Y + end + attribute \src "ls180.v:3627.66-3627.246" + cell $and $and$ls180.v:3627$273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3627$272_Y + connect \Y $and$ls180.v:3627$273_Y + end + attribute \src "ls180.v:3628.64-3628.187" + cell $and $and$ls180.v:3628$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3628$274_Y + end + attribute \src "ls180.v:3652.9-3652.86" + cell $and $and$ls180.v:3652$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3652$280_Y + end + attribute \src "ls180.v:3664.9-3664.86" + cell $and $and$ls180.v:3664$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3664$281_Y + end + attribute \src "ls180.v:3714.13-3714.87" + cell $and $and$ls180.v:3714$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3714$283_Y + end + attribute \src "ls180.v:3750.50-3750.119" + cell $and $and$ls180.v:3750$290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3750$290_Y + end + attribute \src "ls180.v:3750.49-3750.167" + cell $and $and$ls180.v:3750$291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3750$290_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3750$291_Y + end + attribute \src "ls180.v:3751.49-3751.118" + cell $and $and$ls180.v:3751$292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3751$292_Y + end + attribute \src "ls180.v:3751.48-3751.154" + cell $and $and$ls180.v:3751$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3751$292_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3751$293_Y + end + attribute \src "ls180.v:3752.50-3752.119" + cell $and $and$ls180.v:3752$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3752$294_Y + end + attribute \src "ls180.v:3752.49-3752.155" + cell $and $and$ls180.v:3752$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3752$294_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3752$295_Y + end + attribute \src "ls180.v:3755.7-3755.114" + cell $and $and$ls180.v:3755$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3755$297_Y + end + attribute \src "ls180.v:3784.66-3784.246" + cell $and $and$ls180.v:3784$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3784$302_Y + connect \Y $and$ls180.v:3784$303_Y + end + attribute \src "ls180.v:3785.64-3785.187" + cell $and $and$ls180.v:3785$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3785$304_Y + end + attribute \src "ls180.v:3809.9-3809.86" + cell $and $and$ls180.v:3809$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3809$310_Y + end + attribute \src "ls180.v:3821.9-3821.86" + cell $and $and$ls180.v:3821$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3821$311_Y + end + attribute \src "ls180.v:3871.13-3871.87" + cell $and $and$ls180.v:3871$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3871$313_Y + end + attribute \src "ls180.v:3886.37-3886.102" + cell $and $and$ls180.v:3886$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3886$314_Y + end + attribute \src "ls180.v:3886.108-3886.188" + cell $and $and$ls180.v:3886$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3886$315_Y + connect \Y $and$ls180.v:3886$316_Y + end + attribute \src "ls180.v:3886.107-3886.231" + cell $and $and$ls180.v:3886$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3886$316_Y + connect \B $not$ls180.v:3886$317_Y + connect \Y $and$ls180.v:3886$318_Y + end + attribute \src "ls180.v:3886.36-3886.232" + cell $and $and$ls180.v:3886$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3886$314_Y + connect \B $and$ls180.v:3886$318_Y + connect \Y $and$ls180.v:3886$319_Y + end + attribute \src "ls180.v:3887.37-3887.102" + cell $and $and$ls180.v:3887$320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3887$320_Y + end + attribute \src "ls180.v:3887.108-3887.188" + cell $and $and$ls180.v:3887$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3887$321_Y + connect \Y $and$ls180.v:3887$322_Y + end + attribute \src "ls180.v:3887.107-3887.231" + cell $and $and$ls180.v:3887$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3887$322_Y + connect \B $not$ls180.v:3887$323_Y + connect \Y $and$ls180.v:3887$324_Y + end + attribute \src "ls180.v:3887.36-3887.232" + cell $and $and$ls180.v:3887$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3887$320_Y + connect \B $and$ls180.v:3887$324_Y + connect \Y $and$ls180.v:3887$325_Y + end + attribute \src "ls180.v:3888.34-3888.85" + cell $and $and$ls180.v:3888$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3888$326_Y + end + attribute \src "ls180.v:3889.37-3889.102" + cell $and $and$ls180.v:3889$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3889$327_Y + end + attribute \src "ls180.v:3889.36-3889.194" + cell $and $and$ls180.v:3889$329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3889$327_Y + connect \B $or$ls180.v:3889$328_Y + connect \Y $and$ls180.v:3889$329_Y + end + attribute \src "ls180.v:3891.37-3891.102" + cell $and $and$ls180.v:3891$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3891$330_Y + end + attribute \src "ls180.v:3891.36-3891.148" + cell $and $and$ls180.v:3891$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3891$330_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3891$331_Y + end + attribute \src "ls180.v:3892.40-3892.119" + cell $and $and$ls180.v:3892$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3892$332_Y + end + attribute \src "ls180.v:3892.124-3892.203" + cell $and $and$ls180.v:3892$333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3892$333_Y + end + attribute \src "ls180.v:3892.209-3892.288" + cell $and $and$ls180.v:3892$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3892$335_Y + end + attribute \src "ls180.v:3892.294-3892.373" + cell $and $and$ls180.v:3892$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3892$337_Y + end + attribute \src "ls180.v:3893.41-3893.121" + cell $and $and$ls180.v:3893$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3893$339_Y + end + attribute \src "ls180.v:3893.126-3893.206" + cell $and $and$ls180.v:3893$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3893$340_Y + end + attribute \src "ls180.v:3893.212-3893.292" + cell $and $and$ls180.v:3893$342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3893$342_Y + end + attribute \src "ls180.v:3893.298-3893.378" + cell $and $and$ls180.v:3893$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3893$344_Y + end + attribute \src "ls180.v:3900.38-3900.111" + cell $and $and$ls180.v:3900$348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3900$348_Y + end + attribute \src "ls180.v:3900.37-3900.150" + cell $and $and$ls180.v:3900$349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3900$348_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3900$349_Y + end + attribute \src "ls180.v:3900.36-3900.189" + cell $and $and$ls180.v:3900$350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3900$349_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3900$350_Y + end + attribute \src "ls180.v:3906.77-3906.153" + cell $and $and$ls180.v:3906$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3906$353_Y + end + attribute \src "ls180.v:3906.162-3906.246" + cell $and $and$ls180.v:3906$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3906$354_Y + connect \Y $and$ls180.v:3906$355_Y + end + attribute \src "ls180.v:3906.161-3906.291" + cell $and $and$ls180.v:3906$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3906$355_Y + connect \B $not$ls180.v:3906$356_Y + connect \Y $and$ls180.v:3906$357_Y + end + attribute \src "ls180.v:3906.76-3906.333" + cell $and $and$ls180.v:3906$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3906$353_Y + connect \B $or$ls180.v:3906$359_Y + connect \Y $and$ls180.v:3906$360_Y + end + attribute \src "ls180.v:3906.338-3906.505" + cell $and $and$ls180.v:3906$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3906$361_Y + connect \B $eq$ls180.v:3906$362_Y + connect \Y $and$ls180.v:3906$363_Y + end + attribute \src "ls180.v:3906.38-3906.507" + cell $and $and$ls180.v:3906$365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3906$364_Y + connect \Y $and$ls180.v:3906$365_Y + end + attribute \src "ls180.v:3907.77-3907.153" + cell $and $and$ls180.v:3907$366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236997,65 +238651,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3809$251_Y + connect \Y $and$ls180.v:3907$366_Y end - attribute \src "ls180.v:3809.162-3809.246" - cell $and $and$ls180.v:3809$253 + attribute \src "ls180.v:3907.162-3907.246" + cell $and $and$ls180.v:3907$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3809$252_Y - connect \Y $and$ls180.v:3809$253_Y + connect \B $not$ls180.v:3907$367_Y + connect \Y $and$ls180.v:3907$368_Y end - attribute \src "ls180.v:3809.161-3809.291" - cell $and $and$ls180.v:3809$255 + attribute \src "ls180.v:3907.161-3907.291" + cell $and $and$ls180.v:3907$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$253_Y - connect \B $not$ls180.v:3809$254_Y - connect \Y $and$ls180.v:3809$255_Y + connect \A $and$ls180.v:3907$368_Y + connect \B $not$ls180.v:3907$369_Y + connect \Y $and$ls180.v:3907$370_Y end - attribute \src "ls180.v:3809.76-3809.333" - cell $and $and$ls180.v:3809$258 + attribute \src "ls180.v:3907.76-3907.333" + cell $and $and$ls180.v:3907$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$251_Y - connect \B $or$ls180.v:3809$257_Y - connect \Y $and$ls180.v:3809$258_Y + connect \A $and$ls180.v:3907$366_Y + connect \B $or$ls180.v:3907$372_Y + connect \Y $and$ls180.v:3907$373_Y end - attribute \src "ls180.v:3809.338-3809.505" - cell $and $and$ls180.v:3809$261 + attribute \src "ls180.v:3907.338-3907.505" + cell $and $and$ls180.v:3907$376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3809$259_Y - connect \B $eq$ls180.v:3809$260_Y - connect \Y $and$ls180.v:3809$261_Y + connect \A $eq$ls180.v:3907$374_Y + connect \B $eq$ls180.v:3907$375_Y + connect \Y $and$ls180.v:3907$376_Y end - attribute \src "ls180.v:3809.38-3809.507" - cell $and $and$ls180.v:3809$263 + attribute \src "ls180.v:3907.38-3907.507" + cell $and $and$ls180.v:3907$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3809$262_Y - connect \Y $and$ls180.v:3809$263_Y + connect \B $or$ls180.v:3907$377_Y + connect \Y $and$ls180.v:3907$378_Y end - attribute \src "ls180.v:3810.77-3810.153" - cell $and $and$ls180.v:3810$264 + attribute \src "ls180.v:3908.77-3908.153" + cell $and $and$ls180.v:3908$379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237063,65 +238717,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3810$264_Y + connect \Y $and$ls180.v:3908$379_Y end - attribute \src "ls180.v:3810.162-3810.246" - cell $and $and$ls180.v:3810$266 + attribute \src "ls180.v:3908.162-3908.246" + cell $and $and$ls180.v:3908$381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3810$265_Y - connect \Y $and$ls180.v:3810$266_Y + connect \B $not$ls180.v:3908$380_Y + connect \Y $and$ls180.v:3908$381_Y end - attribute \src "ls180.v:3810.161-3810.291" - cell $and $and$ls180.v:3810$268 + attribute \src "ls180.v:3908.161-3908.291" + cell $and $and$ls180.v:3908$383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3810$266_Y - connect \B $not$ls180.v:3810$267_Y - connect \Y $and$ls180.v:3810$268_Y + connect \A $and$ls180.v:3908$381_Y + connect \B $not$ls180.v:3908$382_Y + connect \Y $and$ls180.v:3908$383_Y end - attribute \src "ls180.v:3810.76-3810.333" - cell $and $and$ls180.v:3810$271 + attribute \src "ls180.v:3908.76-3908.333" + cell $and $and$ls180.v:3908$386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3810$264_Y - connect \B $or$ls180.v:3810$270_Y - connect \Y $and$ls180.v:3810$271_Y + connect \A $and$ls180.v:3908$379_Y + connect \B $or$ls180.v:3908$385_Y + connect \Y $and$ls180.v:3908$386_Y end - attribute \src "ls180.v:3810.338-3810.505" - cell $and $and$ls180.v:3810$274 + attribute \src "ls180.v:3908.338-3908.505" + cell $and $and$ls180.v:3908$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3810$272_Y - connect \B $eq$ls180.v:3810$273_Y - connect \Y $and$ls180.v:3810$274_Y + connect \A $eq$ls180.v:3908$387_Y + connect \B $eq$ls180.v:3908$388_Y + connect \Y $and$ls180.v:3908$389_Y end - attribute \src "ls180.v:3810.38-3810.507" - cell $and $and$ls180.v:3810$276 + attribute \src "ls180.v:3908.38-3908.507" + cell $and $and$ls180.v:3908$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3810$275_Y - connect \Y $and$ls180.v:3810$276_Y + connect \B $or$ls180.v:3908$390_Y + connect \Y $and$ls180.v:3908$391_Y end - attribute \src "ls180.v:3811.77-3811.153" - cell $and $and$ls180.v:3811$277 + attribute \src "ls180.v:3909.77-3909.153" + cell $and $and$ls180.v:3909$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237129,65 +238783,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3811$277_Y + connect \Y $and$ls180.v:3909$392_Y end - attribute \src "ls180.v:3811.162-3811.246" - cell $and $and$ls180.v:3811$279 + attribute \src "ls180.v:3909.162-3909.246" + cell $and $and$ls180.v:3909$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3811$278_Y - connect \Y $and$ls180.v:3811$279_Y + connect \B $not$ls180.v:3909$393_Y + connect \Y $and$ls180.v:3909$394_Y end - attribute \src "ls180.v:3811.161-3811.291" - cell $and $and$ls180.v:3811$281 + attribute \src "ls180.v:3909.161-3909.291" + cell $and $and$ls180.v:3909$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3811$279_Y - connect \B $not$ls180.v:3811$280_Y - connect \Y $and$ls180.v:3811$281_Y + connect \A $and$ls180.v:3909$394_Y + connect \B $not$ls180.v:3909$395_Y + connect \Y $and$ls180.v:3909$396_Y end - attribute \src "ls180.v:3811.76-3811.333" - cell $and $and$ls180.v:3811$284 + attribute \src "ls180.v:3909.76-3909.333" + cell $and $and$ls180.v:3909$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3811$277_Y - connect \B $or$ls180.v:3811$283_Y - connect \Y $and$ls180.v:3811$284_Y + connect \A $and$ls180.v:3909$392_Y + connect \B $or$ls180.v:3909$398_Y + connect \Y $and$ls180.v:3909$399_Y end - attribute \src "ls180.v:3811.338-3811.505" - cell $and $and$ls180.v:3811$287 + attribute \src "ls180.v:3909.338-3909.505" + cell $and $and$ls180.v:3909$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3811$285_Y - connect \B $eq$ls180.v:3811$286_Y - connect \Y $and$ls180.v:3811$287_Y + connect \A $eq$ls180.v:3909$400_Y + connect \B $eq$ls180.v:3909$401_Y + connect \Y $and$ls180.v:3909$402_Y end - attribute \src "ls180.v:3811.38-3811.507" - cell $and $and$ls180.v:3811$289 + attribute \src "ls180.v:3909.38-3909.507" + cell $and $and$ls180.v:3909$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3811$288_Y - connect \Y $and$ls180.v:3811$289_Y + connect \B $or$ls180.v:3909$403_Y + connect \Y $and$ls180.v:3909$404_Y end - attribute \src "ls180.v:3841.77-3841.153" - cell $and $and$ls180.v:3841$296 + attribute \src "ls180.v:3939.77-3939.153" + cell $and $and$ls180.v:3939$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237195,65 +238849,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3841$296_Y + connect \Y $and$ls180.v:3939$411_Y end - attribute \src "ls180.v:3841.162-3841.246" - cell $and $and$ls180.v:3841$298 + attribute \src "ls180.v:3939.162-3939.246" + cell $and $and$ls180.v:3939$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3841$297_Y - connect \Y $and$ls180.v:3841$298_Y + connect \B $not$ls180.v:3939$412_Y + connect \Y $and$ls180.v:3939$413_Y end - attribute \src "ls180.v:3841.161-3841.291" - cell $and $and$ls180.v:3841$300 + attribute \src "ls180.v:3939.161-3939.291" + cell $and $and$ls180.v:3939$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3841$298_Y - connect \B $not$ls180.v:3841$299_Y - connect \Y $and$ls180.v:3841$300_Y + connect \A $and$ls180.v:3939$413_Y + connect \B $not$ls180.v:3939$414_Y + connect \Y $and$ls180.v:3939$415_Y end - attribute \src "ls180.v:3841.76-3841.333" - cell $and $and$ls180.v:3841$303 + attribute \src "ls180.v:3939.76-3939.333" + cell $and $and$ls180.v:3939$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3841$296_Y - connect \B $or$ls180.v:3841$302_Y - connect \Y $and$ls180.v:3841$303_Y + connect \A $and$ls180.v:3939$411_Y + connect \B $or$ls180.v:3939$417_Y + connect \Y $and$ls180.v:3939$418_Y end - attribute \src "ls180.v:3841.338-3841.505" - cell $and $and$ls180.v:3841$306 + attribute \src "ls180.v:3939.338-3939.505" + cell $and $and$ls180.v:3939$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3841$304_Y - connect \B $eq$ls180.v:3841$305_Y - connect \Y $and$ls180.v:3841$306_Y + connect \A $eq$ls180.v:3939$419_Y + connect \B $eq$ls180.v:3939$420_Y + connect \Y $and$ls180.v:3939$421_Y end - attribute \src "ls180.v:3841.38-3841.507" - cell $and $and$ls180.v:3841$308 + attribute \src "ls180.v:3939.38-3939.507" + cell $and $and$ls180.v:3939$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3841$307_Y - connect \Y $and$ls180.v:3841$308_Y + connect \B $or$ls180.v:3939$422_Y + connect \Y $and$ls180.v:3939$423_Y end - attribute \src "ls180.v:3842.77-3842.153" - cell $and $and$ls180.v:3842$309 + attribute \src "ls180.v:3940.77-3940.153" + cell $and $and$ls180.v:3940$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237261,65 +238915,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3842$309_Y + connect \Y $and$ls180.v:3940$424_Y end - attribute \src "ls180.v:3842.162-3842.246" - cell $and $and$ls180.v:3842$311 + attribute \src "ls180.v:3940.162-3940.246" + cell $and $and$ls180.v:3940$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3842$310_Y - connect \Y $and$ls180.v:3842$311_Y + connect \B $not$ls180.v:3940$425_Y + connect \Y $and$ls180.v:3940$426_Y end - attribute \src "ls180.v:3842.161-3842.291" - cell $and $and$ls180.v:3842$313 + attribute \src "ls180.v:3940.161-3940.291" + cell $and $and$ls180.v:3940$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$311_Y - connect \B $not$ls180.v:3842$312_Y - connect \Y $and$ls180.v:3842$313_Y + connect \A $and$ls180.v:3940$426_Y + connect \B $not$ls180.v:3940$427_Y + connect \Y $and$ls180.v:3940$428_Y end - attribute \src "ls180.v:3842.76-3842.333" - cell $and $and$ls180.v:3842$316 + attribute \src "ls180.v:3940.76-3940.333" + cell $and $and$ls180.v:3940$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$309_Y - connect \B $or$ls180.v:3842$315_Y - connect \Y $and$ls180.v:3842$316_Y + connect \A $and$ls180.v:3940$424_Y + connect \B $or$ls180.v:3940$430_Y + connect \Y $and$ls180.v:3940$431_Y end - attribute \src "ls180.v:3842.338-3842.505" - cell $and $and$ls180.v:3842$319 + attribute \src "ls180.v:3940.338-3940.505" + cell $and $and$ls180.v:3940$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3842$317_Y - connect \B $eq$ls180.v:3842$318_Y - connect \Y $and$ls180.v:3842$319_Y + connect \A $eq$ls180.v:3940$432_Y + connect \B $eq$ls180.v:3940$433_Y + connect \Y $and$ls180.v:3940$434_Y end - attribute \src "ls180.v:3842.38-3842.507" - cell $and $and$ls180.v:3842$321 + attribute \src "ls180.v:3940.38-3940.507" + cell $and $and$ls180.v:3940$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3842$320_Y - connect \Y $and$ls180.v:3842$321_Y + connect \B $or$ls180.v:3940$435_Y + connect \Y $and$ls180.v:3940$436_Y end - attribute \src "ls180.v:3843.77-3843.153" - cell $and $and$ls180.v:3843$322 + attribute \src "ls180.v:3941.77-3941.153" + cell $and $and$ls180.v:3941$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237327,65 +238981,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3843$322_Y + connect \Y $and$ls180.v:3941$437_Y end - attribute \src "ls180.v:3843.162-3843.246" - cell $and $and$ls180.v:3843$324 + attribute \src "ls180.v:3941.162-3941.246" + cell $and $and$ls180.v:3941$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3843$323_Y - connect \Y $and$ls180.v:3843$324_Y + connect \B $not$ls180.v:3941$438_Y + connect \Y $and$ls180.v:3941$439_Y end - attribute \src "ls180.v:3843.161-3843.291" - cell $and $and$ls180.v:3843$326 + attribute \src "ls180.v:3941.161-3941.291" + cell $and $and$ls180.v:3941$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$324_Y - connect \B $not$ls180.v:3843$325_Y - connect \Y $and$ls180.v:3843$326_Y + connect \A $and$ls180.v:3941$439_Y + connect \B $not$ls180.v:3941$440_Y + connect \Y $and$ls180.v:3941$441_Y end - attribute \src "ls180.v:3843.76-3843.333" - cell $and $and$ls180.v:3843$329 + attribute \src "ls180.v:3941.76-3941.333" + cell $and $and$ls180.v:3941$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$322_Y - connect \B $or$ls180.v:3843$328_Y - connect \Y $and$ls180.v:3843$329_Y + connect \A $and$ls180.v:3941$437_Y + connect \B $or$ls180.v:3941$443_Y + connect \Y $and$ls180.v:3941$444_Y end - attribute \src "ls180.v:3843.338-3843.505" - cell $and $and$ls180.v:3843$332 + attribute \src "ls180.v:3941.338-3941.505" + cell $and $and$ls180.v:3941$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3843$330_Y - connect \B $eq$ls180.v:3843$331_Y - connect \Y $and$ls180.v:3843$332_Y + connect \A $eq$ls180.v:3941$445_Y + connect \B $eq$ls180.v:3941$446_Y + connect \Y $and$ls180.v:3941$447_Y end - attribute \src "ls180.v:3843.38-3843.507" - cell $and $and$ls180.v:3843$334 + attribute \src "ls180.v:3941.38-3941.507" + cell $and $and$ls180.v:3941$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3843$333_Y - connect \Y $and$ls180.v:3843$334_Y + connect \B $or$ls180.v:3941$448_Y + connect \Y $and$ls180.v:3941$449_Y end - attribute \src "ls180.v:3844.77-3844.153" - cell $and $and$ls180.v:3844$335 + attribute \src "ls180.v:3942.77-3942.153" + cell $and $and$ls180.v:3942$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237393,65 +239047,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3844$335_Y + connect \Y $and$ls180.v:3942$450_Y end - attribute \src "ls180.v:3844.162-3844.246" - cell $and $and$ls180.v:3844$337 + attribute \src "ls180.v:3942.162-3942.246" + cell $and $and$ls180.v:3942$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3844$336_Y - connect \Y $and$ls180.v:3844$337_Y + connect \B $not$ls180.v:3942$451_Y + connect \Y $and$ls180.v:3942$452_Y end - attribute \src "ls180.v:3844.161-3844.291" - cell $and $and$ls180.v:3844$339 + attribute \src "ls180.v:3942.161-3942.291" + cell $and $and$ls180.v:3942$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$337_Y - connect \B $not$ls180.v:3844$338_Y - connect \Y $and$ls180.v:3844$339_Y + connect \A $and$ls180.v:3942$452_Y + connect \B $not$ls180.v:3942$453_Y + connect \Y $and$ls180.v:3942$454_Y end - attribute \src "ls180.v:3844.76-3844.333" - cell $and $and$ls180.v:3844$342 + attribute \src "ls180.v:3942.76-3942.333" + cell $and $and$ls180.v:3942$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$335_Y - connect \B $or$ls180.v:3844$341_Y - connect \Y $and$ls180.v:3844$342_Y + connect \A $and$ls180.v:3942$450_Y + connect \B $or$ls180.v:3942$456_Y + connect \Y $and$ls180.v:3942$457_Y end - attribute \src "ls180.v:3844.338-3844.505" - cell $and $and$ls180.v:3844$345 + attribute \src "ls180.v:3942.338-3942.505" + cell $and $and$ls180.v:3942$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3844$343_Y - connect \B $eq$ls180.v:3844$344_Y - connect \Y $and$ls180.v:3844$345_Y + connect \A $eq$ls180.v:3942$458_Y + connect \B $eq$ls180.v:3942$459_Y + connect \Y $and$ls180.v:3942$460_Y end - attribute \src "ls180.v:3844.38-3844.507" - cell $and $and$ls180.v:3844$347 + attribute \src "ls180.v:3942.38-3942.507" + cell $and $and$ls180.v:3942$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3844$346_Y - connect \Y $and$ls180.v:3844$347_Y + connect \B $or$ls180.v:3942$461_Y + connect \Y $and$ls180.v:3942$462_Y end - attribute \src "ls180.v:3873.8-3873.73" - cell $and $and$ls180.v:3873$352 + attribute \src "ls180.v:3971.8-3971.73" + cell $and $and$ls180.v:3971$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237459,21 +239113,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3873$352_Y + connect \Y $and$ls180.v:3971$467_Y end - attribute \src "ls180.v:3873.7-3873.114" - cell $and $and$ls180.v:3873$354 + attribute \src "ls180.v:3971.7-3971.114" + cell $and $and$ls180.v:3971$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3873$352_Y - connect \B $eq$ls180.v:3873$353_Y - connect \Y $and$ls180.v:3873$354_Y + connect \A $and$ls180.v:3971$467_Y + connect \B $eq$ls180.v:3971$468_Y + connect \Y $and$ls180.v:3971$469_Y end - attribute \src "ls180.v:3876.8-3876.73" - cell $and $and$ls180.v:3876$355 + attribute \src "ls180.v:3974.8-3974.73" + cell $and $and$ls180.v:3974$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237481,21 +239135,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3876$355_Y + connect \Y $and$ls180.v:3974$470_Y end - attribute \src "ls180.v:3876.7-3876.114" - cell $and $and$ls180.v:3876$357 + attribute \src "ls180.v:3974.7-3974.114" + cell $and $and$ls180.v:3974$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3876$355_Y - connect \B $eq$ls180.v:3876$356_Y - connect \Y $and$ls180.v:3876$357_Y + connect \A $and$ls180.v:3974$470_Y + connect \B $eq$ls180.v:3974$471_Y + connect \Y $and$ls180.v:3974$472_Y end - attribute \src "ls180.v:3882.8-3882.73" - cell $and $and$ls180.v:3882$359 + attribute \src "ls180.v:3980.8-3980.73" + cell $and $and$ls180.v:3980$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237503,21 +239157,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3882$359_Y + connect \Y $and$ls180.v:3980$474_Y end - attribute \src "ls180.v:3882.7-3882.114" - cell $and $and$ls180.v:3882$361 + attribute \src "ls180.v:3980.7-3980.114" + cell $and $and$ls180.v:3980$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3882$359_Y - connect \B $eq$ls180.v:3882$360_Y - connect \Y $and$ls180.v:3882$361_Y + connect \A $and$ls180.v:3980$474_Y + connect \B $eq$ls180.v:3980$475_Y + connect \Y $and$ls180.v:3980$476_Y end - attribute \src "ls180.v:3885.8-3885.73" - cell $and $and$ls180.v:3885$362 + attribute \src "ls180.v:3983.8-3983.73" + cell $and $and$ls180.v:3983$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237525,21 +239179,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3885$362_Y + connect \Y $and$ls180.v:3983$477_Y end - attribute \src "ls180.v:3885.7-3885.114" - cell $and $and$ls180.v:3885$364 + attribute \src "ls180.v:3983.7-3983.114" + cell $and $and$ls180.v:3983$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$362_Y - connect \B $eq$ls180.v:3885$363_Y - connect \Y $and$ls180.v:3885$364_Y + connect \A $and$ls180.v:3983$477_Y + connect \B $eq$ls180.v:3983$478_Y + connect \Y $and$ls180.v:3983$479_Y end - attribute \src "ls180.v:3891.8-3891.73" - cell $and $and$ls180.v:3891$366 + attribute \src "ls180.v:3989.8-3989.73" + cell $and $and$ls180.v:3989$481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237547,21 +239201,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3891$366_Y + connect \Y $and$ls180.v:3989$481_Y end - attribute \src "ls180.v:3891.7-3891.114" - cell $and $and$ls180.v:3891$368 + attribute \src "ls180.v:3989.7-3989.114" + cell $and $and$ls180.v:3989$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3891$366_Y - connect \B $eq$ls180.v:3891$367_Y - connect \Y $and$ls180.v:3891$368_Y + connect \A $and$ls180.v:3989$481_Y + connect \B $eq$ls180.v:3989$482_Y + connect \Y $and$ls180.v:3989$483_Y end - attribute \src "ls180.v:3894.8-3894.73" - cell $and $and$ls180.v:3894$369 + attribute \src "ls180.v:3992.8-3992.73" + cell $and $and$ls180.v:3992$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237569,21 +239223,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3894$369_Y + connect \Y $and$ls180.v:3992$484_Y end - attribute \src "ls180.v:3894.7-3894.114" - cell $and $and$ls180.v:3894$371 + attribute \src "ls180.v:3992.7-3992.114" + cell $and $and$ls180.v:3992$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3894$369_Y - connect \B $eq$ls180.v:3894$370_Y - connect \Y $and$ls180.v:3894$371_Y + connect \A $and$ls180.v:3992$484_Y + connect \B $eq$ls180.v:3992$485_Y + connect \Y $and$ls180.v:3992$486_Y end - attribute \src "ls180.v:3900.8-3900.73" - cell $and $and$ls180.v:3900$373 + attribute \src "ls180.v:3998.8-3998.73" + cell $and $and$ls180.v:3998$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237591,21 +239245,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3900$373_Y + connect \Y $and$ls180.v:3998$488_Y end - attribute \src "ls180.v:3900.7-3900.114" - cell $and $and$ls180.v:3900$375 + attribute \src "ls180.v:3998.7-3998.114" + cell $and $and$ls180.v:3998$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3900$373_Y - connect \B $eq$ls180.v:3900$374_Y - connect \Y $and$ls180.v:3900$375_Y + connect \A $and$ls180.v:3998$488_Y + connect \B $eq$ls180.v:3998$489_Y + connect \Y $and$ls180.v:3998$490_Y end - attribute \src "ls180.v:3903.8-3903.73" - cell $and $and$ls180.v:3903$376 + attribute \src "ls180.v:4001.8-4001.73" + cell $and $and$ls180.v:4001$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237613,615 +239267,615 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3903$376_Y + connect \Y $and$ls180.v:4001$491_Y end - attribute \src "ls180.v:3903.7-3903.114" - cell $and $and$ls180.v:3903$378 + attribute \src "ls180.v:4001.7-4001.114" + cell $and $and$ls180.v:4001$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3903$376_Y - connect \B $eq$ls180.v:3903$377_Y - connect \Y $and$ls180.v:3903$378_Y + connect \A $and$ls180.v:4001$491_Y + connect \B $eq$ls180.v:4001$492_Y + connect \Y $and$ls180.v:4001$493_Y end - attribute \src "ls180.v:3928.71-3928.151" - cell $and $and$ls180.v:3928$383 + attribute \src "ls180.v:4026.71-4026.151" + cell $and $and$ls180.v:4026$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3928$382_Y - connect \Y $and$ls180.v:3928$383_Y + connect \B $not$ls180.v:4026$497_Y + connect \Y $and$ls180.v:4026$498_Y end - attribute \src "ls180.v:3928.70-3928.194" - cell $and $and$ls180.v:3928$385 + attribute \src "ls180.v:4026.70-4026.194" + cell $and $and$ls180.v:4026$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3928$383_Y - connect \B $not$ls180.v:3928$384_Y - connect \Y $and$ls180.v:3928$385_Y + connect \A $and$ls180.v:4026$498_Y + connect \B $not$ls180.v:4026$499_Y + connect \Y $and$ls180.v:4026$500_Y end - attribute \src "ls180.v:3928.41-3928.222" - cell $and $and$ls180.v:3928$388 + attribute \src "ls180.v:4026.41-4026.222" + cell $and $and$ls180.v:4026$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3928$387_Y - connect \Y $and$ls180.v:3928$388_Y + connect \B $or$ls180.v:4026$502_Y + connect \Y $and$ls180.v:4026$503_Y end - attribute \src "ls180.v:3966.71-3966.151" - cell $and $and$ls180.v:3966$392 + attribute \src "ls180.v:4064.71-4064.151" + cell $and $and$ls180.v:4064$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3966$391_Y - connect \Y $and$ls180.v:3966$392_Y + connect \B $not$ls180.v:4064$506_Y + connect \Y $and$ls180.v:4064$507_Y end - attribute \src "ls180.v:3966.70-3966.194" - cell $and $and$ls180.v:3966$394 + attribute \src "ls180.v:4064.70-4064.194" + cell $and $and$ls180.v:4064$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3966$392_Y - connect \B $not$ls180.v:3966$393_Y - connect \Y $and$ls180.v:3966$394_Y + connect \A $and$ls180.v:4064$507_Y + connect \B $not$ls180.v:4064$508_Y + connect \Y $and$ls180.v:4064$509_Y end - attribute \src "ls180.v:3966.41-3966.222" - cell $and $and$ls180.v:3966$397 + attribute \src "ls180.v:4064.41-4064.222" + cell $and $and$ls180.v:4064$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3966$396_Y - connect \Y $and$ls180.v:3966$397_Y + connect \B $or$ls180.v:4064$511_Y + connect \Y $and$ls180.v:4064$512_Y end - attribute \src "ls180.v:3984.110-3984.179" - cell $and $and$ls180.v:3984$402 + attribute \src "ls180.v:4082.110-4082.179" + cell $and $and$ls180.v:4082$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3984$401_Y - connect \Y $and$ls180.v:3984$402_Y + connect \B $eq$ls180.v:4082$516_Y + connect \Y $and$ls180.v:4082$517_Y end - attribute \src "ls180.v:3984.185-3984.254" - cell $and $and$ls180.v:3984$405 + attribute \src "ls180.v:4082.185-4082.254" + cell $and $and$ls180.v:4082$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3984$404_Y - connect \Y $and$ls180.v:3984$405_Y + connect \B $eq$ls180.v:4082$519_Y + connect \Y $and$ls180.v:4082$520_Y end - attribute \src "ls180.v:3984.260-3984.329" - cell $and $and$ls180.v:3984$408 + attribute \src "ls180.v:4082.260-4082.329" + cell $and $and$ls180.v:4082$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3984$407_Y - connect \Y $and$ls180.v:3984$408_Y + connect \B $eq$ls180.v:4082$522_Y + connect \Y $and$ls180.v:4082$523_Y end - attribute \src "ls180.v:3984.41-3984.332" - cell $and $and$ls180.v:3984$411 + attribute \src "ls180.v:4082.41-4082.332" + cell $and $and$ls180.v:4082$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3984$400_Y - connect \B $not$ls180.v:3984$410_Y - connect \Y $and$ls180.v:3984$411_Y + connect \A $eq$ls180.v:4082$515_Y + connect \B $not$ls180.v:4082$525_Y + connect \Y $and$ls180.v:4082$526_Y end - attribute \src "ls180.v:3984.40-3984.355" - cell $and $and$ls180.v:3984$412 + attribute \src "ls180.v:4082.40-4082.355" + cell $and $and$ls180.v:4082$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3984$411_Y + connect \A $and$ls180.v:4082$526_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3984$412_Y + connect \Y $and$ls180.v:4082$527_Y end - attribute \src "ls180.v:3985.34-3985.106" - cell $and $and$ls180.v:3985$415 + attribute \src "ls180.v:4083.34-4083.106" + cell $and $and$ls180.v:4083$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3985$413_Y - connect \B $not$ls180.v:3985$414_Y - connect \Y $and$ls180.v:3985$415_Y + connect \A $not$ls180.v:4083$528_Y + connect \B $not$ls180.v:4083$529_Y + connect \Y $and$ls180.v:4083$530_Y end - attribute \src "ls180.v:3989.110-3989.179" - cell $and $and$ls180.v:3989$418 + attribute \src "ls180.v:4087.110-4087.179" + cell $and $and$ls180.v:4087$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3989$417_Y - connect \Y $and$ls180.v:3989$418_Y + connect \B $eq$ls180.v:4087$532_Y + connect \Y $and$ls180.v:4087$533_Y end - attribute \src "ls180.v:3989.185-3989.254" - cell $and $and$ls180.v:3989$421 + attribute \src "ls180.v:4087.185-4087.254" + cell $and $and$ls180.v:4087$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3989$420_Y - connect \Y $and$ls180.v:3989$421_Y + connect \B $eq$ls180.v:4087$535_Y + connect \Y $and$ls180.v:4087$536_Y end - attribute \src "ls180.v:3989.260-3989.329" - cell $and $and$ls180.v:3989$424 + attribute \src "ls180.v:4087.260-4087.329" + cell $and $and$ls180.v:4087$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3989$423_Y - connect \Y $and$ls180.v:3989$424_Y + connect \B $eq$ls180.v:4087$538_Y + connect \Y $and$ls180.v:4087$539_Y end - attribute \src "ls180.v:3989.41-3989.332" - cell $and $and$ls180.v:3989$427 + attribute \src "ls180.v:4087.41-4087.332" + cell $and $and$ls180.v:4087$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3989$416_Y - connect \B $not$ls180.v:3989$426_Y - connect \Y $and$ls180.v:3989$427_Y + connect \A $eq$ls180.v:4087$531_Y + connect \B $not$ls180.v:4087$541_Y + connect \Y $and$ls180.v:4087$542_Y end - attribute \src "ls180.v:3989.40-3989.355" - cell $and $and$ls180.v:3989$428 + attribute \src "ls180.v:4087.40-4087.355" + cell $and $and$ls180.v:4087$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$427_Y + connect \A $and$ls180.v:4087$542_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3989$428_Y + connect \Y $and$ls180.v:4087$543_Y end - attribute \src "ls180.v:3990.34-3990.106" - cell $and $and$ls180.v:3990$431 + attribute \src "ls180.v:4088.34-4088.106" + cell $and $and$ls180.v:4088$546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3990$429_Y - connect \B $not$ls180.v:3990$430_Y - connect \Y $and$ls180.v:3990$431_Y + connect \A $not$ls180.v:4088$544_Y + connect \B $not$ls180.v:4088$545_Y + connect \Y $and$ls180.v:4088$546_Y end - attribute \src "ls180.v:3994.110-3994.179" - cell $and $and$ls180.v:3994$434 + attribute \src "ls180.v:4092.110-4092.179" + cell $and $and$ls180.v:4092$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3994$433_Y - connect \Y $and$ls180.v:3994$434_Y + connect \B $eq$ls180.v:4092$548_Y + connect \Y $and$ls180.v:4092$549_Y end - attribute \src "ls180.v:3994.185-3994.254" - cell $and $and$ls180.v:3994$437 + attribute \src "ls180.v:4092.185-4092.254" + cell $and $and$ls180.v:4092$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3994$436_Y - connect \Y $and$ls180.v:3994$437_Y + connect \B $eq$ls180.v:4092$551_Y + connect \Y $and$ls180.v:4092$552_Y end - attribute \src "ls180.v:3994.260-3994.329" - cell $and $and$ls180.v:3994$440 + attribute \src "ls180.v:4092.260-4092.329" + cell $and $and$ls180.v:4092$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3994$439_Y - connect \Y $and$ls180.v:3994$440_Y + connect \B $eq$ls180.v:4092$554_Y + connect \Y $and$ls180.v:4092$555_Y end - attribute \src "ls180.v:3994.41-3994.332" - cell $and $and$ls180.v:3994$443 + attribute \src "ls180.v:4092.41-4092.332" + cell $and $and$ls180.v:4092$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3994$432_Y - connect \B $not$ls180.v:3994$442_Y - connect \Y $and$ls180.v:3994$443_Y + connect \A $eq$ls180.v:4092$547_Y + connect \B $not$ls180.v:4092$557_Y + connect \Y $and$ls180.v:4092$558_Y end - attribute \src "ls180.v:3994.40-3994.355" - cell $and $and$ls180.v:3994$444 + attribute \src "ls180.v:4092.40-4092.355" + cell $and $and$ls180.v:4092$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3994$443_Y + connect \A $and$ls180.v:4092$558_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3994$444_Y + connect \Y $and$ls180.v:4092$559_Y end - attribute \src "ls180.v:3995.34-3995.106" - cell $and $and$ls180.v:3995$447 + attribute \src "ls180.v:4093.34-4093.106" + cell $and $and$ls180.v:4093$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3995$445_Y - connect \B $not$ls180.v:3995$446_Y - connect \Y $and$ls180.v:3995$447_Y + connect \A $not$ls180.v:4093$560_Y + connect \B $not$ls180.v:4093$561_Y + connect \Y $and$ls180.v:4093$562_Y end - attribute \src "ls180.v:3999.110-3999.179" - cell $and $and$ls180.v:3999$450 + attribute \src "ls180.v:4097.110-4097.179" + cell $and $and$ls180.v:4097$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3999$449_Y - connect \Y $and$ls180.v:3999$450_Y + connect \B $eq$ls180.v:4097$564_Y + connect \Y $and$ls180.v:4097$565_Y end - attribute \src "ls180.v:3999.185-3999.254" - cell $and $and$ls180.v:3999$453 + attribute \src "ls180.v:4097.185-4097.254" + cell $and $and$ls180.v:4097$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3999$452_Y - connect \Y $and$ls180.v:3999$453_Y + connect \B $eq$ls180.v:4097$567_Y + connect \Y $and$ls180.v:4097$568_Y end - attribute \src "ls180.v:3999.260-3999.329" - cell $and $and$ls180.v:3999$456 + attribute \src "ls180.v:4097.260-4097.329" + cell $and $and$ls180.v:4097$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3999$455_Y - connect \Y $and$ls180.v:3999$456_Y + connect \B $eq$ls180.v:4097$570_Y + connect \Y $and$ls180.v:4097$571_Y end - attribute \src "ls180.v:3999.41-3999.332" - cell $and $and$ls180.v:3999$459 + attribute \src "ls180.v:4097.41-4097.332" + cell $and $and$ls180.v:4097$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3999$448_Y - connect \B $not$ls180.v:3999$458_Y - connect \Y $and$ls180.v:3999$459_Y + connect \A $eq$ls180.v:4097$563_Y + connect \B $not$ls180.v:4097$573_Y + connect \Y $and$ls180.v:4097$574_Y end - attribute \src "ls180.v:3999.40-3999.355" - cell $and $and$ls180.v:3999$460 + attribute \src "ls180.v:4097.40-4097.355" + cell $and $and$ls180.v:4097$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3999$459_Y + connect \A $and$ls180.v:4097$574_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3999$460_Y + connect \Y $and$ls180.v:4097$575_Y end - attribute \src "ls180.v:4000.34-4000.106" - cell $and $and$ls180.v:4000$463 + attribute \src "ls180.v:4098.34-4098.106" + cell $and $and$ls180.v:4098$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4000$461_Y - connect \B $not$ls180.v:4000$462_Y - connect \Y $and$ls180.v:4000$463_Y + connect \A $not$ls180.v:4098$576_Y + connect \B $not$ls180.v:4098$577_Y + connect \Y $and$ls180.v:4098$578_Y end - attribute \src "ls180.v:4004.151-4004.220" - cell $and $and$ls180.v:4004$467 + attribute \src "ls180.v:4102.151-4102.220" + cell $and $and$ls180.v:4102$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4004$466_Y - connect \Y $and$ls180.v:4004$467_Y + connect \B $eq$ls180.v:4102$581_Y + connect \Y $and$ls180.v:4102$582_Y end - attribute \src "ls180.v:4004.226-4004.295" - cell $and $and$ls180.v:4004$470 + attribute \src "ls180.v:4102.226-4102.295" + cell $and $and$ls180.v:4102$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4004$469_Y - connect \Y $and$ls180.v:4004$470_Y + connect \B $eq$ls180.v:4102$584_Y + connect \Y $and$ls180.v:4102$585_Y end - attribute \src "ls180.v:4004.301-4004.370" - cell $and $and$ls180.v:4004$473 + attribute \src "ls180.v:4102.301-4102.370" + cell $and $and$ls180.v:4102$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4004$472_Y - connect \Y $and$ls180.v:4004$473_Y + connect \B $eq$ls180.v:4102$587_Y + connect \Y $and$ls180.v:4102$588_Y end - attribute \src "ls180.v:4004.82-4004.373" - cell $and $and$ls180.v:4004$476 + attribute \src "ls180.v:4102.82-4102.373" + cell $and $and$ls180.v:4102$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4004$465_Y - connect \B $not$ls180.v:4004$475_Y - connect \Y $and$ls180.v:4004$476_Y + connect \A $eq$ls180.v:4102$580_Y + connect \B $not$ls180.v:4102$590_Y + connect \Y $and$ls180.v:4102$591_Y end - attribute \src "ls180.v:4004.43-4004.374" - cell $and $and$ls180.v:4004$477 + attribute \src "ls180.v:4102.43-4102.374" + cell $and $and$ls180.v:4102$592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4004$464_Y - connect \B $and$ls180.v:4004$476_Y - connect \Y $and$ls180.v:4004$477_Y + connect \A $eq$ls180.v:4102$579_Y + connect \B $and$ls180.v:4102$591_Y + connect \Y $and$ls180.v:4102$592_Y end - attribute \src "ls180.v:4004.42-4004.410" - cell $and $and$ls180.v:4004$478 + attribute \src "ls180.v:4102.42-4102.410" + cell $and $and$ls180.v:4102$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4004$477_Y + connect \A $and$ls180.v:4102$592_Y connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4004$478_Y + connect \Y $and$ls180.v:4102$593_Y end - attribute \src "ls180.v:4004.525-4004.594" - cell $and $and$ls180.v:4004$483 + attribute \src "ls180.v:4102.525-4102.594" + cell $and $and$ls180.v:4102$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4004$482_Y - connect \Y $and$ls180.v:4004$483_Y + connect \B $eq$ls180.v:4102$597_Y + connect \Y $and$ls180.v:4102$598_Y end - attribute \src "ls180.v:4004.600-4004.669" - cell $and $and$ls180.v:4004$486 + attribute \src "ls180.v:4102.600-4102.669" + cell $and $and$ls180.v:4102$601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4004$485_Y - connect \Y $and$ls180.v:4004$486_Y + connect \B $eq$ls180.v:4102$600_Y + connect \Y $and$ls180.v:4102$601_Y end - attribute \src "ls180.v:4004.675-4004.744" - cell $and $and$ls180.v:4004$489 + attribute \src "ls180.v:4102.675-4102.744" + cell $and $and$ls180.v:4102$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4004$488_Y - connect \Y $and$ls180.v:4004$489_Y + connect \B $eq$ls180.v:4102$603_Y + connect \Y $and$ls180.v:4102$604_Y end - attribute \src "ls180.v:4004.456-4004.747" - cell $and $and$ls180.v:4004$492 + attribute \src "ls180.v:4102.456-4102.747" + cell $and $and$ls180.v:4102$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4004$481_Y - connect \B $not$ls180.v:4004$491_Y - connect \Y $and$ls180.v:4004$492_Y + connect \A $eq$ls180.v:4102$596_Y + connect \B $not$ls180.v:4102$606_Y + connect \Y $and$ls180.v:4102$607_Y end - attribute \src "ls180.v:4004.417-4004.748" - cell $and $and$ls180.v:4004$493 + attribute \src "ls180.v:4102.417-4102.748" + cell $and $and$ls180.v:4102$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4004$480_Y - connect \B $and$ls180.v:4004$492_Y - connect \Y $and$ls180.v:4004$493_Y + connect \A $eq$ls180.v:4102$595_Y + connect \B $and$ls180.v:4102$607_Y + connect \Y $and$ls180.v:4102$608_Y end - attribute \src "ls180.v:4004.416-4004.784" - cell $and $and$ls180.v:4004$494 + attribute \src "ls180.v:4102.416-4102.784" + cell $and $and$ls180.v:4102$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4004$493_Y + connect \A $and$ls180.v:4102$608_Y connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4004$494_Y + connect \Y $and$ls180.v:4102$609_Y end - attribute \src "ls180.v:4004.899-4004.968" - cell $and $and$ls180.v:4004$499 + attribute \src "ls180.v:4102.899-4102.968" + cell $and $and$ls180.v:4102$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4004$498_Y - connect \Y $and$ls180.v:4004$499_Y + connect \B $eq$ls180.v:4102$613_Y + connect \Y $and$ls180.v:4102$614_Y end - attribute \src "ls180.v:4004.974-4004.1043" - cell $and $and$ls180.v:4004$502 + attribute \src "ls180.v:4102.974-4102.1043" + cell $and $and$ls180.v:4102$617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4004$501_Y - connect \Y $and$ls180.v:4004$502_Y + connect \B $eq$ls180.v:4102$616_Y + connect \Y $and$ls180.v:4102$617_Y end - attribute \src "ls180.v:4004.1049-4004.1118" - cell $and $and$ls180.v:4004$505 + attribute \src "ls180.v:4102.1049-4102.1118" + cell $and $and$ls180.v:4102$620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4004$504_Y - connect \Y $and$ls180.v:4004$505_Y + connect \B $eq$ls180.v:4102$619_Y + connect \Y $and$ls180.v:4102$620_Y end - attribute \src "ls180.v:4004.830-4004.1121" - cell $and $and$ls180.v:4004$508 + attribute \src "ls180.v:4102.830-4102.1121" + cell $and $and$ls180.v:4102$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4004$497_Y - connect \B $not$ls180.v:4004$507_Y - connect \Y $and$ls180.v:4004$508_Y + connect \A $eq$ls180.v:4102$612_Y + connect \B $not$ls180.v:4102$622_Y + connect \Y $and$ls180.v:4102$623_Y end - attribute \src "ls180.v:4004.791-4004.1122" - cell $and $and$ls180.v:4004$509 + attribute \src "ls180.v:4102.791-4102.1122" + cell $and $and$ls180.v:4102$624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4004$496_Y - connect \B $and$ls180.v:4004$508_Y - connect \Y $and$ls180.v:4004$509_Y + connect \A $eq$ls180.v:4102$611_Y + connect \B $and$ls180.v:4102$623_Y + connect \Y $and$ls180.v:4102$624_Y end - attribute \src "ls180.v:4004.790-4004.1158" - cell $and $and$ls180.v:4004$510 + attribute \src "ls180.v:4102.790-4102.1158" + cell $and $and$ls180.v:4102$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4004$509_Y + connect \A $and$ls180.v:4102$624_Y connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4004$510_Y + connect \Y $and$ls180.v:4102$625_Y end - attribute \src "ls180.v:4004.1273-4004.1342" - cell $and $and$ls180.v:4004$515 + attribute \src "ls180.v:4102.1273-4102.1342" + cell $and $and$ls180.v:4102$630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4004$514_Y - connect \Y $and$ls180.v:4004$515_Y + connect \B $eq$ls180.v:4102$629_Y + connect \Y $and$ls180.v:4102$630_Y end - attribute \src "ls180.v:4004.1348-4004.1417" - cell $and $and$ls180.v:4004$518 + attribute \src "ls180.v:4102.1348-4102.1417" + cell $and $and$ls180.v:4102$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4004$517_Y - connect \Y $and$ls180.v:4004$518_Y + connect \B $eq$ls180.v:4102$632_Y + connect \Y $and$ls180.v:4102$633_Y end - attribute \src "ls180.v:4004.1423-4004.1492" - cell $and $and$ls180.v:4004$521 + attribute \src "ls180.v:4102.1423-4102.1492" + cell $and $and$ls180.v:4102$636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4004$520_Y - connect \Y $and$ls180.v:4004$521_Y + connect \B $eq$ls180.v:4102$635_Y + connect \Y $and$ls180.v:4102$636_Y end - attribute \src "ls180.v:4004.1204-4004.1495" - cell $and $and$ls180.v:4004$524 + attribute \src "ls180.v:4102.1204-4102.1495" + cell $and $and$ls180.v:4102$639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4004$513_Y - connect \B $not$ls180.v:4004$523_Y - connect \Y $and$ls180.v:4004$524_Y + connect \A $eq$ls180.v:4102$628_Y + connect \B $not$ls180.v:4102$638_Y + connect \Y $and$ls180.v:4102$639_Y end - attribute \src "ls180.v:4004.1165-4004.1496" - cell $and $and$ls180.v:4004$525 + attribute \src "ls180.v:4102.1165-4102.1496" + cell $and $and$ls180.v:4102$640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4004$512_Y - connect \B $and$ls180.v:4004$524_Y - connect \Y $and$ls180.v:4004$525_Y + connect \A $eq$ls180.v:4102$627_Y + connect \B $and$ls180.v:4102$639_Y + connect \Y $and$ls180.v:4102$640_Y end - attribute \src "ls180.v:4004.1164-4004.1532" - cell $and $and$ls180.v:4004$526 + attribute \src "ls180.v:4102.1164-4102.1532" + cell $and $and$ls180.v:4102$641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4004$525_Y + connect \A $and$ls180.v:4102$640_Y connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4004$526_Y + connect \Y $and$ls180.v:4102$641_Y end - attribute \src "ls180.v:4062.9-4062.46" - cell $and $and$ls180.v:4062$532 + attribute \src "ls180.v:4160.9-4160.46" + cell $and $and$ls180.v:4160$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238229,10 +239883,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4062$532_Y + connect \Y $and$ls180.v:4160$647_Y end - attribute \src "ls180.v:4080.9-4080.46" - cell $and $and$ls180.v:4080$539 + attribute \src "ls180.v:4178.9-4178.46" + cell $and $and$ls180.v:4178$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238240,10 +239894,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4080$539_Y + connect \Y $and$ls180.v:4178$654_Y end - attribute \src "ls180.v:4093.32-4093.75" - cell $and $and$ls180.v:4093$543 + attribute \src "ls180.v:4191.32-4191.75" + cell $and $and$ls180.v:4191$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238251,54 +239905,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4093$543_Y + connect \Y $and$ls180.v:4191$658_Y end - attribute \src "ls180.v:4093.31-4093.99" - cell $and $and$ls180.v:4093$545 + attribute \src "ls180.v:4191.31-4191.99" + cell $and $and$ls180.v:4191$660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4093$543_Y - connect \B $not$ls180.v:4093$544_Y - connect \Y $and$ls180.v:4093$545_Y + connect \A $and$ls180.v:4191$658_Y + connect \B $not$ls180.v:4191$659_Y + connect \Y $and$ls180.v:4191$660_Y end - attribute \src "ls180.v:4094.34-4094.102" - cell $and $and$ls180.v:4094$547 + attribute \src "ls180.v:4192.34-4192.102" + cell $and $and$ls180.v:4192$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4094$546_Y + connect \A $or$ls180.v:4192$661_Y connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4094$547_Y + connect \Y $and$ls180.v:4192$662_Y end - attribute \src "ls180.v:4094.33-4094.128" - cell $and $and$ls180.v:4094$549 + attribute \src "ls180.v:4192.33-4192.128" + cell $and $and$ls180.v:4192$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4094$547_Y - connect \B $not$ls180.v:4094$548_Y - connect \Y $and$ls180.v:4094$549_Y + connect \A $and$ls180.v:4192$662_Y + connect \B $not$ls180.v:4192$663_Y + connect \Y $and$ls180.v:4192$664_Y end - attribute \src "ls180.v:4095.33-4095.104" - cell $and $and$ls180.v:4095$552 + attribute \src "ls180.v:4193.33-4193.104" + cell $and $and$ls180.v:4193$667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4095$550_Y - connect \B $not$ls180.v:4095$551_Y - connect \Y $and$ls180.v:4095$552_Y + connect \A $or$ls180.v:4193$665_Y + connect \B $not$ls180.v:4193$666_Y + connect \Y $and$ls180.v:4193$667_Y end - attribute \src "ls180.v:4096.49-4096.85" - cell $and $and$ls180.v:4096$553 + attribute \src "ls180.v:4194.49-4194.85" + cell $and $and$ls180.v:4194$668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238306,32 +239960,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we connect \B \main_ack_wdata - connect \Y $and$ls180.v:4096$553_Y + connect \Y $and$ls180.v:4194$668_Y end - attribute \src "ls180.v:4096.90-4096.129" - cell $and $and$ls180.v:4096$555 + attribute \src "ls180.v:4194.90-4194.129" + cell $and $and$ls180.v:4194$670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4096$554_Y + connect \A $not$ls180.v:4194$669_Y connect \B \main_ack_rdata - connect \Y $and$ls180.v:4096$555_Y + connect \Y $and$ls180.v:4194$670_Y end - attribute \src "ls180.v:4096.32-4096.131" - cell $and $and$ls180.v:4096$557 + attribute \src "ls180.v:4194.32-4194.131" + cell $and $and$ls180.v:4194$672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_ack_cmd - connect \B $or$ls180.v:4096$556_Y - connect \Y $and$ls180.v:4096$557_Y + connect \B $or$ls180.v:4194$671_Y + connect \Y $and$ls180.v:4194$672_Y end - attribute \src "ls180.v:4097.25-4097.66" - cell $and $and$ls180.v:4097$558 + attribute \src "ls180.v:4195.25-4195.66" + cell $and $and$ls180.v:4195$673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238339,10 +239993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4097$558_Y + connect \Y $and$ls180.v:4195$673_Y end - attribute \src "ls180.v:4098.27-4098.72" - cell $and $and$ls180.v:4098$560 + attribute \src "ls180.v:4196.27-4196.72" + cell $and $and$ls180.v:4196$675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238350,10 +240004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4098$560_Y + connect \Y $and$ls180.v:4196$675_Y end - attribute \src "ls180.v:4099.26-4099.71" - cell $and $and$ls180.v:4099$562 + attribute \src "ls180.v:4197.26-4197.71" + cell $and $and$ls180.v:4197$677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238361,10 +240015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_rdata_valid connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4099$562_Y + connect \Y $and$ls180.v:4197$677_Y end - attribute \src "ls180.v:4128.64-4128.88" - cell $and $and$ls180.v:4128$568 + attribute \src "ls180.v:4226.64-4226.88" + cell $and $and$ls180.v:4226$683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238372,10 +240026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4128$568_Y + connect \Y $and$ls180.v:4226$683_Y end - attribute \src "ls180.v:4132.7-4132.78" - cell $and $and$ls180.v:4132$572 + attribute \src "ls180.v:4230.7-4230.78" + cell $and $and$ls180.v:4230$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238383,10 +240037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4132$572_Y + connect \Y $and$ls180.v:4230$687_Y end - attribute \src "ls180.v:4143.7-4143.78" - cell $and $and$ls180.v:4143$575 + attribute \src "ls180.v:4241.7-4241.78" + cell $and $and$ls180.v:4241$690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238394,10 +240048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4143$575_Y + connect \Y $and$ls180.v:4241$690_Y end - attribute \src "ls180.v:4152.26-4152.97" - cell $and $and$ls180.v:4152$577 + attribute \src "ls180.v:4250.26-4250.97" + cell $and $and$ls180.v:4250$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238405,10 +240059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [0] connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4152$577_Y + connect \Y $and$ls180.v:4250$692_Y end - attribute \src "ls180.v:4152.102-4152.173" - cell $and $and$ls180.v:4152$578 + attribute \src "ls180.v:4250.102-4250.173" + cell $and $and$ls180.v:4250$693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238416,32 +240070,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [1] connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4152$578_Y + connect \Y $and$ls180.v:4250$693_Y end - attribute \src "ls180.v:4167.41-4167.133" - cell $and $and$ls180.v:4167$582 + attribute \src "ls180.v:4265.41-4265.133" + cell $and $and$ls180.v:4265$697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4167$581_Y - connect \Y $and$ls180.v:4167$582_Y + connect \B $or$ls180.v:4265$696_Y + connect \Y $and$ls180.v:4265$697_Y end - attribute \src "ls180.v:4178.39-4178.136" - cell $and $and$ls180.v:4178$587 + attribute \src "ls180.v:4276.39-4276.136" + cell $and $and$ls180.v:4276$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4178$586_Y - connect \Y $and$ls180.v:4178$587_Y + connect \B $or$ls180.v:4276$701_Y + connect \Y $and$ls180.v:4276$702_Y end - attribute \src "ls180.v:4179.37-4179.104" - cell $and $and$ls180.v:4179$588 + attribute \src "ls180.v:4277.37-4277.104" + cell $and $and$ls180.v:4277$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238449,32 +240103,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4179$588_Y + connect \Y $and$ls180.v:4277$703_Y end - attribute \src "ls180.v:4197.41-4197.133" - cell $and $and$ls180.v:4197$593 + attribute \src "ls180.v:4295.41-4295.133" + cell $and $and$ls180.v:4295$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4197$592_Y - connect \Y $and$ls180.v:4197$593_Y + connect \B $or$ls180.v:4295$707_Y + connect \Y $and$ls180.v:4295$708_Y end - attribute \src "ls180.v:4208.39-4208.136" - cell $and $and$ls180.v:4208$598 + attribute \src "ls180.v:4306.39-4306.136" + cell $and $and$ls180.v:4306$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4208$597_Y - connect \Y $and$ls180.v:4208$598_Y + connect \B $or$ls180.v:4306$712_Y + connect \Y $and$ls180.v:4306$713_Y end - attribute \src "ls180.v:4209.37-4209.104" - cell $and $and$ls180.v:4209$599 + attribute \src "ls180.v:4307.37-4307.104" + cell $and $and$ls180.v:4307$714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238482,21 +240136,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4209$599_Y + connect \Y $and$ls180.v:4307$714_Y end - attribute \src "ls180.v:4397.33-4397.86" - cell $and $and$ls180.v:4397$641 + attribute \src "ls180.v:4495.33-4495.86" + cell $and $and$ls180.v:4495$756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4397$640_Y - connect \Y $and$ls180.v:4397$641_Y + connect \B $not$ls180.v:4495$755_Y + connect \Y $and$ls180.v:4495$756_Y end - attribute \src "ls180.v:4501.9-4501.68" - cell $and $and$ls180.v:4501$650 + attribute \src "ls180.v:4599.9-4599.68" + cell $and $and$ls180.v:4599$765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238504,21 +240158,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4501$650_Y + connect \Y $and$ls180.v:4599$765_Y end - attribute \src "ls180.v:4521.53-4521.145" - cell $and $and$ls180.v:4521$653 + attribute \src "ls180.v:4619.53-4619.145" + cell $and $and$ls180.v:4619$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4521$652_Y - connect \Y $and$ls180.v:4521$653_Y + connect \B $or$ls180.v:4619$767_Y + connect \Y $and$ls180.v:4619$768_Y end - attribute \src "ls180.v:4540.52-4540.137" - cell $and $and$ls180.v:4540$656 + attribute \src "ls180.v:4638.52-4638.137" + cell $and $and$ls180.v:4638$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238526,10 +240180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4540$656_Y + connect \Y $and$ls180.v:4638$771_Y end - attribute \src "ls180.v:4581.9-4581.68" - cell $and $and$ls180.v:4581$664 + attribute \src "ls180.v:4679.9-4679.68" + cell $and $and$ls180.v:4679$779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238537,10 +240191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4581$664_Y + connect \Y $and$ls180.v:4679$779_Y end - attribute \src "ls180.v:4619.9-4619.68" - cell $and $and$ls180.v:4619$670 + attribute \src "ls180.v:4717.9-4717.68" + cell $and $and$ls180.v:4717$785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238548,10 +240202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4619$670_Y + connect \Y $and$ls180.v:4717$785_Y end - attribute \src "ls180.v:4628.10-4628.69" - cell $and $and$ls180.v:4628$671 + attribute \src "ls180.v:4726.10-4726.69" + cell $and $and$ls180.v:4726$786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238559,21 +240213,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_sink_valid connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4628$671_Y + connect \Y $and$ls180.v:4726$786_Y end - attribute \src "ls180.v:4628.9-4628.93" - cell $and $and$ls180.v:4628$672 + attribute \src "ls180.v:4726.9-4726.93" + cell $and $and$ls180.v:4726$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4628$671_Y + connect \A $and$ls180.v:4726$786_Y connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4628$672_Y + connect \Y $and$ls180.v:4726$787_Y end - attribute \src "ls180.v:4648.54-4648.117" - cell $and $and$ls180.v:4648$674 + attribute \src "ls180.v:4746.54-4746.117" + cell $and $and$ls180.v:4746$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238581,10 +240235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_valid connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4648$674_Y + connect \Y $and$ls180.v:4746$789_Y end - attribute \src "ls180.v:4667.53-4667.140" - cell $and $and$ls180.v:4667$677 + attribute \src "ls180.v:4765.53-4765.140" + cell $and $and$ls180.v:4765$792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238592,10 +240246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4667$677_Y + connect \Y $and$ls180.v:4765$792_Y end - attribute \src "ls180.v:4764.9-4764.70" - cell $and $and$ls180.v:4764$687 + attribute \src "ls180.v:4862.9-4862.70" + cell $and $and$ls180.v:4862$802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238603,10 +240257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4764$687_Y + connect \Y $and$ls180.v:4862$802_Y end - attribute \src "ls180.v:4782.55-4782.120" - cell $and $and$ls180.v:4782$689 + attribute \src "ls180.v:4880.55-4880.120" + cell $and $and$ls180.v:4880$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238614,10 +240268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_valid connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4782$689_Y + connect \Y $and$ls180.v:4880$804_Y end - attribute \src "ls180.v:4801.54-4801.143" - cell $and $and$ls180.v:4801$692 + attribute \src "ls180.v:4899.54-4899.143" + cell $and $and$ls180.v:4899$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238625,10 +240279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4801$692_Y + connect \Y $and$ls180.v:4899$807_Y end - attribute \src "ls180.v:4883.9-4883.70" - cell $and $and$ls180.v:4883$707 + attribute \src "ls180.v:4981.9-4981.70" + cell $and $and$ls180.v:4981$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238636,10 +240290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_valid connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:4883$707_Y + connect \Y $and$ls180.v:4981$822_Y end - attribute \src "ls180.v:4890.9-4890.70" - cell $and $and$ls180.v:4890$708 + attribute \src "ls180.v:4988.9-4988.70" + cell $and $and$ls180.v:4988$823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238647,10 +240301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_sink_valid connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:4890$708_Y + connect \Y $and$ls180.v:4988$823_Y end - attribute \src "ls180.v:4971.48-4971.124" - cell $and $and$ls180.v:4971$831 + attribute \src "ls180.v:5069.48-5069.124" + cell $and $and$ls180.v:5069$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238658,21 +240312,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4971$831_Y + connect \Y $and$ls180.v:5069$946_Y end - attribute \src "ls180.v:4971.47-4971.165" - cell $and $and$ls180.v:4971$832 + attribute \src "ls180.v:5069.47-5069.165" + cell $and $and$ls180.v:5069$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4971$831_Y + connect \A $and$ls180.v:5069$946_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4971$832_Y + connect \Y $and$ls180.v:5069$947_Y end - attribute \src "ls180.v:4972.50-4972.127" - cell $and $and$ls180.v:4972$833 + attribute \src "ls180.v:5070.50-5070.127" + cell $and $and$ls180.v:5070$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238680,10 +240334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4972$833_Y + connect \Y $and$ls180.v:5070$948_Y end - attribute \src "ls180.v:4974.48-4974.124" - cell $and $and$ls180.v:4974$834 + attribute \src "ls180.v:5072.48-5072.124" + cell $and $and$ls180.v:5072$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238691,21 +240345,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4974$834_Y + connect \Y $and$ls180.v:5072$949_Y end - attribute \src "ls180.v:4974.47-4974.165" - cell $and $and$ls180.v:4974$835 + attribute \src "ls180.v:5072.47-5072.165" + cell $and $and$ls180.v:5072$950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4974$834_Y + connect \A $and$ls180.v:5072$949_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4974$835_Y + connect \Y $and$ls180.v:5072$950_Y end - attribute \src "ls180.v:4975.50-4975.127" - cell $and $and$ls180.v:4975$836 + attribute \src "ls180.v:5073.50-5073.127" + cell $and $and$ls180.v:5073$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238713,10 +240367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4975$836_Y + connect \Y $and$ls180.v:5073$951_Y end - attribute \src "ls180.v:4977.48-4977.124" - cell $and $and$ls180.v:4977$837 + attribute \src "ls180.v:5075.48-5075.124" + cell $and $and$ls180.v:5075$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238724,21 +240378,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4977$837_Y + connect \Y $and$ls180.v:5075$952_Y end - attribute \src "ls180.v:4977.47-4977.165" - cell $and $and$ls180.v:4977$838 + attribute \src "ls180.v:5075.47-5075.165" + cell $and $and$ls180.v:5075$953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4977$837_Y + connect \A $and$ls180.v:5075$952_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4977$838_Y + connect \Y $and$ls180.v:5075$953_Y end - attribute \src "ls180.v:4978.50-4978.127" - cell $and $and$ls180.v:4978$839 + attribute \src "ls180.v:5076.50-5076.127" + cell $and $and$ls180.v:5076$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238746,10 +240400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4978$839_Y + connect \Y $and$ls180.v:5076$954_Y end - attribute \src "ls180.v:4980.48-4980.124" - cell $and $and$ls180.v:4980$840 + attribute \src "ls180.v:5078.48-5078.124" + cell $and $and$ls180.v:5078$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238757,21 +240411,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4980$840_Y + connect \Y $and$ls180.v:5078$955_Y end - attribute \src "ls180.v:4980.47-4980.165" - cell $and $and$ls180.v:4980$841 + attribute \src "ls180.v:5078.47-5078.165" + cell $and $and$ls180.v:5078$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4980$840_Y + connect \A $and$ls180.v:5078$955_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4980$841_Y + connect \Y $and$ls180.v:5078$956_Y end - attribute \src "ls180.v:4981.50-4981.127" - cell $and $and$ls180.v:4981$842 + attribute \src "ls180.v:5079.50-5079.127" + cell $and $and$ls180.v:5079$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238779,10 +240433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4981$842_Y + connect \Y $and$ls180.v:5079$957_Y end - attribute \src "ls180.v:5094.10-5094.86" - cell $and $and$ls180.v:5094$891 + attribute \src "ls180.v:5192.10-5192.86" + cell $and $and$ls180.v:5192$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238790,54 +240444,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5094$891_Y + connect \Y $and$ls180.v:5192$1006_Y end - attribute \src "ls180.v:5094.9-5094.127" - cell $and $and$ls180.v:5094$892 + attribute \src "ls180.v:5192.9-5192.127" + cell $and $and$ls180.v:5192$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5094$891_Y + connect \A $and$ls180.v:5192$1006_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5094$892_Y + connect \Y $and$ls180.v:5192$1007_Y end - attribute \src "ls180.v:5104.9-5104.152" - cell $and $and$ls180.v:5104$896 + attribute \src "ls180.v:5202.9-5202.152" + cell $and $and$ls180.v:5202$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5104$894_Y - connect \B $eq$ls180.v:5104$895_Y - connect \Y $and$ls180.v:5104$896_Y + connect \A $eq$ls180.v:5202$1009_Y + connect \B $eq$ls180.v:5202$1010_Y + connect \Y $and$ls180.v:5202$1011_Y end - attribute \src "ls180.v:5104.8-5104.226" - cell $and $and$ls180.v:5104$898 + attribute \src "ls180.v:5202.8-5202.226" + cell $and $and$ls180.v:5202$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5104$896_Y - connect \B $eq$ls180.v:5104$897_Y - connect \Y $and$ls180.v:5104$898_Y + connect \A $and$ls180.v:5202$1011_Y + connect \B $eq$ls180.v:5202$1012_Y + connect \Y $and$ls180.v:5202$1013_Y end - attribute \src "ls180.v:5104.7-5104.300" - cell $and $and$ls180.v:5104$900 + attribute \src "ls180.v:5202.7-5202.300" + cell $and $and$ls180.v:5202$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5104$898_Y - connect \B $eq$ls180.v:5104$899_Y - connect \Y $and$ls180.v:5104$900_Y + connect \A $and$ls180.v:5202$1013_Y + connect \B $eq$ls180.v:5202$1014_Y + connect \Y $and$ls180.v:5202$1015_Y end - attribute \src "ls180.v:5109.49-5109.124" - cell $and $and$ls180.v:5109$901 + attribute \src "ls180.v:5207.49-5207.124" + cell $and $and$ls180.v:5207$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238845,10 +240499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5109$901_Y + connect \Y $and$ls180.v:5207$1016_Y end - attribute \src "ls180.v:5119.49-5119.124" - cell $and $and$ls180.v:5119$904 + attribute \src "ls180.v:5217.49-5217.124" + cell $and $and$ls180.v:5217$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238856,10 +240510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5119$904_Y + connect \Y $and$ls180.v:5217$1019_Y end - attribute \src "ls180.v:5129.49-5129.124" - cell $and $and$ls180.v:5129$907 + attribute \src "ls180.v:5227.49-5227.124" + cell $and $and$ls180.v:5227$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238867,10 +240521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5129$907_Y + connect \Y $and$ls180.v:5227$1022_Y end - attribute \src "ls180.v:5139.49-5139.124" - cell $and $and$ls180.v:5139$910 + attribute \src "ls180.v:5237.49-5237.124" + cell $and $and$ls180.v:5237$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238878,21 +240532,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5139$910_Y + connect \Y $and$ls180.v:5237$1025_Y end - attribute \src "ls180.v:5151.7-5151.84" - cell $and $and$ls180.v:5151$915 + attribute \src "ls180.v:5249.7-5249.84" + cell $and $and$ls180.v:5249$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5151$914_Y - connect \Y $and$ls180.v:5151$915_Y + connect \B $gt$ls180.v:5249$1029_Y + connect \Y $and$ls180.v:5249$1030_Y end - attribute \src "ls180.v:5269.9-5269.64" - cell $and $and$ls180.v:5269$964 + attribute \src "ls180.v:5367.9-5367.64" + cell $and $and$ls180.v:5367$1079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238900,10 +240554,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5269$964_Y + connect \Y $and$ls180.v:5367$1079_Y end - attribute \src "ls180.v:5321.10-5321.66" - cell $and $and$ls180.v:5321$973 + attribute \src "ls180.v:5419.10-5419.66" + cell $and $and$ls180.v:5419$1088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238911,21 +240565,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5321$973_Y + connect \Y $and$ls180.v:5419$1088_Y end - attribute \src "ls180.v:5321.9-5321.97" - cell $and $and$ls180.v:5321$974 + attribute \src "ls180.v:5419.9-5419.97" + cell $and $and$ls180.v:5419$1089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5321$973_Y + connect \A $and$ls180.v:5419$1088_Y connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5321$974_Y + connect \Y $and$ls180.v:5419$1089_Y end - attribute \src "ls180.v:5347.11-5347.71" - cell $and $and$ls180.v:5347$982 + attribute \src "ls180.v:5445.11-5445.71" + cell $and $and$ls180.v:5445$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238933,21 +240587,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_last connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5347$982_Y + connect \Y $and$ls180.v:5445$1097_Y end - attribute \src "ls180.v:5431.43-5431.152" - cell $and $and$ls180.v:5431$990 + attribute \src "ls180.v:5529.43-5529.152" + cell $and $and$ls180.v:5529$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5431$989_Y - connect \Y $and$ls180.v:5431$990_Y + connect \B $or$ls180.v:5529$1104_Y + connect \Y $and$ls180.v:5529$1105_Y end - attribute \src "ls180.v:5432.41-5432.116" - cell $and $and$ls180.v:5432$991 + attribute \src "ls180.v:5530.41-5530.116" + cell $and $and$ls180.v:5530$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238955,10 +240609,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_readable connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5432$991_Y + connect \Y $and$ls180.v:5530$1106_Y end - attribute \src "ls180.v:5444.48-5444.125" - cell $and $and$ls180.v:5444$996 + attribute \src "ls180.v:5542.48-5542.125" + cell $and $and$ls180.v:5542$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238966,10 +240620,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5444$996_Y + connect \Y $and$ls180.v:5542$1111_Y end - attribute \src "ls180.v:5471.9-5471.102" - cell $and $and$ls180.v:5471$1000 + attribute \src "ls180.v:5569.9-5569.102" + cell $and $and$ls180.v:5569$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238977,10 +240631,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5471$1000_Y + connect \Y $and$ls180.v:5569$1115_Y end - attribute \src "ls180.v:5544.9-5544.58" - cell $and $and$ls180.v:5544$1006 + attribute \src "ls180.v:5642.9-5642.58" + cell $and $and$ls180.v:5642$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238988,10 +240642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_bus_stb connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5544$1006_Y + connect \Y $and$ls180.v:5642$1121_Y end - attribute \src "ls180.v:5597.51-5597.123" - cell $and $and$ls180.v:5597$1014 + attribute \src "ls180.v:5695.51-5695.123" + cell $and $and$ls180.v:5695$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238999,10 +240653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_first connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5597$1014_Y + connect \Y $and$ls180.v:5695$1129_Y end - attribute \src "ls180.v:5598.50-5598.120" - cell $and $and$ls180.v:5598$1015 + attribute \src "ls180.v:5696.50-5696.120" + cell $and $and$ls180.v:5696$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239010,10 +240664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_last connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5598$1015_Y + connect \Y $and$ls180.v:5696$1130_Y end - attribute \src "ls180.v:5599.49-5599.122" - cell $and $and$ls180.v:5599$1016 + attribute \src "ls180.v:5697.49-5697.122" + cell $and $and$ls180.v:5697$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239021,21 +240675,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_last connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5599$1016_Y + connect \Y $and$ls180.v:5697$1131_Y end - attribute \src "ls180.v:5639.43-5639.152" - cell $and $and$ls180.v:5639$1021 + attribute \src "ls180.v:5749.43-5749.152" + cell $and $and$ls180.v:5749$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5639$1020_Y - connect \Y $and$ls180.v:5639$1021_Y + connect \B $or$ls180.v:5749$1135_Y + connect \Y $and$ls180.v:5749$1136_Y end - attribute \src "ls180.v:5640.41-5640.116" - cell $and $and$ls180.v:5640$1022 + attribute \src "ls180.v:5750.41-5750.116" + cell $and $and$ls180.v:5750$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239043,10 +240697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_readable connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5640$1022_Y + connect \Y $and$ls180.v:5750$1137_Y end - attribute \src "ls180.v:5672.9-5672.76" - cell $and $and$ls180.v:5672$1026 + attribute \src "ls180.v:5782.9-5782.76" + cell $and $and$ls180.v:5782$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239054,131 +240708,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_cyc connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5672$1026_Y + connect \Y $and$ls180.v:5782$1141_Y end - attribute \src "ls180.v:5675.44-5675.120" - cell $and $and$ls180.v:5675$1028 + attribute \src "ls180.v:5785.44-5785.120" + cell $and $and$ls180.v:5785$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5675$1027_Y - connect \Y $and$ls180.v:5675$1028_Y + connect \B $ne$ls180.v:5785$1142_Y + connect \Y $and$ls180.v:5785$1143_Y end - attribute \src "ls180.v:5695.63-5695.107" - cell $and $and$ls180.v:5695$1030 + attribute \src "ls180.v:5805.46-5805.90" + cell $and $and$ls180.v:5805$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5695$1029_Y - connect \Y $and$ls180.v:5695$1030_Y + connect \B $eq$ls180.v:5805$1144_Y + connect \Y $and$ls180.v:5805$1145_Y end - attribute \src "ls180.v:5696.63-5696.107" - cell $and $and$ls180.v:5696$1032 + attribute \src "ls180.v:5806.46-5806.90" + cell $and $and$ls180.v:5806$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5696$1031_Y - connect \Y $and$ls180.v:5696$1032_Y + connect \B $eq$ls180.v:5806$1146_Y + connect \Y $and$ls180.v:5806$1147_Y end - attribute \src "ls180.v:5697.63-5697.107" - cell $and $and$ls180.v:5697$1034 + attribute \src "ls180.v:5807.49-5807.93" + cell $and $and$ls180.v:5807$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5697$1033_Y - connect \Y $and$ls180.v:5697$1034_Y + connect \B $eq$ls180.v:5807$1148_Y + connect \Y $and$ls180.v:5807$1149_Y end - attribute \src "ls180.v:5698.35-5698.79" - cell $and $and$ls180.v:5698$1036 + attribute \src "ls180.v:5808.35-5808.79" + cell $and $and$ls180.v:5808$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5698$1035_Y - connect \Y $and$ls180.v:5698$1036_Y + connect \B $eq$ls180.v:5808$1150_Y + connect \Y $and$ls180.v:5808$1151_Y end - attribute \src "ls180.v:5699.35-5699.79" - cell $and $and$ls180.v:5699$1038 + attribute \src "ls180.v:5809.35-5809.79" + cell $and $and$ls180.v:5809$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5699$1037_Y - connect \Y $and$ls180.v:5699$1038_Y + connect \B $eq$ls180.v:5809$1152_Y + connect \Y $and$ls180.v:5809$1153_Y end - attribute \src "ls180.v:5700.63-5700.107" - cell $and $and$ls180.v:5700$1040 + attribute \src "ls180.v:5810.46-5810.90" + cell $and $and$ls180.v:5810$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5700$1039_Y - connect \Y $and$ls180.v:5700$1040_Y + connect \B $eq$ls180.v:5810$1154_Y + connect \Y $and$ls180.v:5810$1155_Y end - attribute \src "ls180.v:5701.63-5701.107" - cell $and $and$ls180.v:5701$1042 + attribute \src "ls180.v:5811.46-5811.90" + cell $and $and$ls180.v:5811$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5701$1041_Y - connect \Y $and$ls180.v:5701$1042_Y + connect \B $eq$ls180.v:5811$1156_Y + connect \Y $and$ls180.v:5811$1157_Y end - attribute \src "ls180.v:5702.63-5702.107" - cell $and $and$ls180.v:5702$1044 + attribute \src "ls180.v:5812.49-5812.93" + cell $and $and$ls180.v:5812$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5702$1043_Y - connect \Y $and$ls180.v:5702$1044_Y + connect \B $eq$ls180.v:5812$1158_Y + connect \Y $and$ls180.v:5812$1159_Y end - attribute \src "ls180.v:5703.35-5703.79" - cell $and $and$ls180.v:5703$1046 + attribute \src "ls180.v:5813.35-5813.79" + cell $and $and$ls180.v:5813$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5703$1045_Y - connect \Y $and$ls180.v:5703$1046_Y + connect \B $eq$ls180.v:5813$1160_Y + connect \Y $and$ls180.v:5813$1161_Y end - attribute \src "ls180.v:5704.35-5704.79" - cell $and $and$ls180.v:5704$1048 + attribute \src "ls180.v:5814.35-5814.79" + cell $and $and$ls180.v:5814$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5704$1047_Y - connect \Y $and$ls180.v:5704$1048_Y + connect \B $eq$ls180.v:5814$1162_Y + connect \Y $and$ls180.v:5814$1163_Y end - attribute \src "ls180.v:5749.40-5749.81" - cell $and $and$ls180.v:5749$1055 + attribute \src "ls180.v:5883.40-5883.81" + cell $and $and$ls180.v:5883$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239186,10 +240840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5749$1055_Y + connect \Y $and$ls180.v:5883$1173_Y end - attribute \src "ls180.v:5750.50-5750.91" - cell $and $and$ls180.v:5750$1056 + attribute \src "ls180.v:5884.39-5884.80" + cell $and $and$ls180.v:5884$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239197,10 +240851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5750$1056_Y + connect \Y $and$ls180.v:5884$1174_Y end - attribute \src "ls180.v:5751.50-5751.91" - cell $and $and$ls180.v:5751$1057 + attribute \src "ls180.v:5885.39-5885.80" + cell $and $and$ls180.v:5885$1175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239208,10 +240862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5751$1057_Y + connect \Y $and$ls180.v:5885$1175_Y end - attribute \src "ls180.v:5752.29-5752.70" - cell $and $and$ls180.v:5752$1058 + attribute \src "ls180.v:5886.39-5886.80" + cell $and $and$ls180.v:5886$1176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239219,10 +240873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5752$1058_Y + connect \Y $and$ls180.v:5886$1176_Y end - attribute \src "ls180.v:5753.44-5753.85" - cell $and $and$ls180.v:5753$1059 + attribute \src "ls180.v:5887.51-5887.92" + cell $and $and$ls180.v:5887$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239230,10 +240884,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5753$1059_Y + connect \Y $and$ls180.v:5887$1177_Y end - attribute \src "ls180.v:5755.25-5755.64" - cell $and $and$ls180.v:5755$1064 + attribute \src "ls180.v:5888.51-5888.92" + cell $and $and$ls180.v:5888$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [5] + connect \Y $and$ls180.v:5888$1178_Y + end + attribute \src "ls180.v:5889.54-5889.95" + cell $and $and$ls180.v:5889$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [6] + connect \Y $and$ls180.v:5889$1179_Y + end + attribute \src "ls180.v:5890.55-5890.96" + cell $and $and$ls180.v:5890$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [7] + connect \Y $and$ls180.v:5890$1180_Y + end + attribute \src "ls180.v:5892.25-5892.64" + cell $and $and$ls180.v:5892$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239241,76 +240928,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_stb connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5755$1064_Y + connect \Y $and$ls180.v:5892$1188_Y end - attribute \src "ls180.v:5755.24-5755.89" - cell $and $and$ls180.v:5755$1066 + attribute \src "ls180.v:5892.24-5892.89" + cell $and $and$ls180.v:5892$1190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5755$1064_Y - connect \B $not$ls180.v:5755$1065_Y - connect \Y $and$ls180.v:5755$1066_Y + connect \A $and$ls180.v:5892$1188_Y + connect \B $not$ls180.v:5892$1189_Y + connect \Y $and$ls180.v:5892$1190_Y end - attribute \src "ls180.v:5761.31-5761.92" - cell $and $and$ls180.v:5761$1072 + attribute \src "ls180.v:5898.34-5898.95" + cell $and $and$ls180.v:5898$1199 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5761$1072_Y + connect \Y $and$ls180.v:5898$1199_Y end - attribute \src "ls180.v:5761.97-5761.168" - cell $and $and$ls180.v:5761$1073 + attribute \src "ls180.v:5898.100-5898.160" + cell $and $and$ls180.v:5898$1200 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } - connect \B \main_libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:5761$1073_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_interface0_ram_bus_dat_r + connect \Y $and$ls180.v:5898$1200_Y end - attribute \src "ls180.v:5761.174-5761.245" - cell $and $and$ls180.v:5761$1075 + attribute \src "ls180.v:5898.166-5898.226" + cell $and $and$ls180.v:5898$1202 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } - connect \B \main_libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:5761$1075_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_interface1_ram_bus_dat_r + connect \Y $and$ls180.v:5898$1202_Y end - attribute \src "ls180.v:5761.251-5761.301" - cell $and $and$ls180.v:5761$1077 + attribute \src "ls180.v:5898.232-5898.292" + cell $and $and$ls180.v:5898$1204 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } - connect \B \main_wb_sdram_dat_r - connect \Y $and$ls180.v:5761$1077_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_interface2_ram_bus_dat_r + connect \Y $and$ls180.v:5898$1204_Y end - attribute \src "ls180.v:5761.307-5761.372" - cell $and $and$ls180.v:5761$1079 + attribute \src "ls180.v:5898.298-5898.370" + cell $and $and$ls180.v:5898$1206 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \builder_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:5761$1079_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \main_interface0_converted_interface_dat_r + connect \Y $and$ls180.v:5898$1206_Y + end + attribute \src "ls180.v:5898.376-5898.448" + cell $and $and$ls180.v:5898$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } + connect \B \main_interface1_converted_interface_dat_r + connect \Y $and$ls180.v:5898$1208_Y + end + attribute \src "ls180.v:5898.454-5898.529" + cell $and $and$ls180.v:5898$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } + connect \B \main_socbushandler_converted_interface_dat_r + connect \Y $and$ls180.v:5898$1210_Y + end + attribute \src "ls180.v:5898.535-5898.611" + cell $and $and$ls180.v:5898$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } + connect \B \builder_libresocsim_converted_interface_dat_r + connect \Y $and$ls180.v:5898$1212_Y end - attribute \src "ls180.v:5771.39-5771.92" - cell $and $and$ls180.v:5771$1083 + attribute \src "ls180.v:5908.39-5908.92" + cell $and $and$ls180.v:5908$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239318,43 +241038,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5771$1083_Y + connect \Y $and$ls180.v:5908$1216_Y end - attribute \src "ls180.v:5771.38-5771.142" - cell $and $and$ls180.v:5771$1085 + attribute \src "ls180.v:5908.38-5908.142" + cell $and $and$ls180.v:5908$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5771$1083_Y - connect \B $eq$ls180.v:5771$1084_Y - connect \Y $and$ls180.v:5771$1085_Y + connect \A $and$ls180.v:5908$1216_Y + connect \B $eq$ls180.v:5908$1217_Y + connect \Y $and$ls180.v:5908$1218_Y end - attribute \src "ls180.v:5772.39-5772.95" - cell $and $and$ls180.v:5772$1087 + attribute \src "ls180.v:5909.39-5909.95" + cell $and $and$ls180.v:5909$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5772$1086_Y - connect \Y $and$ls180.v:5772$1087_Y + connect \B $not$ls180.v:5909$1219_Y + connect \Y $and$ls180.v:5909$1220_Y end - attribute \src "ls180.v:5772.38-5772.145" - cell $and $and$ls180.v:5772$1089 + attribute \src "ls180.v:5909.38-5909.145" + cell $and $and$ls180.v:5909$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5772$1087_Y - connect \B $eq$ls180.v:5772$1088_Y - connect \Y $and$ls180.v:5772$1089_Y + connect \A $and$ls180.v:5909$1220_Y + connect \B $eq$ls180.v:5909$1221_Y + connect \Y $and$ls180.v:5909$1222_Y end - attribute \src "ls180.v:5774.41-5774.94" - cell $and $and$ls180.v:5774$1090 + attribute \src "ls180.v:5911.41-5911.94" + cell $and $and$ls180.v:5911$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239362,43 +241082,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5774$1090_Y + connect \Y $and$ls180.v:5911$1223_Y end - attribute \src "ls180.v:5774.40-5774.144" - cell $and $and$ls180.v:5774$1092 + attribute \src "ls180.v:5911.40-5911.144" + cell $and $and$ls180.v:5911$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5774$1090_Y - connect \B $eq$ls180.v:5774$1091_Y - connect \Y $and$ls180.v:5774$1092_Y + connect \A $and$ls180.v:5911$1223_Y + connect \B $eq$ls180.v:5911$1224_Y + connect \Y $and$ls180.v:5911$1225_Y end - attribute \src "ls180.v:5775.41-5775.97" - cell $and $and$ls180.v:5775$1094 + attribute \src "ls180.v:5912.41-5912.97" + cell $and $and$ls180.v:5912$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5775$1093_Y - connect \Y $and$ls180.v:5775$1094_Y + connect \B $not$ls180.v:5912$1226_Y + connect \Y $and$ls180.v:5912$1227_Y end - attribute \src "ls180.v:5775.40-5775.147" - cell $and $and$ls180.v:5775$1096 + attribute \src "ls180.v:5912.40-5912.147" + cell $and $and$ls180.v:5912$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5775$1094_Y - connect \B $eq$ls180.v:5775$1095_Y - connect \Y $and$ls180.v:5775$1096_Y + connect \A $and$ls180.v:5912$1227_Y + connect \B $eq$ls180.v:5912$1228_Y + connect \Y $and$ls180.v:5912$1229_Y end - attribute \src "ls180.v:5777.41-5777.94" - cell $and $and$ls180.v:5777$1097 + attribute \src "ls180.v:5914.41-5914.94" + cell $and $and$ls180.v:5914$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239406,43 +241126,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5777$1097_Y + connect \Y $and$ls180.v:5914$1230_Y end - attribute \src "ls180.v:5777.40-5777.144" - cell $and $and$ls180.v:5777$1099 + attribute \src "ls180.v:5914.40-5914.144" + cell $and $and$ls180.v:5914$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5777$1097_Y - connect \B $eq$ls180.v:5777$1098_Y - connect \Y $and$ls180.v:5777$1099_Y + connect \A $and$ls180.v:5914$1230_Y + connect \B $eq$ls180.v:5914$1231_Y + connect \Y $and$ls180.v:5914$1232_Y end - attribute \src "ls180.v:5778.41-5778.97" - cell $and $and$ls180.v:5778$1101 + attribute \src "ls180.v:5915.41-5915.97" + cell $and $and$ls180.v:5915$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5778$1100_Y - connect \Y $and$ls180.v:5778$1101_Y + connect \B $not$ls180.v:5915$1233_Y + connect \Y $and$ls180.v:5915$1234_Y end - attribute \src "ls180.v:5778.40-5778.147" - cell $and $and$ls180.v:5778$1103 + attribute \src "ls180.v:5915.40-5915.147" + cell $and $and$ls180.v:5915$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5778$1101_Y - connect \B $eq$ls180.v:5778$1102_Y - connect \Y $and$ls180.v:5778$1103_Y + connect \A $and$ls180.v:5915$1234_Y + connect \B $eq$ls180.v:5915$1235_Y + connect \Y $and$ls180.v:5915$1236_Y end - attribute \src "ls180.v:5780.41-5780.94" - cell $and $and$ls180.v:5780$1104 + attribute \src "ls180.v:5917.41-5917.94" + cell $and $and$ls180.v:5917$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239450,43 +241170,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5780$1104_Y + connect \Y $and$ls180.v:5917$1237_Y end - attribute \src "ls180.v:5780.40-5780.144" - cell $and $and$ls180.v:5780$1106 + attribute \src "ls180.v:5917.40-5917.144" + cell $and $and$ls180.v:5917$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5780$1104_Y - connect \B $eq$ls180.v:5780$1105_Y - connect \Y $and$ls180.v:5780$1106_Y + connect \A $and$ls180.v:5917$1237_Y + connect \B $eq$ls180.v:5917$1238_Y + connect \Y $and$ls180.v:5917$1239_Y end - attribute \src "ls180.v:5781.41-5781.97" - cell $and $and$ls180.v:5781$1108 + attribute \src "ls180.v:5918.41-5918.97" + cell $and $and$ls180.v:5918$1241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5781$1107_Y - connect \Y $and$ls180.v:5781$1108_Y + connect \B $not$ls180.v:5918$1240_Y + connect \Y $and$ls180.v:5918$1241_Y end - attribute \src "ls180.v:5781.40-5781.147" - cell $and $and$ls180.v:5781$1110 + attribute \src "ls180.v:5918.40-5918.147" + cell $and $and$ls180.v:5918$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5781$1108_Y - connect \B $eq$ls180.v:5781$1109_Y - connect \Y $and$ls180.v:5781$1110_Y + connect \A $and$ls180.v:5918$1241_Y + connect \B $eq$ls180.v:5918$1242_Y + connect \Y $and$ls180.v:5918$1243_Y end - attribute \src "ls180.v:5783.41-5783.94" - cell $and $and$ls180.v:5783$1111 + attribute \src "ls180.v:5920.41-5920.94" + cell $and $and$ls180.v:5920$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239494,43 +241214,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5783$1111_Y + connect \Y $and$ls180.v:5920$1244_Y end - attribute \src "ls180.v:5783.40-5783.144" - cell $and $and$ls180.v:5783$1113 + attribute \src "ls180.v:5920.40-5920.144" + cell $and $and$ls180.v:5920$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5783$1111_Y - connect \B $eq$ls180.v:5783$1112_Y - connect \Y $and$ls180.v:5783$1113_Y + connect \A $and$ls180.v:5920$1244_Y + connect \B $eq$ls180.v:5920$1245_Y + connect \Y $and$ls180.v:5920$1246_Y end - attribute \src "ls180.v:5784.41-5784.97" - cell $and $and$ls180.v:5784$1115 + attribute \src "ls180.v:5921.41-5921.97" + cell $and $and$ls180.v:5921$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5784$1114_Y - connect \Y $and$ls180.v:5784$1115_Y + connect \B $not$ls180.v:5921$1247_Y + connect \Y $and$ls180.v:5921$1248_Y end - attribute \src "ls180.v:5784.40-5784.147" - cell $and $and$ls180.v:5784$1117 + attribute \src "ls180.v:5921.40-5921.147" + cell $and $and$ls180.v:5921$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5784$1115_Y - connect \B $eq$ls180.v:5784$1116_Y - connect \Y $and$ls180.v:5784$1117_Y + connect \A $and$ls180.v:5921$1248_Y + connect \B $eq$ls180.v:5921$1249_Y + connect \Y $and$ls180.v:5921$1250_Y end - attribute \src "ls180.v:5786.44-5786.97" - cell $and $and$ls180.v:5786$1118 + attribute \src "ls180.v:5923.44-5923.97" + cell $and $and$ls180.v:5923$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239538,43 +241258,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5786$1118_Y + connect \Y $and$ls180.v:5923$1251_Y end - attribute \src "ls180.v:5786.43-5786.147" - cell $and $and$ls180.v:5786$1120 + attribute \src "ls180.v:5923.43-5923.147" + cell $and $and$ls180.v:5923$1253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5786$1118_Y - connect \B $eq$ls180.v:5786$1119_Y - connect \Y $and$ls180.v:5786$1120_Y + connect \A $and$ls180.v:5923$1251_Y + connect \B $eq$ls180.v:5923$1252_Y + connect \Y $and$ls180.v:5923$1253_Y end - attribute \src "ls180.v:5787.44-5787.100" - cell $and $and$ls180.v:5787$1122 + attribute \src "ls180.v:5924.44-5924.100" + cell $and $and$ls180.v:5924$1255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5787$1121_Y - connect \Y $and$ls180.v:5787$1122_Y + connect \B $not$ls180.v:5924$1254_Y + connect \Y $and$ls180.v:5924$1255_Y end - attribute \src "ls180.v:5787.43-5787.150" - cell $and $and$ls180.v:5787$1124 + attribute \src "ls180.v:5924.43-5924.150" + cell $and $and$ls180.v:5924$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5787$1122_Y - connect \B $eq$ls180.v:5787$1123_Y - connect \Y $and$ls180.v:5787$1124_Y + connect \A $and$ls180.v:5924$1255_Y + connect \B $eq$ls180.v:5924$1256_Y + connect \Y $and$ls180.v:5924$1257_Y end - attribute \src "ls180.v:5789.44-5789.97" - cell $and $and$ls180.v:5789$1125 + attribute \src "ls180.v:5926.44-5926.97" + cell $and $and$ls180.v:5926$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239582,43 +241302,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5789$1125_Y + connect \Y $and$ls180.v:5926$1258_Y end - attribute \src "ls180.v:5789.43-5789.147" - cell $and $and$ls180.v:5789$1127 + attribute \src "ls180.v:5926.43-5926.147" + cell $and $and$ls180.v:5926$1260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5789$1125_Y - connect \B $eq$ls180.v:5789$1126_Y - connect \Y $and$ls180.v:5789$1127_Y + connect \A $and$ls180.v:5926$1258_Y + connect \B $eq$ls180.v:5926$1259_Y + connect \Y $and$ls180.v:5926$1260_Y end - attribute \src "ls180.v:5790.44-5790.100" - cell $and $and$ls180.v:5790$1129 + attribute \src "ls180.v:5927.44-5927.100" + cell $and $and$ls180.v:5927$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5790$1128_Y - connect \Y $and$ls180.v:5790$1129_Y + connect \B $not$ls180.v:5927$1261_Y + connect \Y $and$ls180.v:5927$1262_Y end - attribute \src "ls180.v:5790.43-5790.150" - cell $and $and$ls180.v:5790$1131 + attribute \src "ls180.v:5927.43-5927.150" + cell $and $and$ls180.v:5927$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5790$1129_Y - connect \B $eq$ls180.v:5790$1130_Y - connect \Y $and$ls180.v:5790$1131_Y + connect \A $and$ls180.v:5927$1262_Y + connect \B $eq$ls180.v:5927$1263_Y + connect \Y $and$ls180.v:5927$1264_Y end - attribute \src "ls180.v:5792.44-5792.97" - cell $and $and$ls180.v:5792$1132 + attribute \src "ls180.v:5929.44-5929.97" + cell $and $and$ls180.v:5929$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239626,43 +241346,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5792$1132_Y + connect \Y $and$ls180.v:5929$1265_Y end - attribute \src "ls180.v:5792.43-5792.147" - cell $and $and$ls180.v:5792$1134 + attribute \src "ls180.v:5929.43-5929.147" + cell $and $and$ls180.v:5929$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5792$1132_Y - connect \B $eq$ls180.v:5792$1133_Y - connect \Y $and$ls180.v:5792$1134_Y + connect \A $and$ls180.v:5929$1265_Y + connect \B $eq$ls180.v:5929$1266_Y + connect \Y $and$ls180.v:5929$1267_Y end - attribute \src "ls180.v:5793.44-5793.100" - cell $and $and$ls180.v:5793$1136 + attribute \src "ls180.v:5930.44-5930.100" + cell $and $and$ls180.v:5930$1269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5793$1135_Y - connect \Y $and$ls180.v:5793$1136_Y + connect \B $not$ls180.v:5930$1268_Y + connect \Y $and$ls180.v:5930$1269_Y end - attribute \src "ls180.v:5793.43-5793.150" - cell $and $and$ls180.v:5793$1138 + attribute \src "ls180.v:5930.43-5930.150" + cell $and $and$ls180.v:5930$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5793$1136_Y - connect \B $eq$ls180.v:5793$1137_Y - connect \Y $and$ls180.v:5793$1138_Y + connect \A $and$ls180.v:5930$1269_Y + connect \B $eq$ls180.v:5930$1270_Y + connect \Y $and$ls180.v:5930$1271_Y end - attribute \src "ls180.v:5795.44-5795.97" - cell $and $and$ls180.v:5795$1139 + attribute \src "ls180.v:5932.44-5932.97" + cell $and $and$ls180.v:5932$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239670,43 +241390,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5795$1139_Y + connect \Y $and$ls180.v:5932$1272_Y end - attribute \src "ls180.v:5795.43-5795.147" - cell $and $and$ls180.v:5795$1141 + attribute \src "ls180.v:5932.43-5932.147" + cell $and $and$ls180.v:5932$1274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5795$1139_Y - connect \B $eq$ls180.v:5795$1140_Y - connect \Y $and$ls180.v:5795$1141_Y + connect \A $and$ls180.v:5932$1272_Y + connect \B $eq$ls180.v:5932$1273_Y + connect \Y $and$ls180.v:5932$1274_Y end - attribute \src "ls180.v:5796.44-5796.100" - cell $and $and$ls180.v:5796$1143 + attribute \src "ls180.v:5933.44-5933.100" + cell $and $and$ls180.v:5933$1276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5796$1142_Y - connect \Y $and$ls180.v:5796$1143_Y + connect \B $not$ls180.v:5933$1275_Y + connect \Y $and$ls180.v:5933$1276_Y end - attribute \src "ls180.v:5796.43-5796.150" - cell $and $and$ls180.v:5796$1145 + attribute \src "ls180.v:5933.43-5933.150" + cell $and $and$ls180.v:5933$1278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5796$1143_Y - connect \B $eq$ls180.v:5796$1144_Y - connect \Y $and$ls180.v:5796$1145_Y + connect \A $and$ls180.v:5933$1276_Y + connect \B $eq$ls180.v:5933$1277_Y + connect \Y $and$ls180.v:5933$1278_Y end - attribute \src "ls180.v:5809.36-5809.89" - cell $and $and$ls180.v:5809$1147 + attribute \src "ls180.v:5946.36-5946.89" + cell $and $and$ls180.v:5946$1280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239714,43 +241434,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5809$1147_Y + connect \Y $and$ls180.v:5946$1280_Y end - attribute \src "ls180.v:5809.35-5809.139" - cell $and $and$ls180.v:5809$1149 + attribute \src "ls180.v:5946.35-5946.139" + cell $and $and$ls180.v:5946$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5809$1147_Y - connect \B $eq$ls180.v:5809$1148_Y - connect \Y $and$ls180.v:5809$1149_Y + connect \A $and$ls180.v:5946$1280_Y + connect \B $eq$ls180.v:5946$1281_Y + connect \Y $and$ls180.v:5946$1282_Y end - attribute \src "ls180.v:5810.36-5810.92" - cell $and $and$ls180.v:5810$1151 + attribute \src "ls180.v:5947.36-5947.92" + cell $and $and$ls180.v:5947$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5810$1150_Y - connect \Y $and$ls180.v:5810$1151_Y + connect \B $not$ls180.v:5947$1283_Y + connect \Y $and$ls180.v:5947$1284_Y end - attribute \src "ls180.v:5810.35-5810.142" - cell $and $and$ls180.v:5810$1153 + attribute \src "ls180.v:5947.35-5947.142" + cell $and $and$ls180.v:5947$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5810$1151_Y - connect \B $eq$ls180.v:5810$1152_Y - connect \Y $and$ls180.v:5810$1153_Y + connect \A $and$ls180.v:5947$1284_Y + connect \B $eq$ls180.v:5947$1285_Y + connect \Y $and$ls180.v:5947$1286_Y end - attribute \src "ls180.v:5812.36-5812.89" - cell $and $and$ls180.v:5812$1154 + attribute \src "ls180.v:5949.36-5949.89" + cell $and $and$ls180.v:5949$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239758,43 +241478,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5812$1154_Y + connect \Y $and$ls180.v:5949$1287_Y end - attribute \src "ls180.v:5812.35-5812.139" - cell $and $and$ls180.v:5812$1156 + attribute \src "ls180.v:5949.35-5949.139" + cell $and $and$ls180.v:5949$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5812$1154_Y - connect \B $eq$ls180.v:5812$1155_Y - connect \Y $and$ls180.v:5812$1156_Y + connect \A $and$ls180.v:5949$1287_Y + connect \B $eq$ls180.v:5949$1288_Y + connect \Y $and$ls180.v:5949$1289_Y end - attribute \src "ls180.v:5813.36-5813.92" - cell $and $and$ls180.v:5813$1158 + attribute \src "ls180.v:5950.36-5950.92" + cell $and $and$ls180.v:5950$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5813$1157_Y - connect \Y $and$ls180.v:5813$1158_Y + connect \B $not$ls180.v:5950$1290_Y + connect \Y $and$ls180.v:5950$1291_Y end - attribute \src "ls180.v:5813.35-5813.142" - cell $and $and$ls180.v:5813$1160 + attribute \src "ls180.v:5950.35-5950.142" + cell $and $and$ls180.v:5950$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5813$1158_Y - connect \B $eq$ls180.v:5813$1159_Y - connect \Y $and$ls180.v:5813$1160_Y + connect \A $and$ls180.v:5950$1291_Y + connect \B $eq$ls180.v:5950$1292_Y + connect \Y $and$ls180.v:5950$1293_Y end - attribute \src "ls180.v:5815.36-5815.89" - cell $and $and$ls180.v:5815$1161 + attribute \src "ls180.v:5952.36-5952.89" + cell $and $and$ls180.v:5952$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239802,43 +241522,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5815$1161_Y + connect \Y $and$ls180.v:5952$1294_Y end - attribute \src "ls180.v:5815.35-5815.139" - cell $and $and$ls180.v:5815$1163 + attribute \src "ls180.v:5952.35-5952.139" + cell $and $and$ls180.v:5952$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5815$1161_Y - connect \B $eq$ls180.v:5815$1162_Y - connect \Y $and$ls180.v:5815$1163_Y + connect \A $and$ls180.v:5952$1294_Y + connect \B $eq$ls180.v:5952$1295_Y + connect \Y $and$ls180.v:5952$1296_Y end - attribute \src "ls180.v:5816.36-5816.92" - cell $and $and$ls180.v:5816$1165 + attribute \src "ls180.v:5953.36-5953.92" + cell $and $and$ls180.v:5953$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5816$1164_Y - connect \Y $and$ls180.v:5816$1165_Y + connect \B $not$ls180.v:5953$1297_Y + connect \Y $and$ls180.v:5953$1298_Y end - attribute \src "ls180.v:5816.35-5816.142" - cell $and $and$ls180.v:5816$1167 + attribute \src "ls180.v:5953.35-5953.142" + cell $and $and$ls180.v:5953$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5816$1165_Y - connect \B $eq$ls180.v:5816$1166_Y - connect \Y $and$ls180.v:5816$1167_Y + connect \A $and$ls180.v:5953$1298_Y + connect \B $eq$ls180.v:5953$1299_Y + connect \Y $and$ls180.v:5953$1300_Y end - attribute \src "ls180.v:5818.36-5818.89" - cell $and $and$ls180.v:5818$1168 + attribute \src "ls180.v:5955.36-5955.89" + cell $and $and$ls180.v:5955$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239846,43 +241566,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5818$1168_Y + connect \Y $and$ls180.v:5955$1301_Y end - attribute \src "ls180.v:5818.35-5818.139" - cell $and $and$ls180.v:5818$1170 + attribute \src "ls180.v:5955.35-5955.139" + cell $and $and$ls180.v:5955$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5818$1168_Y - connect \B $eq$ls180.v:5818$1169_Y - connect \Y $and$ls180.v:5818$1170_Y + connect \A $and$ls180.v:5955$1301_Y + connect \B $eq$ls180.v:5955$1302_Y + connect \Y $and$ls180.v:5955$1303_Y end - attribute \src "ls180.v:5819.36-5819.92" - cell $and $and$ls180.v:5819$1172 + attribute \src "ls180.v:5956.36-5956.92" + cell $and $and$ls180.v:5956$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5819$1171_Y - connect \Y $and$ls180.v:5819$1172_Y + connect \B $not$ls180.v:5956$1304_Y + connect \Y $and$ls180.v:5956$1305_Y end - attribute \src "ls180.v:5819.35-5819.142" - cell $and $and$ls180.v:5819$1174 + attribute \src "ls180.v:5956.35-5956.142" + cell $and $and$ls180.v:5956$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5819$1172_Y - connect \B $eq$ls180.v:5819$1173_Y - connect \Y $and$ls180.v:5819$1174_Y + connect \A $and$ls180.v:5956$1305_Y + connect \B $eq$ls180.v:5956$1306_Y + connect \Y $and$ls180.v:5956$1307_Y end - attribute \src "ls180.v:5821.37-5821.90" - cell $and $and$ls180.v:5821$1175 + attribute \src "ls180.v:5958.37-5958.90" + cell $and $and$ls180.v:5958$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239890,43 +241610,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5821$1175_Y + connect \Y $and$ls180.v:5958$1308_Y end - attribute \src "ls180.v:5821.36-5821.140" - cell $and $and$ls180.v:5821$1177 + attribute \src "ls180.v:5958.36-5958.140" + cell $and $and$ls180.v:5958$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5821$1175_Y - connect \B $eq$ls180.v:5821$1176_Y - connect \Y $and$ls180.v:5821$1177_Y + connect \A $and$ls180.v:5958$1308_Y + connect \B $eq$ls180.v:5958$1309_Y + connect \Y $and$ls180.v:5958$1310_Y end - attribute \src "ls180.v:5822.37-5822.93" - cell $and $and$ls180.v:5822$1179 + attribute \src "ls180.v:5959.37-5959.93" + cell $and $and$ls180.v:5959$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5822$1178_Y - connect \Y $and$ls180.v:5822$1179_Y + connect \B $not$ls180.v:5959$1311_Y + connect \Y $and$ls180.v:5959$1312_Y end - attribute \src "ls180.v:5822.36-5822.143" - cell $and $and$ls180.v:5822$1181 + attribute \src "ls180.v:5959.36-5959.143" + cell $and $and$ls180.v:5959$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5822$1179_Y - connect \B $eq$ls180.v:5822$1180_Y - connect \Y $and$ls180.v:5822$1181_Y + connect \A $and$ls180.v:5959$1312_Y + connect \B $eq$ls180.v:5959$1313_Y + connect \Y $and$ls180.v:5959$1314_Y end - attribute \src "ls180.v:5824.37-5824.90" - cell $and $and$ls180.v:5824$1182 + attribute \src "ls180.v:5961.37-5961.90" + cell $and $and$ls180.v:5961$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239934,43 +241654,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5824$1182_Y + connect \Y $and$ls180.v:5961$1315_Y end - attribute \src "ls180.v:5824.36-5824.140" - cell $and $and$ls180.v:5824$1184 + attribute \src "ls180.v:5961.36-5961.140" + cell $and $and$ls180.v:5961$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5824$1182_Y - connect \B $eq$ls180.v:5824$1183_Y - connect \Y $and$ls180.v:5824$1184_Y + connect \A $and$ls180.v:5961$1315_Y + connect \B $eq$ls180.v:5961$1316_Y + connect \Y $and$ls180.v:5961$1317_Y end - attribute \src "ls180.v:5825.37-5825.93" - cell $and $and$ls180.v:5825$1186 + attribute \src "ls180.v:5962.37-5962.93" + cell $and $and$ls180.v:5962$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5825$1185_Y - connect \Y $and$ls180.v:5825$1186_Y + connect \B $not$ls180.v:5962$1318_Y + connect \Y $and$ls180.v:5962$1319_Y end - attribute \src "ls180.v:5825.36-5825.143" - cell $and $and$ls180.v:5825$1188 + attribute \src "ls180.v:5962.36-5962.143" + cell $and $and$ls180.v:5962$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5825$1186_Y - connect \B $eq$ls180.v:5825$1187_Y - connect \Y $and$ls180.v:5825$1188_Y + connect \A $and$ls180.v:5962$1319_Y + connect \B $eq$ls180.v:5962$1320_Y + connect \Y $and$ls180.v:5962$1321_Y end - attribute \src "ls180.v:5835.35-5835.88" - cell $and $and$ls180.v:5835$1190 + attribute \src "ls180.v:5972.35-5972.88" + cell $and $and$ls180.v:5972$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239978,43 +241698,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5835$1190_Y + connect \Y $and$ls180.v:5972$1323_Y end - attribute \src "ls180.v:5835.34-5835.136" - cell $and $and$ls180.v:5835$1192 + attribute \src "ls180.v:5972.34-5972.136" + cell $and $and$ls180.v:5972$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5835$1190_Y - connect \B $eq$ls180.v:5835$1191_Y - connect \Y $and$ls180.v:5835$1192_Y + connect \A $and$ls180.v:5972$1323_Y + connect \B $eq$ls180.v:5972$1324_Y + connect \Y $and$ls180.v:5972$1325_Y end - attribute \src "ls180.v:5836.35-5836.91" - cell $and $and$ls180.v:5836$1194 + attribute \src "ls180.v:5973.35-5973.91" + cell $and $and$ls180.v:5973$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5836$1193_Y - connect \Y $and$ls180.v:5836$1194_Y + connect \B $not$ls180.v:5973$1326_Y + connect \Y $and$ls180.v:5973$1327_Y end - attribute \src "ls180.v:5836.34-5836.139" - cell $and $and$ls180.v:5836$1196 + attribute \src "ls180.v:5973.34-5973.139" + cell $and $and$ls180.v:5973$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5836$1194_Y - connect \B $eq$ls180.v:5836$1195_Y - connect \Y $and$ls180.v:5836$1196_Y + connect \A $and$ls180.v:5973$1327_Y + connect \B $eq$ls180.v:5973$1328_Y + connect \Y $and$ls180.v:5973$1329_Y end - attribute \src "ls180.v:5838.34-5838.87" - cell $and $and$ls180.v:5838$1197 + attribute \src "ls180.v:5975.34-5975.87" + cell $and $and$ls180.v:5975$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240022,43 +241742,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5838$1197_Y + connect \Y $and$ls180.v:5975$1330_Y end - attribute \src "ls180.v:5838.33-5838.135" - cell $and $and$ls180.v:5838$1199 + attribute \src "ls180.v:5975.33-5975.135" + cell $and $and$ls180.v:5975$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5838$1197_Y - connect \B $eq$ls180.v:5838$1198_Y - connect \Y $and$ls180.v:5838$1199_Y + connect \A $and$ls180.v:5975$1330_Y + connect \B $eq$ls180.v:5975$1331_Y + connect \Y $and$ls180.v:5975$1332_Y end - attribute \src "ls180.v:5839.34-5839.90" - cell $and $and$ls180.v:5839$1201 + attribute \src "ls180.v:5976.34-5976.90" + cell $and $and$ls180.v:5976$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5839$1200_Y - connect \Y $and$ls180.v:5839$1201_Y + connect \B $not$ls180.v:5976$1333_Y + connect \Y $and$ls180.v:5976$1334_Y end - attribute \src "ls180.v:5839.33-5839.138" - cell $and $and$ls180.v:5839$1203 + attribute \src "ls180.v:5976.33-5976.138" + cell $and $and$ls180.v:5976$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5839$1201_Y - connect \B $eq$ls180.v:5839$1202_Y - connect \Y $and$ls180.v:5839$1203_Y + connect \A $and$ls180.v:5976$1334_Y + connect \B $eq$ls180.v:5976$1335_Y + connect \Y $and$ls180.v:5976$1336_Y end - attribute \src "ls180.v:5849.40-5849.93" - cell $and $and$ls180.v:5849$1205 + attribute \src "ls180.v:5986.40-5986.93" + cell $and $and$ls180.v:5986$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240066,43 +241786,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5849$1205_Y + connect \Y $and$ls180.v:5986$1338_Y end - attribute \src "ls180.v:5849.39-5849.143" - cell $and $and$ls180.v:5849$1207 + attribute \src "ls180.v:5986.39-5986.143" + cell $and $and$ls180.v:5986$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5849$1205_Y - connect \B $eq$ls180.v:5849$1206_Y - connect \Y $and$ls180.v:5849$1207_Y + connect \A $and$ls180.v:5986$1338_Y + connect \B $eq$ls180.v:5986$1339_Y + connect \Y $and$ls180.v:5986$1340_Y end - attribute \src "ls180.v:5850.40-5850.96" - cell $and $and$ls180.v:5850$1209 + attribute \src "ls180.v:5987.40-5987.96" + cell $and $and$ls180.v:5987$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5850$1208_Y - connect \Y $and$ls180.v:5850$1209_Y + connect \B $not$ls180.v:5987$1341_Y + connect \Y $and$ls180.v:5987$1342_Y end - attribute \src "ls180.v:5850.39-5850.146" - cell $and $and$ls180.v:5850$1211 + attribute \src "ls180.v:5987.39-5987.146" + cell $and $and$ls180.v:5987$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5850$1209_Y - connect \B $eq$ls180.v:5850$1210_Y - connect \Y $and$ls180.v:5850$1211_Y + connect \A $and$ls180.v:5987$1342_Y + connect \B $eq$ls180.v:5987$1343_Y + connect \Y $and$ls180.v:5987$1344_Y end - attribute \src "ls180.v:5852.39-5852.92" - cell $and $and$ls180.v:5852$1212 + attribute \src "ls180.v:5989.39-5989.92" + cell $and $and$ls180.v:5989$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240110,43 +241830,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5852$1212_Y + connect \Y $and$ls180.v:5989$1345_Y end - attribute \src "ls180.v:5852.38-5852.142" - cell $and $and$ls180.v:5852$1214 + attribute \src "ls180.v:5989.38-5989.142" + cell $and $and$ls180.v:5989$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5852$1212_Y - connect \B $eq$ls180.v:5852$1213_Y - connect \Y $and$ls180.v:5852$1214_Y + connect \A $and$ls180.v:5989$1345_Y + connect \B $eq$ls180.v:5989$1346_Y + connect \Y $and$ls180.v:5989$1347_Y end - attribute \src "ls180.v:5853.39-5853.95" - cell $and $and$ls180.v:5853$1216 + attribute \src "ls180.v:5990.39-5990.95" + cell $and $and$ls180.v:5990$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5853$1215_Y - connect \Y $and$ls180.v:5853$1216_Y + connect \B $not$ls180.v:5990$1348_Y + connect \Y $and$ls180.v:5990$1349_Y end - attribute \src "ls180.v:5853.38-5853.145" - cell $and $and$ls180.v:5853$1218 + attribute \src "ls180.v:5990.38-5990.145" + cell $and $and$ls180.v:5990$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5853$1216_Y - connect \B $eq$ls180.v:5853$1217_Y - connect \Y $and$ls180.v:5853$1218_Y + connect \A $and$ls180.v:5990$1349_Y + connect \B $eq$ls180.v:5990$1350_Y + connect \Y $and$ls180.v:5990$1351_Y end - attribute \src "ls180.v:5855.39-5855.92" - cell $and $and$ls180.v:5855$1219 + attribute \src "ls180.v:5992.39-5992.92" + cell $and $and$ls180.v:5992$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240154,43 +241874,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5855$1219_Y + connect \Y $and$ls180.v:5992$1352_Y end - attribute \src "ls180.v:5855.38-5855.142" - cell $and $and$ls180.v:5855$1221 + attribute \src "ls180.v:5992.38-5992.142" + cell $and $and$ls180.v:5992$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5855$1219_Y - connect \B $eq$ls180.v:5855$1220_Y - connect \Y $and$ls180.v:5855$1221_Y + connect \A $and$ls180.v:5992$1352_Y + connect \B $eq$ls180.v:5992$1353_Y + connect \Y $and$ls180.v:5992$1354_Y end - attribute \src "ls180.v:5856.39-5856.95" - cell $and $and$ls180.v:5856$1223 + attribute \src "ls180.v:5993.39-5993.95" + cell $and $and$ls180.v:5993$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5856$1222_Y - connect \Y $and$ls180.v:5856$1223_Y + connect \B $not$ls180.v:5993$1355_Y + connect \Y $and$ls180.v:5993$1356_Y end - attribute \src "ls180.v:5856.38-5856.145" - cell $and $and$ls180.v:5856$1225 + attribute \src "ls180.v:5993.38-5993.145" + cell $and $and$ls180.v:5993$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5856$1223_Y - connect \B $eq$ls180.v:5856$1224_Y - connect \Y $and$ls180.v:5856$1225_Y + connect \A $and$ls180.v:5993$1356_Y + connect \B $eq$ls180.v:5993$1357_Y + connect \Y $and$ls180.v:5993$1358_Y end - attribute \src "ls180.v:5858.39-5858.92" - cell $and $and$ls180.v:5858$1226 + attribute \src "ls180.v:5995.39-5995.92" + cell $and $and$ls180.v:5995$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240198,43 +241918,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5858$1226_Y + connect \Y $and$ls180.v:5995$1359_Y end - attribute \src "ls180.v:5858.38-5858.142" - cell $and $and$ls180.v:5858$1228 + attribute \src "ls180.v:5995.38-5995.142" + cell $and $and$ls180.v:5995$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5858$1226_Y - connect \B $eq$ls180.v:5858$1227_Y - connect \Y $and$ls180.v:5858$1228_Y + connect \A $and$ls180.v:5995$1359_Y + connect \B $eq$ls180.v:5995$1360_Y + connect \Y $and$ls180.v:5995$1361_Y end - attribute \src "ls180.v:5859.39-5859.95" - cell $and $and$ls180.v:5859$1230 + attribute \src "ls180.v:5996.39-5996.95" + cell $and $and$ls180.v:5996$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5859$1229_Y - connect \Y $and$ls180.v:5859$1230_Y + connect \B $not$ls180.v:5996$1362_Y + connect \Y $and$ls180.v:5996$1363_Y end - attribute \src "ls180.v:5859.38-5859.145" - cell $and $and$ls180.v:5859$1232 + attribute \src "ls180.v:5996.38-5996.145" + cell $and $and$ls180.v:5996$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5859$1230_Y - connect \B $eq$ls180.v:5859$1231_Y - connect \Y $and$ls180.v:5859$1232_Y + connect \A $and$ls180.v:5996$1363_Y + connect \B $eq$ls180.v:5996$1364_Y + connect \Y $and$ls180.v:5996$1365_Y end - attribute \src "ls180.v:5861.39-5861.92" - cell $and $and$ls180.v:5861$1233 + attribute \src "ls180.v:5998.39-5998.92" + cell $and $and$ls180.v:5998$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240242,43 +241962,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5861$1233_Y + connect \Y $and$ls180.v:5998$1366_Y end - attribute \src "ls180.v:5861.38-5861.142" - cell $and $and$ls180.v:5861$1235 + attribute \src "ls180.v:5998.38-5998.142" + cell $and $and$ls180.v:5998$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5861$1233_Y - connect \B $eq$ls180.v:5861$1234_Y - connect \Y $and$ls180.v:5861$1235_Y + connect \A $and$ls180.v:5998$1366_Y + connect \B $eq$ls180.v:5998$1367_Y + connect \Y $and$ls180.v:5998$1368_Y end - attribute \src "ls180.v:5862.39-5862.95" - cell $and $and$ls180.v:5862$1237 + attribute \src "ls180.v:5999.39-5999.95" + cell $and $and$ls180.v:5999$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5862$1236_Y - connect \Y $and$ls180.v:5862$1237_Y + connect \B $not$ls180.v:5999$1369_Y + connect \Y $and$ls180.v:5999$1370_Y end - attribute \src "ls180.v:5862.38-5862.145" - cell $and $and$ls180.v:5862$1239 + attribute \src "ls180.v:5999.38-5999.145" + cell $and $and$ls180.v:5999$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5862$1237_Y - connect \B $eq$ls180.v:5862$1238_Y - connect \Y $and$ls180.v:5862$1239_Y + connect \A $and$ls180.v:5999$1370_Y + connect \B $eq$ls180.v:5999$1371_Y + connect \Y $and$ls180.v:5999$1372_Y end - attribute \src "ls180.v:5864.40-5864.93" - cell $and $and$ls180.v:5864$1240 + attribute \src "ls180.v:6001.40-6001.93" + cell $and $and$ls180.v:6001$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240286,43 +242006,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5864$1240_Y + connect \Y $and$ls180.v:6001$1373_Y end - attribute \src "ls180.v:5864.39-5864.143" - cell $and $and$ls180.v:5864$1242 + attribute \src "ls180.v:6001.39-6001.143" + cell $and $and$ls180.v:6001$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5864$1240_Y - connect \B $eq$ls180.v:5864$1241_Y - connect \Y $and$ls180.v:5864$1242_Y + connect \A $and$ls180.v:6001$1373_Y + connect \B $eq$ls180.v:6001$1374_Y + connect \Y $and$ls180.v:6001$1375_Y end - attribute \src "ls180.v:5865.40-5865.96" - cell $and $and$ls180.v:5865$1244 + attribute \src "ls180.v:6002.40-6002.96" + cell $and $and$ls180.v:6002$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5865$1243_Y - connect \Y $and$ls180.v:5865$1244_Y + connect \B $not$ls180.v:6002$1376_Y + connect \Y $and$ls180.v:6002$1377_Y end - attribute \src "ls180.v:5865.39-5865.146" - cell $and $and$ls180.v:5865$1246 + attribute \src "ls180.v:6002.39-6002.146" + cell $and $and$ls180.v:6002$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5865$1244_Y - connect \B $eq$ls180.v:5865$1245_Y - connect \Y $and$ls180.v:5865$1246_Y + connect \A $and$ls180.v:6002$1377_Y + connect \B $eq$ls180.v:6002$1378_Y + connect \Y $and$ls180.v:6002$1379_Y end - attribute \src "ls180.v:5867.40-5867.93" - cell $and $and$ls180.v:5867$1247 + attribute \src "ls180.v:6004.40-6004.93" + cell $and $and$ls180.v:6004$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240330,43 +242050,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5867$1247_Y + connect \Y $and$ls180.v:6004$1380_Y end - attribute \src "ls180.v:5867.39-5867.143" - cell $and $and$ls180.v:5867$1249 + attribute \src "ls180.v:6004.39-6004.143" + cell $and $and$ls180.v:6004$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5867$1247_Y - connect \B $eq$ls180.v:5867$1248_Y - connect \Y $and$ls180.v:5867$1249_Y + connect \A $and$ls180.v:6004$1380_Y + connect \B $eq$ls180.v:6004$1381_Y + connect \Y $and$ls180.v:6004$1382_Y end - attribute \src "ls180.v:5868.40-5868.96" - cell $and $and$ls180.v:5868$1251 + attribute \src "ls180.v:6005.40-6005.96" + cell $and $and$ls180.v:6005$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5868$1250_Y - connect \Y $and$ls180.v:5868$1251_Y + connect \B $not$ls180.v:6005$1383_Y + connect \Y $and$ls180.v:6005$1384_Y end - attribute \src "ls180.v:5868.39-5868.146" - cell $and $and$ls180.v:5868$1253 + attribute \src "ls180.v:6005.39-6005.146" + cell $and $and$ls180.v:6005$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5868$1251_Y - connect \B $eq$ls180.v:5868$1252_Y - connect \Y $and$ls180.v:5868$1253_Y + connect \A $and$ls180.v:6005$1384_Y + connect \B $eq$ls180.v:6005$1385_Y + connect \Y $and$ls180.v:6005$1386_Y end - attribute \src "ls180.v:5870.40-5870.93" - cell $and $and$ls180.v:5870$1254 + attribute \src "ls180.v:6007.40-6007.93" + cell $and $and$ls180.v:6007$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240374,43 +242094,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5870$1254_Y + connect \Y $and$ls180.v:6007$1387_Y end - attribute \src "ls180.v:5870.39-5870.143" - cell $and $and$ls180.v:5870$1256 + attribute \src "ls180.v:6007.39-6007.143" + cell $and $and$ls180.v:6007$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5870$1254_Y - connect \B $eq$ls180.v:5870$1255_Y - connect \Y $and$ls180.v:5870$1256_Y + connect \A $and$ls180.v:6007$1387_Y + connect \B $eq$ls180.v:6007$1388_Y + connect \Y $and$ls180.v:6007$1389_Y end - attribute \src "ls180.v:5871.40-5871.96" - cell $and $and$ls180.v:5871$1258 + attribute \src "ls180.v:6008.40-6008.96" + cell $and $and$ls180.v:6008$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5871$1257_Y - connect \Y $and$ls180.v:5871$1258_Y + connect \B $not$ls180.v:6008$1390_Y + connect \Y $and$ls180.v:6008$1391_Y end - attribute \src "ls180.v:5871.39-5871.146" - cell $and $and$ls180.v:5871$1260 + attribute \src "ls180.v:6008.39-6008.146" + cell $and $and$ls180.v:6008$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5871$1258_Y - connect \B $eq$ls180.v:5871$1259_Y - connect \Y $and$ls180.v:5871$1260_Y + connect \A $and$ls180.v:6008$1391_Y + connect \B $eq$ls180.v:6008$1392_Y + connect \Y $and$ls180.v:6008$1393_Y end - attribute \src "ls180.v:5873.40-5873.93" - cell $and $and$ls180.v:5873$1261 + attribute \src "ls180.v:6010.40-6010.93" + cell $and $and$ls180.v:6010$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240418,43 +242138,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5873$1261_Y + connect \Y $and$ls180.v:6010$1394_Y end - attribute \src "ls180.v:5873.39-5873.143" - cell $and $and$ls180.v:5873$1263 + attribute \src "ls180.v:6010.39-6010.143" + cell $and $and$ls180.v:6010$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5873$1261_Y - connect \B $eq$ls180.v:5873$1262_Y - connect \Y $and$ls180.v:5873$1263_Y + connect \A $and$ls180.v:6010$1394_Y + connect \B $eq$ls180.v:6010$1395_Y + connect \Y $and$ls180.v:6010$1396_Y end - attribute \src "ls180.v:5874.40-5874.96" - cell $and $and$ls180.v:5874$1265 + attribute \src "ls180.v:6011.40-6011.96" + cell $and $and$ls180.v:6011$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5874$1264_Y - connect \Y $and$ls180.v:5874$1265_Y + connect \B $not$ls180.v:6011$1397_Y + connect \Y $and$ls180.v:6011$1398_Y end - attribute \src "ls180.v:5874.39-5874.146" - cell $and $and$ls180.v:5874$1267 + attribute \src "ls180.v:6011.39-6011.146" + cell $and $and$ls180.v:6011$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1265_Y - connect \B $eq$ls180.v:5874$1266_Y - connect \Y $and$ls180.v:5874$1267_Y + connect \A $and$ls180.v:6011$1398_Y + connect \B $eq$ls180.v:6011$1399_Y + connect \Y $and$ls180.v:6011$1400_Y end - attribute \src "ls180.v:5886.40-5886.93" - cell $and $and$ls180.v:5886$1269 + attribute \src "ls180.v:6023.40-6023.93" + cell $and $and$ls180.v:6023$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240462,43 +242182,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5886$1269_Y + connect \Y $and$ls180.v:6023$1402_Y end - attribute \src "ls180.v:5886.39-5886.143" - cell $and $and$ls180.v:5886$1271 + attribute \src "ls180.v:6023.39-6023.143" + cell $and $and$ls180.v:6023$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5886$1269_Y - connect \B $eq$ls180.v:5886$1270_Y - connect \Y $and$ls180.v:5886$1271_Y + connect \A $and$ls180.v:6023$1402_Y + connect \B $eq$ls180.v:6023$1403_Y + connect \Y $and$ls180.v:6023$1404_Y end - attribute \src "ls180.v:5887.40-5887.96" - cell $and $and$ls180.v:5887$1273 + attribute \src "ls180.v:6024.40-6024.96" + cell $and $and$ls180.v:6024$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5887$1272_Y - connect \Y $and$ls180.v:5887$1273_Y + connect \B $not$ls180.v:6024$1405_Y + connect \Y $and$ls180.v:6024$1406_Y end - attribute \src "ls180.v:5887.39-5887.146" - cell $and $and$ls180.v:5887$1275 + attribute \src "ls180.v:6024.39-6024.146" + cell $and $and$ls180.v:6024$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5887$1273_Y - connect \B $eq$ls180.v:5887$1274_Y - connect \Y $and$ls180.v:5887$1275_Y + connect \A $and$ls180.v:6024$1406_Y + connect \B $eq$ls180.v:6024$1407_Y + connect \Y $and$ls180.v:6024$1408_Y end - attribute \src "ls180.v:5889.39-5889.92" - cell $and $and$ls180.v:5889$1276 + attribute \src "ls180.v:6026.39-6026.92" + cell $and $and$ls180.v:6026$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240506,43 +242226,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5889$1276_Y + connect \Y $and$ls180.v:6026$1409_Y end - attribute \src "ls180.v:5889.38-5889.142" - cell $and $and$ls180.v:5889$1278 + attribute \src "ls180.v:6026.38-6026.142" + cell $and $and$ls180.v:6026$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5889$1276_Y - connect \B $eq$ls180.v:5889$1277_Y - connect \Y $and$ls180.v:5889$1278_Y + connect \A $and$ls180.v:6026$1409_Y + connect \B $eq$ls180.v:6026$1410_Y + connect \Y $and$ls180.v:6026$1411_Y end - attribute \src "ls180.v:5890.39-5890.95" - cell $and $and$ls180.v:5890$1280 + attribute \src "ls180.v:6027.39-6027.95" + cell $and $and$ls180.v:6027$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5890$1279_Y - connect \Y $and$ls180.v:5890$1280_Y + connect \B $not$ls180.v:6027$1412_Y + connect \Y $and$ls180.v:6027$1413_Y end - attribute \src "ls180.v:5890.38-5890.145" - cell $and $and$ls180.v:5890$1282 + attribute \src "ls180.v:6027.38-6027.145" + cell $and $and$ls180.v:6027$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5890$1280_Y - connect \B $eq$ls180.v:5890$1281_Y - connect \Y $and$ls180.v:5890$1282_Y + connect \A $and$ls180.v:6027$1413_Y + connect \B $eq$ls180.v:6027$1414_Y + connect \Y $and$ls180.v:6027$1415_Y end - attribute \src "ls180.v:5892.39-5892.92" - cell $and $and$ls180.v:5892$1283 + attribute \src "ls180.v:6029.39-6029.92" + cell $and $and$ls180.v:6029$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240550,43 +242270,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5892$1283_Y + connect \Y $and$ls180.v:6029$1416_Y end - attribute \src "ls180.v:5892.38-5892.142" - cell $and $and$ls180.v:5892$1285 + attribute \src "ls180.v:6029.38-6029.142" + cell $and $and$ls180.v:6029$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5892$1283_Y - connect \B $eq$ls180.v:5892$1284_Y - connect \Y $and$ls180.v:5892$1285_Y + connect \A $and$ls180.v:6029$1416_Y + connect \B $eq$ls180.v:6029$1417_Y + connect \Y $and$ls180.v:6029$1418_Y end - attribute \src "ls180.v:5893.39-5893.95" - cell $and $and$ls180.v:5893$1287 + attribute \src "ls180.v:6030.39-6030.95" + cell $and $and$ls180.v:6030$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5893$1286_Y - connect \Y $and$ls180.v:5893$1287_Y + connect \B $not$ls180.v:6030$1419_Y + connect \Y $and$ls180.v:6030$1420_Y end - attribute \src "ls180.v:5893.38-5893.145" - cell $and $and$ls180.v:5893$1289 + attribute \src "ls180.v:6030.38-6030.145" + cell $and $and$ls180.v:6030$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5893$1287_Y - connect \B $eq$ls180.v:5893$1288_Y - connect \Y $and$ls180.v:5893$1289_Y + connect \A $and$ls180.v:6030$1420_Y + connect \B $eq$ls180.v:6030$1421_Y + connect \Y $and$ls180.v:6030$1422_Y end - attribute \src "ls180.v:5895.39-5895.92" - cell $and $and$ls180.v:5895$1290 + attribute \src "ls180.v:6032.39-6032.92" + cell $and $and$ls180.v:6032$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240594,43 +242314,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5895$1290_Y + connect \Y $and$ls180.v:6032$1423_Y end - attribute \src "ls180.v:5895.38-5895.142" - cell $and $and$ls180.v:5895$1292 + attribute \src "ls180.v:6032.38-6032.142" + cell $and $and$ls180.v:6032$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5895$1290_Y - connect \B $eq$ls180.v:5895$1291_Y - connect \Y $and$ls180.v:5895$1292_Y + connect \A $and$ls180.v:6032$1423_Y + connect \B $eq$ls180.v:6032$1424_Y + connect \Y $and$ls180.v:6032$1425_Y end - attribute \src "ls180.v:5896.39-5896.95" - cell $and $and$ls180.v:5896$1294 + attribute \src "ls180.v:6033.39-6033.95" + cell $and $and$ls180.v:6033$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5896$1293_Y - connect \Y $and$ls180.v:5896$1294_Y + connect \B $not$ls180.v:6033$1426_Y + connect \Y $and$ls180.v:6033$1427_Y end - attribute \src "ls180.v:5896.38-5896.145" - cell $and $and$ls180.v:5896$1296 + attribute \src "ls180.v:6033.38-6033.145" + cell $and $and$ls180.v:6033$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5896$1294_Y - connect \B $eq$ls180.v:5896$1295_Y - connect \Y $and$ls180.v:5896$1296_Y + connect \A $and$ls180.v:6033$1427_Y + connect \B $eq$ls180.v:6033$1428_Y + connect \Y $and$ls180.v:6033$1429_Y end - attribute \src "ls180.v:5898.39-5898.92" - cell $and $and$ls180.v:5898$1297 + attribute \src "ls180.v:6035.39-6035.92" + cell $and $and$ls180.v:6035$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240638,43 +242358,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5898$1297_Y + connect \Y $and$ls180.v:6035$1430_Y end - attribute \src "ls180.v:5898.38-5898.142" - cell $and $and$ls180.v:5898$1299 + attribute \src "ls180.v:6035.38-6035.142" + cell $and $and$ls180.v:6035$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5898$1297_Y - connect \B $eq$ls180.v:5898$1298_Y - connect \Y $and$ls180.v:5898$1299_Y + connect \A $and$ls180.v:6035$1430_Y + connect \B $eq$ls180.v:6035$1431_Y + connect \Y $and$ls180.v:6035$1432_Y end - attribute \src "ls180.v:5899.39-5899.95" - cell $and $and$ls180.v:5899$1301 + attribute \src "ls180.v:6036.39-6036.95" + cell $and $and$ls180.v:6036$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5899$1300_Y - connect \Y $and$ls180.v:5899$1301_Y + connect \B $not$ls180.v:6036$1433_Y + connect \Y $and$ls180.v:6036$1434_Y end - attribute \src "ls180.v:5899.38-5899.145" - cell $and $and$ls180.v:5899$1303 + attribute \src "ls180.v:6036.38-6036.145" + cell $and $and$ls180.v:6036$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5899$1301_Y - connect \B $eq$ls180.v:5899$1302_Y - connect \Y $and$ls180.v:5899$1303_Y + connect \A $and$ls180.v:6036$1434_Y + connect \B $eq$ls180.v:6036$1435_Y + connect \Y $and$ls180.v:6036$1436_Y end - attribute \src "ls180.v:5901.40-5901.93" - cell $and $and$ls180.v:5901$1304 + attribute \src "ls180.v:6038.40-6038.93" + cell $and $and$ls180.v:6038$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240682,43 +242402,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5901$1304_Y + connect \Y $and$ls180.v:6038$1437_Y end - attribute \src "ls180.v:5901.39-5901.143" - cell $and $and$ls180.v:5901$1306 + attribute \src "ls180.v:6038.39-6038.143" + cell $and $and$ls180.v:6038$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5901$1304_Y - connect \B $eq$ls180.v:5901$1305_Y - connect \Y $and$ls180.v:5901$1306_Y + connect \A $and$ls180.v:6038$1437_Y + connect \B $eq$ls180.v:6038$1438_Y + connect \Y $and$ls180.v:6038$1439_Y end - attribute \src "ls180.v:5902.40-5902.96" - cell $and $and$ls180.v:5902$1308 + attribute \src "ls180.v:6039.40-6039.96" + cell $and $and$ls180.v:6039$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5902$1307_Y - connect \Y $and$ls180.v:5902$1308_Y + connect \B $not$ls180.v:6039$1440_Y + connect \Y $and$ls180.v:6039$1441_Y end - attribute \src "ls180.v:5902.39-5902.146" - cell $and $and$ls180.v:5902$1310 + attribute \src "ls180.v:6039.39-6039.146" + cell $and $and$ls180.v:6039$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5902$1308_Y - connect \B $eq$ls180.v:5902$1309_Y - connect \Y $and$ls180.v:5902$1310_Y + connect \A $and$ls180.v:6039$1441_Y + connect \B $eq$ls180.v:6039$1442_Y + connect \Y $and$ls180.v:6039$1443_Y end - attribute \src "ls180.v:5904.40-5904.93" - cell $and $and$ls180.v:5904$1311 + attribute \src "ls180.v:6041.40-6041.93" + cell $and $and$ls180.v:6041$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240726,43 +242446,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5904$1311_Y + connect \Y $and$ls180.v:6041$1444_Y end - attribute \src "ls180.v:5904.39-5904.143" - cell $and $and$ls180.v:5904$1313 + attribute \src "ls180.v:6041.39-6041.143" + cell $and $and$ls180.v:6041$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5904$1311_Y - connect \B $eq$ls180.v:5904$1312_Y - connect \Y $and$ls180.v:5904$1313_Y + connect \A $and$ls180.v:6041$1444_Y + connect \B $eq$ls180.v:6041$1445_Y + connect \Y $and$ls180.v:6041$1446_Y end - attribute \src "ls180.v:5905.40-5905.96" - cell $and $and$ls180.v:5905$1315 + attribute \src "ls180.v:6042.40-6042.96" + cell $and $and$ls180.v:6042$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5905$1314_Y - connect \Y $and$ls180.v:5905$1315_Y + connect \B $not$ls180.v:6042$1447_Y + connect \Y $and$ls180.v:6042$1448_Y end - attribute \src "ls180.v:5905.39-5905.146" - cell $and $and$ls180.v:5905$1317 + attribute \src "ls180.v:6042.39-6042.146" + cell $and $and$ls180.v:6042$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5905$1315_Y - connect \B $eq$ls180.v:5905$1316_Y - connect \Y $and$ls180.v:5905$1317_Y + connect \A $and$ls180.v:6042$1448_Y + connect \B $eq$ls180.v:6042$1449_Y + connect \Y $and$ls180.v:6042$1450_Y end - attribute \src "ls180.v:5907.40-5907.93" - cell $and $and$ls180.v:5907$1318 + attribute \src "ls180.v:6044.40-6044.93" + cell $and $and$ls180.v:6044$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240770,43 +242490,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5907$1318_Y + connect \Y $and$ls180.v:6044$1451_Y end - attribute \src "ls180.v:5907.39-5907.143" - cell $and $and$ls180.v:5907$1320 + attribute \src "ls180.v:6044.39-6044.143" + cell $and $and$ls180.v:6044$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5907$1318_Y - connect \B $eq$ls180.v:5907$1319_Y - connect \Y $and$ls180.v:5907$1320_Y + connect \A $and$ls180.v:6044$1451_Y + connect \B $eq$ls180.v:6044$1452_Y + connect \Y $and$ls180.v:6044$1453_Y end - attribute \src "ls180.v:5908.40-5908.96" - cell $and $and$ls180.v:5908$1322 + attribute \src "ls180.v:6045.40-6045.96" + cell $and $and$ls180.v:6045$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5908$1321_Y - connect \Y $and$ls180.v:5908$1322_Y + connect \B $not$ls180.v:6045$1454_Y + connect \Y $and$ls180.v:6045$1455_Y end - attribute \src "ls180.v:5908.39-5908.146" - cell $and $and$ls180.v:5908$1324 + attribute \src "ls180.v:6045.39-6045.146" + cell $and $and$ls180.v:6045$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5908$1322_Y - connect \B $eq$ls180.v:5908$1323_Y - connect \Y $and$ls180.v:5908$1324_Y + connect \A $and$ls180.v:6045$1455_Y + connect \B $eq$ls180.v:6045$1456_Y + connect \Y $and$ls180.v:6045$1457_Y end - attribute \src "ls180.v:5910.40-5910.93" - cell $and $and$ls180.v:5910$1325 + attribute \src "ls180.v:6047.40-6047.93" + cell $and $and$ls180.v:6047$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240814,43 +242534,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5910$1325_Y + connect \Y $and$ls180.v:6047$1458_Y end - attribute \src "ls180.v:5910.39-5910.143" - cell $and $and$ls180.v:5910$1327 + attribute \src "ls180.v:6047.39-6047.143" + cell $and $and$ls180.v:6047$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5910$1325_Y - connect \B $eq$ls180.v:5910$1326_Y - connect \Y $and$ls180.v:5910$1327_Y + connect \A $and$ls180.v:6047$1458_Y + connect \B $eq$ls180.v:6047$1459_Y + connect \Y $and$ls180.v:6047$1460_Y end - attribute \src "ls180.v:5911.40-5911.96" - cell $and $and$ls180.v:5911$1329 + attribute \src "ls180.v:6048.40-6048.96" + cell $and $and$ls180.v:6048$1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5911$1328_Y - connect \Y $and$ls180.v:5911$1329_Y + connect \B $not$ls180.v:6048$1461_Y + connect \Y $and$ls180.v:6048$1462_Y end - attribute \src "ls180.v:5911.39-5911.146" - cell $and $and$ls180.v:5911$1331 + attribute \src "ls180.v:6048.39-6048.146" + cell $and $and$ls180.v:6048$1464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5911$1329_Y - connect \B $eq$ls180.v:5911$1330_Y - connect \Y $and$ls180.v:5911$1331_Y + connect \A $and$ls180.v:6048$1462_Y + connect \B $eq$ls180.v:6048$1463_Y + connect \Y $and$ls180.v:6048$1464_Y end - attribute \src "ls180.v:5923.42-5923.95" - cell $and $and$ls180.v:5923$1333 + attribute \src "ls180.v:6060.42-6060.95" + cell $and $and$ls180.v:6060$1466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240858,43 +242578,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5923$1333_Y + connect \Y $and$ls180.v:6060$1466_Y end - attribute \src "ls180.v:5923.41-5923.145" - cell $and $and$ls180.v:5923$1335 + attribute \src "ls180.v:6060.41-6060.145" + cell $and $and$ls180.v:6060$1468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5923$1333_Y - connect \B $eq$ls180.v:5923$1334_Y - connect \Y $and$ls180.v:5923$1335_Y + connect \A $and$ls180.v:6060$1466_Y + connect \B $eq$ls180.v:6060$1467_Y + connect \Y $and$ls180.v:6060$1468_Y end - attribute \src "ls180.v:5924.42-5924.98" - cell $and $and$ls180.v:5924$1337 + attribute \src "ls180.v:6061.42-6061.98" + cell $and $and$ls180.v:6061$1470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5924$1336_Y - connect \Y $and$ls180.v:5924$1337_Y + connect \B $not$ls180.v:6061$1469_Y + connect \Y $and$ls180.v:6061$1470_Y end - attribute \src "ls180.v:5924.41-5924.148" - cell $and $and$ls180.v:5924$1339 + attribute \src "ls180.v:6061.41-6061.148" + cell $and $and$ls180.v:6061$1472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5924$1337_Y - connect \B $eq$ls180.v:5924$1338_Y - connect \Y $and$ls180.v:5924$1339_Y + connect \A $and$ls180.v:6061$1470_Y + connect \B $eq$ls180.v:6061$1471_Y + connect \Y $and$ls180.v:6061$1472_Y end - attribute \src "ls180.v:5926.42-5926.95" - cell $and $and$ls180.v:5926$1340 + attribute \src "ls180.v:6063.42-6063.95" + cell $and $and$ls180.v:6063$1473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240902,43 +242622,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5926$1340_Y + connect \Y $and$ls180.v:6063$1473_Y end - attribute \src "ls180.v:5926.41-5926.145" - cell $and $and$ls180.v:5926$1342 + attribute \src "ls180.v:6063.41-6063.145" + cell $and $and$ls180.v:6063$1475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5926$1340_Y - connect \B $eq$ls180.v:5926$1341_Y - connect \Y $and$ls180.v:5926$1342_Y + connect \A $and$ls180.v:6063$1473_Y + connect \B $eq$ls180.v:6063$1474_Y + connect \Y $and$ls180.v:6063$1475_Y end - attribute \src "ls180.v:5927.42-5927.98" - cell $and $and$ls180.v:5927$1344 + attribute \src "ls180.v:6064.42-6064.98" + cell $and $and$ls180.v:6064$1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5927$1343_Y - connect \Y $and$ls180.v:5927$1344_Y + connect \B $not$ls180.v:6064$1476_Y + connect \Y $and$ls180.v:6064$1477_Y end - attribute \src "ls180.v:5927.41-5927.148" - cell $and $and$ls180.v:5927$1346 + attribute \src "ls180.v:6064.41-6064.148" + cell $and $and$ls180.v:6064$1479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5927$1344_Y - connect \B $eq$ls180.v:5927$1345_Y - connect \Y $and$ls180.v:5927$1346_Y + connect \A $and$ls180.v:6064$1477_Y + connect \B $eq$ls180.v:6064$1478_Y + connect \Y $and$ls180.v:6064$1479_Y end - attribute \src "ls180.v:5929.42-5929.95" - cell $and $and$ls180.v:5929$1347 + attribute \src "ls180.v:6066.42-6066.95" + cell $and $and$ls180.v:6066$1480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240946,43 +242666,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5929$1347_Y + connect \Y $and$ls180.v:6066$1480_Y end - attribute \src "ls180.v:5929.41-5929.145" - cell $and $and$ls180.v:5929$1349 + attribute \src "ls180.v:6066.41-6066.145" + cell $and $and$ls180.v:6066$1482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5929$1347_Y - connect \B $eq$ls180.v:5929$1348_Y - connect \Y $and$ls180.v:5929$1349_Y + connect \A $and$ls180.v:6066$1480_Y + connect \B $eq$ls180.v:6066$1481_Y + connect \Y $and$ls180.v:6066$1482_Y end - attribute \src "ls180.v:5930.42-5930.98" - cell $and $and$ls180.v:5930$1351 + attribute \src "ls180.v:6067.42-6067.98" + cell $and $and$ls180.v:6067$1484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5930$1350_Y - connect \Y $and$ls180.v:5930$1351_Y + connect \B $not$ls180.v:6067$1483_Y + connect \Y $and$ls180.v:6067$1484_Y end - attribute \src "ls180.v:5930.41-5930.148" - cell $and $and$ls180.v:5930$1353 + attribute \src "ls180.v:6067.41-6067.148" + cell $and $and$ls180.v:6067$1486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5930$1351_Y - connect \B $eq$ls180.v:5930$1352_Y - connect \Y $and$ls180.v:5930$1353_Y + connect \A $and$ls180.v:6067$1484_Y + connect \B $eq$ls180.v:6067$1485_Y + connect \Y $and$ls180.v:6067$1486_Y end - attribute \src "ls180.v:5932.42-5932.95" - cell $and $and$ls180.v:5932$1354 + attribute \src "ls180.v:6069.42-6069.95" + cell $and $and$ls180.v:6069$1487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240990,43 +242710,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5932$1354_Y + connect \Y $and$ls180.v:6069$1487_Y end - attribute \src "ls180.v:5932.41-5932.145" - cell $and $and$ls180.v:5932$1356 + attribute \src "ls180.v:6069.41-6069.145" + cell $and $and$ls180.v:6069$1489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5932$1354_Y - connect \B $eq$ls180.v:5932$1355_Y - connect \Y $and$ls180.v:5932$1356_Y + connect \A $and$ls180.v:6069$1487_Y + connect \B $eq$ls180.v:6069$1488_Y + connect \Y $and$ls180.v:6069$1489_Y end - attribute \src "ls180.v:5933.42-5933.98" - cell $and $and$ls180.v:5933$1358 + attribute \src "ls180.v:6070.42-6070.98" + cell $and $and$ls180.v:6070$1491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5933$1357_Y - connect \Y $and$ls180.v:5933$1358_Y + connect \B $not$ls180.v:6070$1490_Y + connect \Y $and$ls180.v:6070$1491_Y end - attribute \src "ls180.v:5933.41-5933.148" - cell $and $and$ls180.v:5933$1360 + attribute \src "ls180.v:6070.41-6070.148" + cell $and $and$ls180.v:6070$1493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5933$1358_Y - connect \B $eq$ls180.v:5933$1359_Y - connect \Y $and$ls180.v:5933$1360_Y + connect \A $and$ls180.v:6070$1491_Y + connect \B $eq$ls180.v:6070$1492_Y + connect \Y $and$ls180.v:6070$1493_Y end - attribute \src "ls180.v:5935.42-5935.95" - cell $and $and$ls180.v:5935$1361 + attribute \src "ls180.v:6072.42-6072.95" + cell $and $and$ls180.v:6072$1494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241034,43 +242754,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5935$1361_Y + connect \Y $and$ls180.v:6072$1494_Y end - attribute \src "ls180.v:5935.41-5935.145" - cell $and $and$ls180.v:5935$1363 + attribute \src "ls180.v:6072.41-6072.145" + cell $and $and$ls180.v:6072$1496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5935$1361_Y - connect \B $eq$ls180.v:5935$1362_Y - connect \Y $and$ls180.v:5935$1363_Y + connect \A $and$ls180.v:6072$1494_Y + connect \B $eq$ls180.v:6072$1495_Y + connect \Y $and$ls180.v:6072$1496_Y end - attribute \src "ls180.v:5936.42-5936.98" - cell $and $and$ls180.v:5936$1365 + attribute \src "ls180.v:6073.42-6073.98" + cell $and $and$ls180.v:6073$1498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5936$1364_Y - connect \Y $and$ls180.v:5936$1365_Y + connect \B $not$ls180.v:6073$1497_Y + connect \Y $and$ls180.v:6073$1498_Y end - attribute \src "ls180.v:5936.41-5936.148" - cell $and $and$ls180.v:5936$1367 + attribute \src "ls180.v:6073.41-6073.148" + cell $and $and$ls180.v:6073$1500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5936$1365_Y - connect \B $eq$ls180.v:5936$1366_Y - connect \Y $and$ls180.v:5936$1367_Y + connect \A $and$ls180.v:6073$1498_Y + connect \B $eq$ls180.v:6073$1499_Y + connect \Y $and$ls180.v:6073$1500_Y end - attribute \src "ls180.v:5938.42-5938.95" - cell $and $and$ls180.v:5938$1368 + attribute \src "ls180.v:6075.42-6075.95" + cell $and $and$ls180.v:6075$1501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241078,43 +242798,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5938$1368_Y + connect \Y $and$ls180.v:6075$1501_Y end - attribute \src "ls180.v:5938.41-5938.145" - cell $and $and$ls180.v:5938$1370 + attribute \src "ls180.v:6075.41-6075.145" + cell $and $and$ls180.v:6075$1503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5938$1368_Y - connect \B $eq$ls180.v:5938$1369_Y - connect \Y $and$ls180.v:5938$1370_Y + connect \A $and$ls180.v:6075$1501_Y + connect \B $eq$ls180.v:6075$1502_Y + connect \Y $and$ls180.v:6075$1503_Y end - attribute \src "ls180.v:5939.42-5939.98" - cell $and $and$ls180.v:5939$1372 + attribute \src "ls180.v:6076.42-6076.98" + cell $and $and$ls180.v:6076$1505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5939$1371_Y - connect \Y $and$ls180.v:5939$1372_Y + connect \B $not$ls180.v:6076$1504_Y + connect \Y $and$ls180.v:6076$1505_Y end - attribute \src "ls180.v:5939.41-5939.148" - cell $and $and$ls180.v:5939$1374 + attribute \src "ls180.v:6076.41-6076.148" + cell $and $and$ls180.v:6076$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5939$1372_Y - connect \B $eq$ls180.v:5939$1373_Y - connect \Y $and$ls180.v:5939$1374_Y + connect \A $and$ls180.v:6076$1505_Y + connect \B $eq$ls180.v:6076$1506_Y + connect \Y $and$ls180.v:6076$1507_Y end - attribute \src "ls180.v:5941.42-5941.95" - cell $and $and$ls180.v:5941$1375 + attribute \src "ls180.v:6078.42-6078.95" + cell $and $and$ls180.v:6078$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241122,43 +242842,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5941$1375_Y + connect \Y $and$ls180.v:6078$1508_Y end - attribute \src "ls180.v:5941.41-5941.145" - cell $and $and$ls180.v:5941$1377 + attribute \src "ls180.v:6078.41-6078.145" + cell $and $and$ls180.v:6078$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5941$1375_Y - connect \B $eq$ls180.v:5941$1376_Y - connect \Y $and$ls180.v:5941$1377_Y + connect \A $and$ls180.v:6078$1508_Y + connect \B $eq$ls180.v:6078$1509_Y + connect \Y $and$ls180.v:6078$1510_Y end - attribute \src "ls180.v:5942.42-5942.98" - cell $and $and$ls180.v:5942$1379 + attribute \src "ls180.v:6079.42-6079.98" + cell $and $and$ls180.v:6079$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5942$1378_Y - connect \Y $and$ls180.v:5942$1379_Y + connect \B $not$ls180.v:6079$1511_Y + connect \Y $and$ls180.v:6079$1512_Y end - attribute \src "ls180.v:5942.41-5942.148" - cell $and $and$ls180.v:5942$1381 + attribute \src "ls180.v:6079.41-6079.148" + cell $and $and$ls180.v:6079$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5942$1379_Y - connect \B $eq$ls180.v:5942$1380_Y - connect \Y $and$ls180.v:5942$1381_Y + connect \A $and$ls180.v:6079$1512_Y + connect \B $eq$ls180.v:6079$1513_Y + connect \Y $and$ls180.v:6079$1514_Y end - attribute \src "ls180.v:5944.42-5944.95" - cell $and $and$ls180.v:5944$1382 + attribute \src "ls180.v:6081.42-6081.95" + cell $and $and$ls180.v:6081$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241166,43 +242886,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5944$1382_Y + connect \Y $and$ls180.v:6081$1515_Y end - attribute \src "ls180.v:5944.41-5944.145" - cell $and $and$ls180.v:5944$1384 + attribute \src "ls180.v:6081.41-6081.145" + cell $and $and$ls180.v:6081$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5944$1382_Y - connect \B $eq$ls180.v:5944$1383_Y - connect \Y $and$ls180.v:5944$1384_Y + connect \A $and$ls180.v:6081$1515_Y + connect \B $eq$ls180.v:6081$1516_Y + connect \Y $and$ls180.v:6081$1517_Y end - attribute \src "ls180.v:5945.42-5945.98" - cell $and $and$ls180.v:5945$1386 + attribute \src "ls180.v:6082.42-6082.98" + cell $and $and$ls180.v:6082$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5945$1385_Y - connect \Y $and$ls180.v:5945$1386_Y + connect \B $not$ls180.v:6082$1518_Y + connect \Y $and$ls180.v:6082$1519_Y end - attribute \src "ls180.v:5945.41-5945.148" - cell $and $and$ls180.v:5945$1388 + attribute \src "ls180.v:6082.41-6082.148" + cell $and $and$ls180.v:6082$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5945$1386_Y - connect \B $eq$ls180.v:5945$1387_Y - connect \Y $and$ls180.v:5945$1388_Y + connect \A $and$ls180.v:6082$1519_Y + connect \B $eq$ls180.v:6082$1520_Y + connect \Y $and$ls180.v:6082$1521_Y end - attribute \src "ls180.v:5947.44-5947.97" - cell $and $and$ls180.v:5947$1389 + attribute \src "ls180.v:6084.44-6084.97" + cell $and $and$ls180.v:6084$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241210,43 +242930,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5947$1389_Y + connect \Y $and$ls180.v:6084$1522_Y end - attribute \src "ls180.v:5947.43-5947.147" - cell $and $and$ls180.v:5947$1391 + attribute \src "ls180.v:6084.43-6084.147" + cell $and $and$ls180.v:6084$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5947$1389_Y - connect \B $eq$ls180.v:5947$1390_Y - connect \Y $and$ls180.v:5947$1391_Y + connect \A $and$ls180.v:6084$1522_Y + connect \B $eq$ls180.v:6084$1523_Y + connect \Y $and$ls180.v:6084$1524_Y end - attribute \src "ls180.v:5948.44-5948.100" - cell $and $and$ls180.v:5948$1393 + attribute \src "ls180.v:6085.44-6085.100" + cell $and $and$ls180.v:6085$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5948$1392_Y - connect \Y $and$ls180.v:5948$1393_Y + connect \B $not$ls180.v:6085$1525_Y + connect \Y $and$ls180.v:6085$1526_Y end - attribute \src "ls180.v:5948.43-5948.150" - cell $and $and$ls180.v:5948$1395 + attribute \src "ls180.v:6085.43-6085.150" + cell $and $and$ls180.v:6085$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5948$1393_Y - connect \B $eq$ls180.v:5948$1394_Y - connect \Y $and$ls180.v:5948$1395_Y + connect \A $and$ls180.v:6085$1526_Y + connect \B $eq$ls180.v:6085$1527_Y + connect \Y $and$ls180.v:6085$1528_Y end - attribute \src "ls180.v:5950.44-5950.97" - cell $and $and$ls180.v:5950$1396 + attribute \src "ls180.v:6087.44-6087.97" + cell $and $and$ls180.v:6087$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241254,43 +242974,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5950$1396_Y + connect \Y $and$ls180.v:6087$1529_Y end - attribute \src "ls180.v:5950.43-5950.147" - cell $and $and$ls180.v:5950$1398 + attribute \src "ls180.v:6087.43-6087.147" + cell $and $and$ls180.v:6087$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5950$1396_Y - connect \B $eq$ls180.v:5950$1397_Y - connect \Y $and$ls180.v:5950$1398_Y + connect \A $and$ls180.v:6087$1529_Y + connect \B $eq$ls180.v:6087$1530_Y + connect \Y $and$ls180.v:6087$1531_Y end - attribute \src "ls180.v:5951.44-5951.100" - cell $and $and$ls180.v:5951$1400 + attribute \src "ls180.v:6088.44-6088.100" + cell $and $and$ls180.v:6088$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5951$1399_Y - connect \Y $and$ls180.v:5951$1400_Y + connect \B $not$ls180.v:6088$1532_Y + connect \Y $and$ls180.v:6088$1533_Y end - attribute \src "ls180.v:5951.43-5951.150" - cell $and $and$ls180.v:5951$1402 + attribute \src "ls180.v:6088.43-6088.150" + cell $and $and$ls180.v:6088$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5951$1400_Y - connect \B $eq$ls180.v:5951$1401_Y - connect \Y $and$ls180.v:5951$1402_Y + connect \A $and$ls180.v:6088$1533_Y + connect \B $eq$ls180.v:6088$1534_Y + connect \Y $and$ls180.v:6088$1535_Y end - attribute \src "ls180.v:5953.44-5953.97" - cell $and $and$ls180.v:5953$1403 + attribute \src "ls180.v:6090.44-6090.97" + cell $and $and$ls180.v:6090$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241298,43 +243018,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5953$1403_Y + connect \Y $and$ls180.v:6090$1536_Y end - attribute \src "ls180.v:5953.43-5953.148" - cell $and $and$ls180.v:5953$1405 + attribute \src "ls180.v:6090.43-6090.148" + cell $and $and$ls180.v:6090$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5953$1403_Y - connect \B $eq$ls180.v:5953$1404_Y - connect \Y $and$ls180.v:5953$1405_Y + connect \A $and$ls180.v:6090$1536_Y + connect \B $eq$ls180.v:6090$1537_Y + connect \Y $and$ls180.v:6090$1538_Y end - attribute \src "ls180.v:5954.44-5954.100" - cell $and $and$ls180.v:5954$1407 + attribute \src "ls180.v:6091.44-6091.100" + cell $and $and$ls180.v:6091$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5954$1406_Y - connect \Y $and$ls180.v:5954$1407_Y + connect \B $not$ls180.v:6091$1539_Y + connect \Y $and$ls180.v:6091$1540_Y end - attribute \src "ls180.v:5954.43-5954.151" - cell $and $and$ls180.v:5954$1409 + attribute \src "ls180.v:6091.43-6091.151" + cell $and $and$ls180.v:6091$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5954$1407_Y - connect \B $eq$ls180.v:5954$1408_Y - connect \Y $and$ls180.v:5954$1409_Y + connect \A $and$ls180.v:6091$1540_Y + connect \B $eq$ls180.v:6091$1541_Y + connect \Y $and$ls180.v:6091$1542_Y end - attribute \src "ls180.v:5956.44-5956.97" - cell $and $and$ls180.v:5956$1410 + attribute \src "ls180.v:6093.44-6093.97" + cell $and $and$ls180.v:6093$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241342,43 +243062,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5956$1410_Y + connect \Y $and$ls180.v:6093$1543_Y end - attribute \src "ls180.v:5956.43-5956.148" - cell $and $and$ls180.v:5956$1412 + attribute \src "ls180.v:6093.43-6093.148" + cell $and $and$ls180.v:6093$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5956$1410_Y - connect \B $eq$ls180.v:5956$1411_Y - connect \Y $and$ls180.v:5956$1412_Y + connect \A $and$ls180.v:6093$1543_Y + connect \B $eq$ls180.v:6093$1544_Y + connect \Y $and$ls180.v:6093$1545_Y end - attribute \src "ls180.v:5957.44-5957.100" - cell $and $and$ls180.v:5957$1414 + attribute \src "ls180.v:6094.44-6094.100" + cell $and $and$ls180.v:6094$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5957$1413_Y - connect \Y $and$ls180.v:5957$1414_Y + connect \B $not$ls180.v:6094$1546_Y + connect \Y $and$ls180.v:6094$1547_Y end - attribute \src "ls180.v:5957.43-5957.151" - cell $and $and$ls180.v:5957$1416 + attribute \src "ls180.v:6094.43-6094.151" + cell $and $and$ls180.v:6094$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5957$1414_Y - connect \B $eq$ls180.v:5957$1415_Y - connect \Y $and$ls180.v:5957$1416_Y + connect \A $and$ls180.v:6094$1547_Y + connect \B $eq$ls180.v:6094$1548_Y + connect \Y $and$ls180.v:6094$1549_Y end - attribute \src "ls180.v:5959.44-5959.97" - cell $and $and$ls180.v:5959$1417 + attribute \src "ls180.v:6096.44-6096.97" + cell $and $and$ls180.v:6096$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241386,43 +243106,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5959$1417_Y + connect \Y $and$ls180.v:6096$1550_Y end - attribute \src "ls180.v:5959.43-5959.148" - cell $and $and$ls180.v:5959$1419 + attribute \src "ls180.v:6096.43-6096.148" + cell $and $and$ls180.v:6096$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5959$1417_Y - connect \B $eq$ls180.v:5959$1418_Y - connect \Y $and$ls180.v:5959$1419_Y + connect \A $and$ls180.v:6096$1550_Y + connect \B $eq$ls180.v:6096$1551_Y + connect \Y $and$ls180.v:6096$1552_Y end - attribute \src "ls180.v:5960.44-5960.100" - cell $and $and$ls180.v:5960$1421 + attribute \src "ls180.v:6097.44-6097.100" + cell $and $and$ls180.v:6097$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5960$1420_Y - connect \Y $and$ls180.v:5960$1421_Y + connect \B $not$ls180.v:6097$1553_Y + connect \Y $and$ls180.v:6097$1554_Y end - attribute \src "ls180.v:5960.43-5960.151" - cell $and $and$ls180.v:5960$1423 + attribute \src "ls180.v:6097.43-6097.151" + cell $and $and$ls180.v:6097$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5960$1421_Y - connect \B $eq$ls180.v:5960$1422_Y - connect \Y $and$ls180.v:5960$1423_Y + connect \A $and$ls180.v:6097$1554_Y + connect \B $eq$ls180.v:6097$1555_Y + connect \Y $and$ls180.v:6097$1556_Y end - attribute \src "ls180.v:5962.41-5962.94" - cell $and $and$ls180.v:5962$1424 + attribute \src "ls180.v:6099.41-6099.94" + cell $and $and$ls180.v:6099$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241430,43 +243150,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5962$1424_Y + connect \Y $and$ls180.v:6099$1557_Y end - attribute \src "ls180.v:5962.40-5962.145" - cell $and $and$ls180.v:5962$1426 + attribute \src "ls180.v:6099.40-6099.145" + cell $and $and$ls180.v:6099$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5962$1424_Y - connect \B $eq$ls180.v:5962$1425_Y - connect \Y $and$ls180.v:5962$1426_Y + connect \A $and$ls180.v:6099$1557_Y + connect \B $eq$ls180.v:6099$1558_Y + connect \Y $and$ls180.v:6099$1559_Y end - attribute \src "ls180.v:5963.41-5963.97" - cell $and $and$ls180.v:5963$1428 + attribute \src "ls180.v:6100.41-6100.97" + cell $and $and$ls180.v:6100$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5963$1427_Y - connect \Y $and$ls180.v:5963$1428_Y + connect \B $not$ls180.v:6100$1560_Y + connect \Y $and$ls180.v:6100$1561_Y end - attribute \src "ls180.v:5963.40-5963.148" - cell $and $and$ls180.v:5963$1430 + attribute \src "ls180.v:6100.40-6100.148" + cell $and $and$ls180.v:6100$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5963$1428_Y - connect \B $eq$ls180.v:5963$1429_Y - connect \Y $and$ls180.v:5963$1430_Y + connect \A $and$ls180.v:6100$1561_Y + connect \B $eq$ls180.v:6100$1562_Y + connect \Y $and$ls180.v:6100$1563_Y end - attribute \src "ls180.v:5965.42-5965.95" - cell $and $and$ls180.v:5965$1431 + attribute \src "ls180.v:6102.42-6102.95" + cell $and $and$ls180.v:6102$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241474,43 +243194,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5965$1431_Y + connect \Y $and$ls180.v:6102$1564_Y end - attribute \src "ls180.v:5965.41-5965.146" - cell $and $and$ls180.v:5965$1433 + attribute \src "ls180.v:6102.41-6102.146" + cell $and $and$ls180.v:6102$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5965$1431_Y - connect \B $eq$ls180.v:5965$1432_Y - connect \Y $and$ls180.v:5965$1433_Y + connect \A $and$ls180.v:6102$1564_Y + connect \B $eq$ls180.v:6102$1565_Y + connect \Y $and$ls180.v:6102$1566_Y end - attribute \src "ls180.v:5966.42-5966.98" - cell $and $and$ls180.v:5966$1435 + attribute \src "ls180.v:6103.42-6103.98" + cell $and $and$ls180.v:6103$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5966$1434_Y - connect \Y $and$ls180.v:5966$1435_Y + connect \B $not$ls180.v:6103$1567_Y + connect \Y $and$ls180.v:6103$1568_Y end - attribute \src "ls180.v:5966.41-5966.149" - cell $and $and$ls180.v:5966$1437 + attribute \src "ls180.v:6103.41-6103.149" + cell $and $and$ls180.v:6103$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5966$1435_Y - connect \B $eq$ls180.v:5966$1436_Y - connect \Y $and$ls180.v:5966$1437_Y + connect \A $and$ls180.v:6103$1568_Y + connect \B $eq$ls180.v:6103$1569_Y + connect \Y $and$ls180.v:6103$1570_Y end - attribute \src "ls180.v:5985.46-5985.99" - cell $and $and$ls180.v:5985$1439 + attribute \src "ls180.v:6122.46-6122.99" + cell $and $and$ls180.v:6122$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241518,43 +243238,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5985$1439_Y + connect \Y $and$ls180.v:6122$1572_Y end - attribute \src "ls180.v:5985.45-5985.149" - cell $and $and$ls180.v:5985$1441 + attribute \src "ls180.v:6122.45-6122.149" + cell $and $and$ls180.v:6122$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5985$1439_Y - connect \B $eq$ls180.v:5985$1440_Y - connect \Y $and$ls180.v:5985$1441_Y + connect \A $and$ls180.v:6122$1572_Y + connect \B $eq$ls180.v:6122$1573_Y + connect \Y $and$ls180.v:6122$1574_Y end - attribute \src "ls180.v:5986.46-5986.102" - cell $and $and$ls180.v:5986$1443 + attribute \src "ls180.v:6123.46-6123.102" + cell $and $and$ls180.v:6123$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5986$1442_Y - connect \Y $and$ls180.v:5986$1443_Y + connect \B $not$ls180.v:6123$1575_Y + connect \Y $and$ls180.v:6123$1576_Y end - attribute \src "ls180.v:5986.45-5986.152" - cell $and $and$ls180.v:5986$1445 + attribute \src "ls180.v:6123.45-6123.152" + cell $and $and$ls180.v:6123$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5986$1443_Y - connect \B $eq$ls180.v:5986$1444_Y - connect \Y $and$ls180.v:5986$1445_Y + connect \A $and$ls180.v:6123$1576_Y + connect \B $eq$ls180.v:6123$1577_Y + connect \Y $and$ls180.v:6123$1578_Y end - attribute \src "ls180.v:5988.46-5988.99" - cell $and $and$ls180.v:5988$1446 + attribute \src "ls180.v:6125.46-6125.99" + cell $and $and$ls180.v:6125$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241562,43 +243282,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5988$1446_Y + connect \Y $and$ls180.v:6125$1579_Y end - attribute \src "ls180.v:5988.45-5988.149" - cell $and $and$ls180.v:5988$1448 + attribute \src "ls180.v:6125.45-6125.149" + cell $and $and$ls180.v:6125$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5988$1446_Y - connect \B $eq$ls180.v:5988$1447_Y - connect \Y $and$ls180.v:5988$1448_Y + connect \A $and$ls180.v:6125$1579_Y + connect \B $eq$ls180.v:6125$1580_Y + connect \Y $and$ls180.v:6125$1581_Y end - attribute \src "ls180.v:5989.46-5989.102" - cell $and $and$ls180.v:5989$1450 + attribute \src "ls180.v:6126.46-6126.102" + cell $and $and$ls180.v:6126$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5989$1449_Y - connect \Y $and$ls180.v:5989$1450_Y + connect \B $not$ls180.v:6126$1582_Y + connect \Y $and$ls180.v:6126$1583_Y end - attribute \src "ls180.v:5989.45-5989.152" - cell $and $and$ls180.v:5989$1452 + attribute \src "ls180.v:6126.45-6126.152" + cell $and $and$ls180.v:6126$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5989$1450_Y - connect \B $eq$ls180.v:5989$1451_Y - connect \Y $and$ls180.v:5989$1452_Y + connect \A $and$ls180.v:6126$1583_Y + connect \B $eq$ls180.v:6126$1584_Y + connect \Y $and$ls180.v:6126$1585_Y end - attribute \src "ls180.v:5991.46-5991.99" - cell $and $and$ls180.v:5991$1453 + attribute \src "ls180.v:6128.46-6128.99" + cell $and $and$ls180.v:6128$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241606,43 +243326,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5991$1453_Y + connect \Y $and$ls180.v:6128$1586_Y end - attribute \src "ls180.v:5991.45-5991.149" - cell $and $and$ls180.v:5991$1455 + attribute \src "ls180.v:6128.45-6128.149" + cell $and $and$ls180.v:6128$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5991$1453_Y - connect \B $eq$ls180.v:5991$1454_Y - connect \Y $and$ls180.v:5991$1455_Y + connect \A $and$ls180.v:6128$1586_Y + connect \B $eq$ls180.v:6128$1587_Y + connect \Y $and$ls180.v:6128$1588_Y end - attribute \src "ls180.v:5992.46-5992.102" - cell $and $and$ls180.v:5992$1457 + attribute \src "ls180.v:6129.46-6129.102" + cell $and $and$ls180.v:6129$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5992$1456_Y - connect \Y $and$ls180.v:5992$1457_Y + connect \B $not$ls180.v:6129$1589_Y + connect \Y $and$ls180.v:6129$1590_Y end - attribute \src "ls180.v:5992.45-5992.152" - cell $and $and$ls180.v:5992$1459 + attribute \src "ls180.v:6129.45-6129.152" + cell $and $and$ls180.v:6129$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5992$1457_Y - connect \B $eq$ls180.v:5992$1458_Y - connect \Y $and$ls180.v:5992$1459_Y + connect \A $and$ls180.v:6129$1590_Y + connect \B $eq$ls180.v:6129$1591_Y + connect \Y $and$ls180.v:6129$1592_Y end - attribute \src "ls180.v:5994.46-5994.99" - cell $and $and$ls180.v:5994$1460 + attribute \src "ls180.v:6131.46-6131.99" + cell $and $and$ls180.v:6131$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241650,43 +243370,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5994$1460_Y + connect \Y $and$ls180.v:6131$1593_Y end - attribute \src "ls180.v:5994.45-5994.149" - cell $and $and$ls180.v:5994$1462 + attribute \src "ls180.v:6131.45-6131.149" + cell $and $and$ls180.v:6131$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5994$1460_Y - connect \B $eq$ls180.v:5994$1461_Y - connect \Y $and$ls180.v:5994$1462_Y + connect \A $and$ls180.v:6131$1593_Y + connect \B $eq$ls180.v:6131$1594_Y + connect \Y $and$ls180.v:6131$1595_Y end - attribute \src "ls180.v:5995.46-5995.102" - cell $and $and$ls180.v:5995$1464 + attribute \src "ls180.v:6132.46-6132.102" + cell $and $and$ls180.v:6132$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5995$1463_Y - connect \Y $and$ls180.v:5995$1464_Y + connect \B $not$ls180.v:6132$1596_Y + connect \Y $and$ls180.v:6132$1597_Y end - attribute \src "ls180.v:5995.45-5995.152" - cell $and $and$ls180.v:5995$1466 + attribute \src "ls180.v:6132.45-6132.152" + cell $and $and$ls180.v:6132$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5995$1464_Y - connect \B $eq$ls180.v:5995$1465_Y - connect \Y $and$ls180.v:5995$1466_Y + connect \A $and$ls180.v:6132$1597_Y + connect \B $eq$ls180.v:6132$1598_Y + connect \Y $and$ls180.v:6132$1599_Y end - attribute \src "ls180.v:5997.45-5997.98" - cell $and $and$ls180.v:5997$1467 + attribute \src "ls180.v:6134.45-6134.98" + cell $and $and$ls180.v:6134$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241694,43 +243414,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5997$1467_Y + connect \Y $and$ls180.v:6134$1600_Y end - attribute \src "ls180.v:5997.44-5997.148" - cell $and $and$ls180.v:5997$1469 + attribute \src "ls180.v:6134.44-6134.148" + cell $and $and$ls180.v:6134$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5997$1467_Y - connect \B $eq$ls180.v:5997$1468_Y - connect \Y $and$ls180.v:5997$1469_Y + connect \A $and$ls180.v:6134$1600_Y + connect \B $eq$ls180.v:6134$1601_Y + connect \Y $and$ls180.v:6134$1602_Y end - attribute \src "ls180.v:5998.45-5998.101" - cell $and $and$ls180.v:5998$1471 + attribute \src "ls180.v:6135.45-6135.101" + cell $and $and$ls180.v:6135$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5998$1470_Y - connect \Y $and$ls180.v:5998$1471_Y + connect \B $not$ls180.v:6135$1603_Y + connect \Y $and$ls180.v:6135$1604_Y end - attribute \src "ls180.v:5998.44-5998.151" - cell $and $and$ls180.v:5998$1473 + attribute \src "ls180.v:6135.44-6135.151" + cell $and $and$ls180.v:6135$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5998$1471_Y - connect \B $eq$ls180.v:5998$1472_Y - connect \Y $and$ls180.v:5998$1473_Y + connect \A $and$ls180.v:6135$1604_Y + connect \B $eq$ls180.v:6135$1605_Y + connect \Y $and$ls180.v:6135$1606_Y end - attribute \src "ls180.v:6000.45-6000.98" - cell $and $and$ls180.v:6000$1474 + attribute \src "ls180.v:6137.45-6137.98" + cell $and $and$ls180.v:6137$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241738,43 +243458,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6000$1474_Y + connect \Y $and$ls180.v:6137$1607_Y end - attribute \src "ls180.v:6000.44-6000.148" - cell $and $and$ls180.v:6000$1476 + attribute \src "ls180.v:6137.44-6137.148" + cell $and $and$ls180.v:6137$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6000$1474_Y - connect \B $eq$ls180.v:6000$1475_Y - connect \Y $and$ls180.v:6000$1476_Y + connect \A $and$ls180.v:6137$1607_Y + connect \B $eq$ls180.v:6137$1608_Y + connect \Y $and$ls180.v:6137$1609_Y end - attribute \src "ls180.v:6001.45-6001.101" - cell $and $and$ls180.v:6001$1478 + attribute \src "ls180.v:6138.45-6138.101" + cell $and $and$ls180.v:6138$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6001$1477_Y - connect \Y $and$ls180.v:6001$1478_Y + connect \B $not$ls180.v:6138$1610_Y + connect \Y $and$ls180.v:6138$1611_Y end - attribute \src "ls180.v:6001.44-6001.151" - cell $and $and$ls180.v:6001$1480 + attribute \src "ls180.v:6138.44-6138.151" + cell $and $and$ls180.v:6138$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6001$1478_Y - connect \B $eq$ls180.v:6001$1479_Y - connect \Y $and$ls180.v:6001$1480_Y + connect \A $and$ls180.v:6138$1611_Y + connect \B $eq$ls180.v:6138$1612_Y + connect \Y $and$ls180.v:6138$1613_Y end - attribute \src "ls180.v:6003.45-6003.98" - cell $and $and$ls180.v:6003$1481 + attribute \src "ls180.v:6140.45-6140.98" + cell $and $and$ls180.v:6140$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241782,43 +243502,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6003$1481_Y + connect \Y $and$ls180.v:6140$1614_Y end - attribute \src "ls180.v:6003.44-6003.148" - cell $and $and$ls180.v:6003$1483 + attribute \src "ls180.v:6140.44-6140.148" + cell $and $and$ls180.v:6140$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6003$1481_Y - connect \B $eq$ls180.v:6003$1482_Y - connect \Y $and$ls180.v:6003$1483_Y + connect \A $and$ls180.v:6140$1614_Y + connect \B $eq$ls180.v:6140$1615_Y + connect \Y $and$ls180.v:6140$1616_Y end - attribute \src "ls180.v:6004.45-6004.101" - cell $and $and$ls180.v:6004$1485 + attribute \src "ls180.v:6141.45-6141.101" + cell $and $and$ls180.v:6141$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6004$1484_Y - connect \Y $and$ls180.v:6004$1485_Y + connect \B $not$ls180.v:6141$1617_Y + connect \Y $and$ls180.v:6141$1618_Y end - attribute \src "ls180.v:6004.44-6004.151" - cell $and $and$ls180.v:6004$1487 + attribute \src "ls180.v:6141.44-6141.151" + cell $and $and$ls180.v:6141$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6004$1485_Y - connect \B $eq$ls180.v:6004$1486_Y - connect \Y $and$ls180.v:6004$1487_Y + connect \A $and$ls180.v:6141$1618_Y + connect \B $eq$ls180.v:6141$1619_Y + connect \Y $and$ls180.v:6141$1620_Y end - attribute \src "ls180.v:6006.45-6006.98" - cell $and $and$ls180.v:6006$1488 + attribute \src "ls180.v:6143.45-6143.98" + cell $and $and$ls180.v:6143$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241826,43 +243546,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6006$1488_Y + connect \Y $and$ls180.v:6143$1621_Y end - attribute \src "ls180.v:6006.44-6006.148" - cell $and $and$ls180.v:6006$1490 + attribute \src "ls180.v:6143.44-6143.148" + cell $and $and$ls180.v:6143$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6006$1488_Y - connect \B $eq$ls180.v:6006$1489_Y - connect \Y $and$ls180.v:6006$1490_Y + connect \A $and$ls180.v:6143$1621_Y + connect \B $eq$ls180.v:6143$1622_Y + connect \Y $and$ls180.v:6143$1623_Y end - attribute \src "ls180.v:6007.45-6007.101" - cell $and $and$ls180.v:6007$1492 + attribute \src "ls180.v:6144.45-6144.101" + cell $and $and$ls180.v:6144$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6007$1491_Y - connect \Y $and$ls180.v:6007$1492_Y + connect \B $not$ls180.v:6144$1624_Y + connect \Y $and$ls180.v:6144$1625_Y end - attribute \src "ls180.v:6007.44-6007.151" - cell $and $and$ls180.v:6007$1494 + attribute \src "ls180.v:6144.44-6144.151" + cell $and $and$ls180.v:6144$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6007$1492_Y - connect \B $eq$ls180.v:6007$1493_Y - connect \Y $and$ls180.v:6007$1494_Y + connect \A $and$ls180.v:6144$1625_Y + connect \B $eq$ls180.v:6144$1626_Y + connect \Y $and$ls180.v:6144$1627_Y end - attribute \src "ls180.v:6009.36-6009.89" - cell $and $and$ls180.v:6009$1495 + attribute \src "ls180.v:6146.36-6146.89" + cell $and $and$ls180.v:6146$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241870,43 +243590,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6009$1495_Y + connect \Y $and$ls180.v:6146$1628_Y end - attribute \src "ls180.v:6009.35-6009.139" - cell $and $and$ls180.v:6009$1497 + attribute \src "ls180.v:6146.35-6146.139" + cell $and $and$ls180.v:6146$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6009$1495_Y - connect \B $eq$ls180.v:6009$1496_Y - connect \Y $and$ls180.v:6009$1497_Y + connect \A $and$ls180.v:6146$1628_Y + connect \B $eq$ls180.v:6146$1629_Y + connect \Y $and$ls180.v:6146$1630_Y end - attribute \src "ls180.v:6010.36-6010.92" - cell $and $and$ls180.v:6010$1499 + attribute \src "ls180.v:6147.36-6147.92" + cell $and $and$ls180.v:6147$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6010$1498_Y - connect \Y $and$ls180.v:6010$1499_Y + connect \B $not$ls180.v:6147$1631_Y + connect \Y $and$ls180.v:6147$1632_Y end - attribute \src "ls180.v:6010.35-6010.142" - cell $and $and$ls180.v:6010$1501 + attribute \src "ls180.v:6147.35-6147.142" + cell $and $and$ls180.v:6147$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6010$1499_Y - connect \B $eq$ls180.v:6010$1500_Y - connect \Y $and$ls180.v:6010$1501_Y + connect \A $and$ls180.v:6147$1632_Y + connect \B $eq$ls180.v:6147$1633_Y + connect \Y $and$ls180.v:6147$1634_Y end - attribute \src "ls180.v:6012.47-6012.100" - cell $and $and$ls180.v:6012$1502 + attribute \src "ls180.v:6149.47-6149.100" + cell $and $and$ls180.v:6149$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241914,43 +243634,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6012$1502_Y + connect \Y $and$ls180.v:6149$1635_Y end - attribute \src "ls180.v:6012.46-6012.150" - cell $and $and$ls180.v:6012$1504 + attribute \src "ls180.v:6149.46-6149.150" + cell $and $and$ls180.v:6149$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6012$1502_Y - connect \B $eq$ls180.v:6012$1503_Y - connect \Y $and$ls180.v:6012$1504_Y + connect \A $and$ls180.v:6149$1635_Y + connect \B $eq$ls180.v:6149$1636_Y + connect \Y $and$ls180.v:6149$1637_Y end - attribute \src "ls180.v:6013.47-6013.103" - cell $and $and$ls180.v:6013$1506 + attribute \src "ls180.v:6150.47-6150.103" + cell $and $and$ls180.v:6150$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6013$1505_Y - connect \Y $and$ls180.v:6013$1506_Y + connect \B $not$ls180.v:6150$1638_Y + connect \Y $and$ls180.v:6150$1639_Y end - attribute \src "ls180.v:6013.46-6013.153" - cell $and $and$ls180.v:6013$1508 + attribute \src "ls180.v:6150.46-6150.153" + cell $and $and$ls180.v:6150$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6013$1506_Y - connect \B $eq$ls180.v:6013$1507_Y - connect \Y $and$ls180.v:6013$1508_Y + connect \A $and$ls180.v:6150$1639_Y + connect \B $eq$ls180.v:6150$1640_Y + connect \Y $and$ls180.v:6150$1641_Y end - attribute \src "ls180.v:6015.47-6015.100" - cell $and $and$ls180.v:6015$1509 + attribute \src "ls180.v:6152.47-6152.100" + cell $and $and$ls180.v:6152$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241958,43 +243678,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6015$1509_Y + connect \Y $and$ls180.v:6152$1642_Y end - attribute \src "ls180.v:6015.46-6015.151" - cell $and $and$ls180.v:6015$1511 + attribute \src "ls180.v:6152.46-6152.151" + cell $and $and$ls180.v:6152$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6015$1509_Y - connect \B $eq$ls180.v:6015$1510_Y - connect \Y $and$ls180.v:6015$1511_Y + connect \A $and$ls180.v:6152$1642_Y + connect \B $eq$ls180.v:6152$1643_Y + connect \Y $and$ls180.v:6152$1644_Y end - attribute \src "ls180.v:6016.47-6016.103" - cell $and $and$ls180.v:6016$1513 + attribute \src "ls180.v:6153.47-6153.103" + cell $and $and$ls180.v:6153$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6016$1512_Y - connect \Y $and$ls180.v:6016$1513_Y + connect \B $not$ls180.v:6153$1645_Y + connect \Y $and$ls180.v:6153$1646_Y end - attribute \src "ls180.v:6016.46-6016.154" - cell $and $and$ls180.v:6016$1515 + attribute \src "ls180.v:6153.46-6153.154" + cell $and $and$ls180.v:6153$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6016$1513_Y - connect \B $eq$ls180.v:6016$1514_Y - connect \Y $and$ls180.v:6016$1515_Y + connect \A $and$ls180.v:6153$1646_Y + connect \B $eq$ls180.v:6153$1647_Y + connect \Y $and$ls180.v:6153$1648_Y end - attribute \src "ls180.v:6018.47-6018.100" - cell $and $and$ls180.v:6018$1516 + attribute \src "ls180.v:6155.47-6155.100" + cell $and $and$ls180.v:6155$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242002,43 +243722,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6018$1516_Y + connect \Y $and$ls180.v:6155$1649_Y end - attribute \src "ls180.v:6018.46-6018.151" - cell $and $and$ls180.v:6018$1518 + attribute \src "ls180.v:6155.46-6155.151" + cell $and $and$ls180.v:6155$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6018$1516_Y - connect \B $eq$ls180.v:6018$1517_Y - connect \Y $and$ls180.v:6018$1518_Y + connect \A $and$ls180.v:6155$1649_Y + connect \B $eq$ls180.v:6155$1650_Y + connect \Y $and$ls180.v:6155$1651_Y end - attribute \src "ls180.v:6019.47-6019.103" - cell $and $and$ls180.v:6019$1520 + attribute \src "ls180.v:6156.47-6156.103" + cell $and $and$ls180.v:6156$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6019$1519_Y - connect \Y $and$ls180.v:6019$1520_Y + connect \B $not$ls180.v:6156$1652_Y + connect \Y $and$ls180.v:6156$1653_Y end - attribute \src "ls180.v:6019.46-6019.154" - cell $and $and$ls180.v:6019$1522 + attribute \src "ls180.v:6156.46-6156.154" + cell $and $and$ls180.v:6156$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6019$1520_Y - connect \B $eq$ls180.v:6019$1521_Y - connect \Y $and$ls180.v:6019$1522_Y + connect \A $and$ls180.v:6156$1653_Y + connect \B $eq$ls180.v:6156$1654_Y + connect \Y $and$ls180.v:6156$1655_Y end - attribute \src "ls180.v:6021.47-6021.100" - cell $and $and$ls180.v:6021$1523 + attribute \src "ls180.v:6158.47-6158.100" + cell $and $and$ls180.v:6158$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242046,43 +243766,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6021$1523_Y + connect \Y $and$ls180.v:6158$1656_Y end - attribute \src "ls180.v:6021.46-6021.151" - cell $and $and$ls180.v:6021$1525 + attribute \src "ls180.v:6158.46-6158.151" + cell $and $and$ls180.v:6158$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6021$1523_Y - connect \B $eq$ls180.v:6021$1524_Y - connect \Y $and$ls180.v:6021$1525_Y + connect \A $and$ls180.v:6158$1656_Y + connect \B $eq$ls180.v:6158$1657_Y + connect \Y $and$ls180.v:6158$1658_Y end - attribute \src "ls180.v:6022.47-6022.103" - cell $and $and$ls180.v:6022$1527 + attribute \src "ls180.v:6159.47-6159.103" + cell $and $and$ls180.v:6159$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6022$1526_Y - connect \Y $and$ls180.v:6022$1527_Y + connect \B $not$ls180.v:6159$1659_Y + connect \Y $and$ls180.v:6159$1660_Y end - attribute \src "ls180.v:6022.46-6022.154" - cell $and $and$ls180.v:6022$1529 + attribute \src "ls180.v:6159.46-6159.154" + cell $and $and$ls180.v:6159$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6022$1527_Y - connect \B $eq$ls180.v:6022$1528_Y - connect \Y $and$ls180.v:6022$1529_Y + connect \A $and$ls180.v:6159$1660_Y + connect \B $eq$ls180.v:6159$1661_Y + connect \Y $and$ls180.v:6159$1662_Y end - attribute \src "ls180.v:6024.47-6024.100" - cell $and $and$ls180.v:6024$1530 + attribute \src "ls180.v:6161.47-6161.100" + cell $and $and$ls180.v:6161$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242090,43 +243810,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6024$1530_Y + connect \Y $and$ls180.v:6161$1663_Y end - attribute \src "ls180.v:6024.46-6024.151" - cell $and $and$ls180.v:6024$1532 + attribute \src "ls180.v:6161.46-6161.151" + cell $and $and$ls180.v:6161$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6024$1530_Y - connect \B $eq$ls180.v:6024$1531_Y - connect \Y $and$ls180.v:6024$1532_Y + connect \A $and$ls180.v:6161$1663_Y + connect \B $eq$ls180.v:6161$1664_Y + connect \Y $and$ls180.v:6161$1665_Y end - attribute \src "ls180.v:6025.47-6025.103" - cell $and $and$ls180.v:6025$1534 + attribute \src "ls180.v:6162.47-6162.103" + cell $and $and$ls180.v:6162$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6025$1533_Y - connect \Y $and$ls180.v:6025$1534_Y + connect \B $not$ls180.v:6162$1666_Y + connect \Y $and$ls180.v:6162$1667_Y end - attribute \src "ls180.v:6025.46-6025.154" - cell $and $and$ls180.v:6025$1536 + attribute \src "ls180.v:6162.46-6162.154" + cell $and $and$ls180.v:6162$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6025$1534_Y - connect \B $eq$ls180.v:6025$1535_Y - connect \Y $and$ls180.v:6025$1536_Y + connect \A $and$ls180.v:6162$1667_Y + connect \B $eq$ls180.v:6162$1668_Y + connect \Y $and$ls180.v:6162$1669_Y end - attribute \src "ls180.v:6027.47-6027.100" - cell $and $and$ls180.v:6027$1537 + attribute \src "ls180.v:6164.47-6164.100" + cell $and $and$ls180.v:6164$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242134,43 +243854,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6027$1537_Y + connect \Y $and$ls180.v:6164$1670_Y end - attribute \src "ls180.v:6027.46-6027.151" - cell $and $and$ls180.v:6027$1539 + attribute \src "ls180.v:6164.46-6164.151" + cell $and $and$ls180.v:6164$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6027$1537_Y - connect \B $eq$ls180.v:6027$1538_Y - connect \Y $and$ls180.v:6027$1539_Y + connect \A $and$ls180.v:6164$1670_Y + connect \B $eq$ls180.v:6164$1671_Y + connect \Y $and$ls180.v:6164$1672_Y end - attribute \src "ls180.v:6028.47-6028.103" - cell $and $and$ls180.v:6028$1541 + attribute \src "ls180.v:6165.47-6165.103" + cell $and $and$ls180.v:6165$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6028$1540_Y - connect \Y $and$ls180.v:6028$1541_Y + connect \B $not$ls180.v:6165$1673_Y + connect \Y $and$ls180.v:6165$1674_Y end - attribute \src "ls180.v:6028.46-6028.154" - cell $and $and$ls180.v:6028$1543 + attribute \src "ls180.v:6165.46-6165.154" + cell $and $and$ls180.v:6165$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6028$1541_Y - connect \B $eq$ls180.v:6028$1542_Y - connect \Y $and$ls180.v:6028$1543_Y + connect \A $and$ls180.v:6165$1674_Y + connect \B $eq$ls180.v:6165$1675_Y + connect \Y $and$ls180.v:6165$1676_Y end - attribute \src "ls180.v:6030.46-6030.99" - cell $and $and$ls180.v:6030$1544 + attribute \src "ls180.v:6167.46-6167.99" + cell $and $and$ls180.v:6167$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242178,43 +243898,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6030$1544_Y + connect \Y $and$ls180.v:6167$1677_Y end - attribute \src "ls180.v:6030.45-6030.150" - cell $and $and$ls180.v:6030$1546 + attribute \src "ls180.v:6167.45-6167.150" + cell $and $and$ls180.v:6167$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6030$1544_Y - connect \B $eq$ls180.v:6030$1545_Y - connect \Y $and$ls180.v:6030$1546_Y + connect \A $and$ls180.v:6167$1677_Y + connect \B $eq$ls180.v:6167$1678_Y + connect \Y $and$ls180.v:6167$1679_Y end - attribute \src "ls180.v:6031.46-6031.102" - cell $and $and$ls180.v:6031$1548 + attribute \src "ls180.v:6168.46-6168.102" + cell $and $and$ls180.v:6168$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6031$1547_Y - connect \Y $and$ls180.v:6031$1548_Y + connect \B $not$ls180.v:6168$1680_Y + connect \Y $and$ls180.v:6168$1681_Y end - attribute \src "ls180.v:6031.45-6031.153" - cell $and $and$ls180.v:6031$1550 + attribute \src "ls180.v:6168.45-6168.153" + cell $and $and$ls180.v:6168$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6031$1548_Y - connect \B $eq$ls180.v:6031$1549_Y - connect \Y $and$ls180.v:6031$1550_Y + connect \A $and$ls180.v:6168$1681_Y + connect \B $eq$ls180.v:6168$1682_Y + connect \Y $and$ls180.v:6168$1683_Y end - attribute \src "ls180.v:6033.46-6033.99" - cell $and $and$ls180.v:6033$1551 + attribute \src "ls180.v:6170.46-6170.99" + cell $and $and$ls180.v:6170$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242222,43 +243942,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6033$1551_Y + connect \Y $and$ls180.v:6170$1684_Y end - attribute \src "ls180.v:6033.45-6033.150" - cell $and $and$ls180.v:6033$1553 + attribute \src "ls180.v:6170.45-6170.150" + cell $and $and$ls180.v:6170$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6033$1551_Y - connect \B $eq$ls180.v:6033$1552_Y - connect \Y $and$ls180.v:6033$1553_Y + connect \A $and$ls180.v:6170$1684_Y + connect \B $eq$ls180.v:6170$1685_Y + connect \Y $and$ls180.v:6170$1686_Y end - attribute \src "ls180.v:6034.46-6034.102" - cell $and $and$ls180.v:6034$1555 + attribute \src "ls180.v:6171.46-6171.102" + cell $and $and$ls180.v:6171$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6034$1554_Y - connect \Y $and$ls180.v:6034$1555_Y + connect \B $not$ls180.v:6171$1687_Y + connect \Y $and$ls180.v:6171$1688_Y end - attribute \src "ls180.v:6034.45-6034.153" - cell $and $and$ls180.v:6034$1557 + attribute \src "ls180.v:6171.45-6171.153" + cell $and $and$ls180.v:6171$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6034$1555_Y - connect \B $eq$ls180.v:6034$1556_Y - connect \Y $and$ls180.v:6034$1557_Y + connect \A $and$ls180.v:6171$1688_Y + connect \B $eq$ls180.v:6171$1689_Y + connect \Y $and$ls180.v:6171$1690_Y end - attribute \src "ls180.v:6036.46-6036.99" - cell $and $and$ls180.v:6036$1558 + attribute \src "ls180.v:6173.46-6173.99" + cell $and $and$ls180.v:6173$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242266,43 +243986,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6036$1558_Y + connect \Y $and$ls180.v:6173$1691_Y end - attribute \src "ls180.v:6036.45-6036.150" - cell $and $and$ls180.v:6036$1560 + attribute \src "ls180.v:6173.45-6173.150" + cell $and $and$ls180.v:6173$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6036$1558_Y - connect \B $eq$ls180.v:6036$1559_Y - connect \Y $and$ls180.v:6036$1560_Y + connect \A $and$ls180.v:6173$1691_Y + connect \B $eq$ls180.v:6173$1692_Y + connect \Y $and$ls180.v:6173$1693_Y end - attribute \src "ls180.v:6037.46-6037.102" - cell $and $and$ls180.v:6037$1562 + attribute \src "ls180.v:6174.46-6174.102" + cell $and $and$ls180.v:6174$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6037$1561_Y - connect \Y $and$ls180.v:6037$1562_Y + connect \B $not$ls180.v:6174$1694_Y + connect \Y $and$ls180.v:6174$1695_Y end - attribute \src "ls180.v:6037.45-6037.153" - cell $and $and$ls180.v:6037$1564 + attribute \src "ls180.v:6174.45-6174.153" + cell $and $and$ls180.v:6174$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6037$1562_Y - connect \B $eq$ls180.v:6037$1563_Y - connect \Y $and$ls180.v:6037$1564_Y + connect \A $and$ls180.v:6174$1695_Y + connect \B $eq$ls180.v:6174$1696_Y + connect \Y $and$ls180.v:6174$1697_Y end - attribute \src "ls180.v:6039.46-6039.99" - cell $and $and$ls180.v:6039$1565 + attribute \src "ls180.v:6176.46-6176.99" + cell $and $and$ls180.v:6176$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242310,43 +244030,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6039$1565_Y + connect \Y $and$ls180.v:6176$1698_Y end - attribute \src "ls180.v:6039.45-6039.150" - cell $and $and$ls180.v:6039$1567 + attribute \src "ls180.v:6176.45-6176.150" + cell $and $and$ls180.v:6176$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6039$1565_Y - connect \B $eq$ls180.v:6039$1566_Y - connect \Y $and$ls180.v:6039$1567_Y + connect \A $and$ls180.v:6176$1698_Y + connect \B $eq$ls180.v:6176$1699_Y + connect \Y $and$ls180.v:6176$1700_Y end - attribute \src "ls180.v:6040.46-6040.102" - cell $and $and$ls180.v:6040$1569 + attribute \src "ls180.v:6177.46-6177.102" + cell $and $and$ls180.v:6177$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6040$1568_Y - connect \Y $and$ls180.v:6040$1569_Y + connect \B $not$ls180.v:6177$1701_Y + connect \Y $and$ls180.v:6177$1702_Y end - attribute \src "ls180.v:6040.45-6040.153" - cell $and $and$ls180.v:6040$1571 + attribute \src "ls180.v:6177.45-6177.153" + cell $and $and$ls180.v:6177$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6040$1569_Y - connect \B $eq$ls180.v:6040$1570_Y - connect \Y $and$ls180.v:6040$1571_Y + connect \A $and$ls180.v:6177$1702_Y + connect \B $eq$ls180.v:6177$1703_Y + connect \Y $and$ls180.v:6177$1704_Y end - attribute \src "ls180.v:6042.46-6042.99" - cell $and $and$ls180.v:6042$1572 + attribute \src "ls180.v:6179.46-6179.99" + cell $and $and$ls180.v:6179$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242354,43 +244074,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6042$1572_Y + connect \Y $and$ls180.v:6179$1705_Y end - attribute \src "ls180.v:6042.45-6042.150" - cell $and $and$ls180.v:6042$1574 + attribute \src "ls180.v:6179.45-6179.150" + cell $and $and$ls180.v:6179$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6042$1572_Y - connect \B $eq$ls180.v:6042$1573_Y - connect \Y $and$ls180.v:6042$1574_Y + connect \A $and$ls180.v:6179$1705_Y + connect \B $eq$ls180.v:6179$1706_Y + connect \Y $and$ls180.v:6179$1707_Y end - attribute \src "ls180.v:6043.46-6043.102" - cell $and $and$ls180.v:6043$1576 + attribute \src "ls180.v:6180.46-6180.102" + cell $and $and$ls180.v:6180$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6043$1575_Y - connect \Y $and$ls180.v:6043$1576_Y + connect \B $not$ls180.v:6180$1708_Y + connect \Y $and$ls180.v:6180$1709_Y end - attribute \src "ls180.v:6043.45-6043.153" - cell $and $and$ls180.v:6043$1578 + attribute \src "ls180.v:6180.45-6180.153" + cell $and $and$ls180.v:6180$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6043$1576_Y - connect \B $eq$ls180.v:6043$1577_Y - connect \Y $and$ls180.v:6043$1578_Y + connect \A $and$ls180.v:6180$1709_Y + connect \B $eq$ls180.v:6180$1710_Y + connect \Y $and$ls180.v:6180$1711_Y end - attribute \src "ls180.v:6045.46-6045.99" - cell $and $and$ls180.v:6045$1579 + attribute \src "ls180.v:6182.46-6182.99" + cell $and $and$ls180.v:6182$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242398,43 +244118,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6045$1579_Y + connect \Y $and$ls180.v:6182$1712_Y end - attribute \src "ls180.v:6045.45-6045.150" - cell $and $and$ls180.v:6045$1581 + attribute \src "ls180.v:6182.45-6182.150" + cell $and $and$ls180.v:6182$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6045$1579_Y - connect \B $eq$ls180.v:6045$1580_Y - connect \Y $and$ls180.v:6045$1581_Y + connect \A $and$ls180.v:6182$1712_Y + connect \B $eq$ls180.v:6182$1713_Y + connect \Y $and$ls180.v:6182$1714_Y end - attribute \src "ls180.v:6046.46-6046.102" - cell $and $and$ls180.v:6046$1583 + attribute \src "ls180.v:6183.46-6183.102" + cell $and $and$ls180.v:6183$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6046$1582_Y - connect \Y $and$ls180.v:6046$1583_Y + connect \B $not$ls180.v:6183$1715_Y + connect \Y $and$ls180.v:6183$1716_Y end - attribute \src "ls180.v:6046.45-6046.153" - cell $and $and$ls180.v:6046$1585 + attribute \src "ls180.v:6183.45-6183.153" + cell $and $and$ls180.v:6183$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1583_Y - connect \B $eq$ls180.v:6046$1584_Y - connect \Y $and$ls180.v:6046$1585_Y + connect \A $and$ls180.v:6183$1716_Y + connect \B $eq$ls180.v:6183$1717_Y + connect \Y $and$ls180.v:6183$1718_Y end - attribute \src "ls180.v:6048.46-6048.99" - cell $and $and$ls180.v:6048$1586 + attribute \src "ls180.v:6185.46-6185.99" + cell $and $and$ls180.v:6185$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242442,43 +244162,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6048$1586_Y + connect \Y $and$ls180.v:6185$1719_Y end - attribute \src "ls180.v:6048.45-6048.150" - cell $and $and$ls180.v:6048$1588 + attribute \src "ls180.v:6185.45-6185.150" + cell $and $and$ls180.v:6185$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6048$1586_Y - connect \B $eq$ls180.v:6048$1587_Y - connect \Y $and$ls180.v:6048$1588_Y + connect \A $and$ls180.v:6185$1719_Y + connect \B $eq$ls180.v:6185$1720_Y + connect \Y $and$ls180.v:6185$1721_Y end - attribute \src "ls180.v:6049.46-6049.102" - cell $and $and$ls180.v:6049$1590 + attribute \src "ls180.v:6186.46-6186.102" + cell $and $and$ls180.v:6186$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6049$1589_Y - connect \Y $and$ls180.v:6049$1590_Y + connect \B $not$ls180.v:6186$1722_Y + connect \Y $and$ls180.v:6186$1723_Y end - attribute \src "ls180.v:6049.45-6049.153" - cell $and $and$ls180.v:6049$1592 + attribute \src "ls180.v:6186.45-6186.153" + cell $and $and$ls180.v:6186$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1590_Y - connect \B $eq$ls180.v:6049$1591_Y - connect \Y $and$ls180.v:6049$1592_Y + connect \A $and$ls180.v:6186$1723_Y + connect \B $eq$ls180.v:6186$1724_Y + connect \Y $and$ls180.v:6186$1725_Y end - attribute \src "ls180.v:6051.46-6051.99" - cell $and $and$ls180.v:6051$1593 + attribute \src "ls180.v:6188.46-6188.99" + cell $and $and$ls180.v:6188$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242486,43 +244206,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6051$1593_Y + connect \Y $and$ls180.v:6188$1726_Y end - attribute \src "ls180.v:6051.45-6051.150" - cell $and $and$ls180.v:6051$1595 + attribute \src "ls180.v:6188.45-6188.150" + cell $and $and$ls180.v:6188$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6051$1593_Y - connect \B $eq$ls180.v:6051$1594_Y - connect \Y $and$ls180.v:6051$1595_Y + connect \A $and$ls180.v:6188$1726_Y + connect \B $eq$ls180.v:6188$1727_Y + connect \Y $and$ls180.v:6188$1728_Y end - attribute \src "ls180.v:6052.46-6052.102" - cell $and $and$ls180.v:6052$1597 + attribute \src "ls180.v:6189.46-6189.102" + cell $and $and$ls180.v:6189$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6052$1596_Y - connect \Y $and$ls180.v:6052$1597_Y + connect \B $not$ls180.v:6189$1729_Y + connect \Y $and$ls180.v:6189$1730_Y end - attribute \src "ls180.v:6052.45-6052.153" - cell $and $and$ls180.v:6052$1599 + attribute \src "ls180.v:6189.45-6189.153" + cell $and $and$ls180.v:6189$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6052$1597_Y - connect \B $eq$ls180.v:6052$1598_Y - connect \Y $and$ls180.v:6052$1599_Y + connect \A $and$ls180.v:6189$1730_Y + connect \B $eq$ls180.v:6189$1731_Y + connect \Y $and$ls180.v:6189$1732_Y end - attribute \src "ls180.v:6054.46-6054.99" - cell $and $and$ls180.v:6054$1600 + attribute \src "ls180.v:6191.46-6191.99" + cell $and $and$ls180.v:6191$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242530,43 +244250,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6054$1600_Y + connect \Y $and$ls180.v:6191$1733_Y end - attribute \src "ls180.v:6054.45-6054.150" - cell $and $and$ls180.v:6054$1602 + attribute \src "ls180.v:6191.45-6191.150" + cell $and $and$ls180.v:6191$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6054$1600_Y - connect \B $eq$ls180.v:6054$1601_Y - connect \Y $and$ls180.v:6054$1602_Y + connect \A $and$ls180.v:6191$1733_Y + connect \B $eq$ls180.v:6191$1734_Y + connect \Y $and$ls180.v:6191$1735_Y end - attribute \src "ls180.v:6055.46-6055.102" - cell $and $and$ls180.v:6055$1604 + attribute \src "ls180.v:6192.46-6192.102" + cell $and $and$ls180.v:6192$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6055$1603_Y - connect \Y $and$ls180.v:6055$1604_Y + connect \B $not$ls180.v:6192$1736_Y + connect \Y $and$ls180.v:6192$1737_Y end - attribute \src "ls180.v:6055.45-6055.153" - cell $and $and$ls180.v:6055$1606 + attribute \src "ls180.v:6192.45-6192.153" + cell $and $and$ls180.v:6192$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1604_Y - connect \B $eq$ls180.v:6055$1605_Y - connect \Y $and$ls180.v:6055$1606_Y + connect \A $and$ls180.v:6192$1737_Y + connect \B $eq$ls180.v:6192$1738_Y + connect \Y $and$ls180.v:6192$1739_Y end - attribute \src "ls180.v:6057.46-6057.99" - cell $and $and$ls180.v:6057$1607 + attribute \src "ls180.v:6194.46-6194.99" + cell $and $and$ls180.v:6194$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242574,43 +244294,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6057$1607_Y + connect \Y $and$ls180.v:6194$1740_Y end - attribute \src "ls180.v:6057.45-6057.150" - cell $and $and$ls180.v:6057$1609 + attribute \src "ls180.v:6194.45-6194.150" + cell $and $and$ls180.v:6194$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6057$1607_Y - connect \B $eq$ls180.v:6057$1608_Y - connect \Y $and$ls180.v:6057$1609_Y + connect \A $and$ls180.v:6194$1740_Y + connect \B $eq$ls180.v:6194$1741_Y + connect \Y $and$ls180.v:6194$1742_Y end - attribute \src "ls180.v:6058.46-6058.102" - cell $and $and$ls180.v:6058$1611 + attribute \src "ls180.v:6195.46-6195.102" + cell $and $and$ls180.v:6195$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6058$1610_Y - connect \Y $and$ls180.v:6058$1611_Y + connect \B $not$ls180.v:6195$1743_Y + connect \Y $and$ls180.v:6195$1744_Y end - attribute \src "ls180.v:6058.45-6058.153" - cell $and $and$ls180.v:6058$1613 + attribute \src "ls180.v:6195.45-6195.153" + cell $and $and$ls180.v:6195$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1611_Y - connect \B $eq$ls180.v:6058$1612_Y - connect \Y $and$ls180.v:6058$1613_Y + connect \A $and$ls180.v:6195$1744_Y + connect \B $eq$ls180.v:6195$1745_Y + connect \Y $and$ls180.v:6195$1746_Y end - attribute \src "ls180.v:6060.42-6060.95" - cell $and $and$ls180.v:6060$1614 + attribute \src "ls180.v:6197.42-6197.95" + cell $and $and$ls180.v:6197$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242618,43 +244338,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6060$1614_Y + connect \Y $and$ls180.v:6197$1747_Y end - attribute \src "ls180.v:6060.41-6060.146" - cell $and $and$ls180.v:6060$1616 + attribute \src "ls180.v:6197.41-6197.146" + cell $and $and$ls180.v:6197$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6060$1614_Y - connect \B $eq$ls180.v:6060$1615_Y - connect \Y $and$ls180.v:6060$1616_Y + connect \A $and$ls180.v:6197$1747_Y + connect \B $eq$ls180.v:6197$1748_Y + connect \Y $and$ls180.v:6197$1749_Y end - attribute \src "ls180.v:6061.42-6061.98" - cell $and $and$ls180.v:6061$1618 + attribute \src "ls180.v:6198.42-6198.98" + cell $and $and$ls180.v:6198$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6061$1617_Y - connect \Y $and$ls180.v:6061$1618_Y + connect \B $not$ls180.v:6198$1750_Y + connect \Y $and$ls180.v:6198$1751_Y end - attribute \src "ls180.v:6061.41-6061.149" - cell $and $and$ls180.v:6061$1620 + attribute \src "ls180.v:6198.41-6198.149" + cell $and $and$ls180.v:6198$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1618_Y - connect \B $eq$ls180.v:6061$1619_Y - connect \Y $and$ls180.v:6061$1620_Y + connect \A $and$ls180.v:6198$1751_Y + connect \B $eq$ls180.v:6198$1752_Y + connect \Y $and$ls180.v:6198$1753_Y end - attribute \src "ls180.v:6063.43-6063.96" - cell $and $and$ls180.v:6063$1621 + attribute \src "ls180.v:6200.43-6200.96" + cell $and $and$ls180.v:6200$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242662,43 +244382,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6063$1621_Y + connect \Y $and$ls180.v:6200$1754_Y end - attribute \src "ls180.v:6063.42-6063.147" - cell $and $and$ls180.v:6063$1623 + attribute \src "ls180.v:6200.42-6200.147" + cell $and $and$ls180.v:6200$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6063$1621_Y - connect \B $eq$ls180.v:6063$1622_Y - connect \Y $and$ls180.v:6063$1623_Y + connect \A $and$ls180.v:6200$1754_Y + connect \B $eq$ls180.v:6200$1755_Y + connect \Y $and$ls180.v:6200$1756_Y end - attribute \src "ls180.v:6064.43-6064.99" - cell $and $and$ls180.v:6064$1625 + attribute \src "ls180.v:6201.43-6201.99" + cell $and $and$ls180.v:6201$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6064$1624_Y - connect \Y $and$ls180.v:6064$1625_Y + connect \B $not$ls180.v:6201$1757_Y + connect \Y $and$ls180.v:6201$1758_Y end - attribute \src "ls180.v:6064.42-6064.150" - cell $and $and$ls180.v:6064$1627 + attribute \src "ls180.v:6201.42-6201.150" + cell $and $and$ls180.v:6201$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1625_Y - connect \B $eq$ls180.v:6064$1626_Y - connect \Y $and$ls180.v:6064$1627_Y + connect \A $and$ls180.v:6201$1758_Y + connect \B $eq$ls180.v:6201$1759_Y + connect \Y $and$ls180.v:6201$1760_Y end - attribute \src "ls180.v:6066.46-6066.99" - cell $and $and$ls180.v:6066$1628 + attribute \src "ls180.v:6203.46-6203.99" + cell $and $and$ls180.v:6203$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242706,43 +244426,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6066$1628_Y + connect \Y $and$ls180.v:6203$1761_Y end - attribute \src "ls180.v:6066.45-6066.150" - cell $and $and$ls180.v:6066$1630 + attribute \src "ls180.v:6203.45-6203.150" + cell $and $and$ls180.v:6203$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6066$1628_Y - connect \B $eq$ls180.v:6066$1629_Y - connect \Y $and$ls180.v:6066$1630_Y + connect \A $and$ls180.v:6203$1761_Y + connect \B $eq$ls180.v:6203$1762_Y + connect \Y $and$ls180.v:6203$1763_Y end - attribute \src "ls180.v:6067.46-6067.102" - cell $and $and$ls180.v:6067$1632 + attribute \src "ls180.v:6204.46-6204.102" + cell $and $and$ls180.v:6204$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6067$1631_Y - connect \Y $and$ls180.v:6067$1632_Y + connect \B $not$ls180.v:6204$1764_Y + connect \Y $and$ls180.v:6204$1765_Y end - attribute \src "ls180.v:6067.45-6067.153" - cell $and $and$ls180.v:6067$1634 + attribute \src "ls180.v:6204.45-6204.153" + cell $and $and$ls180.v:6204$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1632_Y - connect \B $eq$ls180.v:6067$1633_Y - connect \Y $and$ls180.v:6067$1634_Y + connect \A $and$ls180.v:6204$1765_Y + connect \B $eq$ls180.v:6204$1766_Y + connect \Y $and$ls180.v:6204$1767_Y end - attribute \src "ls180.v:6069.46-6069.99" - cell $and $and$ls180.v:6069$1635 + attribute \src "ls180.v:6206.46-6206.99" + cell $and $and$ls180.v:6206$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242750,43 +244470,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6069$1635_Y + connect \Y $and$ls180.v:6206$1768_Y end - attribute \src "ls180.v:6069.45-6069.150" - cell $and $and$ls180.v:6069$1637 + attribute \src "ls180.v:6206.45-6206.150" + cell $and $and$ls180.v:6206$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6069$1635_Y - connect \B $eq$ls180.v:6069$1636_Y - connect \Y $and$ls180.v:6069$1637_Y + connect \A $and$ls180.v:6206$1768_Y + connect \B $eq$ls180.v:6206$1769_Y + connect \Y $and$ls180.v:6206$1770_Y end - attribute \src "ls180.v:6070.46-6070.102" - cell $and $and$ls180.v:6070$1639 + attribute \src "ls180.v:6207.46-6207.102" + cell $and $and$ls180.v:6207$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6070$1638_Y - connect \Y $and$ls180.v:6070$1639_Y + connect \B $not$ls180.v:6207$1771_Y + connect \Y $and$ls180.v:6207$1772_Y end - attribute \src "ls180.v:6070.45-6070.153" - cell $and $and$ls180.v:6070$1641 + attribute \src "ls180.v:6207.45-6207.153" + cell $and $and$ls180.v:6207$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6070$1639_Y - connect \B $eq$ls180.v:6070$1640_Y - connect \Y $and$ls180.v:6070$1641_Y + connect \A $and$ls180.v:6207$1772_Y + connect \B $eq$ls180.v:6207$1773_Y + connect \Y $and$ls180.v:6207$1774_Y end - attribute \src "ls180.v:6072.45-6072.98" - cell $and $and$ls180.v:6072$1642 + attribute \src "ls180.v:6209.45-6209.98" + cell $and $and$ls180.v:6209$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242794,43 +244514,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6072$1642_Y + connect \Y $and$ls180.v:6209$1775_Y end - attribute \src "ls180.v:6072.44-6072.149" - cell $and $and$ls180.v:6072$1644 + attribute \src "ls180.v:6209.44-6209.149" + cell $and $and$ls180.v:6209$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6072$1642_Y - connect \B $eq$ls180.v:6072$1643_Y - connect \Y $and$ls180.v:6072$1644_Y + connect \A $and$ls180.v:6209$1775_Y + connect \B $eq$ls180.v:6209$1776_Y + connect \Y $and$ls180.v:6209$1777_Y end - attribute \src "ls180.v:6073.45-6073.101" - cell $and $and$ls180.v:6073$1646 + attribute \src "ls180.v:6210.45-6210.101" + cell $and $and$ls180.v:6210$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6073$1645_Y - connect \Y $and$ls180.v:6073$1646_Y + connect \B $not$ls180.v:6210$1778_Y + connect \Y $and$ls180.v:6210$1779_Y end - attribute \src "ls180.v:6073.44-6073.152" - cell $and $and$ls180.v:6073$1648 + attribute \src "ls180.v:6210.44-6210.152" + cell $and $and$ls180.v:6210$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6073$1646_Y - connect \B $eq$ls180.v:6073$1647_Y - connect \Y $and$ls180.v:6073$1648_Y + connect \A $and$ls180.v:6210$1779_Y + connect \B $eq$ls180.v:6210$1780_Y + connect \Y $and$ls180.v:6210$1781_Y end - attribute \src "ls180.v:6075.45-6075.98" - cell $and $and$ls180.v:6075$1649 + attribute \src "ls180.v:6212.45-6212.98" + cell $and $and$ls180.v:6212$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242838,43 +244558,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6075$1649_Y + connect \Y $and$ls180.v:6212$1782_Y end - attribute \src "ls180.v:6075.44-6075.149" - cell $and $and$ls180.v:6075$1651 + attribute \src "ls180.v:6212.44-6212.149" + cell $and $and$ls180.v:6212$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6075$1649_Y - connect \B $eq$ls180.v:6075$1650_Y - connect \Y $and$ls180.v:6075$1651_Y + connect \A $and$ls180.v:6212$1782_Y + connect \B $eq$ls180.v:6212$1783_Y + connect \Y $and$ls180.v:6212$1784_Y end - attribute \src "ls180.v:6076.45-6076.101" - cell $and $and$ls180.v:6076$1653 + attribute \src "ls180.v:6213.45-6213.101" + cell $and $and$ls180.v:6213$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6076$1652_Y - connect \Y $and$ls180.v:6076$1653_Y + connect \B $not$ls180.v:6213$1785_Y + connect \Y $and$ls180.v:6213$1786_Y end - attribute \src "ls180.v:6076.44-6076.152" - cell $and $and$ls180.v:6076$1655 + attribute \src "ls180.v:6213.44-6213.152" + cell $and $and$ls180.v:6213$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6076$1653_Y - connect \B $eq$ls180.v:6076$1654_Y - connect \Y $and$ls180.v:6076$1655_Y + connect \A $and$ls180.v:6213$1786_Y + connect \B $eq$ls180.v:6213$1787_Y + connect \Y $and$ls180.v:6213$1788_Y end - attribute \src "ls180.v:6078.45-6078.98" - cell $and $and$ls180.v:6078$1656 + attribute \src "ls180.v:6215.45-6215.98" + cell $and $and$ls180.v:6215$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242882,43 +244602,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6078$1656_Y + connect \Y $and$ls180.v:6215$1789_Y end - attribute \src "ls180.v:6078.44-6078.149" - cell $and $and$ls180.v:6078$1658 + attribute \src "ls180.v:6215.44-6215.149" + cell $and $and$ls180.v:6215$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6078$1656_Y - connect \B $eq$ls180.v:6078$1657_Y - connect \Y $and$ls180.v:6078$1658_Y + connect \A $and$ls180.v:6215$1789_Y + connect \B $eq$ls180.v:6215$1790_Y + connect \Y $and$ls180.v:6215$1791_Y end - attribute \src "ls180.v:6079.45-6079.101" - cell $and $and$ls180.v:6079$1660 + attribute \src "ls180.v:6216.45-6216.101" + cell $and $and$ls180.v:6216$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6079$1659_Y - connect \Y $and$ls180.v:6079$1660_Y + connect \B $not$ls180.v:6216$1792_Y + connect \Y $and$ls180.v:6216$1793_Y end - attribute \src "ls180.v:6079.44-6079.152" - cell $and $and$ls180.v:6079$1662 + attribute \src "ls180.v:6216.44-6216.152" + cell $and $and$ls180.v:6216$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6079$1660_Y - connect \B $eq$ls180.v:6079$1661_Y - connect \Y $and$ls180.v:6079$1662_Y + connect \A $and$ls180.v:6216$1793_Y + connect \B $eq$ls180.v:6216$1794_Y + connect \Y $and$ls180.v:6216$1795_Y end - attribute \src "ls180.v:6081.45-6081.98" - cell $and $and$ls180.v:6081$1663 + attribute \src "ls180.v:6218.45-6218.98" + cell $and $and$ls180.v:6218$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242926,43 +244646,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6081$1663_Y + connect \Y $and$ls180.v:6218$1796_Y end - attribute \src "ls180.v:6081.44-6081.149" - cell $and $and$ls180.v:6081$1665 + attribute \src "ls180.v:6218.44-6218.149" + cell $and $and$ls180.v:6218$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6081$1663_Y - connect \B $eq$ls180.v:6081$1664_Y - connect \Y $and$ls180.v:6081$1665_Y + connect \A $and$ls180.v:6218$1796_Y + connect \B $eq$ls180.v:6218$1797_Y + connect \Y $and$ls180.v:6218$1798_Y end - attribute \src "ls180.v:6082.45-6082.101" - cell $and $and$ls180.v:6082$1667 + attribute \src "ls180.v:6219.45-6219.101" + cell $and $and$ls180.v:6219$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6082$1666_Y - connect \Y $and$ls180.v:6082$1667_Y + connect \B $not$ls180.v:6219$1799_Y + connect \Y $and$ls180.v:6219$1800_Y end - attribute \src "ls180.v:6082.44-6082.152" - cell $and $and$ls180.v:6082$1669 + attribute \src "ls180.v:6219.44-6219.152" + cell $and $and$ls180.v:6219$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6082$1667_Y - connect \B $eq$ls180.v:6082$1668_Y - connect \Y $and$ls180.v:6082$1669_Y + connect \A $and$ls180.v:6219$1800_Y + connect \B $eq$ls180.v:6219$1801_Y + connect \Y $and$ls180.v:6219$1802_Y end - attribute \src "ls180.v:6120.42-6120.95" - cell $and $and$ls180.v:6120$1671 + attribute \src "ls180.v:6257.42-6257.95" + cell $and $and$ls180.v:6257$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242970,43 +244690,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6120$1671_Y + connect \Y $and$ls180.v:6257$1804_Y end - attribute \src "ls180.v:6120.41-6120.145" - cell $and $and$ls180.v:6120$1673 + attribute \src "ls180.v:6257.41-6257.145" + cell $and $and$ls180.v:6257$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6120$1671_Y - connect \B $eq$ls180.v:6120$1672_Y - connect \Y $and$ls180.v:6120$1673_Y + connect \A $and$ls180.v:6257$1804_Y + connect \B $eq$ls180.v:6257$1805_Y + connect \Y $and$ls180.v:6257$1806_Y end - attribute \src "ls180.v:6121.42-6121.98" - cell $and $and$ls180.v:6121$1675 + attribute \src "ls180.v:6258.42-6258.98" + cell $and $and$ls180.v:6258$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6121$1674_Y - connect \Y $and$ls180.v:6121$1675_Y + connect \B $not$ls180.v:6258$1807_Y + connect \Y $and$ls180.v:6258$1808_Y end - attribute \src "ls180.v:6121.41-6121.148" - cell $and $and$ls180.v:6121$1677 + attribute \src "ls180.v:6258.41-6258.148" + cell $and $and$ls180.v:6258$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6121$1675_Y - connect \B $eq$ls180.v:6121$1676_Y - connect \Y $and$ls180.v:6121$1677_Y + connect \A $and$ls180.v:6258$1808_Y + connect \B $eq$ls180.v:6258$1809_Y + connect \Y $and$ls180.v:6258$1810_Y end - attribute \src "ls180.v:6123.42-6123.95" - cell $and $and$ls180.v:6123$1678 + attribute \src "ls180.v:6260.42-6260.95" + cell $and $and$ls180.v:6260$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243014,43 +244734,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6123$1678_Y + connect \Y $and$ls180.v:6260$1811_Y end - attribute \src "ls180.v:6123.41-6123.145" - cell $and $and$ls180.v:6123$1680 + attribute \src "ls180.v:6260.41-6260.145" + cell $and $and$ls180.v:6260$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6123$1678_Y - connect \B $eq$ls180.v:6123$1679_Y - connect \Y $and$ls180.v:6123$1680_Y + connect \A $and$ls180.v:6260$1811_Y + connect \B $eq$ls180.v:6260$1812_Y + connect \Y $and$ls180.v:6260$1813_Y end - attribute \src "ls180.v:6124.42-6124.98" - cell $and $and$ls180.v:6124$1682 + attribute \src "ls180.v:6261.42-6261.98" + cell $and $and$ls180.v:6261$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6124$1681_Y - connect \Y $and$ls180.v:6124$1682_Y + connect \B $not$ls180.v:6261$1814_Y + connect \Y $and$ls180.v:6261$1815_Y end - attribute \src "ls180.v:6124.41-6124.148" - cell $and $and$ls180.v:6124$1684 + attribute \src "ls180.v:6261.41-6261.148" + cell $and $and$ls180.v:6261$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1682_Y - connect \B $eq$ls180.v:6124$1683_Y - connect \Y $and$ls180.v:6124$1684_Y + connect \A $and$ls180.v:6261$1815_Y + connect \B $eq$ls180.v:6261$1816_Y + connect \Y $and$ls180.v:6261$1817_Y end - attribute \src "ls180.v:6126.42-6126.95" - cell $and $and$ls180.v:6126$1685 + attribute \src "ls180.v:6263.42-6263.95" + cell $and $and$ls180.v:6263$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243058,43 +244778,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6126$1685_Y + connect \Y $and$ls180.v:6263$1818_Y end - attribute \src "ls180.v:6126.41-6126.145" - cell $and $and$ls180.v:6126$1687 + attribute \src "ls180.v:6263.41-6263.145" + cell $and $and$ls180.v:6263$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6126$1685_Y - connect \B $eq$ls180.v:6126$1686_Y - connect \Y $and$ls180.v:6126$1687_Y + connect \A $and$ls180.v:6263$1818_Y + connect \B $eq$ls180.v:6263$1819_Y + connect \Y $and$ls180.v:6263$1820_Y end - attribute \src "ls180.v:6127.42-6127.98" - cell $and $and$ls180.v:6127$1689 + attribute \src "ls180.v:6264.42-6264.98" + cell $and $and$ls180.v:6264$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6127$1688_Y - connect \Y $and$ls180.v:6127$1689_Y + connect \B $not$ls180.v:6264$1821_Y + connect \Y $and$ls180.v:6264$1822_Y end - attribute \src "ls180.v:6127.41-6127.148" - cell $and $and$ls180.v:6127$1691 + attribute \src "ls180.v:6264.41-6264.148" + cell $and $and$ls180.v:6264$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1689_Y - connect \B $eq$ls180.v:6127$1690_Y - connect \Y $and$ls180.v:6127$1691_Y + connect \A $and$ls180.v:6264$1822_Y + connect \B $eq$ls180.v:6264$1823_Y + connect \Y $and$ls180.v:6264$1824_Y end - attribute \src "ls180.v:6129.42-6129.95" - cell $and $and$ls180.v:6129$1692 + attribute \src "ls180.v:6266.42-6266.95" + cell $and $and$ls180.v:6266$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243102,43 +244822,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6129$1692_Y + connect \Y $and$ls180.v:6266$1825_Y end - attribute \src "ls180.v:6129.41-6129.145" - cell $and $and$ls180.v:6129$1694 + attribute \src "ls180.v:6266.41-6266.145" + cell $and $and$ls180.v:6266$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6129$1692_Y - connect \B $eq$ls180.v:6129$1693_Y - connect \Y $and$ls180.v:6129$1694_Y + connect \A $and$ls180.v:6266$1825_Y + connect \B $eq$ls180.v:6266$1826_Y + connect \Y $and$ls180.v:6266$1827_Y end - attribute \src "ls180.v:6130.42-6130.98" - cell $and $and$ls180.v:6130$1696 + attribute \src "ls180.v:6267.42-6267.98" + cell $and $and$ls180.v:6267$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6130$1695_Y - connect \Y $and$ls180.v:6130$1696_Y + connect \B $not$ls180.v:6267$1828_Y + connect \Y $and$ls180.v:6267$1829_Y end - attribute \src "ls180.v:6130.41-6130.148" - cell $and $and$ls180.v:6130$1698 + attribute \src "ls180.v:6267.41-6267.148" + cell $and $and$ls180.v:6267$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1696_Y - connect \B $eq$ls180.v:6130$1697_Y - connect \Y $and$ls180.v:6130$1698_Y + connect \A $and$ls180.v:6267$1829_Y + connect \B $eq$ls180.v:6267$1830_Y + connect \Y $and$ls180.v:6267$1831_Y end - attribute \src "ls180.v:6132.42-6132.95" - cell $and $and$ls180.v:6132$1699 + attribute \src "ls180.v:6269.42-6269.95" + cell $and $and$ls180.v:6269$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243146,43 +244866,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6132$1699_Y + connect \Y $and$ls180.v:6269$1832_Y end - attribute \src "ls180.v:6132.41-6132.145" - cell $and $and$ls180.v:6132$1701 + attribute \src "ls180.v:6269.41-6269.145" + cell $and $and$ls180.v:6269$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6132$1699_Y - connect \B $eq$ls180.v:6132$1700_Y - connect \Y $and$ls180.v:6132$1701_Y + connect \A $and$ls180.v:6269$1832_Y + connect \B $eq$ls180.v:6269$1833_Y + connect \Y $and$ls180.v:6269$1834_Y end - attribute \src "ls180.v:6133.42-6133.98" - cell $and $and$ls180.v:6133$1703 + attribute \src "ls180.v:6270.42-6270.98" + cell $and $and$ls180.v:6270$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6133$1702_Y - connect \Y $and$ls180.v:6133$1703_Y + connect \B $not$ls180.v:6270$1835_Y + connect \Y $and$ls180.v:6270$1836_Y end - attribute \src "ls180.v:6133.41-6133.148" - cell $and $and$ls180.v:6133$1705 + attribute \src "ls180.v:6270.41-6270.148" + cell $and $and$ls180.v:6270$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1703_Y - connect \B $eq$ls180.v:6133$1704_Y - connect \Y $and$ls180.v:6133$1705_Y + connect \A $and$ls180.v:6270$1836_Y + connect \B $eq$ls180.v:6270$1837_Y + connect \Y $and$ls180.v:6270$1838_Y end - attribute \src "ls180.v:6135.42-6135.95" - cell $and $and$ls180.v:6135$1706 + attribute \src "ls180.v:6272.42-6272.95" + cell $and $and$ls180.v:6272$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243190,43 +244910,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6135$1706_Y + connect \Y $and$ls180.v:6272$1839_Y end - attribute \src "ls180.v:6135.41-6135.145" - cell $and $and$ls180.v:6135$1708 + attribute \src "ls180.v:6272.41-6272.145" + cell $and $and$ls180.v:6272$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6135$1706_Y - connect \B $eq$ls180.v:6135$1707_Y - connect \Y $and$ls180.v:6135$1708_Y + connect \A $and$ls180.v:6272$1839_Y + connect \B $eq$ls180.v:6272$1840_Y + connect \Y $and$ls180.v:6272$1841_Y end - attribute \src "ls180.v:6136.42-6136.98" - cell $and $and$ls180.v:6136$1710 + attribute \src "ls180.v:6273.42-6273.98" + cell $and $and$ls180.v:6273$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6136$1709_Y - connect \Y $and$ls180.v:6136$1710_Y + connect \B $not$ls180.v:6273$1842_Y + connect \Y $and$ls180.v:6273$1843_Y end - attribute \src "ls180.v:6136.41-6136.148" - cell $and $and$ls180.v:6136$1712 + attribute \src "ls180.v:6273.41-6273.148" + cell $and $and$ls180.v:6273$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1710_Y - connect \B $eq$ls180.v:6136$1711_Y - connect \Y $and$ls180.v:6136$1712_Y + connect \A $and$ls180.v:6273$1843_Y + connect \B $eq$ls180.v:6273$1844_Y + connect \Y $and$ls180.v:6273$1845_Y end - attribute \src "ls180.v:6138.42-6138.95" - cell $and $and$ls180.v:6138$1713 + attribute \src "ls180.v:6275.42-6275.95" + cell $and $and$ls180.v:6275$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243234,43 +244954,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6138$1713_Y + connect \Y $and$ls180.v:6275$1846_Y end - attribute \src "ls180.v:6138.41-6138.145" - cell $and $and$ls180.v:6138$1715 + attribute \src "ls180.v:6275.41-6275.145" + cell $and $and$ls180.v:6275$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6138$1713_Y - connect \B $eq$ls180.v:6138$1714_Y - connect \Y $and$ls180.v:6138$1715_Y + connect \A $and$ls180.v:6275$1846_Y + connect \B $eq$ls180.v:6275$1847_Y + connect \Y $and$ls180.v:6275$1848_Y end - attribute \src "ls180.v:6139.42-6139.98" - cell $and $and$ls180.v:6139$1717 + attribute \src "ls180.v:6276.42-6276.98" + cell $and $and$ls180.v:6276$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6139$1716_Y - connect \Y $and$ls180.v:6139$1717_Y + connect \B $not$ls180.v:6276$1849_Y + connect \Y $and$ls180.v:6276$1850_Y end - attribute \src "ls180.v:6139.41-6139.148" - cell $and $and$ls180.v:6139$1719 + attribute \src "ls180.v:6276.41-6276.148" + cell $and $and$ls180.v:6276$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1717_Y - connect \B $eq$ls180.v:6139$1718_Y - connect \Y $and$ls180.v:6139$1719_Y + connect \A $and$ls180.v:6276$1850_Y + connect \B $eq$ls180.v:6276$1851_Y + connect \Y $and$ls180.v:6276$1852_Y end - attribute \src "ls180.v:6141.42-6141.95" - cell $and $and$ls180.v:6141$1720 + attribute \src "ls180.v:6278.42-6278.95" + cell $and $and$ls180.v:6278$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243278,43 +244998,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6141$1720_Y + connect \Y $and$ls180.v:6278$1853_Y end - attribute \src "ls180.v:6141.41-6141.145" - cell $and $and$ls180.v:6141$1722 + attribute \src "ls180.v:6278.41-6278.145" + cell $and $and$ls180.v:6278$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6141$1720_Y - connect \B $eq$ls180.v:6141$1721_Y - connect \Y $and$ls180.v:6141$1722_Y + connect \A $and$ls180.v:6278$1853_Y + connect \B $eq$ls180.v:6278$1854_Y + connect \Y $and$ls180.v:6278$1855_Y end - attribute \src "ls180.v:6142.42-6142.98" - cell $and $and$ls180.v:6142$1724 + attribute \src "ls180.v:6279.42-6279.98" + cell $and $and$ls180.v:6279$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6142$1723_Y - connect \Y $and$ls180.v:6142$1724_Y + connect \B $not$ls180.v:6279$1856_Y + connect \Y $and$ls180.v:6279$1857_Y end - attribute \src "ls180.v:6142.41-6142.148" - cell $and $and$ls180.v:6142$1726 + attribute \src "ls180.v:6279.41-6279.148" + cell $and $and$ls180.v:6279$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1724_Y - connect \B $eq$ls180.v:6142$1725_Y - connect \Y $and$ls180.v:6142$1726_Y + connect \A $and$ls180.v:6279$1857_Y + connect \B $eq$ls180.v:6279$1858_Y + connect \Y $and$ls180.v:6279$1859_Y end - attribute \src "ls180.v:6144.44-6144.97" - cell $and $and$ls180.v:6144$1727 + attribute \src "ls180.v:6281.44-6281.97" + cell $and $and$ls180.v:6281$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243322,43 +245042,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6144$1727_Y + connect \Y $and$ls180.v:6281$1860_Y end - attribute \src "ls180.v:6144.43-6144.147" - cell $and $and$ls180.v:6144$1729 + attribute \src "ls180.v:6281.43-6281.147" + cell $and $and$ls180.v:6281$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6144$1727_Y - connect \B $eq$ls180.v:6144$1728_Y - connect \Y $and$ls180.v:6144$1729_Y + connect \A $and$ls180.v:6281$1860_Y + connect \B $eq$ls180.v:6281$1861_Y + connect \Y $and$ls180.v:6281$1862_Y end - attribute \src "ls180.v:6145.44-6145.100" - cell $and $and$ls180.v:6145$1731 + attribute \src "ls180.v:6282.44-6282.100" + cell $and $and$ls180.v:6282$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6145$1730_Y - connect \Y $and$ls180.v:6145$1731_Y + connect \B $not$ls180.v:6282$1863_Y + connect \Y $and$ls180.v:6282$1864_Y end - attribute \src "ls180.v:6145.43-6145.150" - cell $and $and$ls180.v:6145$1733 + attribute \src "ls180.v:6282.43-6282.150" + cell $and $and$ls180.v:6282$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1731_Y - connect \B $eq$ls180.v:6145$1732_Y - connect \Y $and$ls180.v:6145$1733_Y + connect \A $and$ls180.v:6282$1864_Y + connect \B $eq$ls180.v:6282$1865_Y + connect \Y $and$ls180.v:6282$1866_Y end - attribute \src "ls180.v:6147.44-6147.97" - cell $and $and$ls180.v:6147$1734 + attribute \src "ls180.v:6284.44-6284.97" + cell $and $and$ls180.v:6284$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243366,43 +245086,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6147$1734_Y + connect \Y $and$ls180.v:6284$1867_Y end - attribute \src "ls180.v:6147.43-6147.147" - cell $and $and$ls180.v:6147$1736 + attribute \src "ls180.v:6284.43-6284.147" + cell $and $and$ls180.v:6284$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6147$1734_Y - connect \B $eq$ls180.v:6147$1735_Y - connect \Y $and$ls180.v:6147$1736_Y + connect \A $and$ls180.v:6284$1867_Y + connect \B $eq$ls180.v:6284$1868_Y + connect \Y $and$ls180.v:6284$1869_Y end - attribute \src "ls180.v:6148.44-6148.100" - cell $and $and$ls180.v:6148$1738 + attribute \src "ls180.v:6285.44-6285.100" + cell $and $and$ls180.v:6285$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6148$1737_Y - connect \Y $and$ls180.v:6148$1738_Y + connect \B $not$ls180.v:6285$1870_Y + connect \Y $and$ls180.v:6285$1871_Y end - attribute \src "ls180.v:6148.43-6148.150" - cell $and $and$ls180.v:6148$1740 + attribute \src "ls180.v:6285.43-6285.150" + cell $and $and$ls180.v:6285$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6148$1738_Y - connect \B $eq$ls180.v:6148$1739_Y - connect \Y $and$ls180.v:6148$1740_Y + connect \A $and$ls180.v:6285$1871_Y + connect \B $eq$ls180.v:6285$1872_Y + connect \Y $and$ls180.v:6285$1873_Y end - attribute \src "ls180.v:6150.44-6150.97" - cell $and $and$ls180.v:6150$1741 + attribute \src "ls180.v:6287.44-6287.97" + cell $and $and$ls180.v:6287$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243410,43 +245130,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6150$1741_Y + connect \Y $and$ls180.v:6287$1874_Y end - attribute \src "ls180.v:6150.43-6150.148" - cell $and $and$ls180.v:6150$1743 + attribute \src "ls180.v:6287.43-6287.148" + cell $and $and$ls180.v:6287$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6150$1741_Y - connect \B $eq$ls180.v:6150$1742_Y - connect \Y $and$ls180.v:6150$1743_Y + connect \A $and$ls180.v:6287$1874_Y + connect \B $eq$ls180.v:6287$1875_Y + connect \Y $and$ls180.v:6287$1876_Y end - attribute \src "ls180.v:6151.44-6151.100" - cell $and $and$ls180.v:6151$1745 + attribute \src "ls180.v:6288.44-6288.100" + cell $and $and$ls180.v:6288$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6151$1744_Y - connect \Y $and$ls180.v:6151$1745_Y + connect \B $not$ls180.v:6288$1877_Y + connect \Y $and$ls180.v:6288$1878_Y end - attribute \src "ls180.v:6151.43-6151.151" - cell $and $and$ls180.v:6151$1747 + attribute \src "ls180.v:6288.43-6288.151" + cell $and $and$ls180.v:6288$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6151$1745_Y - connect \B $eq$ls180.v:6151$1746_Y - connect \Y $and$ls180.v:6151$1747_Y + connect \A $and$ls180.v:6288$1878_Y + connect \B $eq$ls180.v:6288$1879_Y + connect \Y $and$ls180.v:6288$1880_Y end - attribute \src "ls180.v:6153.44-6153.97" - cell $and $and$ls180.v:6153$1748 + attribute \src "ls180.v:6290.44-6290.97" + cell $and $and$ls180.v:6290$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243454,43 +245174,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6153$1748_Y + connect \Y $and$ls180.v:6290$1881_Y end - attribute \src "ls180.v:6153.43-6153.148" - cell $and $and$ls180.v:6153$1750 + attribute \src "ls180.v:6290.43-6290.148" + cell $and $and$ls180.v:6290$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6153$1748_Y - connect \B $eq$ls180.v:6153$1749_Y - connect \Y $and$ls180.v:6153$1750_Y + connect \A $and$ls180.v:6290$1881_Y + connect \B $eq$ls180.v:6290$1882_Y + connect \Y $and$ls180.v:6290$1883_Y end - attribute \src "ls180.v:6154.44-6154.100" - cell $and $and$ls180.v:6154$1752 + attribute \src "ls180.v:6291.44-6291.100" + cell $and $and$ls180.v:6291$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6154$1751_Y - connect \Y $and$ls180.v:6154$1752_Y + connect \B $not$ls180.v:6291$1884_Y + connect \Y $and$ls180.v:6291$1885_Y end - attribute \src "ls180.v:6154.43-6154.151" - cell $and $and$ls180.v:6154$1754 + attribute \src "ls180.v:6291.43-6291.151" + cell $and $and$ls180.v:6291$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6154$1752_Y - connect \B $eq$ls180.v:6154$1753_Y - connect \Y $and$ls180.v:6154$1754_Y + connect \A $and$ls180.v:6291$1885_Y + connect \B $eq$ls180.v:6291$1886_Y + connect \Y $and$ls180.v:6291$1887_Y end - attribute \src "ls180.v:6156.44-6156.97" - cell $and $and$ls180.v:6156$1755 + attribute \src "ls180.v:6293.44-6293.97" + cell $and $and$ls180.v:6293$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243498,43 +245218,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6156$1755_Y + connect \Y $and$ls180.v:6293$1888_Y end - attribute \src "ls180.v:6156.43-6156.148" - cell $and $and$ls180.v:6156$1757 + attribute \src "ls180.v:6293.43-6293.148" + cell $and $and$ls180.v:6293$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6156$1755_Y - connect \B $eq$ls180.v:6156$1756_Y - connect \Y $and$ls180.v:6156$1757_Y + connect \A $and$ls180.v:6293$1888_Y + connect \B $eq$ls180.v:6293$1889_Y + connect \Y $and$ls180.v:6293$1890_Y end - attribute \src "ls180.v:6157.44-6157.100" - cell $and $and$ls180.v:6157$1759 + attribute \src "ls180.v:6294.44-6294.100" + cell $and $and$ls180.v:6294$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6157$1758_Y - connect \Y $and$ls180.v:6157$1759_Y + connect \B $not$ls180.v:6294$1891_Y + connect \Y $and$ls180.v:6294$1892_Y end - attribute \src "ls180.v:6157.43-6157.151" - cell $and $and$ls180.v:6157$1761 + attribute \src "ls180.v:6294.43-6294.151" + cell $and $and$ls180.v:6294$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6157$1759_Y - connect \B $eq$ls180.v:6157$1760_Y - connect \Y $and$ls180.v:6157$1761_Y + connect \A $and$ls180.v:6294$1892_Y + connect \B $eq$ls180.v:6294$1893_Y + connect \Y $and$ls180.v:6294$1894_Y end - attribute \src "ls180.v:6159.41-6159.94" - cell $and $and$ls180.v:6159$1762 + attribute \src "ls180.v:6296.41-6296.94" + cell $and $and$ls180.v:6296$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243542,43 +245262,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6159$1762_Y + connect \Y $and$ls180.v:6296$1895_Y end - attribute \src "ls180.v:6159.40-6159.145" - cell $and $and$ls180.v:6159$1764 + attribute \src "ls180.v:6296.40-6296.145" + cell $and $and$ls180.v:6296$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6159$1762_Y - connect \B $eq$ls180.v:6159$1763_Y - connect \Y $and$ls180.v:6159$1764_Y + connect \A $and$ls180.v:6296$1895_Y + connect \B $eq$ls180.v:6296$1896_Y + connect \Y $and$ls180.v:6296$1897_Y end - attribute \src "ls180.v:6160.41-6160.97" - cell $and $and$ls180.v:6160$1766 + attribute \src "ls180.v:6297.41-6297.97" + cell $and $and$ls180.v:6297$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6160$1765_Y - connect \Y $and$ls180.v:6160$1766_Y + connect \B $not$ls180.v:6297$1898_Y + connect \Y $and$ls180.v:6297$1899_Y end - attribute \src "ls180.v:6160.40-6160.148" - cell $and $and$ls180.v:6160$1768 + attribute \src "ls180.v:6297.40-6297.148" + cell $and $and$ls180.v:6297$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6160$1766_Y - connect \B $eq$ls180.v:6160$1767_Y - connect \Y $and$ls180.v:6160$1768_Y + connect \A $and$ls180.v:6297$1899_Y + connect \B $eq$ls180.v:6297$1900_Y + connect \Y $and$ls180.v:6297$1901_Y end - attribute \src "ls180.v:6162.42-6162.95" - cell $and $and$ls180.v:6162$1769 + attribute \src "ls180.v:6299.42-6299.95" + cell $and $and$ls180.v:6299$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243586,43 +245306,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6162$1769_Y + connect \Y $and$ls180.v:6299$1902_Y end - attribute \src "ls180.v:6162.41-6162.146" - cell $and $and$ls180.v:6162$1771 + attribute \src "ls180.v:6299.41-6299.146" + cell $and $and$ls180.v:6299$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1769_Y - connect \B $eq$ls180.v:6162$1770_Y - connect \Y $and$ls180.v:6162$1771_Y + connect \A $and$ls180.v:6299$1902_Y + connect \B $eq$ls180.v:6299$1903_Y + connect \Y $and$ls180.v:6299$1904_Y end - attribute \src "ls180.v:6163.42-6163.98" - cell $and $and$ls180.v:6163$1773 + attribute \src "ls180.v:6300.42-6300.98" + cell $and $and$ls180.v:6300$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6163$1772_Y - connect \Y $and$ls180.v:6163$1773_Y + connect \B $not$ls180.v:6300$1905_Y + connect \Y $and$ls180.v:6300$1906_Y end - attribute \src "ls180.v:6163.41-6163.149" - cell $and $and$ls180.v:6163$1775 + attribute \src "ls180.v:6300.41-6300.149" + cell $and $and$ls180.v:6300$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6163$1773_Y - connect \B $eq$ls180.v:6163$1774_Y - connect \Y $and$ls180.v:6163$1775_Y + connect \A $and$ls180.v:6300$1906_Y + connect \B $eq$ls180.v:6300$1907_Y + connect \Y $and$ls180.v:6300$1908_Y end - attribute \src "ls180.v:6165.44-6165.97" - cell $and $and$ls180.v:6165$1776 + attribute \src "ls180.v:6302.44-6302.97" + cell $and $and$ls180.v:6302$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243630,43 +245350,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6165$1776_Y + connect \Y $and$ls180.v:6302$1909_Y end - attribute \src "ls180.v:6165.43-6165.148" - cell $and $and$ls180.v:6165$1778 + attribute \src "ls180.v:6302.43-6302.148" + cell $and $and$ls180.v:6302$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6165$1776_Y - connect \B $eq$ls180.v:6165$1777_Y - connect \Y $and$ls180.v:6165$1778_Y + connect \A $and$ls180.v:6302$1909_Y + connect \B $eq$ls180.v:6302$1910_Y + connect \Y $and$ls180.v:6302$1911_Y end - attribute \src "ls180.v:6166.44-6166.100" - cell $and $and$ls180.v:6166$1780 + attribute \src "ls180.v:6303.44-6303.100" + cell $and $and$ls180.v:6303$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6166$1779_Y - connect \Y $and$ls180.v:6166$1780_Y + connect \B $not$ls180.v:6303$1912_Y + connect \Y $and$ls180.v:6303$1913_Y end - attribute \src "ls180.v:6166.43-6166.151" - cell $and $and$ls180.v:6166$1782 + attribute \src "ls180.v:6303.43-6303.151" + cell $and $and$ls180.v:6303$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6166$1780_Y - connect \B $eq$ls180.v:6166$1781_Y - connect \Y $and$ls180.v:6166$1782_Y + connect \A $and$ls180.v:6303$1913_Y + connect \B $eq$ls180.v:6303$1914_Y + connect \Y $and$ls180.v:6303$1915_Y end - attribute \src "ls180.v:6168.44-6168.97" - cell $and $and$ls180.v:6168$1783 + attribute \src "ls180.v:6305.44-6305.97" + cell $and $and$ls180.v:6305$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243674,43 +245394,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6168$1783_Y + connect \Y $and$ls180.v:6305$1916_Y end - attribute \src "ls180.v:6168.43-6168.148" - cell $and $and$ls180.v:6168$1785 + attribute \src "ls180.v:6305.43-6305.148" + cell $and $and$ls180.v:6305$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6168$1783_Y - connect \B $eq$ls180.v:6168$1784_Y - connect \Y $and$ls180.v:6168$1785_Y + connect \A $and$ls180.v:6305$1916_Y + connect \B $eq$ls180.v:6305$1917_Y + connect \Y $and$ls180.v:6305$1918_Y end - attribute \src "ls180.v:6169.44-6169.100" - cell $and $and$ls180.v:6169$1787 + attribute \src "ls180.v:6306.44-6306.100" + cell $and $and$ls180.v:6306$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6169$1786_Y - connect \Y $and$ls180.v:6169$1787_Y + connect \B $not$ls180.v:6306$1919_Y + connect \Y $and$ls180.v:6306$1920_Y end - attribute \src "ls180.v:6169.43-6169.151" - cell $and $and$ls180.v:6169$1789 + attribute \src "ls180.v:6306.43-6306.151" + cell $and $and$ls180.v:6306$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6169$1787_Y - connect \B $eq$ls180.v:6169$1788_Y - connect \Y $and$ls180.v:6169$1789_Y + connect \A $and$ls180.v:6306$1920_Y + connect \B $eq$ls180.v:6306$1921_Y + connect \Y $and$ls180.v:6306$1922_Y end - attribute \src "ls180.v:6171.44-6171.97" - cell $and $and$ls180.v:6171$1790 + attribute \src "ls180.v:6308.44-6308.97" + cell $and $and$ls180.v:6308$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243718,43 +245438,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6171$1790_Y + connect \Y $and$ls180.v:6308$1923_Y end - attribute \src "ls180.v:6171.43-6171.148" - cell $and $and$ls180.v:6171$1792 + attribute \src "ls180.v:6308.43-6308.148" + cell $and $and$ls180.v:6308$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6171$1790_Y - connect \B $eq$ls180.v:6171$1791_Y - connect \Y $and$ls180.v:6171$1792_Y + connect \A $and$ls180.v:6308$1923_Y + connect \B $eq$ls180.v:6308$1924_Y + connect \Y $and$ls180.v:6308$1925_Y end - attribute \src "ls180.v:6172.44-6172.100" - cell $and $and$ls180.v:6172$1794 + attribute \src "ls180.v:6309.44-6309.100" + cell $and $and$ls180.v:6309$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6172$1793_Y - connect \Y $and$ls180.v:6172$1794_Y + connect \B $not$ls180.v:6309$1926_Y + connect \Y $and$ls180.v:6309$1927_Y end - attribute \src "ls180.v:6172.43-6172.151" - cell $and $and$ls180.v:6172$1796 + attribute \src "ls180.v:6309.43-6309.151" + cell $and $and$ls180.v:6309$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6172$1794_Y - connect \B $eq$ls180.v:6172$1795_Y - connect \Y $and$ls180.v:6172$1796_Y + connect \A $and$ls180.v:6309$1927_Y + connect \B $eq$ls180.v:6309$1928_Y + connect \Y $and$ls180.v:6309$1929_Y end - attribute \src "ls180.v:6174.44-6174.97" - cell $and $and$ls180.v:6174$1797 + attribute \src "ls180.v:6311.44-6311.97" + cell $and $and$ls180.v:6311$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243762,43 +245482,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6174$1797_Y + connect \Y $and$ls180.v:6311$1930_Y end - attribute \src "ls180.v:6174.43-6174.148" - cell $and $and$ls180.v:6174$1799 + attribute \src "ls180.v:6311.43-6311.148" + cell $and $and$ls180.v:6311$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6174$1797_Y - connect \B $eq$ls180.v:6174$1798_Y - connect \Y $and$ls180.v:6174$1799_Y + connect \A $and$ls180.v:6311$1930_Y + connect \B $eq$ls180.v:6311$1931_Y + connect \Y $and$ls180.v:6311$1932_Y end - attribute \src "ls180.v:6175.44-6175.100" - cell $and $and$ls180.v:6175$1801 + attribute \src "ls180.v:6312.44-6312.100" + cell $and $and$ls180.v:6312$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6175$1800_Y - connect \Y $and$ls180.v:6175$1801_Y + connect \B $not$ls180.v:6312$1933_Y + connect \Y $and$ls180.v:6312$1934_Y end - attribute \src "ls180.v:6175.43-6175.151" - cell $and $and$ls180.v:6175$1803 + attribute \src "ls180.v:6312.43-6312.151" + cell $and $and$ls180.v:6312$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6175$1801_Y - connect \B $eq$ls180.v:6175$1802_Y - connect \Y $and$ls180.v:6175$1803_Y + connect \A $and$ls180.v:6312$1934_Y + connect \B $eq$ls180.v:6312$1935_Y + connect \Y $and$ls180.v:6312$1936_Y end - attribute \src "ls180.v:6199.44-6199.97" - cell $and $and$ls180.v:6199$1805 + attribute \src "ls180.v:6336.44-6336.97" + cell $and $and$ls180.v:6336$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243806,43 +245526,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6199$1805_Y + connect \Y $and$ls180.v:6336$1938_Y end - attribute \src "ls180.v:6199.43-6199.147" - cell $and $and$ls180.v:6199$1807 + attribute \src "ls180.v:6336.43-6336.147" + cell $and $and$ls180.v:6336$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6199$1805_Y - connect \B $eq$ls180.v:6199$1806_Y - connect \Y $and$ls180.v:6199$1807_Y + connect \A $and$ls180.v:6336$1938_Y + connect \B $eq$ls180.v:6336$1939_Y + connect \Y $and$ls180.v:6336$1940_Y end - attribute \src "ls180.v:6200.44-6200.100" - cell $and $and$ls180.v:6200$1809 + attribute \src "ls180.v:6337.44-6337.100" + cell $and $and$ls180.v:6337$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6200$1808_Y - connect \Y $and$ls180.v:6200$1809_Y + connect \B $not$ls180.v:6337$1941_Y + connect \Y $and$ls180.v:6337$1942_Y end - attribute \src "ls180.v:6200.43-6200.150" - cell $and $and$ls180.v:6200$1811 + attribute \src "ls180.v:6337.43-6337.150" + cell $and $and$ls180.v:6337$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6200$1809_Y - connect \B $eq$ls180.v:6200$1810_Y - connect \Y $and$ls180.v:6200$1811_Y + connect \A $and$ls180.v:6337$1942_Y + connect \B $eq$ls180.v:6337$1943_Y + connect \Y $and$ls180.v:6337$1944_Y end - attribute \src "ls180.v:6202.49-6202.102" - cell $and $and$ls180.v:6202$1812 + attribute \src "ls180.v:6339.49-6339.102" + cell $and $and$ls180.v:6339$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243850,43 +245570,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6202$1812_Y + connect \Y $and$ls180.v:6339$1945_Y end - attribute \src "ls180.v:6202.48-6202.152" - cell $and $and$ls180.v:6202$1814 + attribute \src "ls180.v:6339.48-6339.152" + cell $and $and$ls180.v:6339$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6202$1812_Y - connect \B $eq$ls180.v:6202$1813_Y - connect \Y $and$ls180.v:6202$1814_Y + connect \A $and$ls180.v:6339$1945_Y + connect \B $eq$ls180.v:6339$1946_Y + connect \Y $and$ls180.v:6339$1947_Y end - attribute \src "ls180.v:6203.49-6203.105" - cell $and $and$ls180.v:6203$1816 + attribute \src "ls180.v:6340.49-6340.105" + cell $and $and$ls180.v:6340$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6203$1815_Y - connect \Y $and$ls180.v:6203$1816_Y + connect \B $not$ls180.v:6340$1948_Y + connect \Y $and$ls180.v:6340$1949_Y end - attribute \src "ls180.v:6203.48-6203.155" - cell $and $and$ls180.v:6203$1818 + attribute \src "ls180.v:6340.48-6340.155" + cell $and $and$ls180.v:6340$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6203$1816_Y - connect \B $eq$ls180.v:6203$1817_Y - connect \Y $and$ls180.v:6203$1818_Y + connect \A $and$ls180.v:6340$1949_Y + connect \B $eq$ls180.v:6340$1950_Y + connect \Y $and$ls180.v:6340$1951_Y end - attribute \src "ls180.v:6205.49-6205.102" - cell $and $and$ls180.v:6205$1819 + attribute \src "ls180.v:6342.49-6342.102" + cell $and $and$ls180.v:6342$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243894,43 +245614,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6205$1819_Y + connect \Y $and$ls180.v:6342$1952_Y end - attribute \src "ls180.v:6205.48-6205.152" - cell $and $and$ls180.v:6205$1821 + attribute \src "ls180.v:6342.48-6342.152" + cell $and $and$ls180.v:6342$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6205$1819_Y - connect \B $eq$ls180.v:6205$1820_Y - connect \Y $and$ls180.v:6205$1821_Y + connect \A $and$ls180.v:6342$1952_Y + connect \B $eq$ls180.v:6342$1953_Y + connect \Y $and$ls180.v:6342$1954_Y end - attribute \src "ls180.v:6206.49-6206.105" - cell $and $and$ls180.v:6206$1823 + attribute \src "ls180.v:6343.49-6343.105" + cell $and $and$ls180.v:6343$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6206$1822_Y - connect \Y $and$ls180.v:6206$1823_Y + connect \B $not$ls180.v:6343$1955_Y + connect \Y $and$ls180.v:6343$1956_Y end - attribute \src "ls180.v:6206.48-6206.155" - cell $and $and$ls180.v:6206$1825 + attribute \src "ls180.v:6343.48-6343.155" + cell $and $and$ls180.v:6343$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6206$1823_Y - connect \B $eq$ls180.v:6206$1824_Y - connect \Y $and$ls180.v:6206$1825_Y + connect \A $and$ls180.v:6343$1956_Y + connect \B $eq$ls180.v:6343$1957_Y + connect \Y $and$ls180.v:6343$1958_Y end - attribute \src "ls180.v:6208.42-6208.95" - cell $and $and$ls180.v:6208$1826 + attribute \src "ls180.v:6345.42-6345.95" + cell $and $and$ls180.v:6345$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243938,43 +245658,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6208$1826_Y + connect \Y $and$ls180.v:6345$1959_Y end - attribute \src "ls180.v:6208.41-6208.145" - cell $and $and$ls180.v:6208$1828 + attribute \src "ls180.v:6345.41-6345.145" + cell $and $and$ls180.v:6345$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6208$1826_Y - connect \B $eq$ls180.v:6208$1827_Y - connect \Y $and$ls180.v:6208$1828_Y + connect \A $and$ls180.v:6345$1959_Y + connect \B $eq$ls180.v:6345$1960_Y + connect \Y $and$ls180.v:6345$1961_Y end - attribute \src "ls180.v:6209.42-6209.98" - cell $and $and$ls180.v:6209$1830 + attribute \src "ls180.v:6346.42-6346.98" + cell $and $and$ls180.v:6346$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6209$1829_Y - connect \Y $and$ls180.v:6209$1830_Y + connect \B $not$ls180.v:6346$1962_Y + connect \Y $and$ls180.v:6346$1963_Y end - attribute \src "ls180.v:6209.41-6209.148" - cell $and $and$ls180.v:6209$1832 + attribute \src "ls180.v:6346.41-6346.148" + cell $and $and$ls180.v:6346$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6209$1830_Y - connect \B $eq$ls180.v:6209$1831_Y - connect \Y $and$ls180.v:6209$1832_Y + connect \A $and$ls180.v:6346$1963_Y + connect \B $eq$ls180.v:6346$1964_Y + connect \Y $and$ls180.v:6346$1965_Y end - attribute \src "ls180.v:6216.46-6216.99" - cell $and $and$ls180.v:6216$1834 + attribute \src "ls180.v:6353.46-6353.99" + cell $and $and$ls180.v:6353$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243982,43 +245702,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6216$1834_Y + connect \Y $and$ls180.v:6353$1967_Y end - attribute \src "ls180.v:6216.45-6216.149" - cell $and $and$ls180.v:6216$1836 + attribute \src "ls180.v:6353.45-6353.149" + cell $and $and$ls180.v:6353$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6216$1834_Y - connect \B $eq$ls180.v:6216$1835_Y - connect \Y $and$ls180.v:6216$1836_Y + connect \A $and$ls180.v:6353$1967_Y + connect \B $eq$ls180.v:6353$1968_Y + connect \Y $and$ls180.v:6353$1969_Y end - attribute \src "ls180.v:6217.46-6217.102" - cell $and $and$ls180.v:6217$1838 + attribute \src "ls180.v:6354.46-6354.102" + cell $and $and$ls180.v:6354$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6217$1837_Y - connect \Y $and$ls180.v:6217$1838_Y + connect \B $not$ls180.v:6354$1970_Y + connect \Y $and$ls180.v:6354$1971_Y end - attribute \src "ls180.v:6217.45-6217.152" - cell $and $and$ls180.v:6217$1840 + attribute \src "ls180.v:6354.45-6354.152" + cell $and $and$ls180.v:6354$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6217$1838_Y - connect \B $eq$ls180.v:6217$1839_Y - connect \Y $and$ls180.v:6217$1840_Y + connect \A $and$ls180.v:6354$1971_Y + connect \B $eq$ls180.v:6354$1972_Y + connect \Y $and$ls180.v:6354$1973_Y end - attribute \src "ls180.v:6219.50-6219.103" - cell $and $and$ls180.v:6219$1841 + attribute \src "ls180.v:6356.50-6356.103" + cell $and $and$ls180.v:6356$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244026,43 +245746,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6219$1841_Y + connect \Y $and$ls180.v:6356$1974_Y end - attribute \src "ls180.v:6219.49-6219.153" - cell $and $and$ls180.v:6219$1843 + attribute \src "ls180.v:6356.49-6356.153" + cell $and $and$ls180.v:6356$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6219$1841_Y - connect \B $eq$ls180.v:6219$1842_Y - connect \Y $and$ls180.v:6219$1843_Y + connect \A $and$ls180.v:6356$1974_Y + connect \B $eq$ls180.v:6356$1975_Y + connect \Y $and$ls180.v:6356$1976_Y end - attribute \src "ls180.v:6220.50-6220.106" - cell $and $and$ls180.v:6220$1845 + attribute \src "ls180.v:6357.50-6357.106" + cell $and $and$ls180.v:6357$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6220$1844_Y - connect \Y $and$ls180.v:6220$1845_Y + connect \B $not$ls180.v:6357$1977_Y + connect \Y $and$ls180.v:6357$1978_Y end - attribute \src "ls180.v:6220.49-6220.156" - cell $and $and$ls180.v:6220$1847 + attribute \src "ls180.v:6357.49-6357.156" + cell $and $and$ls180.v:6357$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6220$1845_Y - connect \B $eq$ls180.v:6220$1846_Y - connect \Y $and$ls180.v:6220$1847_Y + connect \A $and$ls180.v:6357$1978_Y + connect \B $eq$ls180.v:6357$1979_Y + connect \Y $and$ls180.v:6357$1980_Y end - attribute \src "ls180.v:6222.40-6222.93" - cell $and $and$ls180.v:6222$1848 + attribute \src "ls180.v:6359.40-6359.93" + cell $and $and$ls180.v:6359$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244070,43 +245790,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6222$1848_Y + connect \Y $and$ls180.v:6359$1981_Y end - attribute \src "ls180.v:6222.39-6222.143" - cell $and $and$ls180.v:6222$1850 + attribute \src "ls180.v:6359.39-6359.143" + cell $and $and$ls180.v:6359$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1848_Y - connect \B $eq$ls180.v:6222$1849_Y - connect \Y $and$ls180.v:6222$1850_Y + connect \A $and$ls180.v:6359$1981_Y + connect \B $eq$ls180.v:6359$1982_Y + connect \Y $and$ls180.v:6359$1983_Y end - attribute \src "ls180.v:6223.40-6223.96" - cell $and $and$ls180.v:6223$1852 + attribute \src "ls180.v:6360.40-6360.96" + cell $and $and$ls180.v:6360$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6223$1851_Y - connect \Y $and$ls180.v:6223$1852_Y + connect \B $not$ls180.v:6360$1984_Y + connect \Y $and$ls180.v:6360$1985_Y end - attribute \src "ls180.v:6223.39-6223.146" - cell $and $and$ls180.v:6223$1854 + attribute \src "ls180.v:6360.39-6360.146" + cell $and $and$ls180.v:6360$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1852_Y - connect \B $eq$ls180.v:6223$1853_Y - connect \Y $and$ls180.v:6223$1854_Y + connect \A $and$ls180.v:6360$1985_Y + connect \B $eq$ls180.v:6360$1986_Y + connect \Y $and$ls180.v:6360$1987_Y end - attribute \src "ls180.v:6225.50-6225.103" - cell $and $and$ls180.v:6225$1855 + attribute \src "ls180.v:6362.50-6362.103" + cell $and $and$ls180.v:6362$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244114,43 +245834,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6225$1855_Y + connect \Y $and$ls180.v:6362$1988_Y end - attribute \src "ls180.v:6225.49-6225.153" - cell $and $and$ls180.v:6225$1857 + attribute \src "ls180.v:6362.49-6362.153" + cell $and $and$ls180.v:6362$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1855_Y - connect \B $eq$ls180.v:6225$1856_Y - connect \Y $and$ls180.v:6225$1857_Y + connect \A $and$ls180.v:6362$1988_Y + connect \B $eq$ls180.v:6362$1989_Y + connect \Y $and$ls180.v:6362$1990_Y end - attribute \src "ls180.v:6226.50-6226.106" - cell $and $and$ls180.v:6226$1859 + attribute \src "ls180.v:6363.50-6363.106" + cell $and $and$ls180.v:6363$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6226$1858_Y - connect \Y $and$ls180.v:6226$1859_Y + connect \B $not$ls180.v:6363$1991_Y + connect \Y $and$ls180.v:6363$1992_Y end - attribute \src "ls180.v:6226.49-6226.156" - cell $and $and$ls180.v:6226$1861 + attribute \src "ls180.v:6363.49-6363.156" + cell $and $and$ls180.v:6363$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1859_Y - connect \B $eq$ls180.v:6226$1860_Y - connect \Y $and$ls180.v:6226$1861_Y + connect \A $and$ls180.v:6363$1992_Y + connect \B $eq$ls180.v:6363$1993_Y + connect \Y $and$ls180.v:6363$1994_Y end - attribute \src "ls180.v:6228.50-6228.103" - cell $and $and$ls180.v:6228$1862 + attribute \src "ls180.v:6365.50-6365.103" + cell $and $and$ls180.v:6365$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244158,43 +245878,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6228$1862_Y + connect \Y $and$ls180.v:6365$1995_Y end - attribute \src "ls180.v:6228.49-6228.153" - cell $and $and$ls180.v:6228$1864 + attribute \src "ls180.v:6365.49-6365.153" + cell $and $and$ls180.v:6365$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1862_Y - connect \B $eq$ls180.v:6228$1863_Y - connect \Y $and$ls180.v:6228$1864_Y + connect \A $and$ls180.v:6365$1995_Y + connect \B $eq$ls180.v:6365$1996_Y + connect \Y $and$ls180.v:6365$1997_Y end - attribute \src "ls180.v:6229.50-6229.106" - cell $and $and$ls180.v:6229$1866 + attribute \src "ls180.v:6366.50-6366.106" + cell $and $and$ls180.v:6366$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6229$1865_Y - connect \Y $and$ls180.v:6229$1866_Y + connect \B $not$ls180.v:6366$1998_Y + connect \Y $and$ls180.v:6366$1999_Y end - attribute \src "ls180.v:6229.49-6229.156" - cell $and $and$ls180.v:6229$1868 + attribute \src "ls180.v:6366.49-6366.156" + cell $and $and$ls180.v:6366$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1866_Y - connect \B $eq$ls180.v:6229$1867_Y - connect \Y $and$ls180.v:6229$1868_Y + connect \A $and$ls180.v:6366$1999_Y + connect \B $eq$ls180.v:6366$2000_Y + connect \Y $and$ls180.v:6366$2001_Y end - attribute \src "ls180.v:6231.51-6231.104" - cell $and $and$ls180.v:6231$1869 + attribute \src "ls180.v:6368.51-6368.104" + cell $and $and$ls180.v:6368$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244202,43 +245922,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6231$1869_Y + connect \Y $and$ls180.v:6368$2002_Y end - attribute \src "ls180.v:6231.50-6231.154" - cell $and $and$ls180.v:6231$1871 + attribute \src "ls180.v:6368.50-6368.154" + cell $and $and$ls180.v:6368$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6231$1869_Y - connect \B $eq$ls180.v:6231$1870_Y - connect \Y $and$ls180.v:6231$1871_Y + connect \A $and$ls180.v:6368$2002_Y + connect \B $eq$ls180.v:6368$2003_Y + connect \Y $and$ls180.v:6368$2004_Y end - attribute \src "ls180.v:6232.51-6232.107" - cell $and $and$ls180.v:6232$1873 + attribute \src "ls180.v:6369.51-6369.107" + cell $and $and$ls180.v:6369$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6232$1872_Y - connect \Y $and$ls180.v:6232$1873_Y + connect \B $not$ls180.v:6369$2005_Y + connect \Y $and$ls180.v:6369$2006_Y end - attribute \src "ls180.v:6232.50-6232.157" - cell $and $and$ls180.v:6232$1875 + attribute \src "ls180.v:6369.50-6369.157" + cell $and $and$ls180.v:6369$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1873_Y - connect \B $eq$ls180.v:6232$1874_Y - connect \Y $and$ls180.v:6232$1875_Y + connect \A $and$ls180.v:6369$2006_Y + connect \B $eq$ls180.v:6369$2007_Y + connect \Y $and$ls180.v:6369$2008_Y end - attribute \src "ls180.v:6234.49-6234.102" - cell $and $and$ls180.v:6234$1876 + attribute \src "ls180.v:6371.49-6371.102" + cell $and $and$ls180.v:6371$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244246,43 +245966,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6234$1876_Y + connect \Y $and$ls180.v:6371$2009_Y end - attribute \src "ls180.v:6234.48-6234.152" - cell $and $and$ls180.v:6234$1878 + attribute \src "ls180.v:6371.48-6371.152" + cell $and $and$ls180.v:6371$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6234$1876_Y - connect \B $eq$ls180.v:6234$1877_Y - connect \Y $and$ls180.v:6234$1878_Y + connect \A $and$ls180.v:6371$2009_Y + connect \B $eq$ls180.v:6371$2010_Y + connect \Y $and$ls180.v:6371$2011_Y end - attribute \src "ls180.v:6235.49-6235.105" - cell $and $and$ls180.v:6235$1880 + attribute \src "ls180.v:6372.49-6372.105" + cell $and $and$ls180.v:6372$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6235$1879_Y - connect \Y $and$ls180.v:6235$1880_Y + connect \B $not$ls180.v:6372$2012_Y + connect \Y $and$ls180.v:6372$2013_Y end - attribute \src "ls180.v:6235.48-6235.155" - cell $and $and$ls180.v:6235$1882 + attribute \src "ls180.v:6372.48-6372.155" + cell $and $and$ls180.v:6372$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1880_Y - connect \B $eq$ls180.v:6235$1881_Y - connect \Y $and$ls180.v:6235$1882_Y + connect \A $and$ls180.v:6372$2013_Y + connect \B $eq$ls180.v:6372$2014_Y + connect \Y $and$ls180.v:6372$2015_Y end - attribute \src "ls180.v:6237.49-6237.102" - cell $and $and$ls180.v:6237$1883 + attribute \src "ls180.v:6374.49-6374.102" + cell $and $and$ls180.v:6374$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244290,43 +246010,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6237$1883_Y + connect \Y $and$ls180.v:6374$2016_Y end - attribute \src "ls180.v:6237.48-6237.152" - cell $and $and$ls180.v:6237$1885 + attribute \src "ls180.v:6374.48-6374.152" + cell $and $and$ls180.v:6374$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1883_Y - connect \B $eq$ls180.v:6237$1884_Y - connect \Y $and$ls180.v:6237$1885_Y + connect \A $and$ls180.v:6374$2016_Y + connect \B $eq$ls180.v:6374$2017_Y + connect \Y $and$ls180.v:6374$2018_Y end - attribute \src "ls180.v:6238.49-6238.105" - cell $and $and$ls180.v:6238$1887 + attribute \src "ls180.v:6375.49-6375.105" + cell $and $and$ls180.v:6375$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6238$1886_Y - connect \Y $and$ls180.v:6238$1887_Y + connect \B $not$ls180.v:6375$2019_Y + connect \Y $and$ls180.v:6375$2020_Y end - attribute \src "ls180.v:6238.48-6238.155" - cell $and $and$ls180.v:6238$1889 + attribute \src "ls180.v:6375.48-6375.155" + cell $and $and$ls180.v:6375$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1887_Y - connect \B $eq$ls180.v:6238$1888_Y - connect \Y $and$ls180.v:6238$1889_Y + connect \A $and$ls180.v:6375$2020_Y + connect \B $eq$ls180.v:6375$2021_Y + connect \Y $and$ls180.v:6375$2022_Y end - attribute \src "ls180.v:6240.49-6240.102" - cell $and $and$ls180.v:6240$1890 + attribute \src "ls180.v:6377.49-6377.102" + cell $and $and$ls180.v:6377$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244334,43 +246054,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6240$1890_Y + connect \Y $and$ls180.v:6377$2023_Y end - attribute \src "ls180.v:6240.48-6240.152" - cell $and $and$ls180.v:6240$1892 + attribute \src "ls180.v:6377.48-6377.152" + cell $and $and$ls180.v:6377$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6240$1890_Y - connect \B $eq$ls180.v:6240$1891_Y - connect \Y $and$ls180.v:6240$1892_Y + connect \A $and$ls180.v:6377$2023_Y + connect \B $eq$ls180.v:6377$2024_Y + connect \Y $and$ls180.v:6377$2025_Y end - attribute \src "ls180.v:6241.49-6241.105" - cell $and $and$ls180.v:6241$1894 + attribute \src "ls180.v:6378.49-6378.105" + cell $and $and$ls180.v:6378$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6241$1893_Y - connect \Y $and$ls180.v:6241$1894_Y + connect \B $not$ls180.v:6378$2026_Y + connect \Y $and$ls180.v:6378$2027_Y end - attribute \src "ls180.v:6241.48-6241.155" - cell $and $and$ls180.v:6241$1896 + attribute \src "ls180.v:6378.48-6378.155" + cell $and $and$ls180.v:6378$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6241$1894_Y - connect \B $eq$ls180.v:6241$1895_Y - connect \Y $and$ls180.v:6241$1896_Y + connect \A $and$ls180.v:6378$2027_Y + connect \B $eq$ls180.v:6378$2028_Y + connect \Y $and$ls180.v:6378$2029_Y end - attribute \src "ls180.v:6243.49-6243.102" - cell $and $and$ls180.v:6243$1897 + attribute \src "ls180.v:6380.49-6380.102" + cell $and $and$ls180.v:6380$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244378,43 +246098,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6243$1897_Y + connect \Y $and$ls180.v:6380$2030_Y end - attribute \src "ls180.v:6243.48-6243.152" - cell $and $and$ls180.v:6243$1899 + attribute \src "ls180.v:6380.48-6380.152" + cell $and $and$ls180.v:6380$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6243$1897_Y - connect \B $eq$ls180.v:6243$1898_Y - connect \Y $and$ls180.v:6243$1899_Y + connect \A $and$ls180.v:6380$2030_Y + connect \B $eq$ls180.v:6380$2031_Y + connect \Y $and$ls180.v:6380$2032_Y end - attribute \src "ls180.v:6244.49-6244.105" - cell $and $and$ls180.v:6244$1901 + attribute \src "ls180.v:6381.49-6381.105" + cell $and $and$ls180.v:6381$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6244$1900_Y - connect \Y $and$ls180.v:6244$1901_Y + connect \B $not$ls180.v:6381$2033_Y + connect \Y $and$ls180.v:6381$2034_Y end - attribute \src "ls180.v:6244.48-6244.155" - cell $and $and$ls180.v:6244$1903 + attribute \src "ls180.v:6381.48-6381.155" + cell $and $and$ls180.v:6381$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6244$1901_Y - connect \B $eq$ls180.v:6244$1902_Y - connect \Y $and$ls180.v:6244$1903_Y + connect \A $and$ls180.v:6381$2034_Y + connect \B $eq$ls180.v:6381$2035_Y + connect \Y $and$ls180.v:6381$2036_Y end - attribute \src "ls180.v:6261.42-6261.97" - cell $and $and$ls180.v:6261$1905 + attribute \src "ls180.v:6398.42-6398.97" + cell $and $and$ls180.v:6398$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244422,43 +246142,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6261$1905_Y + connect \Y $and$ls180.v:6398$2038_Y end - attribute \src "ls180.v:6261.41-6261.148" - cell $and $and$ls180.v:6261$1907 + attribute \src "ls180.v:6398.41-6398.148" + cell $and $and$ls180.v:6398$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1905_Y - connect \B $eq$ls180.v:6261$1906_Y - connect \Y $and$ls180.v:6261$1907_Y + connect \A $and$ls180.v:6398$2038_Y + connect \B $eq$ls180.v:6398$2039_Y + connect \Y $and$ls180.v:6398$2040_Y end - attribute \src "ls180.v:6262.42-6262.100" - cell $and $and$ls180.v:6262$1909 + attribute \src "ls180.v:6399.42-6399.100" + cell $and $and$ls180.v:6399$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6262$1908_Y - connect \Y $and$ls180.v:6262$1909_Y + connect \B $not$ls180.v:6399$2041_Y + connect \Y $and$ls180.v:6399$2042_Y end - attribute \src "ls180.v:6262.41-6262.151" - cell $and $and$ls180.v:6262$1911 + attribute \src "ls180.v:6399.41-6399.151" + cell $and $and$ls180.v:6399$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6262$1909_Y - connect \B $eq$ls180.v:6262$1910_Y - connect \Y $and$ls180.v:6262$1911_Y + connect \A $and$ls180.v:6399$2042_Y + connect \B $eq$ls180.v:6399$2043_Y + connect \Y $and$ls180.v:6399$2044_Y end - attribute \src "ls180.v:6264.42-6264.97" - cell $and $and$ls180.v:6264$1912 + attribute \src "ls180.v:6401.42-6401.97" + cell $and $and$ls180.v:6401$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244466,43 +246186,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6264$1912_Y + connect \Y $and$ls180.v:6401$2045_Y end - attribute \src "ls180.v:6264.41-6264.148" - cell $and $and$ls180.v:6264$1914 + attribute \src "ls180.v:6401.41-6401.148" + cell $and $and$ls180.v:6401$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1912_Y - connect \B $eq$ls180.v:6264$1913_Y - connect \Y $and$ls180.v:6264$1914_Y + connect \A $and$ls180.v:6401$2045_Y + connect \B $eq$ls180.v:6401$2046_Y + connect \Y $and$ls180.v:6401$2047_Y end - attribute \src "ls180.v:6265.42-6265.100" - cell $and $and$ls180.v:6265$1916 + attribute \src "ls180.v:6402.42-6402.100" + cell $and $and$ls180.v:6402$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6265$1915_Y - connect \Y $and$ls180.v:6265$1916_Y + connect \B $not$ls180.v:6402$2048_Y + connect \Y $and$ls180.v:6402$2049_Y end - attribute \src "ls180.v:6265.41-6265.151" - cell $and $and$ls180.v:6265$1918 + attribute \src "ls180.v:6402.41-6402.151" + cell $and $and$ls180.v:6402$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6265$1916_Y - connect \B $eq$ls180.v:6265$1917_Y - connect \Y $and$ls180.v:6265$1918_Y + connect \A $and$ls180.v:6402$2049_Y + connect \B $eq$ls180.v:6402$2050_Y + connect \Y $and$ls180.v:6402$2051_Y end - attribute \src "ls180.v:6267.40-6267.95" - cell $and $and$ls180.v:6267$1919 + attribute \src "ls180.v:6404.40-6404.95" + cell $and $and$ls180.v:6404$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244510,43 +246230,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6267$1919_Y + connect \Y $and$ls180.v:6404$2052_Y end - attribute \src "ls180.v:6267.39-6267.146" - cell $and $and$ls180.v:6267$1921 + attribute \src "ls180.v:6404.39-6404.146" + cell $and $and$ls180.v:6404$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6267$1919_Y - connect \B $eq$ls180.v:6267$1920_Y - connect \Y $and$ls180.v:6267$1921_Y + connect \A $and$ls180.v:6404$2052_Y + connect \B $eq$ls180.v:6404$2053_Y + connect \Y $and$ls180.v:6404$2054_Y end - attribute \src "ls180.v:6268.40-6268.98" - cell $and $and$ls180.v:6268$1923 + attribute \src "ls180.v:6405.40-6405.98" + cell $and $and$ls180.v:6405$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6268$1922_Y - connect \Y $and$ls180.v:6268$1923_Y + connect \B $not$ls180.v:6405$2055_Y + connect \Y $and$ls180.v:6405$2056_Y end - attribute \src "ls180.v:6268.39-6268.149" - cell $and $and$ls180.v:6268$1925 + attribute \src "ls180.v:6405.39-6405.149" + cell $and $and$ls180.v:6405$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6268$1923_Y - connect \B $eq$ls180.v:6268$1924_Y - connect \Y $and$ls180.v:6268$1925_Y + connect \A $and$ls180.v:6405$2056_Y + connect \B $eq$ls180.v:6405$2057_Y + connect \Y $and$ls180.v:6405$2058_Y end - attribute \src "ls180.v:6270.39-6270.94" - cell $and $and$ls180.v:6270$1926 + attribute \src "ls180.v:6407.39-6407.94" + cell $and $and$ls180.v:6407$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244554,43 +246274,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6270$1926_Y + connect \Y $and$ls180.v:6407$2059_Y end - attribute \src "ls180.v:6270.38-6270.145" - cell $and $and$ls180.v:6270$1928 + attribute \src "ls180.v:6407.38-6407.145" + cell $and $and$ls180.v:6407$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6270$1926_Y - connect \B $eq$ls180.v:6270$1927_Y - connect \Y $and$ls180.v:6270$1928_Y + connect \A $and$ls180.v:6407$2059_Y + connect \B $eq$ls180.v:6407$2060_Y + connect \Y $and$ls180.v:6407$2061_Y end - attribute \src "ls180.v:6271.39-6271.97" - cell $and $and$ls180.v:6271$1930 + attribute \src "ls180.v:6408.39-6408.97" + cell $and $and$ls180.v:6408$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6271$1929_Y - connect \Y $and$ls180.v:6271$1930_Y + connect \B $not$ls180.v:6408$2062_Y + connect \Y $and$ls180.v:6408$2063_Y end - attribute \src "ls180.v:6271.38-6271.148" - cell $and $and$ls180.v:6271$1932 + attribute \src "ls180.v:6408.38-6408.148" + cell $and $and$ls180.v:6408$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6271$1930_Y - connect \B $eq$ls180.v:6271$1931_Y - connect \Y $and$ls180.v:6271$1932_Y + connect \A $and$ls180.v:6408$2063_Y + connect \B $eq$ls180.v:6408$2064_Y + connect \Y $and$ls180.v:6408$2065_Y end - attribute \src "ls180.v:6273.38-6273.93" - cell $and $and$ls180.v:6273$1933 + attribute \src "ls180.v:6410.38-6410.93" + cell $and $and$ls180.v:6410$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244598,43 +246318,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6273$1933_Y + connect \Y $and$ls180.v:6410$2066_Y end - attribute \src "ls180.v:6273.37-6273.144" - cell $and $and$ls180.v:6273$1935 + attribute \src "ls180.v:6410.37-6410.144" + cell $and $and$ls180.v:6410$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6273$1933_Y - connect \B $eq$ls180.v:6273$1934_Y - connect \Y $and$ls180.v:6273$1935_Y + connect \A $and$ls180.v:6410$2066_Y + connect \B $eq$ls180.v:6410$2067_Y + connect \Y $and$ls180.v:6410$2068_Y end - attribute \src "ls180.v:6274.38-6274.96" - cell $and $and$ls180.v:6274$1937 + attribute \src "ls180.v:6411.38-6411.96" + cell $and $and$ls180.v:6411$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6274$1936_Y - connect \Y $and$ls180.v:6274$1937_Y + connect \B $not$ls180.v:6411$2069_Y + connect \Y $and$ls180.v:6411$2070_Y end - attribute \src "ls180.v:6274.37-6274.147" - cell $and $and$ls180.v:6274$1939 + attribute \src "ls180.v:6411.37-6411.147" + cell $and $and$ls180.v:6411$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6274$1937_Y - connect \B $eq$ls180.v:6274$1938_Y - connect \Y $and$ls180.v:6274$1939_Y + connect \A $and$ls180.v:6411$2070_Y + connect \B $eq$ls180.v:6411$2071_Y + connect \Y $and$ls180.v:6411$2072_Y end - attribute \src "ls180.v:6276.37-6276.92" - cell $and $and$ls180.v:6276$1940 + attribute \src "ls180.v:6413.37-6413.92" + cell $and $and$ls180.v:6413$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244642,43 +246362,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6276$1940_Y + connect \Y $and$ls180.v:6413$2073_Y end - attribute \src "ls180.v:6276.36-6276.143" - cell $and $and$ls180.v:6276$1942 + attribute \src "ls180.v:6413.36-6413.143" + cell $and $and$ls180.v:6413$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6276$1940_Y - connect \B $eq$ls180.v:6276$1941_Y - connect \Y $and$ls180.v:6276$1942_Y + connect \A $and$ls180.v:6413$2073_Y + connect \B $eq$ls180.v:6413$2074_Y + connect \Y $and$ls180.v:6413$2075_Y end - attribute \src "ls180.v:6277.37-6277.95" - cell $and $and$ls180.v:6277$1944 + attribute \src "ls180.v:6414.37-6414.95" + cell $and $and$ls180.v:6414$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6277$1943_Y - connect \Y $and$ls180.v:6277$1944_Y + connect \B $not$ls180.v:6414$2076_Y + connect \Y $and$ls180.v:6414$2077_Y end - attribute \src "ls180.v:6277.36-6277.146" - cell $and $and$ls180.v:6277$1946 + attribute \src "ls180.v:6414.36-6414.146" + cell $and $and$ls180.v:6414$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6277$1944_Y - connect \B $eq$ls180.v:6277$1945_Y - connect \Y $and$ls180.v:6277$1946_Y + connect \A $and$ls180.v:6414$2077_Y + connect \B $eq$ls180.v:6414$2078_Y + connect \Y $and$ls180.v:6414$2079_Y end - attribute \src "ls180.v:6279.43-6279.98" - cell $and $and$ls180.v:6279$1947 + attribute \src "ls180.v:6416.43-6416.98" + cell $and $and$ls180.v:6416$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244686,43 +246406,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6279$1947_Y + connect \Y $and$ls180.v:6416$2080_Y end - attribute \src "ls180.v:6279.42-6279.149" - cell $and $and$ls180.v:6279$1949 + attribute \src "ls180.v:6416.42-6416.149" + cell $and $and$ls180.v:6416$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6279$1947_Y - connect \B $eq$ls180.v:6279$1948_Y - connect \Y $and$ls180.v:6279$1949_Y + connect \A $and$ls180.v:6416$2080_Y + connect \B $eq$ls180.v:6416$2081_Y + connect \Y $and$ls180.v:6416$2082_Y end - attribute \src "ls180.v:6280.43-6280.101" - cell $and $and$ls180.v:6280$1951 + attribute \src "ls180.v:6417.43-6417.101" + cell $and $and$ls180.v:6417$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6280$1950_Y - connect \Y $and$ls180.v:6280$1951_Y + connect \B $not$ls180.v:6417$2083_Y + connect \Y $and$ls180.v:6417$2084_Y end - attribute \src "ls180.v:6280.42-6280.152" - cell $and $and$ls180.v:6280$1953 + attribute \src "ls180.v:6417.42-6417.152" + cell $and $and$ls180.v:6417$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6280$1951_Y - connect \B $eq$ls180.v:6280$1952_Y - connect \Y $and$ls180.v:6280$1953_Y + connect \A $and$ls180.v:6417$2084_Y + connect \B $eq$ls180.v:6417$2085_Y + connect \Y $and$ls180.v:6417$2086_Y end - attribute \src "ls180.v:6301.42-6301.97" - cell $and $and$ls180.v:6301$1956 + attribute \src "ls180.v:6438.42-6438.97" + cell $and $and$ls180.v:6438$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244730,43 +246450,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6301$1956_Y + connect \Y $and$ls180.v:6438$2089_Y end - attribute \src "ls180.v:6301.41-6301.148" - cell $and $and$ls180.v:6301$1958 + attribute \src "ls180.v:6438.41-6438.148" + cell $and $and$ls180.v:6438$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6301$1956_Y - connect \B $eq$ls180.v:6301$1957_Y - connect \Y $and$ls180.v:6301$1958_Y + connect \A $and$ls180.v:6438$2089_Y + connect \B $eq$ls180.v:6438$2090_Y + connect \Y $and$ls180.v:6438$2091_Y end - attribute \src "ls180.v:6302.42-6302.100" - cell $and $and$ls180.v:6302$1960 + attribute \src "ls180.v:6439.42-6439.100" + cell $and $and$ls180.v:6439$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6302$1959_Y - connect \Y $and$ls180.v:6302$1960_Y + connect \B $not$ls180.v:6439$2092_Y + connect \Y $and$ls180.v:6439$2093_Y end - attribute \src "ls180.v:6302.41-6302.151" - cell $and $and$ls180.v:6302$1962 + attribute \src "ls180.v:6439.41-6439.151" + cell $and $and$ls180.v:6439$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$1960_Y - connect \B $eq$ls180.v:6302$1961_Y - connect \Y $and$ls180.v:6302$1962_Y + connect \A $and$ls180.v:6439$2093_Y + connect \B $eq$ls180.v:6439$2094_Y + connect \Y $and$ls180.v:6439$2095_Y end - attribute \src "ls180.v:6304.42-6304.97" - cell $and $and$ls180.v:6304$1963 + attribute \src "ls180.v:6441.42-6441.97" + cell $and $and$ls180.v:6441$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244774,43 +246494,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6304$1963_Y + connect \Y $and$ls180.v:6441$2096_Y end - attribute \src "ls180.v:6304.41-6304.148" - cell $and $and$ls180.v:6304$1965 + attribute \src "ls180.v:6441.41-6441.148" + cell $and $and$ls180.v:6441$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6304$1963_Y - connect \B $eq$ls180.v:6304$1964_Y - connect \Y $and$ls180.v:6304$1965_Y + connect \A $and$ls180.v:6441$2096_Y + connect \B $eq$ls180.v:6441$2097_Y + connect \Y $and$ls180.v:6441$2098_Y end - attribute \src "ls180.v:6305.42-6305.100" - cell $and $and$ls180.v:6305$1967 + attribute \src "ls180.v:6442.42-6442.100" + cell $and $and$ls180.v:6442$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6305$1966_Y - connect \Y $and$ls180.v:6305$1967_Y + connect \B $not$ls180.v:6442$2099_Y + connect \Y $and$ls180.v:6442$2100_Y end - attribute \src "ls180.v:6305.41-6305.151" - cell $and $and$ls180.v:6305$1969 + attribute \src "ls180.v:6442.41-6442.151" + cell $and $and$ls180.v:6442$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$1967_Y - connect \B $eq$ls180.v:6305$1968_Y - connect \Y $and$ls180.v:6305$1969_Y + connect \A $and$ls180.v:6442$2100_Y + connect \B $eq$ls180.v:6442$2101_Y + connect \Y $and$ls180.v:6442$2102_Y end - attribute \src "ls180.v:6307.40-6307.95" - cell $and $and$ls180.v:6307$1970 + attribute \src "ls180.v:6444.40-6444.95" + cell $and $and$ls180.v:6444$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244818,43 +246538,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6307$1970_Y + connect \Y $and$ls180.v:6444$2103_Y end - attribute \src "ls180.v:6307.39-6307.146" - cell $and $and$ls180.v:6307$1972 + attribute \src "ls180.v:6444.39-6444.146" + cell $and $and$ls180.v:6444$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6307$1970_Y - connect \B $eq$ls180.v:6307$1971_Y - connect \Y $and$ls180.v:6307$1972_Y + connect \A $and$ls180.v:6444$2103_Y + connect \B $eq$ls180.v:6444$2104_Y + connect \Y $and$ls180.v:6444$2105_Y end - attribute \src "ls180.v:6308.40-6308.98" - cell $and $and$ls180.v:6308$1974 + attribute \src "ls180.v:6445.40-6445.98" + cell $and $and$ls180.v:6445$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6308$1973_Y - connect \Y $and$ls180.v:6308$1974_Y + connect \B $not$ls180.v:6445$2106_Y + connect \Y $and$ls180.v:6445$2107_Y end - attribute \src "ls180.v:6308.39-6308.149" - cell $and $and$ls180.v:6308$1976 + attribute \src "ls180.v:6445.39-6445.149" + cell $and $and$ls180.v:6445$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$1974_Y - connect \B $eq$ls180.v:6308$1975_Y - connect \Y $and$ls180.v:6308$1976_Y + connect \A $and$ls180.v:6445$2107_Y + connect \B $eq$ls180.v:6445$2108_Y + connect \Y $and$ls180.v:6445$2109_Y end - attribute \src "ls180.v:6310.39-6310.94" - cell $and $and$ls180.v:6310$1977 + attribute \src "ls180.v:6447.39-6447.94" + cell $and $and$ls180.v:6447$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244862,43 +246582,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6310$1977_Y + connect \Y $and$ls180.v:6447$2110_Y end - attribute \src "ls180.v:6310.38-6310.145" - cell $and $and$ls180.v:6310$1979 + attribute \src "ls180.v:6447.38-6447.145" + cell $and $and$ls180.v:6447$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6310$1977_Y - connect \B $eq$ls180.v:6310$1978_Y - connect \Y $and$ls180.v:6310$1979_Y + connect \A $and$ls180.v:6447$2110_Y + connect \B $eq$ls180.v:6447$2111_Y + connect \Y $and$ls180.v:6447$2112_Y end - attribute \src "ls180.v:6311.39-6311.97" - cell $and $and$ls180.v:6311$1981 + attribute \src "ls180.v:6448.39-6448.97" + cell $and $and$ls180.v:6448$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6311$1980_Y - connect \Y $and$ls180.v:6311$1981_Y + connect \B $not$ls180.v:6448$2113_Y + connect \Y $and$ls180.v:6448$2114_Y end - attribute \src "ls180.v:6311.38-6311.148" - cell $and $and$ls180.v:6311$1983 + attribute \src "ls180.v:6448.38-6448.148" + cell $and $and$ls180.v:6448$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$1981_Y - connect \B $eq$ls180.v:6311$1982_Y - connect \Y $and$ls180.v:6311$1983_Y + connect \A $and$ls180.v:6448$2114_Y + connect \B $eq$ls180.v:6448$2115_Y + connect \Y $and$ls180.v:6448$2116_Y end - attribute \src "ls180.v:6313.38-6313.93" - cell $and $and$ls180.v:6313$1984 + attribute \src "ls180.v:6450.38-6450.93" + cell $and $and$ls180.v:6450$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244906,43 +246626,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6313$1984_Y + connect \Y $and$ls180.v:6450$2117_Y end - attribute \src "ls180.v:6313.37-6313.144" - cell $and $and$ls180.v:6313$1986 + attribute \src "ls180.v:6450.37-6450.144" + cell $and $and$ls180.v:6450$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6313$1984_Y - connect \B $eq$ls180.v:6313$1985_Y - connect \Y $and$ls180.v:6313$1986_Y + connect \A $and$ls180.v:6450$2117_Y + connect \B $eq$ls180.v:6450$2118_Y + connect \Y $and$ls180.v:6450$2119_Y end - attribute \src "ls180.v:6314.38-6314.96" - cell $and $and$ls180.v:6314$1988 + attribute \src "ls180.v:6451.38-6451.96" + cell $and $and$ls180.v:6451$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6314$1987_Y - connect \Y $and$ls180.v:6314$1988_Y + connect \B $not$ls180.v:6451$2120_Y + connect \Y $and$ls180.v:6451$2121_Y end - attribute \src "ls180.v:6314.37-6314.147" - cell $and $and$ls180.v:6314$1990 + attribute \src "ls180.v:6451.37-6451.147" + cell $and $and$ls180.v:6451$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6314$1988_Y - connect \B $eq$ls180.v:6314$1989_Y - connect \Y $and$ls180.v:6314$1990_Y + connect \A $and$ls180.v:6451$2121_Y + connect \B $eq$ls180.v:6451$2122_Y + connect \Y $and$ls180.v:6451$2123_Y end - attribute \src "ls180.v:6316.37-6316.92" - cell $and $and$ls180.v:6316$1991 + attribute \src "ls180.v:6453.37-6453.92" + cell $and $and$ls180.v:6453$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244950,43 +246670,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6316$1991_Y + connect \Y $and$ls180.v:6453$2124_Y end - attribute \src "ls180.v:6316.36-6316.143" - cell $and $and$ls180.v:6316$1993 + attribute \src "ls180.v:6453.36-6453.143" + cell $and $and$ls180.v:6453$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6316$1991_Y - connect \B $eq$ls180.v:6316$1992_Y - connect \Y $and$ls180.v:6316$1993_Y + connect \A $and$ls180.v:6453$2124_Y + connect \B $eq$ls180.v:6453$2125_Y + connect \Y $and$ls180.v:6453$2126_Y end - attribute \src "ls180.v:6317.37-6317.95" - cell $and $and$ls180.v:6317$1995 + attribute \src "ls180.v:6454.37-6454.95" + cell $and $and$ls180.v:6454$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6317$1994_Y - connect \Y $and$ls180.v:6317$1995_Y + connect \B $not$ls180.v:6454$2127_Y + connect \Y $and$ls180.v:6454$2128_Y end - attribute \src "ls180.v:6317.36-6317.146" - cell $and $and$ls180.v:6317$1997 + attribute \src "ls180.v:6454.36-6454.146" + cell $and $and$ls180.v:6454$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6317$1995_Y - connect \B $eq$ls180.v:6317$1996_Y - connect \Y $and$ls180.v:6317$1997_Y + connect \A $and$ls180.v:6454$2128_Y + connect \B $eq$ls180.v:6454$2129_Y + connect \Y $and$ls180.v:6454$2130_Y end - attribute \src "ls180.v:6319.43-6319.98" - cell $and $and$ls180.v:6319$1998 + attribute \src "ls180.v:6456.43-6456.98" + cell $and $and$ls180.v:6456$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244994,43 +246714,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6319$1998_Y + connect \Y $and$ls180.v:6456$2131_Y end - attribute \src "ls180.v:6319.42-6319.149" - cell $and $and$ls180.v:6319$2000 + attribute \src "ls180.v:6456.42-6456.149" + cell $and $and$ls180.v:6456$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6319$1998_Y - connect \B $eq$ls180.v:6319$1999_Y - connect \Y $and$ls180.v:6319$2000_Y + connect \A $and$ls180.v:6456$2131_Y + connect \B $eq$ls180.v:6456$2132_Y + connect \Y $and$ls180.v:6456$2133_Y end - attribute \src "ls180.v:6320.43-6320.101" - cell $and $and$ls180.v:6320$2002 + attribute \src "ls180.v:6457.43-6457.101" + cell $and $and$ls180.v:6457$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6320$2001_Y - connect \Y $and$ls180.v:6320$2002_Y + connect \B $not$ls180.v:6457$2134_Y + connect \Y $and$ls180.v:6457$2135_Y end - attribute \src "ls180.v:6320.42-6320.152" - cell $and $and$ls180.v:6320$2004 + attribute \src "ls180.v:6457.42-6457.152" + cell $and $and$ls180.v:6457$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6320$2002_Y - connect \B $eq$ls180.v:6320$2003_Y - connect \Y $and$ls180.v:6320$2004_Y + connect \A $and$ls180.v:6457$2135_Y + connect \B $eq$ls180.v:6457$2136_Y + connect \Y $and$ls180.v:6457$2137_Y end - attribute \src "ls180.v:6322.46-6322.101" - cell $and $and$ls180.v:6322$2005 + attribute \src "ls180.v:6459.46-6459.101" + cell $and $and$ls180.v:6459$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245038,43 +246758,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6322$2005_Y + connect \Y $and$ls180.v:6459$2138_Y end - attribute \src "ls180.v:6322.45-6322.152" - cell $and $and$ls180.v:6322$2007 + attribute \src "ls180.v:6459.45-6459.152" + cell $and $and$ls180.v:6459$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6322$2005_Y - connect \B $eq$ls180.v:6322$2006_Y - connect \Y $and$ls180.v:6322$2007_Y + connect \A $and$ls180.v:6459$2138_Y + connect \B $eq$ls180.v:6459$2139_Y + connect \Y $and$ls180.v:6459$2140_Y end - attribute \src "ls180.v:6323.46-6323.104" - cell $and $and$ls180.v:6323$2009 + attribute \src "ls180.v:6460.46-6460.104" + cell $and $and$ls180.v:6460$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6323$2008_Y - connect \Y $and$ls180.v:6323$2009_Y + connect \B $not$ls180.v:6460$2141_Y + connect \Y $and$ls180.v:6460$2142_Y end - attribute \src "ls180.v:6323.45-6323.155" - cell $and $and$ls180.v:6323$2011 + attribute \src "ls180.v:6460.45-6460.155" + cell $and $and$ls180.v:6460$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6323$2009_Y - connect \B $eq$ls180.v:6323$2010_Y - connect \Y $and$ls180.v:6323$2011_Y + connect \A $and$ls180.v:6460$2142_Y + connect \B $eq$ls180.v:6460$2143_Y + connect \Y $and$ls180.v:6460$2144_Y end - attribute \src "ls180.v:6325.46-6325.101" - cell $and $and$ls180.v:6325$2012 + attribute \src "ls180.v:6462.46-6462.101" + cell $and $and$ls180.v:6462$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245082,43 +246802,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6325$2012_Y + connect \Y $and$ls180.v:6462$2145_Y end - attribute \src "ls180.v:6325.45-6325.152" - cell $and $and$ls180.v:6325$2014 + attribute \src "ls180.v:6462.45-6462.152" + cell $and $and$ls180.v:6462$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6325$2012_Y - connect \B $eq$ls180.v:6325$2013_Y - connect \Y $and$ls180.v:6325$2014_Y + connect \A $and$ls180.v:6462$2145_Y + connect \B $eq$ls180.v:6462$2146_Y + connect \Y $and$ls180.v:6462$2147_Y end - attribute \src "ls180.v:6326.46-6326.104" - cell $and $and$ls180.v:6326$2016 + attribute \src "ls180.v:6463.46-6463.104" + cell $and $and$ls180.v:6463$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6326$2015_Y - connect \Y $and$ls180.v:6326$2016_Y + connect \B $not$ls180.v:6463$2148_Y + connect \Y $and$ls180.v:6463$2149_Y end - attribute \src "ls180.v:6326.45-6326.155" - cell $and $and$ls180.v:6326$2018 + attribute \src "ls180.v:6463.45-6463.155" + cell $and $and$ls180.v:6463$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6326$2016_Y - connect \B $eq$ls180.v:6326$2017_Y - connect \Y $and$ls180.v:6326$2018_Y + connect \A $and$ls180.v:6463$2149_Y + connect \B $eq$ls180.v:6463$2150_Y + connect \Y $and$ls180.v:6463$2151_Y end - attribute \src "ls180.v:6349.39-6349.94" - cell $and $and$ls180.v:6349$2021 + attribute \src "ls180.v:6486.39-6486.94" + cell $and $and$ls180.v:6486$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245126,43 +246846,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6349$2021_Y + connect \Y $and$ls180.v:6486$2154_Y end - attribute \src "ls180.v:6349.38-6349.145" - cell $and $and$ls180.v:6349$2023 + attribute \src "ls180.v:6486.38-6486.145" + cell $and $and$ls180.v:6486$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6349$2021_Y - connect \B $eq$ls180.v:6349$2022_Y - connect \Y $and$ls180.v:6349$2023_Y + connect \A $and$ls180.v:6486$2154_Y + connect \B $eq$ls180.v:6486$2155_Y + connect \Y $and$ls180.v:6486$2156_Y end - attribute \src "ls180.v:6350.39-6350.97" - cell $and $and$ls180.v:6350$2025 + attribute \src "ls180.v:6487.39-6487.97" + cell $and $and$ls180.v:6487$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6350$2024_Y - connect \Y $and$ls180.v:6350$2025_Y + connect \B $not$ls180.v:6487$2157_Y + connect \Y $and$ls180.v:6487$2158_Y end - attribute \src "ls180.v:6350.38-6350.148" - cell $and $and$ls180.v:6350$2027 + attribute \src "ls180.v:6487.38-6487.148" + cell $and $and$ls180.v:6487$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6350$2025_Y - connect \B $eq$ls180.v:6350$2026_Y - connect \Y $and$ls180.v:6350$2027_Y + connect \A $and$ls180.v:6487$2158_Y + connect \B $eq$ls180.v:6487$2159_Y + connect \Y $and$ls180.v:6487$2160_Y end - attribute \src "ls180.v:6352.39-6352.94" - cell $and $and$ls180.v:6352$2028 + attribute \src "ls180.v:6489.39-6489.94" + cell $and $and$ls180.v:6489$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245170,43 +246890,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6352$2028_Y + connect \Y $and$ls180.v:6489$2161_Y end - attribute \src "ls180.v:6352.38-6352.145" - cell $and $and$ls180.v:6352$2030 + attribute \src "ls180.v:6489.38-6489.145" + cell $and $and$ls180.v:6489$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6352$2028_Y - connect \B $eq$ls180.v:6352$2029_Y - connect \Y $and$ls180.v:6352$2030_Y + connect \A $and$ls180.v:6489$2161_Y + connect \B $eq$ls180.v:6489$2162_Y + connect \Y $and$ls180.v:6489$2163_Y end - attribute \src "ls180.v:6353.39-6353.97" - cell $and $and$ls180.v:6353$2032 + attribute \src "ls180.v:6490.39-6490.97" + cell $and $and$ls180.v:6490$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6353$2031_Y - connect \Y $and$ls180.v:6353$2032_Y + connect \B $not$ls180.v:6490$2164_Y + connect \Y $and$ls180.v:6490$2165_Y end - attribute \src "ls180.v:6353.38-6353.148" - cell $and $and$ls180.v:6353$2034 + attribute \src "ls180.v:6490.38-6490.148" + cell $and $and$ls180.v:6490$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6353$2032_Y - connect \B $eq$ls180.v:6353$2033_Y - connect \Y $and$ls180.v:6353$2034_Y + connect \A $and$ls180.v:6490$2165_Y + connect \B $eq$ls180.v:6490$2166_Y + connect \Y $and$ls180.v:6490$2167_Y end - attribute \src "ls180.v:6355.39-6355.94" - cell $and $and$ls180.v:6355$2035 + attribute \src "ls180.v:6492.39-6492.94" + cell $and $and$ls180.v:6492$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245214,43 +246934,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6355$2035_Y + connect \Y $and$ls180.v:6492$2168_Y end - attribute \src "ls180.v:6355.38-6355.145" - cell $and $and$ls180.v:6355$2037 + attribute \src "ls180.v:6492.38-6492.145" + cell $and $and$ls180.v:6492$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6355$2035_Y - connect \B $eq$ls180.v:6355$2036_Y - connect \Y $and$ls180.v:6355$2037_Y + connect \A $and$ls180.v:6492$2168_Y + connect \B $eq$ls180.v:6492$2169_Y + connect \Y $and$ls180.v:6492$2170_Y end - attribute \src "ls180.v:6356.39-6356.97" - cell $and $and$ls180.v:6356$2039 + attribute \src "ls180.v:6493.39-6493.97" + cell $and $and$ls180.v:6493$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6356$2038_Y - connect \Y $and$ls180.v:6356$2039_Y + connect \B $not$ls180.v:6493$2171_Y + connect \Y $and$ls180.v:6493$2172_Y end - attribute \src "ls180.v:6356.38-6356.148" - cell $and $and$ls180.v:6356$2041 + attribute \src "ls180.v:6493.38-6493.148" + cell $and $and$ls180.v:6493$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6356$2039_Y - connect \B $eq$ls180.v:6356$2040_Y - connect \Y $and$ls180.v:6356$2041_Y + connect \A $and$ls180.v:6493$2172_Y + connect \B $eq$ls180.v:6493$2173_Y + connect \Y $and$ls180.v:6493$2174_Y end - attribute \src "ls180.v:6358.39-6358.94" - cell $and $and$ls180.v:6358$2042 + attribute \src "ls180.v:6495.39-6495.94" + cell $and $and$ls180.v:6495$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245258,43 +246978,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6358$2042_Y + connect \Y $and$ls180.v:6495$2175_Y end - attribute \src "ls180.v:6358.38-6358.145" - cell $and $and$ls180.v:6358$2044 + attribute \src "ls180.v:6495.38-6495.145" + cell $and $and$ls180.v:6495$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6358$2042_Y - connect \B $eq$ls180.v:6358$2043_Y - connect \Y $and$ls180.v:6358$2044_Y + connect \A $and$ls180.v:6495$2175_Y + connect \B $eq$ls180.v:6495$2176_Y + connect \Y $and$ls180.v:6495$2177_Y end - attribute \src "ls180.v:6359.39-6359.97" - cell $and $and$ls180.v:6359$2046 + attribute \src "ls180.v:6496.39-6496.97" + cell $and $and$ls180.v:6496$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6359$2045_Y - connect \Y $and$ls180.v:6359$2046_Y + connect \B $not$ls180.v:6496$2178_Y + connect \Y $and$ls180.v:6496$2179_Y end - attribute \src "ls180.v:6359.38-6359.148" - cell $and $and$ls180.v:6359$2048 + attribute \src "ls180.v:6496.38-6496.148" + cell $and $and$ls180.v:6496$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6359$2046_Y - connect \B $eq$ls180.v:6359$2047_Y - connect \Y $and$ls180.v:6359$2048_Y + connect \A $and$ls180.v:6496$2179_Y + connect \B $eq$ls180.v:6496$2180_Y + connect \Y $and$ls180.v:6496$2181_Y end - attribute \src "ls180.v:6361.41-6361.96" - cell $and $and$ls180.v:6361$2049 + attribute \src "ls180.v:6498.41-6498.96" + cell $and $and$ls180.v:6498$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245302,43 +247022,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6361$2049_Y + connect \Y $and$ls180.v:6498$2182_Y end - attribute \src "ls180.v:6361.40-6361.147" - cell $and $and$ls180.v:6361$2051 + attribute \src "ls180.v:6498.40-6498.147" + cell $and $and$ls180.v:6498$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6361$2049_Y - connect \B $eq$ls180.v:6361$2050_Y - connect \Y $and$ls180.v:6361$2051_Y + connect \A $and$ls180.v:6498$2182_Y + connect \B $eq$ls180.v:6498$2183_Y + connect \Y $and$ls180.v:6498$2184_Y end - attribute \src "ls180.v:6362.41-6362.99" - cell $and $and$ls180.v:6362$2053 + attribute \src "ls180.v:6499.41-6499.99" + cell $and $and$ls180.v:6499$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6362$2052_Y - connect \Y $and$ls180.v:6362$2053_Y + connect \B $not$ls180.v:6499$2185_Y + connect \Y $and$ls180.v:6499$2186_Y end - attribute \src "ls180.v:6362.40-6362.150" - cell $and $and$ls180.v:6362$2055 + attribute \src "ls180.v:6499.40-6499.150" + cell $and $and$ls180.v:6499$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6362$2053_Y - connect \B $eq$ls180.v:6362$2054_Y - connect \Y $and$ls180.v:6362$2055_Y + connect \A $and$ls180.v:6499$2186_Y + connect \B $eq$ls180.v:6499$2187_Y + connect \Y $and$ls180.v:6499$2188_Y end - attribute \src "ls180.v:6364.41-6364.96" - cell $and $and$ls180.v:6364$2056 + attribute \src "ls180.v:6501.41-6501.96" + cell $and $and$ls180.v:6501$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245346,43 +247066,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6364$2056_Y + connect \Y $and$ls180.v:6501$2189_Y end - attribute \src "ls180.v:6364.40-6364.147" - cell $and $and$ls180.v:6364$2058 + attribute \src "ls180.v:6501.40-6501.147" + cell $and $and$ls180.v:6501$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6364$2056_Y - connect \B $eq$ls180.v:6364$2057_Y - connect \Y $and$ls180.v:6364$2058_Y + connect \A $and$ls180.v:6501$2189_Y + connect \B $eq$ls180.v:6501$2190_Y + connect \Y $and$ls180.v:6501$2191_Y end - attribute \src "ls180.v:6365.41-6365.99" - cell $and $and$ls180.v:6365$2060 + attribute \src "ls180.v:6502.41-6502.99" + cell $and $and$ls180.v:6502$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6365$2059_Y - connect \Y $and$ls180.v:6365$2060_Y + connect \B $not$ls180.v:6502$2192_Y + connect \Y $and$ls180.v:6502$2193_Y end - attribute \src "ls180.v:6365.40-6365.150" - cell $and $and$ls180.v:6365$2062 + attribute \src "ls180.v:6502.40-6502.150" + cell $and $and$ls180.v:6502$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6365$2060_Y - connect \B $eq$ls180.v:6365$2061_Y - connect \Y $and$ls180.v:6365$2062_Y + connect \A $and$ls180.v:6502$2193_Y + connect \B $eq$ls180.v:6502$2194_Y + connect \Y $and$ls180.v:6502$2195_Y end - attribute \src "ls180.v:6367.41-6367.96" - cell $and $and$ls180.v:6367$2063 + attribute \src "ls180.v:6504.41-6504.96" + cell $and $and$ls180.v:6504$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245390,43 +247110,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6367$2063_Y + connect \Y $and$ls180.v:6504$2196_Y end - attribute \src "ls180.v:6367.40-6367.147" - cell $and $and$ls180.v:6367$2065 + attribute \src "ls180.v:6504.40-6504.147" + cell $and $and$ls180.v:6504$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6367$2063_Y - connect \B $eq$ls180.v:6367$2064_Y - connect \Y $and$ls180.v:6367$2065_Y + connect \A $and$ls180.v:6504$2196_Y + connect \B $eq$ls180.v:6504$2197_Y + connect \Y $and$ls180.v:6504$2198_Y end - attribute \src "ls180.v:6368.41-6368.99" - cell $and $and$ls180.v:6368$2067 + attribute \src "ls180.v:6505.41-6505.99" + cell $and $and$ls180.v:6505$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6368$2066_Y - connect \Y $and$ls180.v:6368$2067_Y + connect \B $not$ls180.v:6505$2199_Y + connect \Y $and$ls180.v:6505$2200_Y end - attribute \src "ls180.v:6368.40-6368.150" - cell $and $and$ls180.v:6368$2069 + attribute \src "ls180.v:6505.40-6505.150" + cell $and $and$ls180.v:6505$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6368$2067_Y - connect \B $eq$ls180.v:6368$2068_Y - connect \Y $and$ls180.v:6368$2069_Y + connect \A $and$ls180.v:6505$2200_Y + connect \B $eq$ls180.v:6505$2201_Y + connect \Y $and$ls180.v:6505$2202_Y end - attribute \src "ls180.v:6370.41-6370.96" - cell $and $and$ls180.v:6370$2070 + attribute \src "ls180.v:6507.41-6507.96" + cell $and $and$ls180.v:6507$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245434,43 +247154,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6370$2070_Y + connect \Y $and$ls180.v:6507$2203_Y end - attribute \src "ls180.v:6370.40-6370.147" - cell $and $and$ls180.v:6370$2072 + attribute \src "ls180.v:6507.40-6507.147" + cell $and $and$ls180.v:6507$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6370$2070_Y - connect \B $eq$ls180.v:6370$2071_Y - connect \Y $and$ls180.v:6370$2072_Y + connect \A $and$ls180.v:6507$2203_Y + connect \B $eq$ls180.v:6507$2204_Y + connect \Y $and$ls180.v:6507$2205_Y end - attribute \src "ls180.v:6371.41-6371.99" - cell $and $and$ls180.v:6371$2074 + attribute \src "ls180.v:6508.41-6508.99" + cell $and $and$ls180.v:6508$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6371$2073_Y - connect \Y $and$ls180.v:6371$2074_Y + connect \B $not$ls180.v:6508$2206_Y + connect \Y $and$ls180.v:6508$2207_Y end - attribute \src "ls180.v:6371.40-6371.150" - cell $and $and$ls180.v:6371$2076 + attribute \src "ls180.v:6508.40-6508.150" + cell $and $and$ls180.v:6508$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6371$2074_Y - connect \B $eq$ls180.v:6371$2075_Y - connect \Y $and$ls180.v:6371$2076_Y + connect \A $and$ls180.v:6508$2207_Y + connect \B $eq$ls180.v:6508$2208_Y + connect \Y $and$ls180.v:6508$2209_Y end - attribute \src "ls180.v:6373.37-6373.92" - cell $and $and$ls180.v:6373$2077 + attribute \src "ls180.v:6510.37-6510.92" + cell $and $and$ls180.v:6510$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245478,43 +247198,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6373$2077_Y + connect \Y $and$ls180.v:6510$2210_Y end - attribute \src "ls180.v:6373.36-6373.143" - cell $and $and$ls180.v:6373$2079 + attribute \src "ls180.v:6510.36-6510.143" + cell $and $and$ls180.v:6510$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6373$2077_Y - connect \B $eq$ls180.v:6373$2078_Y - connect \Y $and$ls180.v:6373$2079_Y + connect \A $and$ls180.v:6510$2210_Y + connect \B $eq$ls180.v:6510$2211_Y + connect \Y $and$ls180.v:6510$2212_Y end - attribute \src "ls180.v:6374.37-6374.95" - cell $and $and$ls180.v:6374$2081 + attribute \src "ls180.v:6511.37-6511.95" + cell $and $and$ls180.v:6511$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6374$2080_Y - connect \Y $and$ls180.v:6374$2081_Y + connect \B $not$ls180.v:6511$2213_Y + connect \Y $and$ls180.v:6511$2214_Y end - attribute \src "ls180.v:6374.36-6374.146" - cell $and $and$ls180.v:6374$2083 + attribute \src "ls180.v:6511.36-6511.146" + cell $and $and$ls180.v:6511$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6374$2081_Y - connect \B $eq$ls180.v:6374$2082_Y - connect \Y $and$ls180.v:6374$2083_Y + connect \A $and$ls180.v:6511$2214_Y + connect \B $eq$ls180.v:6511$2215_Y + connect \Y $and$ls180.v:6511$2216_Y end - attribute \src "ls180.v:6376.47-6376.102" - cell $and $and$ls180.v:6376$2084 + attribute \src "ls180.v:6513.47-6513.102" + cell $and $and$ls180.v:6513$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245522,43 +247242,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6376$2084_Y + connect \Y $and$ls180.v:6513$2217_Y end - attribute \src "ls180.v:6376.46-6376.153" - cell $and $and$ls180.v:6376$2086 + attribute \src "ls180.v:6513.46-6513.153" + cell $and $and$ls180.v:6513$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6376$2084_Y - connect \B $eq$ls180.v:6376$2085_Y - connect \Y $and$ls180.v:6376$2086_Y + connect \A $and$ls180.v:6513$2217_Y + connect \B $eq$ls180.v:6513$2218_Y + connect \Y $and$ls180.v:6513$2219_Y end - attribute \src "ls180.v:6377.47-6377.105" - cell $and $and$ls180.v:6377$2088 + attribute \src "ls180.v:6514.47-6514.105" + cell $and $and$ls180.v:6514$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6377$2087_Y - connect \Y $and$ls180.v:6377$2088_Y + connect \B $not$ls180.v:6514$2220_Y + connect \Y $and$ls180.v:6514$2221_Y end - attribute \src "ls180.v:6377.46-6377.156" - cell $and $and$ls180.v:6377$2090 + attribute \src "ls180.v:6514.46-6514.156" + cell $and $and$ls180.v:6514$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6377$2088_Y - connect \B $eq$ls180.v:6377$2089_Y - connect \Y $and$ls180.v:6377$2090_Y + connect \A $and$ls180.v:6514$2221_Y + connect \B $eq$ls180.v:6514$2222_Y + connect \Y $and$ls180.v:6514$2223_Y end - attribute \src "ls180.v:6379.40-6379.95" - cell $and $and$ls180.v:6379$2091 + attribute \src "ls180.v:6516.40-6516.95" + cell $and $and$ls180.v:6516$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245566,43 +247286,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6379$2091_Y + connect \Y $and$ls180.v:6516$2224_Y end - attribute \src "ls180.v:6379.39-6379.147" - cell $and $and$ls180.v:6379$2093 + attribute \src "ls180.v:6516.39-6516.147" + cell $and $and$ls180.v:6516$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6379$2091_Y - connect \B $eq$ls180.v:6379$2092_Y - connect \Y $and$ls180.v:6379$2093_Y + connect \A $and$ls180.v:6516$2224_Y + connect \B $eq$ls180.v:6516$2225_Y + connect \Y $and$ls180.v:6516$2226_Y end - attribute \src "ls180.v:6380.40-6380.98" - cell $and $and$ls180.v:6380$2095 + attribute \src "ls180.v:6517.40-6517.98" + cell $and $and$ls180.v:6517$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6380$2094_Y - connect \Y $and$ls180.v:6380$2095_Y + connect \B $not$ls180.v:6517$2227_Y + connect \Y $and$ls180.v:6517$2228_Y end - attribute \src "ls180.v:6380.39-6380.150" - cell $and $and$ls180.v:6380$2097 + attribute \src "ls180.v:6517.39-6517.150" + cell $and $and$ls180.v:6517$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6380$2095_Y - connect \B $eq$ls180.v:6380$2096_Y - connect \Y $and$ls180.v:6380$2097_Y + connect \A $and$ls180.v:6517$2228_Y + connect \B $eq$ls180.v:6517$2229_Y + connect \Y $and$ls180.v:6517$2230_Y end - attribute \src "ls180.v:6382.40-6382.95" - cell $and $and$ls180.v:6382$2098 + attribute \src "ls180.v:6519.40-6519.95" + cell $and $and$ls180.v:6519$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245610,43 +247330,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6382$2098_Y + connect \Y $and$ls180.v:6519$2231_Y end - attribute \src "ls180.v:6382.39-6382.147" - cell $and $and$ls180.v:6382$2100 + attribute \src "ls180.v:6519.39-6519.147" + cell $and $and$ls180.v:6519$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6382$2098_Y - connect \B $eq$ls180.v:6382$2099_Y - connect \Y $and$ls180.v:6382$2100_Y + connect \A $and$ls180.v:6519$2231_Y + connect \B $eq$ls180.v:6519$2232_Y + connect \Y $and$ls180.v:6519$2233_Y end - attribute \src "ls180.v:6383.40-6383.98" - cell $and $and$ls180.v:6383$2102 + attribute \src "ls180.v:6520.40-6520.98" + cell $and $and$ls180.v:6520$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6383$2101_Y - connect \Y $and$ls180.v:6383$2102_Y + connect \B $not$ls180.v:6520$2234_Y + connect \Y $and$ls180.v:6520$2235_Y end - attribute \src "ls180.v:6383.39-6383.150" - cell $and $and$ls180.v:6383$2104 + attribute \src "ls180.v:6520.39-6520.150" + cell $and $and$ls180.v:6520$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6383$2102_Y - connect \B $eq$ls180.v:6383$2103_Y - connect \Y $and$ls180.v:6383$2104_Y + connect \A $and$ls180.v:6520$2235_Y + connect \B $eq$ls180.v:6520$2236_Y + connect \Y $and$ls180.v:6520$2237_Y end - attribute \src "ls180.v:6385.40-6385.95" - cell $and $and$ls180.v:6385$2105 + attribute \src "ls180.v:6522.40-6522.95" + cell $and $and$ls180.v:6522$2238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245654,43 +247374,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6385$2105_Y + connect \Y $and$ls180.v:6522$2238_Y end - attribute \src "ls180.v:6385.39-6385.147" - cell $and $and$ls180.v:6385$2107 + attribute \src "ls180.v:6522.39-6522.147" + cell $and $and$ls180.v:6522$2240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6385$2105_Y - connect \B $eq$ls180.v:6385$2106_Y - connect \Y $and$ls180.v:6385$2107_Y + connect \A $and$ls180.v:6522$2238_Y + connect \B $eq$ls180.v:6522$2239_Y + connect \Y $and$ls180.v:6522$2240_Y end - attribute \src "ls180.v:6386.40-6386.98" - cell $and $and$ls180.v:6386$2109 + attribute \src "ls180.v:6523.40-6523.98" + cell $and $and$ls180.v:6523$2242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6386$2108_Y - connect \Y $and$ls180.v:6386$2109_Y + connect \B $not$ls180.v:6523$2241_Y + connect \Y $and$ls180.v:6523$2242_Y end - attribute \src "ls180.v:6386.39-6386.150" - cell $and $and$ls180.v:6386$2111 + attribute \src "ls180.v:6523.39-6523.150" + cell $and $and$ls180.v:6523$2244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6386$2109_Y - connect \B $eq$ls180.v:6386$2110_Y - connect \Y $and$ls180.v:6386$2111_Y + connect \A $and$ls180.v:6523$2242_Y + connect \B $eq$ls180.v:6523$2243_Y + connect \Y $and$ls180.v:6523$2244_Y end - attribute \src "ls180.v:6388.40-6388.95" - cell $and $and$ls180.v:6388$2112 + attribute \src "ls180.v:6525.40-6525.95" + cell $and $and$ls180.v:6525$2245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245698,43 +247418,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6388$2112_Y + connect \Y $and$ls180.v:6525$2245_Y end - attribute \src "ls180.v:6388.39-6388.147" - cell $and $and$ls180.v:6388$2114 + attribute \src "ls180.v:6525.39-6525.147" + cell $and $and$ls180.v:6525$2247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6388$2112_Y - connect \B $eq$ls180.v:6388$2113_Y - connect \Y $and$ls180.v:6388$2114_Y + connect \A $and$ls180.v:6525$2245_Y + connect \B $eq$ls180.v:6525$2246_Y + connect \Y $and$ls180.v:6525$2247_Y end - attribute \src "ls180.v:6389.40-6389.98" - cell $and $and$ls180.v:6389$2116 + attribute \src "ls180.v:6526.40-6526.98" + cell $and $and$ls180.v:6526$2249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6389$2115_Y - connect \Y $and$ls180.v:6389$2116_Y + connect \B $not$ls180.v:6526$2248_Y + connect \Y $and$ls180.v:6526$2249_Y end - attribute \src "ls180.v:6389.39-6389.150" - cell $and $and$ls180.v:6389$2118 + attribute \src "ls180.v:6526.39-6526.150" + cell $and $and$ls180.v:6526$2251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6389$2116_Y - connect \B $eq$ls180.v:6389$2117_Y - connect \Y $and$ls180.v:6389$2118_Y + connect \A $and$ls180.v:6526$2249_Y + connect \B $eq$ls180.v:6526$2250_Y + connect \Y $and$ls180.v:6526$2251_Y end - attribute \src "ls180.v:6391.52-6391.107" - cell $and $and$ls180.v:6391$2119 + attribute \src "ls180.v:6528.52-6528.107" + cell $and $and$ls180.v:6528$2252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245742,43 +247462,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6391$2119_Y + connect \Y $and$ls180.v:6528$2252_Y end - attribute \src "ls180.v:6391.51-6391.159" - cell $and $and$ls180.v:6391$2121 + attribute \src "ls180.v:6528.51-6528.159" + cell $and $and$ls180.v:6528$2254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6391$2119_Y - connect \B $eq$ls180.v:6391$2120_Y - connect \Y $and$ls180.v:6391$2121_Y + connect \A $and$ls180.v:6528$2252_Y + connect \B $eq$ls180.v:6528$2253_Y + connect \Y $and$ls180.v:6528$2254_Y end - attribute \src "ls180.v:6392.52-6392.110" - cell $and $and$ls180.v:6392$2123 + attribute \src "ls180.v:6529.52-6529.110" + cell $and $and$ls180.v:6529$2256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6392$2122_Y - connect \Y $and$ls180.v:6392$2123_Y + connect \B $not$ls180.v:6529$2255_Y + connect \Y $and$ls180.v:6529$2256_Y end - attribute \src "ls180.v:6392.51-6392.162" - cell $and $and$ls180.v:6392$2125 + attribute \src "ls180.v:6529.51-6529.162" + cell $and $and$ls180.v:6529$2258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6392$2123_Y - connect \B $eq$ls180.v:6392$2124_Y - connect \Y $and$ls180.v:6392$2125_Y + connect \A $and$ls180.v:6529$2256_Y + connect \B $eq$ls180.v:6529$2257_Y + connect \Y $and$ls180.v:6529$2258_Y end - attribute \src "ls180.v:6394.53-6394.108" - cell $and $and$ls180.v:6394$2126 + attribute \src "ls180.v:6531.53-6531.108" + cell $and $and$ls180.v:6531$2259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245786,43 +247506,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6394$2126_Y + connect \Y $and$ls180.v:6531$2259_Y end - attribute \src "ls180.v:6394.52-6394.160" - cell $and $and$ls180.v:6394$2128 + attribute \src "ls180.v:6531.52-6531.160" + cell $and $and$ls180.v:6531$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6394$2126_Y - connect \B $eq$ls180.v:6394$2127_Y - connect \Y $and$ls180.v:6394$2128_Y + connect \A $and$ls180.v:6531$2259_Y + connect \B $eq$ls180.v:6531$2260_Y + connect \Y $and$ls180.v:6531$2261_Y end - attribute \src "ls180.v:6395.53-6395.111" - cell $and $and$ls180.v:6395$2130 + attribute \src "ls180.v:6532.53-6532.111" + cell $and $and$ls180.v:6532$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6395$2129_Y - connect \Y $and$ls180.v:6395$2130_Y + connect \B $not$ls180.v:6532$2262_Y + connect \Y $and$ls180.v:6532$2263_Y end - attribute \src "ls180.v:6395.52-6395.163" - cell $and $and$ls180.v:6395$2132 + attribute \src "ls180.v:6532.52-6532.163" + cell $and $and$ls180.v:6532$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6395$2130_Y - connect \B $eq$ls180.v:6395$2131_Y - connect \Y $and$ls180.v:6395$2132_Y + connect \A $and$ls180.v:6532$2263_Y + connect \B $eq$ls180.v:6532$2264_Y + connect \Y $and$ls180.v:6532$2265_Y end - attribute \src "ls180.v:6397.44-6397.99" - cell $and $and$ls180.v:6397$2133 + attribute \src "ls180.v:6534.44-6534.99" + cell $and $and$ls180.v:6534$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245830,43 +247550,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6397$2133_Y + connect \Y $and$ls180.v:6534$2266_Y end - attribute \src "ls180.v:6397.43-6397.151" - cell $and $and$ls180.v:6397$2135 + attribute \src "ls180.v:6534.43-6534.151" + cell $and $and$ls180.v:6534$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6397$2133_Y - connect \B $eq$ls180.v:6397$2134_Y - connect \Y $and$ls180.v:6397$2135_Y + connect \A $and$ls180.v:6534$2266_Y + connect \B $eq$ls180.v:6534$2267_Y + connect \Y $and$ls180.v:6534$2268_Y end - attribute \src "ls180.v:6398.44-6398.102" - cell $and $and$ls180.v:6398$2137 + attribute \src "ls180.v:6535.44-6535.102" + cell $and $and$ls180.v:6535$2270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6398$2136_Y - connect \Y $and$ls180.v:6398$2137_Y + connect \B $not$ls180.v:6535$2269_Y + connect \Y $and$ls180.v:6535$2270_Y end - attribute \src "ls180.v:6398.43-6398.154" - cell $and $and$ls180.v:6398$2139 + attribute \src "ls180.v:6535.43-6535.154" + cell $and $and$ls180.v:6535$2272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6398$2137_Y - connect \B $eq$ls180.v:6398$2138_Y - connect \Y $and$ls180.v:6398$2139_Y + connect \A $and$ls180.v:6535$2270_Y + connect \B $eq$ls180.v:6535$2271_Y + connect \Y $and$ls180.v:6535$2272_Y end - attribute \src "ls180.v:6417.30-6417.85" - cell $and $and$ls180.v:6417$2141 + attribute \src "ls180.v:6554.30-6554.85" + cell $and $and$ls180.v:6554$2274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245874,43 +247594,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6417$2141_Y + connect \Y $and$ls180.v:6554$2274_Y end - attribute \src "ls180.v:6417.29-6417.136" - cell $and $and$ls180.v:6417$2143 + attribute \src "ls180.v:6554.29-6554.136" + cell $and $and$ls180.v:6554$2276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6417$2141_Y - connect \B $eq$ls180.v:6417$2142_Y - connect \Y $and$ls180.v:6417$2143_Y + connect \A $and$ls180.v:6554$2274_Y + connect \B $eq$ls180.v:6554$2275_Y + connect \Y $and$ls180.v:6554$2276_Y end - attribute \src "ls180.v:6418.30-6418.88" - cell $and $and$ls180.v:6418$2145 + attribute \src "ls180.v:6555.30-6555.88" + cell $and $and$ls180.v:6555$2278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6418$2144_Y - connect \Y $and$ls180.v:6418$2145_Y + connect \B $not$ls180.v:6555$2277_Y + connect \Y $and$ls180.v:6555$2278_Y end - attribute \src "ls180.v:6418.29-6418.139" - cell $and $and$ls180.v:6418$2147 + attribute \src "ls180.v:6555.29-6555.139" + cell $and $and$ls180.v:6555$2280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6418$2145_Y - connect \B $eq$ls180.v:6418$2146_Y - connect \Y $and$ls180.v:6418$2147_Y + connect \A $and$ls180.v:6555$2278_Y + connect \B $eq$ls180.v:6555$2279_Y + connect \Y $and$ls180.v:6555$2280_Y end - attribute \src "ls180.v:6420.40-6420.95" - cell $and $and$ls180.v:6420$2148 + attribute \src "ls180.v:6557.40-6557.95" + cell $and $and$ls180.v:6557$2281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245918,43 +247638,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6420$2148_Y + connect \Y $and$ls180.v:6557$2281_Y end - attribute \src "ls180.v:6420.39-6420.146" - cell $and $and$ls180.v:6420$2150 + attribute \src "ls180.v:6557.39-6557.146" + cell $and $and$ls180.v:6557$2283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6420$2148_Y - connect \B $eq$ls180.v:6420$2149_Y - connect \Y $and$ls180.v:6420$2150_Y + connect \A $and$ls180.v:6557$2281_Y + connect \B $eq$ls180.v:6557$2282_Y + connect \Y $and$ls180.v:6557$2283_Y end - attribute \src "ls180.v:6421.40-6421.98" - cell $and $and$ls180.v:6421$2152 + attribute \src "ls180.v:6558.40-6558.98" + cell $and $and$ls180.v:6558$2285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6421$2151_Y - connect \Y $and$ls180.v:6421$2152_Y + connect \B $not$ls180.v:6558$2284_Y + connect \Y $and$ls180.v:6558$2285_Y end - attribute \src "ls180.v:6421.39-6421.149" - cell $and $and$ls180.v:6421$2154 + attribute \src "ls180.v:6558.39-6558.149" + cell $and $and$ls180.v:6558$2287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6421$2152_Y - connect \B $eq$ls180.v:6421$2153_Y - connect \Y $and$ls180.v:6421$2154_Y + connect \A $and$ls180.v:6558$2285_Y + connect \B $eq$ls180.v:6558$2286_Y + connect \Y $and$ls180.v:6558$2287_Y end - attribute \src "ls180.v:6423.41-6423.96" - cell $and $and$ls180.v:6423$2155 + attribute \src "ls180.v:6560.41-6560.96" + cell $and $and$ls180.v:6560$2288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245962,43 +247682,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6423$2155_Y + connect \Y $and$ls180.v:6560$2288_Y end - attribute \src "ls180.v:6423.40-6423.147" - cell $and $and$ls180.v:6423$2157 + attribute \src "ls180.v:6560.40-6560.147" + cell $and $and$ls180.v:6560$2290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6423$2155_Y - connect \B $eq$ls180.v:6423$2156_Y - connect \Y $and$ls180.v:6423$2157_Y + connect \A $and$ls180.v:6560$2288_Y + connect \B $eq$ls180.v:6560$2289_Y + connect \Y $and$ls180.v:6560$2290_Y end - attribute \src "ls180.v:6424.41-6424.99" - cell $and $and$ls180.v:6424$2159 + attribute \src "ls180.v:6561.41-6561.99" + cell $and $and$ls180.v:6561$2292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6424$2158_Y - connect \Y $and$ls180.v:6424$2159_Y + connect \B $not$ls180.v:6561$2291_Y + connect \Y $and$ls180.v:6561$2292_Y end - attribute \src "ls180.v:6424.40-6424.150" - cell $and $and$ls180.v:6424$2161 + attribute \src "ls180.v:6561.40-6561.150" + cell $and $and$ls180.v:6561$2294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6424$2159_Y - connect \B $eq$ls180.v:6424$2160_Y - connect \Y $and$ls180.v:6424$2161_Y + connect \A $and$ls180.v:6561$2292_Y + connect \B $eq$ls180.v:6561$2293_Y + connect \Y $and$ls180.v:6561$2294_Y end - attribute \src "ls180.v:6426.45-6426.100" - cell $and $and$ls180.v:6426$2162 + attribute \src "ls180.v:6563.45-6563.100" + cell $and $and$ls180.v:6563$2295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246006,43 +247726,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6426$2162_Y + connect \Y $and$ls180.v:6563$2295_Y end - attribute \src "ls180.v:6426.44-6426.151" - cell $and $and$ls180.v:6426$2164 + attribute \src "ls180.v:6563.44-6563.151" + cell $and $and$ls180.v:6563$2297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6426$2162_Y - connect \B $eq$ls180.v:6426$2163_Y - connect \Y $and$ls180.v:6426$2164_Y + connect \A $and$ls180.v:6563$2295_Y + connect \B $eq$ls180.v:6563$2296_Y + connect \Y $and$ls180.v:6563$2297_Y end - attribute \src "ls180.v:6427.45-6427.103" - cell $and $and$ls180.v:6427$2166 + attribute \src "ls180.v:6564.45-6564.103" + cell $and $and$ls180.v:6564$2299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6427$2165_Y - connect \Y $and$ls180.v:6427$2166_Y + connect \B $not$ls180.v:6564$2298_Y + connect \Y $and$ls180.v:6564$2299_Y end - attribute \src "ls180.v:6427.44-6427.154" - cell $and $and$ls180.v:6427$2168 + attribute \src "ls180.v:6564.44-6564.154" + cell $and $and$ls180.v:6564$2301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6427$2166_Y - connect \B $eq$ls180.v:6427$2167_Y - connect \Y $and$ls180.v:6427$2168_Y + connect \A $and$ls180.v:6564$2299_Y + connect \B $eq$ls180.v:6564$2300_Y + connect \Y $and$ls180.v:6564$2301_Y end - attribute \src "ls180.v:6429.46-6429.101" - cell $and $and$ls180.v:6429$2169 + attribute \src "ls180.v:6566.46-6566.101" + cell $and $and$ls180.v:6566$2302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246050,43 +247770,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6429$2169_Y + connect \Y $and$ls180.v:6566$2302_Y end - attribute \src "ls180.v:6429.45-6429.152" - cell $and $and$ls180.v:6429$2171 + attribute \src "ls180.v:6566.45-6566.152" + cell $and $and$ls180.v:6566$2304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6429$2169_Y - connect \B $eq$ls180.v:6429$2170_Y - connect \Y $and$ls180.v:6429$2171_Y + connect \A $and$ls180.v:6566$2302_Y + connect \B $eq$ls180.v:6566$2303_Y + connect \Y $and$ls180.v:6566$2304_Y end - attribute \src "ls180.v:6430.46-6430.104" - cell $and $and$ls180.v:6430$2173 + attribute \src "ls180.v:6567.46-6567.104" + cell $and $and$ls180.v:6567$2306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6430$2172_Y - connect \Y $and$ls180.v:6430$2173_Y + connect \B $not$ls180.v:6567$2305_Y + connect \Y $and$ls180.v:6567$2306_Y end - attribute \src "ls180.v:6430.45-6430.155" - cell $and $and$ls180.v:6430$2175 + attribute \src "ls180.v:6567.45-6567.155" + cell $and $and$ls180.v:6567$2308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6430$2173_Y - connect \B $eq$ls180.v:6430$2174_Y - connect \Y $and$ls180.v:6430$2175_Y + connect \A $and$ls180.v:6567$2306_Y + connect \B $eq$ls180.v:6567$2307_Y + connect \Y $and$ls180.v:6567$2308_Y end - attribute \src "ls180.v:6432.44-6432.99" - cell $and $and$ls180.v:6432$2176 + attribute \src "ls180.v:6569.44-6569.99" + cell $and $and$ls180.v:6569$2309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246094,43 +247814,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6432$2176_Y + connect \Y $and$ls180.v:6569$2309_Y end - attribute \src "ls180.v:6432.43-6432.150" - cell $and $and$ls180.v:6432$2178 + attribute \src "ls180.v:6569.43-6569.150" + cell $and $and$ls180.v:6569$2311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6432$2176_Y - connect \B $eq$ls180.v:6432$2177_Y - connect \Y $and$ls180.v:6432$2178_Y + connect \A $and$ls180.v:6569$2309_Y + connect \B $eq$ls180.v:6569$2310_Y + connect \Y $and$ls180.v:6569$2311_Y end - attribute \src "ls180.v:6433.44-6433.102" - cell $and $and$ls180.v:6433$2180 + attribute \src "ls180.v:6570.44-6570.102" + cell $and $and$ls180.v:6570$2313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6433$2179_Y - connect \Y $and$ls180.v:6433$2180_Y + connect \B $not$ls180.v:6570$2312_Y + connect \Y $and$ls180.v:6570$2313_Y end - attribute \src "ls180.v:6433.43-6433.153" - cell $and $and$ls180.v:6433$2182 + attribute \src "ls180.v:6570.43-6570.153" + cell $and $and$ls180.v:6570$2315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6433$2180_Y - connect \B $eq$ls180.v:6433$2181_Y - connect \Y $and$ls180.v:6433$2182_Y + connect \A $and$ls180.v:6570$2313_Y + connect \B $eq$ls180.v:6570$2314_Y + connect \Y $and$ls180.v:6570$2315_Y end - attribute \src "ls180.v:6435.41-6435.96" - cell $and $and$ls180.v:6435$2183 + attribute \src "ls180.v:6572.41-6572.96" + cell $and $and$ls180.v:6572$2316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246138,43 +247858,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6435$2183_Y + connect \Y $and$ls180.v:6572$2316_Y end - attribute \src "ls180.v:6435.40-6435.147" - cell $and $and$ls180.v:6435$2185 + attribute \src "ls180.v:6572.40-6572.147" + cell $and $and$ls180.v:6572$2318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6435$2183_Y - connect \B $eq$ls180.v:6435$2184_Y - connect \Y $and$ls180.v:6435$2185_Y + connect \A $and$ls180.v:6572$2316_Y + connect \B $eq$ls180.v:6572$2317_Y + connect \Y $and$ls180.v:6572$2318_Y end - attribute \src "ls180.v:6436.41-6436.99" - cell $and $and$ls180.v:6436$2187 + attribute \src "ls180.v:6573.41-6573.99" + cell $and $and$ls180.v:6573$2320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6436$2186_Y - connect \Y $and$ls180.v:6436$2187_Y + connect \B $not$ls180.v:6573$2319_Y + connect \Y $and$ls180.v:6573$2320_Y end - attribute \src "ls180.v:6436.40-6436.150" - cell $and $and$ls180.v:6436$2189 + attribute \src "ls180.v:6573.40-6573.150" + cell $and $and$ls180.v:6573$2322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6436$2187_Y - connect \B $eq$ls180.v:6436$2188_Y - connect \Y $and$ls180.v:6436$2189_Y + connect \A $and$ls180.v:6573$2320_Y + connect \B $eq$ls180.v:6573$2321_Y + connect \Y $and$ls180.v:6573$2322_Y end - attribute \src "ls180.v:6438.40-6438.95" - cell $and $and$ls180.v:6438$2190 + attribute \src "ls180.v:6575.40-6575.95" + cell $and $and$ls180.v:6575$2323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246182,43 +247902,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6438$2190_Y + connect \Y $and$ls180.v:6575$2323_Y end - attribute \src "ls180.v:6438.39-6438.146" - cell $and $and$ls180.v:6438$2192 + attribute \src "ls180.v:6575.39-6575.146" + cell $and $and$ls180.v:6575$2325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6438$2190_Y - connect \B $eq$ls180.v:6438$2191_Y - connect \Y $and$ls180.v:6438$2192_Y + connect \A $and$ls180.v:6575$2323_Y + connect \B $eq$ls180.v:6575$2324_Y + connect \Y $and$ls180.v:6575$2325_Y end - attribute \src "ls180.v:6439.40-6439.98" - cell $and $and$ls180.v:6439$2194 + attribute \src "ls180.v:6576.40-6576.98" + cell $and $and$ls180.v:6576$2327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6439$2193_Y - connect \Y $and$ls180.v:6439$2194_Y + connect \B $not$ls180.v:6576$2326_Y + connect \Y $and$ls180.v:6576$2327_Y end - attribute \src "ls180.v:6439.39-6439.149" - cell $and $and$ls180.v:6439$2196 + attribute \src "ls180.v:6576.39-6576.149" + cell $and $and$ls180.v:6576$2329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6439$2194_Y - connect \B $eq$ls180.v:6439$2195_Y - connect \Y $and$ls180.v:6439$2196_Y + connect \A $and$ls180.v:6576$2327_Y + connect \B $eq$ls180.v:6576$2328_Y + connect \Y $and$ls180.v:6576$2329_Y end - attribute \src "ls180.v:6451.46-6451.101" - cell $and $and$ls180.v:6451$2198 + attribute \src "ls180.v:6588.46-6588.101" + cell $and $and$ls180.v:6588$2331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246226,43 +247946,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6451$2198_Y + connect \Y $and$ls180.v:6588$2331_Y end - attribute \src "ls180.v:6451.45-6451.152" - cell $and $and$ls180.v:6451$2200 + attribute \src "ls180.v:6588.45-6588.152" + cell $and $and$ls180.v:6588$2333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6451$2198_Y - connect \B $eq$ls180.v:6451$2199_Y - connect \Y $and$ls180.v:6451$2200_Y + connect \A $and$ls180.v:6588$2331_Y + connect \B $eq$ls180.v:6588$2332_Y + connect \Y $and$ls180.v:6588$2333_Y end - attribute \src "ls180.v:6452.46-6452.104" - cell $and $and$ls180.v:6452$2202 + attribute \src "ls180.v:6589.46-6589.104" + cell $and $and$ls180.v:6589$2335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6452$2201_Y - connect \Y $and$ls180.v:6452$2202_Y + connect \B $not$ls180.v:6589$2334_Y + connect \Y $and$ls180.v:6589$2335_Y end - attribute \src "ls180.v:6452.45-6452.155" - cell $and $and$ls180.v:6452$2204 + attribute \src "ls180.v:6589.45-6589.155" + cell $and $and$ls180.v:6589$2337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6452$2202_Y - connect \B $eq$ls180.v:6452$2203_Y - connect \Y $and$ls180.v:6452$2204_Y + connect \A $and$ls180.v:6589$2335_Y + connect \B $eq$ls180.v:6589$2336_Y + connect \Y $and$ls180.v:6589$2337_Y end - attribute \src "ls180.v:6454.46-6454.101" - cell $and $and$ls180.v:6454$2205 + attribute \src "ls180.v:6591.46-6591.101" + cell $and $and$ls180.v:6591$2338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246270,43 +247990,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6454$2205_Y + connect \Y $and$ls180.v:6591$2338_Y end - attribute \src "ls180.v:6454.45-6454.152" - cell $and $and$ls180.v:6454$2207 + attribute \src "ls180.v:6591.45-6591.152" + cell $and $and$ls180.v:6591$2340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6454$2205_Y - connect \B $eq$ls180.v:6454$2206_Y - connect \Y $and$ls180.v:6454$2207_Y + connect \A $and$ls180.v:6591$2338_Y + connect \B $eq$ls180.v:6591$2339_Y + connect \Y $and$ls180.v:6591$2340_Y end - attribute \src "ls180.v:6455.46-6455.104" - cell $and $and$ls180.v:6455$2209 + attribute \src "ls180.v:6592.46-6592.104" + cell $and $and$ls180.v:6592$2342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6455$2208_Y - connect \Y $and$ls180.v:6455$2209_Y + connect \B $not$ls180.v:6592$2341_Y + connect \Y $and$ls180.v:6592$2342_Y end - attribute \src "ls180.v:6455.45-6455.155" - cell $and $and$ls180.v:6455$2211 + attribute \src "ls180.v:6592.45-6592.155" + cell $and $and$ls180.v:6592$2344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6455$2209_Y - connect \B $eq$ls180.v:6455$2210_Y - connect \Y $and$ls180.v:6455$2211_Y + connect \A $and$ls180.v:6592$2342_Y + connect \B $eq$ls180.v:6592$2343_Y + connect \Y $and$ls180.v:6592$2344_Y end - attribute \src "ls180.v:6457.46-6457.101" - cell $and $and$ls180.v:6457$2212 + attribute \src "ls180.v:6594.46-6594.101" + cell $and $and$ls180.v:6594$2345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246314,43 +248034,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6457$2212_Y + connect \Y $and$ls180.v:6594$2345_Y end - attribute \src "ls180.v:6457.45-6457.152" - cell $and $and$ls180.v:6457$2214 + attribute \src "ls180.v:6594.45-6594.152" + cell $and $and$ls180.v:6594$2347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6457$2212_Y - connect \B $eq$ls180.v:6457$2213_Y - connect \Y $and$ls180.v:6457$2214_Y + connect \A $and$ls180.v:6594$2345_Y + connect \B $eq$ls180.v:6594$2346_Y + connect \Y $and$ls180.v:6594$2347_Y end - attribute \src "ls180.v:6458.46-6458.104" - cell $and $and$ls180.v:6458$2216 + attribute \src "ls180.v:6595.46-6595.104" + cell $and $and$ls180.v:6595$2349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6458$2215_Y - connect \Y $and$ls180.v:6458$2216_Y + connect \B $not$ls180.v:6595$2348_Y + connect \Y $and$ls180.v:6595$2349_Y end - attribute \src "ls180.v:6458.45-6458.155" - cell $and $and$ls180.v:6458$2218 + attribute \src "ls180.v:6595.45-6595.155" + cell $and $and$ls180.v:6595$2351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6458$2216_Y - connect \B $eq$ls180.v:6458$2217_Y - connect \Y $and$ls180.v:6458$2218_Y + connect \A $and$ls180.v:6595$2349_Y + connect \B $eq$ls180.v:6595$2350_Y + connect \Y $and$ls180.v:6595$2351_Y end - attribute \src "ls180.v:6460.46-6460.101" - cell $and $and$ls180.v:6460$2219 + attribute \src "ls180.v:6597.46-6597.101" + cell $and $and$ls180.v:6597$2352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246358,263 +248078,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6460$2219_Y + connect \Y $and$ls180.v:6597$2352_Y end - attribute \src "ls180.v:6460.45-6460.152" - cell $and $and$ls180.v:6460$2221 + attribute \src "ls180.v:6597.45-6597.152" + cell $and $and$ls180.v:6597$2354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6460$2219_Y - connect \B $eq$ls180.v:6460$2220_Y - connect \Y $and$ls180.v:6460$2221_Y + connect \A $and$ls180.v:6597$2352_Y + connect \B $eq$ls180.v:6597$2353_Y + connect \Y $and$ls180.v:6597$2354_Y end - attribute \src "ls180.v:6461.46-6461.104" - cell $and $and$ls180.v:6461$2223 + attribute \src "ls180.v:6598.46-6598.104" + cell $and $and$ls180.v:6598$2356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6461$2222_Y - connect \Y $and$ls180.v:6461$2223_Y + connect \B $not$ls180.v:6598$2355_Y + connect \Y $and$ls180.v:6598$2356_Y end - attribute \src "ls180.v:6461.45-6461.155" - cell $and $and$ls180.v:6461$2225 + attribute \src "ls180.v:6598.45-6598.155" + cell $and $and$ls180.v:6598$2358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6461$2223_Y - connect \B $eq$ls180.v:6461$2224_Y - connect \Y $and$ls180.v:6461$2225_Y + connect \A $and$ls180.v:6598$2356_Y + connect \B $eq$ls180.v:6598$2357_Y + connect \Y $and$ls180.v:6598$2358_Y end - attribute \src "ls180.v:6842.109-6842.178" - cell $and $and$ls180.v:6842$2263 + attribute \src "ls180.v:6979.109-6979.178" + cell $and $and$ls180.v:6979$2396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6842$2262_Y - connect \Y $and$ls180.v:6842$2263_Y + connect \B $eq$ls180.v:6979$2395_Y + connect \Y $and$ls180.v:6979$2396_Y end - attribute \src "ls180.v:6842.184-6842.253" - cell $and $and$ls180.v:6842$2266 + attribute \src "ls180.v:6979.184-6979.253" + cell $and $and$ls180.v:6979$2399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6842$2265_Y - connect \Y $and$ls180.v:6842$2266_Y + connect \B $eq$ls180.v:6979$2398_Y + connect \Y $and$ls180.v:6979$2399_Y end - attribute \src "ls180.v:6842.259-6842.328" - cell $and $and$ls180.v:6842$2269 + attribute \src "ls180.v:6979.259-6979.328" + cell $and $and$ls180.v:6979$2402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6842$2268_Y - connect \Y $and$ls180.v:6842$2269_Y + connect \B $eq$ls180.v:6979$2401_Y + connect \Y $and$ls180.v:6979$2402_Y end - attribute \src "ls180.v:6842.40-6842.331" - cell $and $and$ls180.v:6842$2272 + attribute \src "ls180.v:6979.40-6979.331" + cell $and $and$ls180.v:6979$2405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6842$2261_Y - connect \B $not$ls180.v:6842$2271_Y - connect \Y $and$ls180.v:6842$2272_Y + connect \A $eq$ls180.v:6979$2394_Y + connect \B $not$ls180.v:6979$2404_Y + connect \Y $and$ls180.v:6979$2405_Y end - attribute \src "ls180.v:6842.39-6842.354" - cell $and $and$ls180.v:6842$2273 + attribute \src "ls180.v:6979.39-6979.354" + cell $and $and$ls180.v:6979$2406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6842$2272_Y + connect \A $and$ls180.v:6979$2405_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6842$2273_Y + connect \Y $and$ls180.v:6979$2406_Y end - attribute \src "ls180.v:6866.109-6866.178" - cell $and $and$ls180.v:6866$2279 + attribute \src "ls180.v:7003.109-7003.178" + cell $and $and$ls180.v:7003$2412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6866$2278_Y - connect \Y $and$ls180.v:6866$2279_Y + connect \B $eq$ls180.v:7003$2411_Y + connect \Y $and$ls180.v:7003$2412_Y end - attribute \src "ls180.v:6866.184-6866.253" - cell $and $and$ls180.v:6866$2282 + attribute \src "ls180.v:7003.184-7003.253" + cell $and $and$ls180.v:7003$2415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6866$2281_Y - connect \Y $and$ls180.v:6866$2282_Y + connect \B $eq$ls180.v:7003$2414_Y + connect \Y $and$ls180.v:7003$2415_Y end - attribute \src "ls180.v:6866.259-6866.328" - cell $and $and$ls180.v:6866$2285 + attribute \src "ls180.v:7003.259-7003.328" + cell $and $and$ls180.v:7003$2418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6866$2284_Y - connect \Y $and$ls180.v:6866$2285_Y + connect \B $eq$ls180.v:7003$2417_Y + connect \Y $and$ls180.v:7003$2418_Y end - attribute \src "ls180.v:6866.40-6866.331" - cell $and $and$ls180.v:6866$2288 + attribute \src "ls180.v:7003.40-7003.331" + cell $and $and$ls180.v:7003$2421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6866$2277_Y - connect \B $not$ls180.v:6866$2287_Y - connect \Y $and$ls180.v:6866$2288_Y + connect \A $eq$ls180.v:7003$2410_Y + connect \B $not$ls180.v:7003$2420_Y + connect \Y $and$ls180.v:7003$2421_Y end - attribute \src "ls180.v:6866.39-6866.354" - cell $and $and$ls180.v:6866$2289 + attribute \src "ls180.v:7003.39-7003.354" + cell $and $and$ls180.v:7003$2422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6866$2288_Y + connect \A $and$ls180.v:7003$2421_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6866$2289_Y + connect \Y $and$ls180.v:7003$2422_Y end - attribute \src "ls180.v:6890.109-6890.178" - cell $and $and$ls180.v:6890$2295 + attribute \src "ls180.v:7027.109-7027.178" + cell $and $and$ls180.v:7027$2428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6890$2294_Y - connect \Y $and$ls180.v:6890$2295_Y + connect \B $eq$ls180.v:7027$2427_Y + connect \Y $and$ls180.v:7027$2428_Y end - attribute \src "ls180.v:6890.184-6890.253" - cell $and $and$ls180.v:6890$2298 + attribute \src "ls180.v:7027.184-7027.253" + cell $and $and$ls180.v:7027$2431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6890$2297_Y - connect \Y $and$ls180.v:6890$2298_Y + connect \B $eq$ls180.v:7027$2430_Y + connect \Y $and$ls180.v:7027$2431_Y end - attribute \src "ls180.v:6890.259-6890.328" - cell $and $and$ls180.v:6890$2301 + attribute \src "ls180.v:7027.259-7027.328" + cell $and $and$ls180.v:7027$2434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6890$2300_Y - connect \Y $and$ls180.v:6890$2301_Y + connect \B $eq$ls180.v:7027$2433_Y + connect \Y $and$ls180.v:7027$2434_Y end - attribute \src "ls180.v:6890.40-6890.331" - cell $and $and$ls180.v:6890$2304 + attribute \src "ls180.v:7027.40-7027.331" + cell $and $and$ls180.v:7027$2437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6890$2293_Y - connect \B $not$ls180.v:6890$2303_Y - connect \Y $and$ls180.v:6890$2304_Y + connect \A $eq$ls180.v:7027$2426_Y + connect \B $not$ls180.v:7027$2436_Y + connect \Y $and$ls180.v:7027$2437_Y end - attribute \src "ls180.v:6890.39-6890.354" - cell $and $and$ls180.v:6890$2305 + attribute \src "ls180.v:7027.39-7027.354" + cell $and $and$ls180.v:7027$2438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6890$2304_Y + connect \A $and$ls180.v:7027$2437_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6890$2305_Y + connect \Y $and$ls180.v:7027$2438_Y end - attribute \src "ls180.v:6914.109-6914.178" - cell $and $and$ls180.v:6914$2311 + attribute \src "ls180.v:7051.109-7051.178" + cell $and $and$ls180.v:7051$2444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6914$2310_Y - connect \Y $and$ls180.v:6914$2311_Y + connect \B $eq$ls180.v:7051$2443_Y + connect \Y $and$ls180.v:7051$2444_Y end - attribute \src "ls180.v:6914.184-6914.253" - cell $and $and$ls180.v:6914$2314 + attribute \src "ls180.v:7051.184-7051.253" + cell $and $and$ls180.v:7051$2447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6914$2313_Y - connect \Y $and$ls180.v:6914$2314_Y + connect \B $eq$ls180.v:7051$2446_Y + connect \Y $and$ls180.v:7051$2447_Y end - attribute \src "ls180.v:6914.259-6914.328" - cell $and $and$ls180.v:6914$2317 + attribute \src "ls180.v:7051.259-7051.328" + cell $and $and$ls180.v:7051$2450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6914$2316_Y - connect \Y $and$ls180.v:6914$2317_Y + connect \B $eq$ls180.v:7051$2449_Y + connect \Y $and$ls180.v:7051$2450_Y end - attribute \src "ls180.v:6914.40-6914.331" - cell $and $and$ls180.v:6914$2320 + attribute \src "ls180.v:7051.40-7051.331" + cell $and $and$ls180.v:7051$2453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6914$2309_Y - connect \B $not$ls180.v:6914$2319_Y - connect \Y $and$ls180.v:6914$2320_Y + connect \A $eq$ls180.v:7051$2442_Y + connect \B $not$ls180.v:7051$2452_Y + connect \Y $and$ls180.v:7051$2453_Y end - attribute \src "ls180.v:6914.39-6914.354" - cell $and $and$ls180.v:6914$2321 + attribute \src "ls180.v:7051.39-7051.354" + cell $and $and$ls180.v:7051$2454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6914$2320_Y + connect \A $and$ls180.v:7051$2453_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6914$2321_Y + connect \Y $and$ls180.v:7051$2454_Y end - attribute \src "ls180.v:7119.39-7119.104" - cell $and $and$ls180.v:7119$2333 + attribute \src "ls180.v:7256.39-7256.104" + cell $and $and$ls180.v:7256$2466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246622,21 +248342,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7119$2333_Y + connect \Y $and$ls180.v:7256$2466_Y end - attribute \src "ls180.v:7119.38-7119.145" - cell $and $and$ls180.v:7119$2334 + attribute \src "ls180.v:7256.38-7256.145" + cell $and $and$ls180.v:7256$2467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7119$2333_Y + connect \A $and$ls180.v:7256$2466_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7119$2334_Y + connect \Y $and$ls180.v:7256$2467_Y end - attribute \src "ls180.v:7122.39-7122.104" - cell $and $and$ls180.v:7122$2335 + attribute \src "ls180.v:7259.39-7259.104" + cell $and $and$ls180.v:7259$2468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246644,21 +248364,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7122$2335_Y + connect \Y $and$ls180.v:7259$2468_Y end - attribute \src "ls180.v:7122.38-7122.145" - cell $and $and$ls180.v:7122$2336 + attribute \src "ls180.v:7259.38-7259.145" + cell $and $and$ls180.v:7259$2469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7122$2335_Y + connect \A $and$ls180.v:7259$2468_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7122$2336_Y + connect \Y $and$ls180.v:7259$2469_Y end - attribute \src "ls180.v:7125.39-7125.82" - cell $and $and$ls180.v:7125$2337 + attribute \src "ls180.v:7262.39-7262.82" + cell $and $and$ls180.v:7262$2470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246666,21 +248386,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7125$2337_Y + connect \Y $and$ls180.v:7262$2470_Y end - attribute \src "ls180.v:7125.38-7125.112" - cell $and $and$ls180.v:7125$2338 + attribute \src "ls180.v:7262.38-7262.112" + cell $and $and$ls180.v:7262$2471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7125$2337_Y + connect \A $and$ls180.v:7262$2470_Y connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7125$2338_Y + connect \Y $and$ls180.v:7262$2471_Y end - attribute \src "ls180.v:7136.39-7136.104" - cell $and $and$ls180.v:7136$2340 + attribute \src "ls180.v:7273.39-7273.104" + cell $and $and$ls180.v:7273$2473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246688,21 +248408,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7136$2340_Y + connect \Y $and$ls180.v:7273$2473_Y end - attribute \src "ls180.v:7136.38-7136.145" - cell $and $and$ls180.v:7136$2341 + attribute \src "ls180.v:7273.38-7273.145" + cell $and $and$ls180.v:7273$2474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7136$2340_Y + connect \A $and$ls180.v:7273$2473_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7136$2341_Y + connect \Y $and$ls180.v:7273$2474_Y end - attribute \src "ls180.v:7139.39-7139.104" - cell $and $and$ls180.v:7139$2342 + attribute \src "ls180.v:7276.39-7276.104" + cell $and $and$ls180.v:7276$2475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246710,21 +248430,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7139$2342_Y + connect \Y $and$ls180.v:7276$2475_Y end - attribute \src "ls180.v:7139.38-7139.145" - cell $and $and$ls180.v:7139$2343 + attribute \src "ls180.v:7276.38-7276.145" + cell $and $and$ls180.v:7276$2476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7139$2342_Y + connect \A $and$ls180.v:7276$2475_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7139$2343_Y + connect \Y $and$ls180.v:7276$2476_Y end - attribute \src "ls180.v:7142.39-7142.82" - cell $and $and$ls180.v:7142$2344 + attribute \src "ls180.v:7279.39-7279.82" + cell $and $and$ls180.v:7279$2477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246732,21 +248452,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7142$2344_Y + connect \Y $and$ls180.v:7279$2477_Y end - attribute \src "ls180.v:7142.38-7142.112" - cell $and $and$ls180.v:7142$2345 + attribute \src "ls180.v:7279.38-7279.112" + cell $and $and$ls180.v:7279$2478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7142$2344_Y + connect \A $and$ls180.v:7279$2477_Y connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7142$2345_Y + connect \Y $and$ls180.v:7279$2478_Y end - attribute \src "ls180.v:7153.39-7153.104" - cell $and $and$ls180.v:7153$2347 + attribute \src "ls180.v:7290.39-7290.104" + cell $and $and$ls180.v:7290$2480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246754,21 +248474,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7153$2347_Y + connect \Y $and$ls180.v:7290$2480_Y end - attribute \src "ls180.v:7153.38-7153.144" - cell $and $and$ls180.v:7153$2348 + attribute \src "ls180.v:7290.38-7290.144" + cell $and $and$ls180.v:7290$2481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7153$2347_Y + connect \A $and$ls180.v:7290$2480_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7153$2348_Y + connect \Y $and$ls180.v:7290$2481_Y end - attribute \src "ls180.v:7156.39-7156.104" - cell $and $and$ls180.v:7156$2349 + attribute \src "ls180.v:7293.39-7293.104" + cell $and $and$ls180.v:7293$2482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246776,21 +248496,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7156$2349_Y + connect \Y $and$ls180.v:7293$2482_Y end - attribute \src "ls180.v:7156.38-7156.144" - cell $and $and$ls180.v:7156$2350 + attribute \src "ls180.v:7293.38-7293.144" + cell $and $and$ls180.v:7293$2483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7156$2349_Y + connect \A $and$ls180.v:7293$2482_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7156$2350_Y + connect \Y $and$ls180.v:7293$2483_Y end - attribute \src "ls180.v:7159.39-7159.82" - cell $and $and$ls180.v:7159$2351 + attribute \src "ls180.v:7296.39-7296.82" + cell $and $and$ls180.v:7296$2484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246798,21 +248518,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7159$2351_Y + connect \Y $and$ls180.v:7296$2484_Y end - attribute \src "ls180.v:7159.38-7159.111" - cell $and $and$ls180.v:7159$2352 + attribute \src "ls180.v:7296.38-7296.111" + cell $and $and$ls180.v:7296$2485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7159$2351_Y + connect \A $and$ls180.v:7296$2484_Y connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7159$2352_Y + connect \Y $and$ls180.v:7296$2485_Y end - attribute \src "ls180.v:7170.39-7170.104" - cell $and $and$ls180.v:7170$2354 + attribute \src "ls180.v:7307.39-7307.104" + cell $and $and$ls180.v:7307$2487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246820,21 +248540,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7170$2354_Y + connect \Y $and$ls180.v:7307$2487_Y end - attribute \src "ls180.v:7170.38-7170.149" - cell $and $and$ls180.v:7170$2355 + attribute \src "ls180.v:7307.38-7307.149" + cell $and $and$ls180.v:7307$2488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7170$2354_Y + connect \A $and$ls180.v:7307$2487_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7170$2355_Y + connect \Y $and$ls180.v:7307$2488_Y end - attribute \src "ls180.v:7173.39-7173.104" - cell $and $and$ls180.v:7173$2356 + attribute \src "ls180.v:7310.39-7310.104" + cell $and $and$ls180.v:7310$2489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246842,21 +248562,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7173$2356_Y + connect \Y $and$ls180.v:7310$2489_Y end - attribute \src "ls180.v:7173.38-7173.149" - cell $and $and$ls180.v:7173$2357 + attribute \src "ls180.v:7310.38-7310.149" + cell $and $and$ls180.v:7310$2490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7173$2356_Y + connect \A $and$ls180.v:7310$2489_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7173$2357_Y + connect \Y $and$ls180.v:7310$2490_Y end - attribute \src "ls180.v:7176.39-7176.82" - cell $and $and$ls180.v:7176$2358 + attribute \src "ls180.v:7313.39-7313.82" + cell $and $and$ls180.v:7313$2491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246864,21 +248584,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7176$2358_Y + connect \Y $and$ls180.v:7313$2491_Y end - attribute \src "ls180.v:7176.38-7176.116" - cell $and $and$ls180.v:7176$2359 + attribute \src "ls180.v:7313.38-7313.116" + cell $and $and$ls180.v:7313$2492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7176$2358_Y + connect \A $and$ls180.v:7313$2491_Y connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7176$2359_Y + connect \Y $and$ls180.v:7313$2492_Y end - attribute \src "ls180.v:7187.39-7187.104" - cell $and $and$ls180.v:7187$2361 + attribute \src "ls180.v:7324.39-7324.104" + cell $and $and$ls180.v:7324$2494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246886,21 +248606,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7187$2361_Y + connect \Y $and$ls180.v:7324$2494_Y end - attribute \src "ls180.v:7187.38-7187.150" - cell $and $and$ls180.v:7187$2362 + attribute \src "ls180.v:7324.38-7324.150" + cell $and $and$ls180.v:7324$2495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7187$2361_Y + connect \A $and$ls180.v:7324$2494_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7187$2362_Y + connect \Y $and$ls180.v:7324$2495_Y end - attribute \src "ls180.v:7190.39-7190.104" - cell $and $and$ls180.v:7190$2363 + attribute \src "ls180.v:7327.39-7327.104" + cell $and $and$ls180.v:7327$2496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246908,21 +248628,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7190$2363_Y + connect \Y $and$ls180.v:7327$2496_Y end - attribute \src "ls180.v:7190.38-7190.150" - cell $and $and$ls180.v:7190$2364 + attribute \src "ls180.v:7327.38-7327.150" + cell $and $and$ls180.v:7327$2497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7190$2363_Y + connect \A $and$ls180.v:7327$2496_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7190$2364_Y + connect \Y $and$ls180.v:7327$2497_Y end - attribute \src "ls180.v:7193.39-7193.82" - cell $and $and$ls180.v:7193$2365 + attribute \src "ls180.v:7330.39-7330.82" + cell $and $and$ls180.v:7330$2498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246930,32 +248650,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7193$2365_Y + connect \Y $and$ls180.v:7330$2498_Y end - attribute \src "ls180.v:7193.38-7193.117" - cell $and $and$ls180.v:7193$2366 + attribute \src "ls180.v:7330.38-7330.117" + cell $and $and$ls180.v:7330$2499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7193$2365_Y + connect \A $and$ls180.v:7330$2498_Y connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7193$2366_Y + connect \Y $and$ls180.v:7330$2499_Y end - attribute \src "ls180.v:7412.17-7412.67" - cell $and $and$ls180.v:7412$2373 + attribute \src "ls180.v:7549.17-7549.67" + cell $and $and$ls180.v:7549$2506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7412$2372_Y + connect \A $not$ls180.v:7549$2505_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7412$2373_Y + connect \Y $and$ls180.v:7549$2506_Y end - attribute \src "ls180.v:7491.8-7491.67" - cell $and $and$ls180.v:7491$2404 + attribute \src "ls180.v:7628.8-7628.67" + cell $and $and$ls180.v:7628$2537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246963,54 +248683,120 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7491$2404_Y + connect \Y $and$ls180.v:7628$2537_Y end - attribute \src "ls180.v:7491.7-7491.102" - cell $and $and$ls180.v:7491$2406 + attribute \src "ls180.v:7628.7-7628.102" + cell $and $and$ls180.v:7628$2539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7491$2404_Y - connect \B $not$ls180.v:7491$2405_Y - connect \Y $and$ls180.v:7491$2406_Y + connect \A $and$ls180.v:7628$2537_Y + connect \B $not$ls180.v:7628$2538_Y + connect \Y $and$ls180.v:7628$2539_Y end - attribute \src "ls180.v:7510.7-7510.75" - cell $and $and$ls180.v:7510$2410 + attribute \src "ls180.v:7647.7-7647.75" + cell $and $and$ls180.v:7647$2543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7510$2409_Y + connect \A $not$ls180.v:7647$2542_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7510$2410_Y + connect \Y $and$ls180.v:7647$2543_Y + end + attribute \src "ls180.v:7651.8-7651.65" + cell $and $and$ls180.v:7651$2544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:7651$2544_Y + end + attribute \src "ls180.v:7651.7-7651.99" + cell $and $and$ls180.v:7651$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7651$2544_Y + connect \B $not$ls180.v:7651$2545_Y + connect \Y $and$ls180.v:7651$2546_Y + end + attribute \src "ls180.v:7655.8-7655.65" + cell $and $and$ls180.v:7655$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:7655$2547_Y + end + attribute \src "ls180.v:7655.7-7655.99" + cell $and $and$ls180.v:7655$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7655$2547_Y + connect \B $not$ls180.v:7655$2548_Y + connect \Y $and$ls180.v:7655$2549_Y + end + attribute \src "ls180.v:7659.8-7659.65" + cell $and $and$ls180.v:7659$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:7659$2550_Y end - attribute \src "ls180.v:7518.7-7518.56" - cell $and $and$ls180.v:7518$2412 + attribute \src "ls180.v:7659.7-7659.99" + cell $and $and$ls180.v:7659$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7659$2550_Y + connect \B $not$ls180.v:7659$2551_Y + connect \Y $and$ls180.v:7659$2552_Y + end + attribute \src "ls180.v:7667.7-7667.56" + cell $and $and$ls180.v:7667$2554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7518$2411_Y - connect \Y $and$ls180.v:7518$2412_Y + connect \B $not$ls180.v:7667$2553_Y + connect \Y $and$ls180.v:7667$2554_Y end - attribute \src "ls180.v:7546.7-7546.75" - cell $and $and$ls180.v:7546$2419 + attribute \src "ls180.v:7695.7-7695.75" + cell $and $and$ls180.v:7695$2561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7546$2418_Y - connect \Y $and$ls180.v:7546$2419_Y + connect \B $eq$ls180.v:7695$2560_Y + connect \Y $and$ls180.v:7695$2561_Y end - attribute \src "ls180.v:7588.8-7588.131" - cell $and $and$ls180.v:7588$2425 + attribute \src "ls180.v:7737.8-7737.131" + cell $and $and$ls180.v:7737$2567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247018,21 +248804,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7588$2425_Y + connect \Y $and$ls180.v:7737$2567_Y end - attribute \src "ls180.v:7588.7-7588.190" - cell $and $and$ls180.v:7588$2427 + attribute \src "ls180.v:7737.7-7737.190" + cell $and $and$ls180.v:7737$2569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7588$2425_Y - connect \B $not$ls180.v:7588$2426_Y - connect \Y $and$ls180.v:7588$2427_Y + connect \A $and$ls180.v:7737$2567_Y + connect \B $not$ls180.v:7737$2568_Y + connect \Y $and$ls180.v:7737$2569_Y end - attribute \src "ls180.v:7594.8-7594.131" - cell $and $and$ls180.v:7594$2430 + attribute \src "ls180.v:7743.8-7743.131" + cell $and $and$ls180.v:7743$2572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247040,21 +248826,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7594$2430_Y + connect \Y $and$ls180.v:7743$2572_Y end - attribute \src "ls180.v:7594.7-7594.190" - cell $and $and$ls180.v:7594$2432 + attribute \src "ls180.v:7743.7-7743.190" + cell $and $and$ls180.v:7743$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7594$2430_Y - connect \B $not$ls180.v:7594$2431_Y - connect \Y $and$ls180.v:7594$2432_Y + connect \A $and$ls180.v:7743$2572_Y + connect \B $not$ls180.v:7743$2573_Y + connect \Y $and$ls180.v:7743$2574_Y end - attribute \src "ls180.v:7634.8-7634.131" - cell $and $and$ls180.v:7634$2441 + attribute \src "ls180.v:7783.8-7783.131" + cell $and $and$ls180.v:7783$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247062,21 +248848,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7634$2441_Y + connect \Y $and$ls180.v:7783$2583_Y end - attribute \src "ls180.v:7634.7-7634.190" - cell $and $and$ls180.v:7634$2443 + attribute \src "ls180.v:7783.7-7783.190" + cell $and $and$ls180.v:7783$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7634$2441_Y - connect \B $not$ls180.v:7634$2442_Y - connect \Y $and$ls180.v:7634$2443_Y + connect \A $and$ls180.v:7783$2583_Y + connect \B $not$ls180.v:7783$2584_Y + connect \Y $and$ls180.v:7783$2585_Y end - attribute \src "ls180.v:7640.8-7640.131" - cell $and $and$ls180.v:7640$2446 + attribute \src "ls180.v:7789.8-7789.131" + cell $and $and$ls180.v:7789$2588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247084,21 +248870,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7640$2446_Y + connect \Y $and$ls180.v:7789$2588_Y end - attribute \src "ls180.v:7640.7-7640.190" - cell $and $and$ls180.v:7640$2448 + attribute \src "ls180.v:7789.7-7789.190" + cell $and $and$ls180.v:7789$2590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7640$2446_Y - connect \B $not$ls180.v:7640$2447_Y - connect \Y $and$ls180.v:7640$2448_Y + connect \A $and$ls180.v:7789$2588_Y + connect \B $not$ls180.v:7789$2589_Y + connect \Y $and$ls180.v:7789$2590_Y end - attribute \src "ls180.v:7680.8-7680.131" - cell $and $and$ls180.v:7680$2457 + attribute \src "ls180.v:7829.8-7829.131" + cell $and $and$ls180.v:7829$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247106,21 +248892,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7680$2457_Y + connect \Y $and$ls180.v:7829$2599_Y end - attribute \src "ls180.v:7680.7-7680.190" - cell $and $and$ls180.v:7680$2459 + attribute \src "ls180.v:7829.7-7829.190" + cell $and $and$ls180.v:7829$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7680$2457_Y - connect \B $not$ls180.v:7680$2458_Y - connect \Y $and$ls180.v:7680$2459_Y + connect \A $and$ls180.v:7829$2599_Y + connect \B $not$ls180.v:7829$2600_Y + connect \Y $and$ls180.v:7829$2601_Y end - attribute \src "ls180.v:7686.8-7686.131" - cell $and $and$ls180.v:7686$2462 + attribute \src "ls180.v:7835.8-7835.131" + cell $and $and$ls180.v:7835$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247128,21 +248914,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7686$2462_Y + connect \Y $and$ls180.v:7835$2604_Y end - attribute \src "ls180.v:7686.7-7686.190" - cell $and $and$ls180.v:7686$2464 + attribute \src "ls180.v:7835.7-7835.190" + cell $and $and$ls180.v:7835$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7686$2462_Y - connect \B $not$ls180.v:7686$2463_Y - connect \Y $and$ls180.v:7686$2464_Y + connect \A $and$ls180.v:7835$2604_Y + connect \B $not$ls180.v:7835$2605_Y + connect \Y $and$ls180.v:7835$2606_Y end - attribute \src "ls180.v:7726.8-7726.131" - cell $and $and$ls180.v:7726$2473 + attribute \src "ls180.v:7875.8-7875.131" + cell $and $and$ls180.v:7875$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247150,21 +248936,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7726$2473_Y + connect \Y $and$ls180.v:7875$2615_Y end - attribute \src "ls180.v:7726.7-7726.190" - cell $and $and$ls180.v:7726$2475 + attribute \src "ls180.v:7875.7-7875.190" + cell $and $and$ls180.v:7875$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7726$2473_Y - connect \B $not$ls180.v:7726$2474_Y - connect \Y $and$ls180.v:7726$2475_Y + connect \A $and$ls180.v:7875$2615_Y + connect \B $not$ls180.v:7875$2616_Y + connect \Y $and$ls180.v:7875$2617_Y end - attribute \src "ls180.v:7732.8-7732.131" - cell $and $and$ls180.v:7732$2478 + attribute \src "ls180.v:7881.8-7881.131" + cell $and $and$ls180.v:7881$2620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247172,109 +248958,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7732$2478_Y + connect \Y $and$ls180.v:7881$2620_Y end - attribute \src "ls180.v:7732.7-7732.190" - cell $and $and$ls180.v:7732$2480 + attribute \src "ls180.v:7881.7-7881.190" + cell $and $and$ls180.v:7881$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7732$2478_Y - connect \B $not$ls180.v:7732$2479_Y - connect \Y $and$ls180.v:7732$2480_Y + connect \A $and$ls180.v:7881$2620_Y + connect \B $not$ls180.v:7881$2621_Y + connect \Y $and$ls180.v:7881$2622_Y end - attribute \src "ls180.v:7929.48-7929.124" - cell $and $and$ls180.v:7929$2505 + attribute \src "ls180.v:8078.48-8078.124" + cell $and $and$ls180.v:8078$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7929$2504_Y + connect \A $eq$ls180.v:8078$2646_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:7929$2505_Y + connect \Y $and$ls180.v:8078$2647_Y end - attribute \src "ls180.v:7929.130-7929.206" - cell $and $and$ls180.v:7929$2508 + attribute \src "ls180.v:8078.130-8078.206" + cell $and $and$ls180.v:8078$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7929$2507_Y + connect \A $eq$ls180.v:8078$2649_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:7929$2508_Y + connect \Y $and$ls180.v:8078$2650_Y end - attribute \src "ls180.v:7929.212-7929.288" - cell $and $and$ls180.v:7929$2511 + attribute \src "ls180.v:8078.212-8078.288" + cell $and $and$ls180.v:8078$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7929$2510_Y + connect \A $eq$ls180.v:8078$2652_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:7929$2511_Y + connect \Y $and$ls180.v:8078$2653_Y end - attribute \src "ls180.v:7929.294-7929.370" - cell $and $and$ls180.v:7929$2514 + attribute \src "ls180.v:8078.294-8078.370" + cell $and $and$ls180.v:8078$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7929$2513_Y + connect \A $eq$ls180.v:8078$2655_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:7929$2514_Y + connect \Y $and$ls180.v:8078$2656_Y end - attribute \src "ls180.v:7930.49-7930.125" - cell $and $and$ls180.v:7930$2517 + attribute \src "ls180.v:8079.49-8079.125" + cell $and $and$ls180.v:8079$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7930$2516_Y + connect \A $eq$ls180.v:8079$2658_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:7930$2517_Y + connect \Y $and$ls180.v:8079$2659_Y end - attribute \src "ls180.v:7930.131-7930.207" - cell $and $and$ls180.v:7930$2520 + attribute \src "ls180.v:8079.131-8079.207" + cell $and $and$ls180.v:8079$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7930$2519_Y + connect \A $eq$ls180.v:8079$2661_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:7930$2520_Y + connect \Y $and$ls180.v:8079$2662_Y end - attribute \src "ls180.v:7930.213-7930.289" - cell $and $and$ls180.v:7930$2523 + attribute \src "ls180.v:8079.213-8079.289" + cell $and $and$ls180.v:8079$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7930$2522_Y + connect \A $eq$ls180.v:8079$2664_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:7930$2523_Y + connect \Y $and$ls180.v:8079$2665_Y end - attribute \src "ls180.v:7930.295-7930.371" - cell $and $and$ls180.v:7930$2526 + attribute \src "ls180.v:8079.295-8079.371" + cell $and $and$ls180.v:8079$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7930$2525_Y + connect \A $eq$ls180.v:8079$2667_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:7930$2526_Y + connect \Y $and$ls180.v:8079$2668_Y end - attribute \src "ls180.v:7949.8-7949.49" - cell $and $and$ls180.v:7949$2529 + attribute \src "ls180.v:8098.8-8098.49" + cell $and $and$ls180.v:8098$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247282,10 +249068,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:7949$2529_Y + connect \Y $and$ls180.v:8098$2671_Y end - attribute \src "ls180.v:7952.8-7952.53" - cell $and $and$ls180.v:7952$2530 + attribute \src "ls180.v:8101.8-8101.53" + cell $and $and$ls180.v:8101$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247293,32 +249079,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:7952$2530_Y + connect \Y $and$ls180.v:8101$2672_Y end - attribute \src "ls180.v:7957.8-7957.59" - cell $and $and$ls180.v:7957$2532 + attribute \src "ls180.v:8106.8-8106.59" + cell $and $and$ls180.v:8106$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:7957$2531_Y - connect \Y $and$ls180.v:7957$2532_Y + connect \B $not$ls180.v:8106$2673_Y + connect \Y $and$ls180.v:8106$2674_Y end - attribute \src "ls180.v:7957.7-7957.90" - cell $and $and$ls180.v:7957$2534 + attribute \src "ls180.v:8106.7-8106.90" + cell $and $and$ls180.v:8106$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7957$2532_Y - connect \B $not$ls180.v:7957$2533_Y - connect \Y $and$ls180.v:7957$2534_Y + connect \A $and$ls180.v:8106$2674_Y + connect \B $not$ls180.v:8106$2675_Y + connect \Y $and$ls180.v:8106$2676_Y end - attribute \src "ls180.v:7963.8-7963.59" - cell $and $and$ls180.v:7963$2535 + attribute \src "ls180.v:8112.8-8112.59" + cell $and $and$ls180.v:8112$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247326,43 +249112,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_uart_clk_txen connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:7963$2535_Y + connect \Y $and$ls180.v:8112$2677_Y end - attribute \src "ls180.v:7987.8-7987.48" - cell $and $and$ls180.v:7987$2542 + attribute \src "ls180.v:8136.8-8136.48" + cell $and $and$ls180.v:8136$2684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7987$2541_Y + connect \A $not$ls180.v:8136$2683_Y connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:7987$2542_Y + connect \Y $and$ls180.v:8136$2684_Y end - attribute \src "ls180.v:8020.7-8020.57" - cell $and $and$ls180.v:8020$2548 + attribute \src "ls180.v:8169.7-8169.57" + cell $and $and$ls180.v:8169$2690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8020$2547_Y + connect \A $not$ls180.v:8169$2689_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8020$2548_Y + connect \Y $and$ls180.v:8169$2690_Y end - attribute \src "ls180.v:8027.7-8027.57" - cell $and $and$ls180.v:8027$2550 + attribute \src "ls180.v:8176.7-8176.57" + cell $and $and$ls180.v:8176$2692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8027$2549_Y + connect \A $not$ls180.v:8176$2691_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8027$2550_Y + connect \Y $and$ls180.v:8176$2692_Y end - attribute \src "ls180.v:8037.8-8037.75" - cell $and $and$ls180.v:8037$2551 + attribute \src "ls180.v:8186.8-8186.75" + cell $and $and$ls180.v:8186$2693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247370,21 +249156,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8037$2551_Y + connect \Y $and$ls180.v:8186$2693_Y end - attribute \src "ls180.v:8037.7-8037.107" - cell $and $and$ls180.v:8037$2553 + attribute \src "ls180.v:8186.7-8186.107" + cell $and $and$ls180.v:8186$2695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8037$2551_Y - connect \B $not$ls180.v:8037$2552_Y - connect \Y $and$ls180.v:8037$2553_Y + connect \A $and$ls180.v:8186$2693_Y + connect \B $not$ls180.v:8186$2694_Y + connect \Y $and$ls180.v:8186$2695_Y end - attribute \src "ls180.v:8043.8-8043.75" - cell $and $and$ls180.v:8043$2556 + attribute \src "ls180.v:8192.8-8192.75" + cell $and $and$ls180.v:8192$2698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247392,21 +249178,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8043$2556_Y + connect \Y $and$ls180.v:8192$2698_Y end - attribute \src "ls180.v:8043.7-8043.107" - cell $and $and$ls180.v:8043$2558 + attribute \src "ls180.v:8192.7-8192.107" + cell $and $and$ls180.v:8192$2700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8043$2556_Y - connect \B $not$ls180.v:8043$2557_Y - connect \Y $and$ls180.v:8043$2558_Y + connect \A $and$ls180.v:8192$2698_Y + connect \B $not$ls180.v:8192$2699_Y + connect \Y $and$ls180.v:8192$2700_Y end - attribute \src "ls180.v:8059.8-8059.75" - cell $and $and$ls180.v:8059$2562 + attribute \src "ls180.v:8208.8-8208.75" + cell $and $and$ls180.v:8208$2704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247414,21 +249200,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8059$2562_Y + connect \Y $and$ls180.v:8208$2704_Y end - attribute \src "ls180.v:8059.7-8059.107" - cell $and $and$ls180.v:8059$2564 + attribute \src "ls180.v:8208.7-8208.107" + cell $and $and$ls180.v:8208$2706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8059$2562_Y - connect \B $not$ls180.v:8059$2563_Y - connect \Y $and$ls180.v:8059$2564_Y + connect \A $and$ls180.v:8208$2704_Y + connect \B $not$ls180.v:8208$2705_Y + connect \Y $and$ls180.v:8208$2706_Y end - attribute \src "ls180.v:8065.8-8065.75" - cell $and $and$ls180.v:8065$2567 + attribute \src "ls180.v:8214.8-8214.75" + cell $and $and$ls180.v:8214$2709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247436,21 +249222,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8065$2567_Y + connect \Y $and$ls180.v:8214$2709_Y end - attribute \src "ls180.v:8065.7-8065.107" - cell $and $and$ls180.v:8065$2569 + attribute \src "ls180.v:8214.7-8214.107" + cell $and $and$ls180.v:8214$2711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8065$2567_Y - connect \B $not$ls180.v:8065$2568_Y - connect \Y $and$ls180.v:8065$2569_Y + connect \A $and$ls180.v:8214$2709_Y + connect \B $not$ls180.v:8214$2710_Y + connect \Y $and$ls180.v:8214$2711_Y end - attribute \src "ls180.v:8213.7-8213.96" - cell $and $and$ls180.v:8213$2597 + attribute \src "ls180.v:8362.7-8362.96" + cell $and $and$ls180.v:8362$2739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247458,10 +249244,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8213$2597_Y + connect \Y $and$ls180.v:8362$2739_Y end - attribute \src "ls180.v:8214.8-8214.93" - cell $and $and$ls180.v:8214$2598 + attribute \src "ls180.v:8363.8-8363.93" + cell $and $and$ls180.v:8363$2740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247469,10 +249255,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8214$2598_Y + connect \Y $and$ls180.v:8363$2740_Y end - attribute \src "ls180.v:8222.8-8222.93" - cell $and $and$ls180.v:8222$2599 + attribute \src "ls180.v:8371.8-8371.93" + cell $and $and$ls180.v:8371$2741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247480,10 +249266,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8222$2599_Y + connect \Y $and$ls180.v:8371$2741_Y end - attribute \src "ls180.v:8294.7-8294.98" - cell $and $and$ls180.v:8294$2609 + attribute \src "ls180.v:8443.7-8443.98" + cell $and $and$ls180.v:8443$2751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247491,10 +249277,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8294$2609_Y + connect \Y $and$ls180.v:8443$2751_Y end - attribute \src "ls180.v:8295.8-8295.95" - cell $and $and$ls180.v:8295$2610 + attribute \src "ls180.v:8444.8-8444.95" + cell $and $and$ls180.v:8444$2752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247502,10 +249288,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8295$2610_Y + connect \Y $and$ls180.v:8444$2752_Y end - attribute \src "ls180.v:8303.8-8303.95" - cell $and $and$ls180.v:8303$2611 + attribute \src "ls180.v:8452.8-8452.95" + cell $and $and$ls180.v:8452$2753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247513,10 +249299,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8303$2611_Y + connect \Y $and$ls180.v:8452$2753_Y end - attribute \src "ls180.v:8373.7-8373.100" - cell $and $and$ls180.v:8373$2621 + attribute \src "ls180.v:8522.7-8522.100" + cell $and $and$ls180.v:8522$2763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247524,10 +249310,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8373$2621_Y + connect \Y $and$ls180.v:8522$2763_Y end - attribute \src "ls180.v:8374.8-8374.97" - cell $and $and$ls180.v:8374$2622 + attribute \src "ls180.v:8523.8-8523.97" + cell $and $and$ls180.v:8523$2764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247535,10 +249321,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8374$2622_Y + connect \Y $and$ls180.v:8523$2764_Y end - attribute \src "ls180.v:8382.8-8382.97" - cell $and $and$ls180.v:8382$2623 + attribute \src "ls180.v:8531.8-8531.97" + cell $and $and$ls180.v:8531$2765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247546,10 +249332,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8382$2623_Y + connect \Y $and$ls180.v:8531$2765_Y end - attribute \src "ls180.v:8473.7-8473.82" - cell $and $and$ls180.v:8473$2629 + attribute \src "ls180.v:8622.7-8622.82" + cell $and $and$ls180.v:8622$2771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247557,10 +249343,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8473$2629_Y + connect \Y $and$ls180.v:8622$2771_Y end - attribute \src "ls180.v:8476.7-8476.82" - cell $and $and$ls180.v:8476$2630 + attribute \src "ls180.v:8625.7-8625.82" + cell $and $and$ls180.v:8625$2772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247568,10 +249354,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8476$2630_Y + connect \Y $and$ls180.v:8625$2772_Y end - attribute \src "ls180.v:8479.7-8479.82" - cell $and $and$ls180.v:8479$2631 + attribute \src "ls180.v:8628.7-8628.82" + cell $and $and$ls180.v:8628$2773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247579,10 +249365,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8479$2631_Y + connect \Y $and$ls180.v:8628$2773_Y end - attribute \src "ls180.v:8482.7-8482.82" - cell $and $and$ls180.v:8482$2632 + attribute \src "ls180.v:8631.7-8631.82" + cell $and $and$ls180.v:8631$2774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247590,10 +249376,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8482$2632_Y + connect \Y $and$ls180.v:8631$2774_Y end - attribute \src "ls180.v:8485.7-8485.82" - cell $and $and$ls180.v:8485$2633 + attribute \src "ls180.v:8634.7-8634.82" + cell $and $and$ls180.v:8634$2775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247601,10 +249387,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8485$2633_Y + connect \Y $and$ls180.v:8634$2775_Y end - attribute \src "ls180.v:8490.7-8490.82" - cell $and $and$ls180.v:8490$2634 + attribute \src "ls180.v:8639.7-8639.82" + cell $and $and$ls180.v:8639$2776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247612,10 +249398,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8490$2634_Y + connect \Y $and$ls180.v:8639$2776_Y end - attribute \src "ls180.v:8495.7-8495.82" - cell $and $and$ls180.v:8495$2635 + attribute \src "ls180.v:8644.7-8644.82" + cell $and $and$ls180.v:8644$2777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247623,10 +249409,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8495$2635_Y + connect \Y $and$ls180.v:8644$2777_Y end - attribute \src "ls180.v:8500.7-8500.82" - cell $and $and$ls180.v:8500$2636 + attribute \src "ls180.v:8649.7-8649.82" + cell $and $and$ls180.v:8649$2778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247634,10 +249420,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8500$2636_Y + connect \Y $and$ls180.v:8649$2778_Y end - attribute \src "ls180.v:8505.7-8505.82" - cell $and $and$ls180.v:8505$2637 + attribute \src "ls180.v:8654.7-8654.82" + cell $and $and$ls180.v:8654$2779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247645,10 +249431,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8505$2637_Y + connect \Y $and$ls180.v:8654$2779_Y end - attribute \src "ls180.v:8570.8-8570.83" - cell $and $and$ls180.v:8570$2640 + attribute \src "ls180.v:8719.8-8719.83" + cell $and $and$ls180.v:8719$2782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247656,21 +249442,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8570$2640_Y + connect \Y $and$ls180.v:8719$2782_Y end - attribute \src "ls180.v:8570.7-8570.119" - cell $and $and$ls180.v:8570$2642 + attribute \src "ls180.v:8719.7-8719.119" + cell $and $and$ls180.v:8719$2784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8570$2640_Y - connect \B $not$ls180.v:8570$2641_Y - connect \Y $and$ls180.v:8570$2642_Y + connect \A $and$ls180.v:8719$2782_Y + connect \B $not$ls180.v:8719$2783_Y + connect \Y $and$ls180.v:8719$2784_Y end - attribute \src "ls180.v:8576.8-8576.83" - cell $and $and$ls180.v:8576$2645 + attribute \src "ls180.v:8725.8-8725.83" + cell $and $and$ls180.v:8725$2787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247678,21 +249464,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8576$2645_Y + connect \Y $and$ls180.v:8725$2787_Y end - attribute \src "ls180.v:8576.7-8576.119" - cell $and $and$ls180.v:8576$2647 + attribute \src "ls180.v:8725.7-8725.119" + cell $and $and$ls180.v:8725$2789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8576$2645_Y - connect \B $not$ls180.v:8576$2646_Y - connect \Y $and$ls180.v:8576$2647_Y + connect \A $and$ls180.v:8725$2787_Y + connect \B $not$ls180.v:8725$2788_Y + connect \Y $and$ls180.v:8725$2789_Y end - attribute \src "ls180.v:8596.7-8596.88" - cell $and $and$ls180.v:8596$2654 + attribute \src "ls180.v:8745.7-8745.88" + cell $and $and$ls180.v:8745$2796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247700,10 +249486,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8596$2654_Y + connect \Y $and$ls180.v:8745$2796_Y end - attribute \src "ls180.v:8597.8-8597.85" - cell $and $and$ls180.v:8597$2655 + attribute \src "ls180.v:8746.8-8746.85" + cell $and $and$ls180.v:8746$2797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247711,10 +249497,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8597$2655_Y + connect \Y $and$ls180.v:8746$2797_Y end - attribute \src "ls180.v:8605.8-8605.85" - cell $and $and$ls180.v:8605$2656 + attribute \src "ls180.v:8754.8-8754.85" + cell $and $and$ls180.v:8754$2798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247722,10 +249508,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8605$2656_Y + connect \Y $and$ls180.v:8754$2798_Y end - attribute \src "ls180.v:8649.7-8649.88" - cell $and $and$ls180.v:8649$2660 + attribute \src "ls180.v:8810.7-8810.88" + cell $and $and$ls180.v:8810$2802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247733,10 +249519,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8649$2660_Y + connect \Y $and$ls180.v:8810$2802_Y end - attribute \src "ls180.v:8656.8-8656.83" - cell $and $and$ls180.v:8656$2662 + attribute \src "ls180.v:8817.8-8817.83" + cell $and $and$ls180.v:8817$2804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247744,21 +249530,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8656$2662_Y + connect \Y $and$ls180.v:8817$2804_Y end - attribute \src "ls180.v:8656.7-8656.119" - cell $and $and$ls180.v:8656$2664 + attribute \src "ls180.v:8817.7-8817.119" + cell $and $and$ls180.v:8817$2806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8656$2662_Y - connect \B $not$ls180.v:8656$2663_Y - connect \Y $and$ls180.v:8656$2664_Y + connect \A $and$ls180.v:8817$2804_Y + connect \B $not$ls180.v:8817$2805_Y + connect \Y $and$ls180.v:8817$2806_Y end - attribute \src "ls180.v:8662.8-8662.83" - cell $and $and$ls180.v:8662$2667 + attribute \src "ls180.v:8823.8-8823.83" + cell $and $and$ls180.v:8823$2809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247766,87 +249552,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8662$2667_Y + connect \Y $and$ls180.v:8823$2809_Y end - attribute \src "ls180.v:8662.7-8662.119" - cell $and $and$ls180.v:8662$2669 + attribute \src "ls180.v:8823.7-8823.119" + cell $and $and$ls180.v:8823$2811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8662$2667_Y - connect \B $not$ls180.v:8662$2668_Y - connect \Y $and$ls180.v:8662$2669_Y + connect \A $and$ls180.v:8823$2809_Y + connect \B $not$ls180.v:8823$2810_Y + connect \Y $and$ls180.v:8823$2811_Y end - attribute \src "ls180.v:2810.42-2810.101" - cell $eq $eq$ls180.v:2810$18 + attribute \src "ls180.v:2862.30-2862.76" + cell $eq $eq$ls180.v:2862$46 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_sel + connect \A \main_libresocsim_libresoc_xics_icp_sel connect \B 1'0 - connect \Y $eq$ls180.v:2810$18_Y + connect \Y $eq$ls180.v:2862$46_Y end - attribute \src "ls180.v:2817.11-2817.54" - cell $eq $eq$ls180.v:2817$23 + attribute \src "ls180.v:2869.11-2869.42" + cell $eq $eq$ls180.v:2869$51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter + connect \A \main_converter0_counter connect \B 1'1 - connect \Y $eq$ls180.v:2817$23_Y + connect \Y $eq$ls180.v:2869$51_Y end - attribute \src "ls180.v:2870.42-2870.101" - cell $eq $eq$ls180.v:2870$29 + attribute \src "ls180.v:2922.30-2922.76" + cell $eq $eq$ls180.v:2922$57 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_sel + connect \A \main_libresocsim_libresoc_xics_ics_sel connect \B 1'0 - connect \Y $eq$ls180.v:2870$29_Y + connect \Y $eq$ls180.v:2922$57_Y end - attribute \src "ls180.v:2877.11-2877.54" - cell $eq $eq$ls180.v:2877$34 + attribute \src "ls180.v:2929.11-2929.42" + cell $eq $eq$ls180.v:2929$62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter + connect \A \main_converter1_counter connect \B 1'1 - connect \Y $eq$ls180.v:2877$34_Y + connect \Y $eq$ls180.v:2929$62_Y end - attribute \src "ls180.v:2930.42-2930.101" - cell $eq $eq$ls180.v:2930$40 + attribute \src "ls180.v:2982.33-2982.58" + cell $eq $eq$ls180.v:2982$68 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_sel + connect \A \main_wb_sdram_sel connect \B 1'0 - connect \Y $eq$ls180.v:2930$40_Y + connect \Y $eq$ls180.v:2982$68_Y end - attribute \src "ls180.v:2937.11-2937.54" - cell $eq $eq$ls180.v:2937$45 + attribute \src "ls180.v:2989.11-2989.45" + cell $eq $eq$ls180.v:2989$73 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter + connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $eq$ls180.v:2937$45_Y + connect \Y $eq$ls180.v:2989$73_Y end - attribute \src "ls180.v:3123.34-3123.65" - cell $eq $eq$ls180.v:3123$73 + attribute \src "ls180.v:3221.34-3221.65" + cell $eq $eq$ls180.v:3221$188 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -247854,10 +249640,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_count1 connect \B 1'0 - connect \Y $eq$ls180.v:3123$73_Y + connect \Y $eq$ls180.v:3221$188_Y end - attribute \src "ls180.v:3127.68-3127.102" - cell $eq $eq$ls180.v:3127$76 + attribute \src "ls180.v:3225.68-3225.102" + cell $eq $eq$ls180.v:3225$191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247865,10 +249651,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $eq$ls180.v:3127$76_Y + connect \Y $eq$ls180.v:3225$191_Y end - attribute \src "ls180.v:3171.43-3171.134" - cell $eq $eq$ls180.v:3171$81 + attribute \src "ls180.v:3269.43-3269.134" + cell $eq $eq$ls180.v:3269$196 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -247876,10 +249662,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3171$81_Y + connect \Y $eq$ls180.v:3269$196_Y end - attribute \src "ls180.v:3188.47-3188.88" - cell $eq $eq$ls180.v:3188$94 + attribute \src "ls180.v:3286.47-3286.88" + cell $eq $eq$ls180.v:3286$209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247887,10 +249673,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3188$94_Y + connect \Y $eq$ls180.v:3286$209_Y end - attribute \src "ls180.v:3328.43-3328.134" - cell $eq $eq$ls180.v:3328$111 + attribute \src "ls180.v:3426.43-3426.134" + cell $eq $eq$ls180.v:3426$226 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -247898,10 +249684,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3328$111_Y + connect \Y $eq$ls180.v:3426$226_Y end - attribute \src "ls180.v:3345.47-3345.88" - cell $eq $eq$ls180.v:3345$124 + attribute \src "ls180.v:3443.47-3443.88" + cell $eq $eq$ls180.v:3443$239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247909,10 +249695,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3345$124_Y + connect \Y $eq$ls180.v:3443$239_Y end - attribute \src "ls180.v:3485.43-3485.134" - cell $eq $eq$ls180.v:3485$141 + attribute \src "ls180.v:3583.43-3583.134" + cell $eq $eq$ls180.v:3583$256 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -247920,10 +249706,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3485$141_Y + connect \Y $eq$ls180.v:3583$256_Y end - attribute \src "ls180.v:3502.47-3502.88" - cell $eq $eq$ls180.v:3502$154 + attribute \src "ls180.v:3600.47-3600.88" + cell $eq $eq$ls180.v:3600$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247931,10 +249717,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3502$154_Y + connect \Y $eq$ls180.v:3600$269_Y end - attribute \src "ls180.v:3642.43-3642.134" - cell $eq $eq$ls180.v:3642$171 + attribute \src "ls180.v:3740.43-3740.134" + cell $eq $eq$ls180.v:3740$286 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -247942,10 +249728,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3642$171_Y + connect \Y $eq$ls180.v:3740$286_Y end - attribute \src "ls180.v:3659.47-3659.88" - cell $eq $eq$ls180.v:3659$184 + attribute \src "ls180.v:3757.47-3757.88" + cell $eq $eq$ls180.v:3757$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247953,10 +249739,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3659$184_Y + connect \Y $eq$ls180.v:3757$299_Y end - attribute \src "ls180.v:3796.32-3796.56" - cell $eq $eq$ls180.v:3796$231 + attribute \src "ls180.v:3894.32-3894.56" + cell $eq $eq$ls180.v:3894$346 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -247964,10 +249750,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time0 connect \B 1'0 - connect \Y $eq$ls180.v:3796$231_Y + connect \Y $eq$ls180.v:3894$346_Y end - attribute \src "ls180.v:3797.32-3797.56" - cell $eq $eq$ls180.v:3797$232 + attribute \src "ls180.v:3895.32-3895.56" + cell $eq $eq$ls180.v:3895$347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -247975,10 +249761,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time1 connect \B 1'0 - connect \Y $eq$ls180.v:3797$232_Y + connect \Y $eq$ls180.v:3895$347_Y end - attribute \src "ls180.v:3808.339-3808.418" - cell $eq $eq$ls180.v:3808$246 + attribute \src "ls180.v:3906.339-3906.418" + cell $eq $eq$ls180.v:3906$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247986,10 +249772,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3808$246_Y + connect \Y $eq$ls180.v:3906$361_Y end - attribute \src "ls180.v:3808.423-3808.504" - cell $eq $eq$ls180.v:3808$247 + attribute \src "ls180.v:3906.423-3906.504" + cell $eq $eq$ls180.v:3906$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247997,10 +249783,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3808$247_Y + connect \Y $eq$ls180.v:3906$362_Y end - attribute \src "ls180.v:3809.339-3809.418" - cell $eq $eq$ls180.v:3809$259 + attribute \src "ls180.v:3907.339-3907.418" + cell $eq $eq$ls180.v:3907$374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248008,10 +249794,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3809$259_Y + connect \Y $eq$ls180.v:3907$374_Y end - attribute \src "ls180.v:3809.423-3809.504" - cell $eq $eq$ls180.v:3809$260 + attribute \src "ls180.v:3907.423-3907.504" + cell $eq $eq$ls180.v:3907$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248019,10 +249805,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3809$260_Y + connect \Y $eq$ls180.v:3907$375_Y end - attribute \src "ls180.v:3810.339-3810.418" - cell $eq $eq$ls180.v:3810$272 + attribute \src "ls180.v:3908.339-3908.418" + cell $eq $eq$ls180.v:3908$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248030,10 +249816,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3810$272_Y + connect \Y $eq$ls180.v:3908$387_Y end - attribute \src "ls180.v:3810.423-3810.504" - cell $eq $eq$ls180.v:3810$273 + attribute \src "ls180.v:3908.423-3908.504" + cell $eq $eq$ls180.v:3908$388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248041,10 +249827,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3810$273_Y + connect \Y $eq$ls180.v:3908$388_Y end - attribute \src "ls180.v:3811.339-3811.418" - cell $eq $eq$ls180.v:3811$285 + attribute \src "ls180.v:3909.339-3909.418" + cell $eq $eq$ls180.v:3909$400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248052,10 +249838,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3811$285_Y + connect \Y $eq$ls180.v:3909$400_Y end - attribute \src "ls180.v:3811.423-3811.504" - cell $eq $eq$ls180.v:3811$286 + attribute \src "ls180.v:3909.423-3909.504" + cell $eq $eq$ls180.v:3909$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248063,10 +249849,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3811$286_Y + connect \Y $eq$ls180.v:3909$401_Y end - attribute \src "ls180.v:3841.339-3841.418" - cell $eq $eq$ls180.v:3841$304 + attribute \src "ls180.v:3939.339-3939.418" + cell $eq $eq$ls180.v:3939$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248074,10 +249860,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3841$304_Y + connect \Y $eq$ls180.v:3939$419_Y end - attribute \src "ls180.v:3841.423-3841.504" - cell $eq $eq$ls180.v:3841$305 + attribute \src "ls180.v:3939.423-3939.504" + cell $eq $eq$ls180.v:3939$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248085,10 +249871,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3841$305_Y + connect \Y $eq$ls180.v:3939$420_Y end - attribute \src "ls180.v:3842.339-3842.418" - cell $eq $eq$ls180.v:3842$317 + attribute \src "ls180.v:3940.339-3940.418" + cell $eq $eq$ls180.v:3940$432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248096,10 +249882,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3842$317_Y + connect \Y $eq$ls180.v:3940$432_Y end - attribute \src "ls180.v:3842.423-3842.504" - cell $eq $eq$ls180.v:3842$318 + attribute \src "ls180.v:3940.423-3940.504" + cell $eq $eq$ls180.v:3940$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248107,10 +249893,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3842$318_Y + connect \Y $eq$ls180.v:3940$433_Y end - attribute \src "ls180.v:3843.339-3843.418" - cell $eq $eq$ls180.v:3843$330 + attribute \src "ls180.v:3941.339-3941.418" + cell $eq $eq$ls180.v:3941$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248118,10 +249904,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3843$330_Y + connect \Y $eq$ls180.v:3941$445_Y end - attribute \src "ls180.v:3843.423-3843.504" - cell $eq $eq$ls180.v:3843$331 + attribute \src "ls180.v:3941.423-3941.504" + cell $eq $eq$ls180.v:3941$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248129,10 +249915,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3843$331_Y + connect \Y $eq$ls180.v:3941$446_Y end - attribute \src "ls180.v:3844.339-3844.418" - cell $eq $eq$ls180.v:3844$343 + attribute \src "ls180.v:3942.339-3942.418" + cell $eq $eq$ls180.v:3942$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248140,10 +249926,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3844$343_Y + connect \Y $eq$ls180.v:3942$458_Y end - attribute \src "ls180.v:3844.423-3844.504" - cell $eq $eq$ls180.v:3844$344 + attribute \src "ls180.v:3942.423-3942.504" + cell $eq $eq$ls180.v:3942$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248151,10 +249937,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3844$344_Y + connect \Y $eq$ls180.v:3942$459_Y end - attribute \src "ls180.v:3873.78-3873.113" - cell $eq $eq$ls180.v:3873$353 + attribute \src "ls180.v:3971.78-3971.113" + cell $eq $eq$ls180.v:3971$468 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248162,10 +249948,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'0 - connect \Y $eq$ls180.v:3873$353_Y + connect \Y $eq$ls180.v:3971$468_Y end - attribute \src "ls180.v:3876.78-3876.113" - cell $eq $eq$ls180.v:3876$356 + attribute \src "ls180.v:3974.78-3974.113" + cell $eq $eq$ls180.v:3974$471 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248173,10 +249959,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'0 - connect \Y $eq$ls180.v:3876$356_Y + connect \Y $eq$ls180.v:3974$471_Y end - attribute \src "ls180.v:3882.78-3882.113" - cell $eq $eq$ls180.v:3882$360 + attribute \src "ls180.v:3980.78-3980.113" + cell $eq $eq$ls180.v:3980$475 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248184,10 +249970,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'1 - connect \Y $eq$ls180.v:3882$360_Y + connect \Y $eq$ls180.v:3980$475_Y end - attribute \src "ls180.v:3885.78-3885.113" - cell $eq $eq$ls180.v:3885$363 + attribute \src "ls180.v:3983.78-3983.113" + cell $eq $eq$ls180.v:3983$478 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248195,10 +249981,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'1 - connect \Y $eq$ls180.v:3885$363_Y + connect \Y $eq$ls180.v:3983$478_Y end - attribute \src "ls180.v:3891.78-3891.113" - cell $eq $eq$ls180.v:3891$367 + attribute \src "ls180.v:3989.78-3989.113" + cell $eq $eq$ls180.v:3989$482 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248206,10 +249992,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'10 - connect \Y $eq$ls180.v:3891$367_Y + connect \Y $eq$ls180.v:3989$482_Y end - attribute \src "ls180.v:3894.78-3894.113" - cell $eq $eq$ls180.v:3894$370 + attribute \src "ls180.v:3992.78-3992.113" + cell $eq $eq$ls180.v:3992$485 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248217,10 +250003,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'10 - connect \Y $eq$ls180.v:3894$370_Y + connect \Y $eq$ls180.v:3992$485_Y end - attribute \src "ls180.v:3900.78-3900.113" - cell $eq $eq$ls180.v:3900$374 + attribute \src "ls180.v:3998.78-3998.113" + cell $eq $eq$ls180.v:3998$489 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248228,10 +250014,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'11 - connect \Y $eq$ls180.v:3900$374_Y + connect \Y $eq$ls180.v:3998$489_Y end - attribute \src "ls180.v:3903.78-3903.113" - cell $eq $eq$ls180.v:3903$377 + attribute \src "ls180.v:4001.78-4001.113" + cell $eq $eq$ls180.v:4001$492 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248239,10 +250025,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'11 - connect \Y $eq$ls180.v:3903$377_Y + connect \Y $eq$ls180.v:4001$492_Y end - attribute \src "ls180.v:3984.42-3984.82" - cell $eq $eq$ls180.v:3984$400 + attribute \src "ls180.v:4082.42-4082.82" + cell $eq $eq$ls180.v:4082$515 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248250,10 +250036,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:3984$400_Y + connect \Y $eq$ls180.v:4082$515_Y end - attribute \src "ls180.v:3984.145-3984.178" - cell $eq $eq$ls180.v:3984$401 + attribute \src "ls180.v:4082.145-4082.178" + cell $eq $eq$ls180.v:4082$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248261,10 +250047,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3984$401_Y + connect \Y $eq$ls180.v:4082$516_Y end - attribute \src "ls180.v:3984.220-3984.253" - cell $eq $eq$ls180.v:3984$404 + attribute \src "ls180.v:4082.220-4082.253" + cell $eq $eq$ls180.v:4082$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248272,10 +250058,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3984$404_Y + connect \Y $eq$ls180.v:4082$519_Y end - attribute \src "ls180.v:3984.295-3984.328" - cell $eq $eq$ls180.v:3984$407 + attribute \src "ls180.v:4082.295-4082.328" + cell $eq $eq$ls180.v:4082$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248283,10 +250069,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3984$407_Y + connect \Y $eq$ls180.v:4082$522_Y end - attribute \src "ls180.v:3989.42-3989.82" - cell $eq $eq$ls180.v:3989$416 + attribute \src "ls180.v:4087.42-4087.82" + cell $eq $eq$ls180.v:4087$531 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248294,10 +250080,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:3989$416_Y + connect \Y $eq$ls180.v:4087$531_Y end - attribute \src "ls180.v:3989.145-3989.178" - cell $eq $eq$ls180.v:3989$417 + attribute \src "ls180.v:4087.145-4087.178" + cell $eq $eq$ls180.v:4087$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248305,10 +250091,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3989$417_Y + connect \Y $eq$ls180.v:4087$532_Y end - attribute \src "ls180.v:3989.220-3989.253" - cell $eq $eq$ls180.v:3989$420 + attribute \src "ls180.v:4087.220-4087.253" + cell $eq $eq$ls180.v:4087$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248316,10 +250102,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3989$420_Y + connect \Y $eq$ls180.v:4087$535_Y end - attribute \src "ls180.v:3989.295-3989.328" - cell $eq $eq$ls180.v:3989$423 + attribute \src "ls180.v:4087.295-4087.328" + cell $eq $eq$ls180.v:4087$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248327,10 +250113,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3989$423_Y + connect \Y $eq$ls180.v:4087$538_Y end - attribute \src "ls180.v:3994.42-3994.82" - cell $eq $eq$ls180.v:3994$432 + attribute \src "ls180.v:4092.42-4092.82" + cell $eq $eq$ls180.v:4092$547 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248338,10 +250124,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:3994$432_Y + connect \Y $eq$ls180.v:4092$547_Y end - attribute \src "ls180.v:3994.145-3994.178" - cell $eq $eq$ls180.v:3994$433 + attribute \src "ls180.v:4092.145-4092.178" + cell $eq $eq$ls180.v:4092$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248349,10 +250135,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3994$433_Y + connect \Y $eq$ls180.v:4092$548_Y end - attribute \src "ls180.v:3994.220-3994.253" - cell $eq $eq$ls180.v:3994$436 + attribute \src "ls180.v:4092.220-4092.253" + cell $eq $eq$ls180.v:4092$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248360,10 +250146,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3994$436_Y + connect \Y $eq$ls180.v:4092$551_Y end - attribute \src "ls180.v:3994.295-3994.328" - cell $eq $eq$ls180.v:3994$439 + attribute \src "ls180.v:4092.295-4092.328" + cell $eq $eq$ls180.v:4092$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248371,10 +250157,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3994$439_Y + connect \Y $eq$ls180.v:4092$554_Y end - attribute \src "ls180.v:3999.42-3999.82" - cell $eq $eq$ls180.v:3999$448 + attribute \src "ls180.v:4097.42-4097.82" + cell $eq $eq$ls180.v:4097$563 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248382,10 +250168,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:3999$448_Y + connect \Y $eq$ls180.v:4097$563_Y end - attribute \src "ls180.v:3999.145-3999.178" - cell $eq $eq$ls180.v:3999$449 + attribute \src "ls180.v:4097.145-4097.178" + cell $eq $eq$ls180.v:4097$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248393,10 +250179,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3999$449_Y + connect \Y $eq$ls180.v:4097$564_Y end - attribute \src "ls180.v:3999.220-3999.253" - cell $eq $eq$ls180.v:3999$452 + attribute \src "ls180.v:4097.220-4097.253" + cell $eq $eq$ls180.v:4097$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248404,10 +250190,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3999$452_Y + connect \Y $eq$ls180.v:4097$567_Y end - attribute \src "ls180.v:3999.295-3999.328" - cell $eq $eq$ls180.v:3999$455 + attribute \src "ls180.v:4097.295-4097.328" + cell $eq $eq$ls180.v:4097$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248415,10 +250201,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3999$455_Y + connect \Y $eq$ls180.v:4097$570_Y end - attribute \src "ls180.v:4004.44-4004.77" - cell $eq $eq$ls180.v:4004$464 + attribute \src "ls180.v:4102.44-4102.77" + cell $eq $eq$ls180.v:4102$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248426,10 +250212,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$464_Y + connect \Y $eq$ls180.v:4102$579_Y end - attribute \src "ls180.v:4004.83-4004.123" - cell $eq $eq$ls180.v:4004$465 + attribute \src "ls180.v:4102.83-4102.123" + cell $eq $eq$ls180.v:4102$580 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248437,10 +250223,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4004$465_Y + connect \Y $eq$ls180.v:4102$580_Y end - attribute \src "ls180.v:4004.186-4004.219" - cell $eq $eq$ls180.v:4004$466 + attribute \src "ls180.v:4102.186-4102.219" + cell $eq $eq$ls180.v:4102$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248448,10 +250234,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$466_Y + connect \Y $eq$ls180.v:4102$581_Y end - attribute \src "ls180.v:4004.261-4004.294" - cell $eq $eq$ls180.v:4004$469 + attribute \src "ls180.v:4102.261-4102.294" + cell $eq $eq$ls180.v:4102$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248459,10 +250245,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$469_Y + connect \Y $eq$ls180.v:4102$584_Y end - attribute \src "ls180.v:4004.336-4004.369" - cell $eq $eq$ls180.v:4004$472 + attribute \src "ls180.v:4102.336-4102.369" + cell $eq $eq$ls180.v:4102$587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248470,10 +250256,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$472_Y + connect \Y $eq$ls180.v:4102$587_Y end - attribute \src "ls180.v:4004.418-4004.451" - cell $eq $eq$ls180.v:4004$480 + attribute \src "ls180.v:4102.418-4102.451" + cell $eq $eq$ls180.v:4102$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248481,10 +250267,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$480_Y + connect \Y $eq$ls180.v:4102$595_Y end - attribute \src "ls180.v:4004.457-4004.497" - cell $eq $eq$ls180.v:4004$481 + attribute \src "ls180.v:4102.457-4102.497" + cell $eq $eq$ls180.v:4102$596 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248492,10 +250278,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4004$481_Y + connect \Y $eq$ls180.v:4102$596_Y end - attribute \src "ls180.v:4004.560-4004.593" - cell $eq $eq$ls180.v:4004$482 + attribute \src "ls180.v:4102.560-4102.593" + cell $eq $eq$ls180.v:4102$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248503,10 +250289,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$482_Y + connect \Y $eq$ls180.v:4102$597_Y end - attribute \src "ls180.v:4004.635-4004.668" - cell $eq $eq$ls180.v:4004$485 + attribute \src "ls180.v:4102.635-4102.668" + cell $eq $eq$ls180.v:4102$600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248514,10 +250300,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$485_Y + connect \Y $eq$ls180.v:4102$600_Y end - attribute \src "ls180.v:4004.710-4004.743" - cell $eq $eq$ls180.v:4004$488 + attribute \src "ls180.v:4102.710-4102.743" + cell $eq $eq$ls180.v:4102$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248525,10 +250311,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$488_Y + connect \Y $eq$ls180.v:4102$603_Y end - attribute \src "ls180.v:4004.792-4004.825" - cell $eq $eq$ls180.v:4004$496 + attribute \src "ls180.v:4102.792-4102.825" + cell $eq $eq$ls180.v:4102$611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248536,10 +250322,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$496_Y + connect \Y $eq$ls180.v:4102$611_Y end - attribute \src "ls180.v:4004.831-4004.871" - cell $eq $eq$ls180.v:4004$497 + attribute \src "ls180.v:4102.831-4102.871" + cell $eq $eq$ls180.v:4102$612 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248547,10 +250333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4004$497_Y + connect \Y $eq$ls180.v:4102$612_Y end - attribute \src "ls180.v:4004.934-4004.967" - cell $eq $eq$ls180.v:4004$498 + attribute \src "ls180.v:4102.934-4102.967" + cell $eq $eq$ls180.v:4102$613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248558,10 +250344,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$498_Y + connect \Y $eq$ls180.v:4102$613_Y end - attribute \src "ls180.v:4004.1009-4004.1042" - cell $eq $eq$ls180.v:4004$501 + attribute \src "ls180.v:4102.1009-4102.1042" + cell $eq $eq$ls180.v:4102$616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248569,10 +250355,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$501_Y + connect \Y $eq$ls180.v:4102$616_Y end - attribute \src "ls180.v:4004.1084-4004.1117" - cell $eq $eq$ls180.v:4004$504 + attribute \src "ls180.v:4102.1084-4102.1117" + cell $eq $eq$ls180.v:4102$619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248580,10 +250366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$504_Y + connect \Y $eq$ls180.v:4102$619_Y end - attribute \src "ls180.v:4004.1166-4004.1199" - cell $eq $eq$ls180.v:4004$512 + attribute \src "ls180.v:4102.1166-4102.1199" + cell $eq $eq$ls180.v:4102$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248591,10 +250377,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$512_Y + connect \Y $eq$ls180.v:4102$627_Y end - attribute \src "ls180.v:4004.1205-4004.1245" - cell $eq $eq$ls180.v:4004$513 + attribute \src "ls180.v:4102.1205-4102.1245" + cell $eq $eq$ls180.v:4102$628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248602,10 +250388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4004$513_Y + connect \Y $eq$ls180.v:4102$628_Y end - attribute \src "ls180.v:4004.1308-4004.1341" - cell $eq $eq$ls180.v:4004$514 + attribute \src "ls180.v:4102.1308-4102.1341" + cell $eq $eq$ls180.v:4102$629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248613,10 +250399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$514_Y + connect \Y $eq$ls180.v:4102$629_Y end - attribute \src "ls180.v:4004.1383-4004.1416" - cell $eq $eq$ls180.v:4004$517 + attribute \src "ls180.v:4102.1383-4102.1416" + cell $eq $eq$ls180.v:4102$632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248624,10 +250410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$517_Y + connect \Y $eq$ls180.v:4102$632_Y end - attribute \src "ls180.v:4004.1458-4004.1491" - cell $eq $eq$ls180.v:4004$520 + attribute \src "ls180.v:4102.1458-4102.1491" + cell $eq $eq$ls180.v:4102$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248635,10 +250421,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4004$520_Y + connect \Y $eq$ls180.v:4102$635_Y end - attribute \src "ls180.v:4063.29-4063.57" - cell $eq $eq$ls180.v:4063$533 + attribute \src "ls180.v:4161.29-4161.57" + cell $eq $eq$ls180.v:4161$648 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248646,10 +250432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_sel connect \B 1'0 - connect \Y $eq$ls180.v:4063$533_Y + connect \Y $eq$ls180.v:4161$648_Y end - attribute \src "ls180.v:4070.11-4070.41" - cell $eq $eq$ls180.v:4070$538 + attribute \src "ls180.v:4168.11-4168.41" + cell $eq $eq$ls180.v:4168$653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248657,76 +250443,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $eq$ls180.v:4070$538_Y + connect \Y $eq$ls180.v:4168$653_Y end - attribute \src "ls180.v:4227.37-4227.111" - cell $eq $eq$ls180.v:4227$603 + attribute \src "ls180.v:4325.37-4325.111" + cell $eq $eq$ls180.v:4325$718 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4227$602_Y - connect \Y $eq$ls180.v:4227$603_Y + connect \B $sub$ls180.v:4325$717_Y + connect \Y $eq$ls180.v:4325$718_Y end - attribute \src "ls180.v:4228.37-4228.105" - cell $eq $eq$ls180.v:4228$605 + attribute \src "ls180.v:4326.37-4326.105" + cell $eq $eq$ls180.v:4326$720 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4228$604_Y - connect \Y $eq$ls180.v:4228$605_Y + connect \B $sub$ls180.v:4326$719_Y + connect \Y $eq$ls180.v:4326$720_Y end - attribute \src "ls180.v:4255.10-4255.67" - cell $eq $eq$ls180.v:4255$609 + attribute \src "ls180.v:4353.10-4353.67" + cell $eq $eq$ls180.v:4353$724 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4255$608_Y - connect \Y $eq$ls180.v:4255$609_Y + connect \B $sub$ls180.v:4353$723_Y + connect \Y $eq$ls180.v:4353$724_Y end - attribute \src "ls180.v:4285.35-4285.108" - cell $eq $eq$ls180.v:4285$611 + attribute \src "ls180.v:4383.35-4383.108" + cell $eq $eq$ls180.v:4383$726 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4285$610_Y - connect \Y $eq$ls180.v:4285$611_Y + connect \B $sub$ls180.v:4383$725_Y + connect \Y $eq$ls180.v:4383$726_Y end - attribute \src "ls180.v:4286.35-4286.102" - cell $eq $eq$ls180.v:4286$613 + attribute \src "ls180.v:4384.35-4384.102" + cell $eq $eq$ls180.v:4384$728 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4286$612_Y - connect \Y $eq$ls180.v:4286$613_Y + connect \B $sub$ls180.v:4384$727_Y + connect \Y $eq$ls180.v:4384$728_Y end - attribute \src "ls180.v:4314.10-4314.65" - cell $eq $eq$ls180.v:4314$617 + attribute \src "ls180.v:4412.10-4412.65" + cell $eq $eq$ls180.v:4412$732 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4314$616_Y - connect \Y $eq$ls180.v:4314$617_Y + connect \B $sub$ls180.v:4412$731_Y + connect \Y $eq$ls180.v:4412$732_Y end - attribute \src "ls180.v:4418.10-4418.40" - cell $eq $eq$ls180.v:4418$644 + attribute \src "ls180.v:4516.10-4516.40" + cell $eq $eq$ls180.v:4516$759 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -248734,10 +250520,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_count connect \B 7'1001111 - connect \Y $eq$ls180.v:4418$644_Y + connect \Y $eq$ls180.v:4516$759_Y end - attribute \src "ls180.v:4475.10-4475.39" - cell $eq $eq$ls180.v:4475$647 + attribute \src "ls180.v:4573.10-4573.39" + cell $eq $eq$ls180.v:4573$762 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -248745,10 +250531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4475$647_Y + connect \Y $eq$ls180.v:4573$762_Y end - attribute \src "ls180.v:4492.10-4492.39" - cell $eq $eq$ls180.v:4492$649 + attribute \src "ls180.v:4590.10-4590.39" + cell $eq $eq$ls180.v:4590$764 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -248756,10 +250542,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4492$649_Y + connect \Y $eq$ls180.v:4590$764_Y end - attribute \src "ls180.v:4520.38-4520.88" - cell $eq $eq$ls180.v:4520$651 + attribute \src "ls180.v:4618.38-4618.88" + cell $eq $eq$ls180.v:4618$766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248767,10 +250553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \B 1'0 - connect \Y $eq$ls180.v:4520$651_Y + connect \Y $eq$ls180.v:4618$766_Y end - attribute \src "ls180.v:4570.9-4570.40" - cell $eq $eq$ls180.v:4570$661 + attribute \src "ls180.v:4668.9-4668.40" + cell $eq $eq$ls180.v:4668$776 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -248778,21 +250564,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4570$661_Y + connect \Y $eq$ls180.v:4668$776_Y end - attribute \src "ls180.v:4579.36-4579.105" - cell $eq $eq$ls180.v:4579$663 + attribute \src "ls180.v:4677.36-4677.105" + cell $eq $eq$ls180.v:4677$778 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4579$662_Y - connect \Y $eq$ls180.v:4579$663_Y + connect \B $sub$ls180.v:4677$777_Y + connect \Y $eq$ls180.v:4677$778_Y end - attribute \src "ls180.v:4598.9-4598.40" - cell $eq $eq$ls180.v:4598$667 + attribute \src "ls180.v:4696.9-4696.40" + cell $eq $eq$ls180.v:4696$782 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -248800,10 +250586,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4598$667_Y + connect \Y $eq$ls180.v:4696$782_Y end - attribute \src "ls180.v:4610.10-4610.39" - cell $eq $eq$ls180.v:4610$669 + attribute \src "ls180.v:4708.10-4708.39" + cell $eq $eq$ls180.v:4708$784 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -248811,10 +250597,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count connect \B 3'111 - connect \Y $eq$ls180.v:4610$669_Y + connect \Y $eq$ls180.v:4708$784_Y end - attribute \src "ls180.v:4647.39-4647.94" - cell $eq $eq$ls180.v:4647$673 + attribute \src "ls180.v:4745.39-4745.94" + cell $eq $eq$ls180.v:4745$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248822,10 +250608,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \B 1'0 - connect \Y $eq$ls180.v:4647$673_Y + connect \Y $eq$ls180.v:4745$788_Y end - attribute \src "ls180.v:4684.32-4684.89" - cell $eq $eq$ls180.v:4684$682 + attribute \src "ls180.v:4782.32-4782.89" + cell $eq $eq$ls180.v:4782$797 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -248833,10 +250619,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $eq$ls180.v:4684$682_Y + connect \Y $eq$ls180.v:4782$797_Y end - attribute \src "ls180.v:4732.10-4732.40" - cell $eq $eq$ls180.v:4732$686 + attribute \src "ls180.v:4830.10-4830.40" + cell $eq $eq$ls180.v:4830$801 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -248844,10 +250630,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $eq$ls180.v:4732$686_Y + connect \Y $eq$ls180.v:4830$801_Y end - attribute \src "ls180.v:4781.40-4781.98" - cell $eq $eq$ls180.v:4781$688 + attribute \src "ls180.v:4879.40-4879.98" + cell $eq $eq$ls180.v:4879$803 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248855,10 +250641,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_payload_data_i connect \B 1'0 - connect \Y $eq$ls180.v:4781$688_Y + connect \Y $eq$ls180.v:4879$803_Y end - attribute \src "ls180.v:4832.9-4832.41" - cell $eq $eq$ls180.v:4832$698 + attribute \src "ls180.v:4930.9-4930.41" + cell $eq $eq$ls180.v:4930$813 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -248866,21 +250652,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4832$698_Y + connect \Y $eq$ls180.v:4930$813_Y end - attribute \src "ls180.v:4841.37-4841.123" - cell $eq $eq$ls180.v:4841$701 + attribute \src "ls180.v:4939.37-4939.123" + cell $eq $eq$ls180.v:4939$816 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:4841$700_Y - connect \Y $eq$ls180.v:4841$701_Y + connect \B $sub$ls180.v:4939$815_Y + connect \Y $eq$ls180.v:4939$816_Y end - attribute \src "ls180.v:4864.9-4864.41" - cell $eq $eq$ls180.v:4864$704 + attribute \src "ls180.v:4962.9-4962.41" + cell $eq $eq$ls180.v:4962$819 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -248888,10 +250674,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4864$704_Y + connect \Y $eq$ls180.v:4962$819_Y end - attribute \src "ls180.v:4874.10-4874.41" - cell $eq $eq$ls180.v:4874$706 + attribute \src "ls180.v:4972.10-4972.41" + cell $eq $eq$ls180.v:4972$821 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -248899,10 +250685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count connect \B 6'100111 - connect \Y $eq$ls180.v:4874$706_Y + connect \Y $eq$ls180.v:4972$821_Y end - attribute \src "ls180.v:5043.9-5043.47" - cell $eq $eq$ls180.v:5043$888 + attribute \src "ls180.v:5141.9-5141.47" + cell $eq $eq$ls180.v:5141$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248910,10 +250696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5043$888_Y + connect \Y $eq$ls180.v:5141$1003_Y end - attribute \src "ls180.v:5073.10-5073.48" - cell $eq $eq$ls180.v:5073$889 + attribute \src "ls180.v:5171.10-5171.48" + cell $eq $eq$ls180.v:5171$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248921,10 +250707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5073$889_Y + connect \Y $eq$ls180.v:5171$1004_Y end - attribute \src "ls180.v:5104.10-5104.78" - cell $eq $eq$ls180.v:5104$894 + attribute \src "ls180.v:5202.10-5202.78" + cell $eq $eq$ls180.v:5202$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -248932,10 +250718,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo0 connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5104$894_Y + connect \Y $eq$ls180.v:5202$1009_Y end - attribute \src "ls180.v:5104.83-5104.151" - cell $eq $eq$ls180.v:5104$895 + attribute \src "ls180.v:5202.83-5202.151" + cell $eq $eq$ls180.v:5202$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -248943,10 +250729,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo1 connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5104$895_Y + connect \Y $eq$ls180.v:5202$1010_Y end - attribute \src "ls180.v:5104.157-5104.225" - cell $eq $eq$ls180.v:5104$897 + attribute \src "ls180.v:5202.157-5202.225" + cell $eq $eq$ls180.v:5202$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -248954,10 +250740,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo2 connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5104$897_Y + connect \Y $eq$ls180.v:5202$1012_Y end - attribute \src "ls180.v:5104.231-5104.299" - cell $eq $eq$ls180.v:5104$899 + attribute \src "ls180.v:5202.231-5202.299" + cell $eq $eq$ls180.v:5202$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -248965,10 +250751,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo3 connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5104$899_Y + connect \Y $eq$ls180.v:5202$1014_Y end - attribute \src "ls180.v:5112.7-5112.44" - cell $eq $eq$ls180.v:5112$903 + attribute \src "ls180.v:5210.7-5210.44" + cell $eq $eq$ls180.v:5210$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248976,10 +250762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5112$903_Y + connect \Y $eq$ls180.v:5210$1018_Y end - attribute \src "ls180.v:5122.7-5122.44" - cell $eq $eq$ls180.v:5122$906 + attribute \src "ls180.v:5220.7-5220.44" + cell $eq $eq$ls180.v:5220$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248987,10 +250773,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5122$906_Y + connect \Y $eq$ls180.v:5220$1021_Y end - attribute \src "ls180.v:5132.7-5132.44" - cell $eq $eq$ls180.v:5132$909 + attribute \src "ls180.v:5230.7-5230.44" + cell $eq $eq$ls180.v:5230$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248998,10 +250784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5132$909_Y + connect \Y $eq$ls180.v:5230$1024_Y end - attribute \src "ls180.v:5142.7-5142.44" - cell $eq $eq$ls180.v:5142$912 + attribute \src "ls180.v:5240.7-5240.44" + cell $eq $eq$ls180.v:5240$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249009,10 +250795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5142$912_Y + connect \Y $eq$ls180.v:5240$1027_Y end - attribute \src "ls180.v:5266.36-5266.64" - cell $eq $eq$ls180.v:5266$963 + attribute \src "ls180.v:5364.36-5364.64" + cell $eq $eq$ls180.v:5364$1078 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249020,10 +250806,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5266$963_Y + connect \Y $eq$ls180.v:5364$1078_Y end - attribute \src "ls180.v:5272.10-5272.39" - cell $eq $eq$ls180.v:5272$966 + attribute \src "ls180.v:5370.10-5370.39" + cell $eq $eq$ls180.v:5370$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249031,10 +250817,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_count connect \B 3'101 - connect \Y $eq$ls180.v:5272$966_Y + connect \Y $eq$ls180.v:5370$1081_Y end - attribute \src "ls180.v:5273.11-5273.39" - cell $eq $eq$ls180.v:5273$967 + attribute \src "ls180.v:5371.11-5371.39" + cell $eq $eq$ls180.v:5371$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249042,10 +250828,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5273$967_Y + connect \Y $eq$ls180.v:5371$1082_Y end - attribute \src "ls180.v:5285.34-5285.63" - cell $eq $eq$ls180.v:5285$968 + attribute \src "ls180.v:5383.34-5383.63" + cell $eq $eq$ls180.v:5383$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249053,10 +250839,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'0 - connect \Y $eq$ls180.v:5285$968_Y + connect \Y $eq$ls180.v:5383$1083_Y end - attribute \src "ls180.v:5286.9-5286.37" - cell $eq $eq$ls180.v:5286$969 + attribute \src "ls180.v:5384.9-5384.37" + cell $eq $eq$ls180.v:5384$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249064,10 +250850,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 2'10 - connect \Y $eq$ls180.v:5286$969_Y + connect \Y $eq$ls180.v:5384$1084_Y end - attribute \src "ls180.v:5293.10-5293.55" - cell $eq $eq$ls180.v:5293$970 + attribute \src "ls180.v:5391.10-5391.55" + cell $eq $eq$ls180.v:5391$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249075,10 +250861,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5293$970_Y + connect \Y $eq$ls180.v:5391$1085_Y end - attribute \src "ls180.v:5299.12-5299.41" - cell $eq $eq$ls180.v:5299$971 + attribute \src "ls180.v:5397.12-5397.41" + cell $eq $eq$ls180.v:5397$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249086,10 +250872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 2'10 - connect \Y $eq$ls180.v:5299$971_Y + connect \Y $eq$ls180.v:5397$1086_Y end - attribute \src "ls180.v:5302.13-5302.42" - cell $eq $eq$ls180.v:5302$972 + attribute \src "ls180.v:5400.13-5400.42" + cell $eq $eq$ls180.v:5400$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249097,32 +250883,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'1 - connect \Y $eq$ls180.v:5302$972_Y + connect \Y $eq$ls180.v:5400$1087_Y end - attribute \src "ls180.v:5324.10-5324.76" - cell $eq $eq$ls180.v:5324$977 + attribute \src "ls180.v:5422.10-5422.76" + cell $eq $eq$ls180.v:5422$1092 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5324$976_Y - connect \Y $eq$ls180.v:5324$977_Y + connect \B $sub$ls180.v:5422$1091_Y + connect \Y $eq$ls180.v:5422$1092_Y end - attribute \src "ls180.v:5339.35-5339.101" - cell $eq $eq$ls180.v:5339$980 + attribute \src "ls180.v:5437.35-5437.101" + cell $eq $eq$ls180.v:5437$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5339$979_Y - connect \Y $eq$ls180.v:5339$980_Y + connect \B $sub$ls180.v:5437$1094_Y + connect \Y $eq$ls180.v:5437$1095_Y end - attribute \src "ls180.v:5341.10-5341.56" - cell $eq $eq$ls180.v:5341$981 + attribute \src "ls180.v:5439.10-5439.56" + cell $eq $eq$ls180.v:5439$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249130,21 +250916,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'0 - connect \Y $eq$ls180.v:5341$981_Y + connect \Y $eq$ls180.v:5439$1096_Y end - attribute \src "ls180.v:5350.12-5350.78" - cell $eq $eq$ls180.v:5350$985 + attribute \src "ls180.v:5448.12-5448.78" + cell $eq $eq$ls180.v:5448$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5350$984_Y - connect \Y $eq$ls180.v:5350$985_Y + connect \B $sub$ls180.v:5448$1099_Y + connect \Y $eq$ls180.v:5448$1100_Y end - attribute \src "ls180.v:5357.11-5357.57" - cell $eq $eq$ls180.v:5357$986 + attribute \src "ls180.v:5455.11-5455.57" + cell $eq $eq$ls180.v:5455$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249152,54 +250938,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5357$986_Y + connect \Y $eq$ls180.v:5455$1101_Y end - attribute \src "ls180.v:5474.10-5474.105" - cell $eq $eq$ls180.v:5474$1003 + attribute \src "ls180.v:5572.10-5572.105" + cell $eq $eq$ls180.v:5572$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5474$1002_Y - connect \Y $eq$ls180.v:5474$1003_Y + connect \B $sub$ls180.v:5572$1117_Y + connect \Y $eq$ls180.v:5572$1118_Y end - attribute \src "ls180.v:5564.39-5564.106" - cell $eq $eq$ls180.v:5564$1009 + attribute \src "ls180.v:5662.39-5662.106" + cell $eq $eq$ls180.v:5662$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5564$1008_Y - connect \Y $eq$ls180.v:5564$1009_Y + connect \B $sub$ls180.v:5662$1123_Y + connect \Y $eq$ls180.v:5662$1124_Y end - attribute \src "ls180.v:5594.44-5594.82" - cell $eq $eq$ls180.v:5594$1012 + attribute \src "ls180.v:5692.44-5692.82" + cell $eq $eq$ls180.v:5692$1127 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 1'0 - connect \Y $eq$ls180.v:5594$1012_Y + connect \Y $eq$ls180.v:5692$1127_Y end - attribute \src "ls180.v:5595.43-5595.81" - cell $eq $eq$ls180.v:5595$1013 + attribute \src "ls180.v:5693.43-5693.81" + cell $eq $eq$ls180.v:5693$1128 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux - connect \B 2'11 - connect \Y $eq$ls180.v:5595$1013_Y + connect \B 3'111 + connect \Y $eq$ls180.v:5693$1128_Y end - attribute \src "ls180.v:5695.85-5695.106" - cell $eq $eq$ls180.v:5695$1029 + attribute \src "ls180.v:5805.68-5805.89" + cell $eq $eq$ls180.v:5805$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249207,10 +250993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5695$1029_Y + connect \Y $eq$ls180.v:5805$1144_Y end - attribute \src "ls180.v:5696.85-5696.106" - cell $eq $eq$ls180.v:5696$1031 + attribute \src "ls180.v:5806.68-5806.89" + cell $eq $eq$ls180.v:5806$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249218,10 +251004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5696$1031_Y + connect \Y $eq$ls180.v:5806$1146_Y end - attribute \src "ls180.v:5697.85-5697.106" - cell $eq $eq$ls180.v:5697$1033 + attribute \src "ls180.v:5807.71-5807.92" + cell $eq $eq$ls180.v:5807$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249229,10 +251015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5697$1033_Y + connect \Y $eq$ls180.v:5807$1148_Y end - attribute \src "ls180.v:5698.57-5698.78" - cell $eq $eq$ls180.v:5698$1035 + attribute \src "ls180.v:5808.57-5808.78" + cell $eq $eq$ls180.v:5808$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249240,10 +251026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5698$1035_Y + connect \Y $eq$ls180.v:5808$1150_Y end - attribute \src "ls180.v:5699.57-5699.78" - cell $eq $eq$ls180.v:5699$1037 + attribute \src "ls180.v:5809.57-5809.78" + cell $eq $eq$ls180.v:5809$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249251,10 +251037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5699$1037_Y + connect \Y $eq$ls180.v:5809$1152_Y end - attribute \src "ls180.v:5700.85-5700.106" - cell $eq $eq$ls180.v:5700$1039 + attribute \src "ls180.v:5810.68-5810.89" + cell $eq $eq$ls180.v:5810$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249262,10 +251048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5700$1039_Y + connect \Y $eq$ls180.v:5810$1154_Y end - attribute \src "ls180.v:5701.85-5701.106" - cell $eq $eq$ls180.v:5701$1041 + attribute \src "ls180.v:5811.68-5811.89" + cell $eq $eq$ls180.v:5811$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249273,10 +251059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5701$1041_Y + connect \Y $eq$ls180.v:5811$1156_Y end - attribute \src "ls180.v:5702.85-5702.106" - cell $eq $eq$ls180.v:5702$1043 + attribute \src "ls180.v:5812.71-5812.92" + cell $eq $eq$ls180.v:5812$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249284,10 +251070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5702$1043_Y + connect \Y $eq$ls180.v:5812$1158_Y end - attribute \src "ls180.v:5703.57-5703.78" - cell $eq $eq$ls180.v:5703$1045 + attribute \src "ls180.v:5813.57-5813.78" + cell $eq $eq$ls180.v:5813$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249295,10 +251081,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5703$1045_Y + connect \Y $eq$ls180.v:5813$1160_Y end - attribute \src "ls180.v:5704.57-5704.78" - cell $eq $eq$ls180.v:5704$1047 + attribute \src "ls180.v:5814.57-5814.78" + cell $eq $eq$ls180.v:5814$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249306,65 +251092,98 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5704$1047_Y + connect \Y $eq$ls180.v:5814$1162_Y end - attribute \src "ls180.v:5708.27-5708.59" - cell $eq $eq$ls180.v:5708$1050 + attribute \src "ls180.v:5818.27-5818.59" + cell $eq $eq$ls180.v:5818$1165 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 21 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] + connect \A \builder_shared_adr [29:9] connect \B 1'0 - connect \Y $eq$ls180.v:5708$1050_Y + connect \Y $eq$ls180.v:5818$1165_Y + end + attribute \src "ls180.v:5819.27-5819.59" + cell $eq $eq$ls180.v:5819$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 1'1 + connect \Y $eq$ls180.v:5819$1166_Y + end + attribute \src "ls180.v:5820.27-5820.59" + cell $eq $eq$ls180.v:5820$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'10 + connect \Y $eq$ls180.v:5820$1167_Y end - attribute \src "ls180.v:5709.27-5709.68" - cell $eq $eq$ls180.v:5709$1051 + attribute \src "ls180.v:5821.27-5821.59" + cell $eq $eq$ls180.v:5821$1168 parameter \A_SIGNED 0 - parameter \A_WIDTH 27 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'11 + connect \Y $eq$ls180.v:5821$1168_Y + end + attribute \src "ls180.v:5822.27-5822.68" + cell $eq $eq$ls180.v:5822$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 28 parameter \B_SIGNED 0 parameter \B_WIDTH 27 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:3] + connect \A \builder_shared_adr [29:2] connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5709$1051_Y + connect \Y $eq$ls180.v:5822$1169_Y end - attribute \src "ls180.v:5710.27-5710.66" - cell $eq $eq$ls180.v:5710$1052 + attribute \src "ls180.v:5823.27-5823.65" + cell $eq $eq$ls180.v:5823$1170 parameter \A_SIGNED 0 - parameter \A_WIDTH 20 + parameter \A_WIDTH 21 parameter \B_SIGNED 0 parameter \B_WIDTH 20 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:10] + connect \A \builder_shared_adr [29:9] connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5710$1052_Y + connect \Y $eq$ls180.v:5823$1170_Y end - attribute \src "ls180.v:5711.27-5711.61" - cell $eq $eq$ls180.v:5711$1053 + attribute \src "ls180.v:5824.27-5824.61" + cell $eq $eq$ls180.v:5824$1171 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:23] + connect \A \builder_shared_adr [29:22] connect \B 7'1001000 - connect \Y $eq$ls180.v:5711$1053_Y + connect \Y $eq$ls180.v:5824$1171_Y end - attribute \src "ls180.v:5712.27-5712.65" - cell $eq $eq$ls180.v:5712$1054 + attribute \src "ls180.v:5825.27-5825.65" + cell $eq $eq$ls180.v:5825$1172 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 17 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:14] + connect \A \builder_shared_adr [29:13] connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5712$1054_Y + connect \Y $eq$ls180.v:5825$1172_Y end - attribute \src "ls180.v:5768.24-5768.45" - cell $eq $eq$ls180.v:5768$1081 + attribute \src "ls180.v:5905.24-5905.45" + cell $eq $eq$ls180.v:5905$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -249372,21 +251191,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_count connect \B 1'0 - connect \Y $eq$ls180.v:5768$1081_Y + connect \Y $eq$ls180.v:5905$1214_Y end - attribute \src "ls180.v:5769.32-5769.77" - cell $eq $eq$ls180.v:5769$1082 + attribute \src "ls180.v:5906.32-5906.77" + cell $eq $eq$ls180.v:5906$1215 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:9] + connect \A \builder_interface0_bank_bus_adr [13:8] connect \B 1'0 - connect \Y $eq$ls180.v:5769$1082_Y + connect \Y $eq$ls180.v:5906$1215_Y end - attribute \src "ls180.v:5771.97-5771.141" - cell $eq $eq$ls180.v:5771$1084 + attribute \src "ls180.v:5908.97-5908.141" + cell $eq $eq$ls180.v:5908$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249394,10 +251213,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5771$1084_Y + connect \Y $eq$ls180.v:5908$1217_Y end - attribute \src "ls180.v:5772.100-5772.144" - cell $eq $eq$ls180.v:5772$1088 + attribute \src "ls180.v:5909.100-5909.144" + cell $eq $eq$ls180.v:5909$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249405,10 +251224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5772$1088_Y + connect \Y $eq$ls180.v:5909$1221_Y end - attribute \src "ls180.v:5774.99-5774.143" - cell $eq $eq$ls180.v:5774$1091 + attribute \src "ls180.v:5911.99-5911.143" + cell $eq $eq$ls180.v:5911$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249416,10 +251235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5774$1091_Y + connect \Y $eq$ls180.v:5911$1224_Y end - attribute \src "ls180.v:5775.102-5775.146" - cell $eq $eq$ls180.v:5775$1095 + attribute \src "ls180.v:5912.102-5912.146" + cell $eq $eq$ls180.v:5912$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249427,10 +251246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5775$1095_Y + connect \Y $eq$ls180.v:5912$1228_Y end - attribute \src "ls180.v:5777.99-5777.143" - cell $eq $eq$ls180.v:5777$1098 + attribute \src "ls180.v:5914.99-5914.143" + cell $eq $eq$ls180.v:5914$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249438,10 +251257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5777$1098_Y + connect \Y $eq$ls180.v:5914$1231_Y end - attribute \src "ls180.v:5778.102-5778.146" - cell $eq $eq$ls180.v:5778$1102 + attribute \src "ls180.v:5915.102-5915.146" + cell $eq $eq$ls180.v:5915$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249449,10 +251268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5778$1102_Y + connect \Y $eq$ls180.v:5915$1235_Y end - attribute \src "ls180.v:5780.99-5780.143" - cell $eq $eq$ls180.v:5780$1105 + attribute \src "ls180.v:5917.99-5917.143" + cell $eq $eq$ls180.v:5917$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249460,10 +251279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5780$1105_Y + connect \Y $eq$ls180.v:5917$1238_Y end - attribute \src "ls180.v:5781.102-5781.146" - cell $eq $eq$ls180.v:5781$1109 + attribute \src "ls180.v:5918.102-5918.146" + cell $eq $eq$ls180.v:5918$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249471,10 +251290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5781$1109_Y + connect \Y $eq$ls180.v:5918$1242_Y end - attribute \src "ls180.v:5783.99-5783.143" - cell $eq $eq$ls180.v:5783$1112 + attribute \src "ls180.v:5920.99-5920.143" + cell $eq $eq$ls180.v:5920$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249482,10 +251301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5783$1112_Y + connect \Y $eq$ls180.v:5920$1245_Y end - attribute \src "ls180.v:5784.102-5784.146" - cell $eq $eq$ls180.v:5784$1116 + attribute \src "ls180.v:5921.102-5921.146" + cell $eq $eq$ls180.v:5921$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249493,10 +251312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5784$1116_Y + connect \Y $eq$ls180.v:5921$1249_Y end - attribute \src "ls180.v:5786.102-5786.146" - cell $eq $eq$ls180.v:5786$1119 + attribute \src "ls180.v:5923.102-5923.146" + cell $eq $eq$ls180.v:5923$1252 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249504,10 +251323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5786$1119_Y + connect \Y $eq$ls180.v:5923$1252_Y end - attribute \src "ls180.v:5787.105-5787.149" - cell $eq $eq$ls180.v:5787$1123 + attribute \src "ls180.v:5924.105-5924.149" + cell $eq $eq$ls180.v:5924$1256 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249515,10 +251334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5787$1123_Y + connect \Y $eq$ls180.v:5924$1256_Y end - attribute \src "ls180.v:5789.102-5789.146" - cell $eq $eq$ls180.v:5789$1126 + attribute \src "ls180.v:5926.102-5926.146" + cell $eq $eq$ls180.v:5926$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249526,10 +251345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5789$1126_Y + connect \Y $eq$ls180.v:5926$1259_Y end - attribute \src "ls180.v:5790.105-5790.149" - cell $eq $eq$ls180.v:5790$1130 + attribute \src "ls180.v:5927.105-5927.149" + cell $eq $eq$ls180.v:5927$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249537,10 +251356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5790$1130_Y + connect \Y $eq$ls180.v:5927$1263_Y end - attribute \src "ls180.v:5792.102-5792.146" - cell $eq $eq$ls180.v:5792$1133 + attribute \src "ls180.v:5929.102-5929.146" + cell $eq $eq$ls180.v:5929$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249548,10 +251367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5792$1133_Y + connect \Y $eq$ls180.v:5929$1266_Y end - attribute \src "ls180.v:5793.105-5793.149" - cell $eq $eq$ls180.v:5793$1137 + attribute \src "ls180.v:5930.105-5930.149" + cell $eq $eq$ls180.v:5930$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249559,10 +251378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5793$1137_Y + connect \Y $eq$ls180.v:5930$1270_Y end - attribute \src "ls180.v:5795.102-5795.146" - cell $eq $eq$ls180.v:5795$1140 + attribute \src "ls180.v:5932.102-5932.146" + cell $eq $eq$ls180.v:5932$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249570,10 +251389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5795$1140_Y + connect \Y $eq$ls180.v:5932$1273_Y end - attribute \src "ls180.v:5796.105-5796.149" - cell $eq $eq$ls180.v:5796$1144 + attribute \src "ls180.v:5933.105-5933.149" + cell $eq $eq$ls180.v:5933$1277 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249581,21 +251400,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5796$1144_Y + connect \Y $eq$ls180.v:5933$1277_Y end - attribute \src "ls180.v:5807.32-5807.77" - cell $eq $eq$ls180.v:5807$1146 + attribute \src "ls180.v:5944.32-5944.77" + cell $eq $eq$ls180.v:5944$1279 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:9] + connect \A \builder_interface1_bank_bus_adr [13:8] connect \B 3'110 - connect \Y $eq$ls180.v:5807$1146_Y + connect \Y $eq$ls180.v:5944$1279_Y end - attribute \src "ls180.v:5809.94-5809.138" - cell $eq $eq$ls180.v:5809$1148 + attribute \src "ls180.v:5946.94-5946.138" + cell $eq $eq$ls180.v:5946$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249603,10 +251422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5809$1148_Y + connect \Y $eq$ls180.v:5946$1281_Y end - attribute \src "ls180.v:5810.97-5810.141" - cell $eq $eq$ls180.v:5810$1152 + attribute \src "ls180.v:5947.97-5947.141" + cell $eq $eq$ls180.v:5947$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249614,10 +251433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5810$1152_Y + connect \Y $eq$ls180.v:5947$1285_Y end - attribute \src "ls180.v:5812.94-5812.138" - cell $eq $eq$ls180.v:5812$1155 + attribute \src "ls180.v:5949.94-5949.138" + cell $eq $eq$ls180.v:5949$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249625,10 +251444,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5812$1155_Y + connect \Y $eq$ls180.v:5949$1288_Y end - attribute \src "ls180.v:5813.97-5813.141" - cell $eq $eq$ls180.v:5813$1159 + attribute \src "ls180.v:5950.97-5950.141" + cell $eq $eq$ls180.v:5950$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249636,10 +251455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5813$1159_Y + connect \Y $eq$ls180.v:5950$1292_Y end - attribute \src "ls180.v:5815.94-5815.138" - cell $eq $eq$ls180.v:5815$1162 + attribute \src "ls180.v:5952.94-5952.138" + cell $eq $eq$ls180.v:5952$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249647,10 +251466,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5815$1162_Y + connect \Y $eq$ls180.v:5952$1295_Y end - attribute \src "ls180.v:5816.97-5816.141" - cell $eq $eq$ls180.v:5816$1166 + attribute \src "ls180.v:5953.97-5953.141" + cell $eq $eq$ls180.v:5953$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249658,10 +251477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5816$1166_Y + connect \Y $eq$ls180.v:5953$1299_Y end - attribute \src "ls180.v:5818.94-5818.138" - cell $eq $eq$ls180.v:5818$1169 + attribute \src "ls180.v:5955.94-5955.138" + cell $eq $eq$ls180.v:5955$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249669,10 +251488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5818$1169_Y + connect \Y $eq$ls180.v:5955$1302_Y end - attribute \src "ls180.v:5819.97-5819.141" - cell $eq $eq$ls180.v:5819$1173 + attribute \src "ls180.v:5956.97-5956.141" + cell $eq $eq$ls180.v:5956$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249680,10 +251499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5819$1173_Y + connect \Y $eq$ls180.v:5956$1306_Y end - attribute \src "ls180.v:5821.95-5821.139" - cell $eq $eq$ls180.v:5821$1176 + attribute \src "ls180.v:5958.95-5958.139" + cell $eq $eq$ls180.v:5958$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249691,10 +251510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5821$1176_Y + connect \Y $eq$ls180.v:5958$1309_Y end - attribute \src "ls180.v:5822.98-5822.142" - cell $eq $eq$ls180.v:5822$1180 + attribute \src "ls180.v:5959.98-5959.142" + cell $eq $eq$ls180.v:5959$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249702,10 +251521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5822$1180_Y + connect \Y $eq$ls180.v:5959$1313_Y end - attribute \src "ls180.v:5824.95-5824.139" - cell $eq $eq$ls180.v:5824$1183 + attribute \src "ls180.v:5961.95-5961.139" + cell $eq $eq$ls180.v:5961$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249713,10 +251532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5824$1183_Y + connect \Y $eq$ls180.v:5961$1316_Y end - attribute \src "ls180.v:5825.98-5825.142" - cell $eq $eq$ls180.v:5825$1187 + attribute \src "ls180.v:5962.98-5962.142" + cell $eq $eq$ls180.v:5962$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249724,21 +251543,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5825$1187_Y + connect \Y $eq$ls180.v:5962$1320_Y end - attribute \src "ls180.v:5833.32-5833.78" - cell $eq $eq$ls180.v:5833$1189 + attribute \src "ls180.v:5970.32-5970.78" + cell $eq $eq$ls180.v:5970$1322 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:9] + connect \A \builder_interface2_bank_bus_adr [13:8] connect \B 4'1011 - connect \Y $eq$ls180.v:5833$1189_Y + connect \Y $eq$ls180.v:5970$1322_Y end - attribute \src "ls180.v:5835.93-5835.135" - cell $eq $eq$ls180.v:5835$1191 + attribute \src "ls180.v:5972.93-5972.135" + cell $eq $eq$ls180.v:5972$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249746,10 +251565,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:5835$1191_Y + connect \Y $eq$ls180.v:5972$1324_Y end - attribute \src "ls180.v:5836.96-5836.138" - cell $eq $eq$ls180.v:5836$1195 + attribute \src "ls180.v:5973.96-5973.138" + cell $eq $eq$ls180.v:5973$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249757,10 +251576,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:5836$1195_Y + connect \Y $eq$ls180.v:5973$1328_Y end - attribute \src "ls180.v:5838.92-5838.134" - cell $eq $eq$ls180.v:5838$1198 + attribute \src "ls180.v:5975.92-5975.134" + cell $eq $eq$ls180.v:5975$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249768,10 +251587,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:5838$1198_Y + connect \Y $eq$ls180.v:5975$1331_Y end - attribute \src "ls180.v:5839.95-5839.137" - cell $eq $eq$ls180.v:5839$1202 + attribute \src "ls180.v:5976.95-5976.137" + cell $eq $eq$ls180.v:5976$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249779,21 +251598,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:5839$1202_Y + connect \Y $eq$ls180.v:5976$1335_Y end - attribute \src "ls180.v:5847.32-5847.77" - cell $eq $eq$ls180.v:5847$1204 + attribute \src "ls180.v:5984.32-5984.77" + cell $eq $eq$ls180.v:5984$1337 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:9] + connect \A \builder_interface3_bank_bus_adr [13:8] connect \B 4'1001 - connect \Y $eq$ls180.v:5847$1204_Y + connect \Y $eq$ls180.v:5984$1337_Y end - attribute \src "ls180.v:5849.98-5849.142" - cell $eq $eq$ls180.v:5849$1206 + attribute \src "ls180.v:5986.98-5986.142" + cell $eq $eq$ls180.v:5986$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249801,10 +251620,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5849$1206_Y + connect \Y $eq$ls180.v:5986$1339_Y end - attribute \src "ls180.v:5850.101-5850.145" - cell $eq $eq$ls180.v:5850$1210 + attribute \src "ls180.v:5987.101-5987.145" + cell $eq $eq$ls180.v:5987$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249812,10 +251631,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5850$1210_Y + connect \Y $eq$ls180.v:5987$1343_Y end - attribute \src "ls180.v:5852.97-5852.141" - cell $eq $eq$ls180.v:5852$1213 + attribute \src "ls180.v:5989.97-5989.141" + cell $eq $eq$ls180.v:5989$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249823,10 +251642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5852$1213_Y + connect \Y $eq$ls180.v:5989$1346_Y end - attribute \src "ls180.v:5853.100-5853.144" - cell $eq $eq$ls180.v:5853$1217 + attribute \src "ls180.v:5990.100-5990.144" + cell $eq $eq$ls180.v:5990$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249834,10 +251653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5853$1217_Y + connect \Y $eq$ls180.v:5990$1350_Y end - attribute \src "ls180.v:5855.97-5855.141" - cell $eq $eq$ls180.v:5855$1220 + attribute \src "ls180.v:5992.97-5992.141" + cell $eq $eq$ls180.v:5992$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249845,10 +251664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5855$1220_Y + connect \Y $eq$ls180.v:5992$1353_Y end - attribute \src "ls180.v:5856.100-5856.144" - cell $eq $eq$ls180.v:5856$1224 + attribute \src "ls180.v:5993.100-5993.144" + cell $eq $eq$ls180.v:5993$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249856,10 +251675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5856$1224_Y + connect \Y $eq$ls180.v:5993$1357_Y end - attribute \src "ls180.v:5858.97-5858.141" - cell $eq $eq$ls180.v:5858$1227 + attribute \src "ls180.v:5995.97-5995.141" + cell $eq $eq$ls180.v:5995$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249867,10 +251686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5858$1227_Y + connect \Y $eq$ls180.v:5995$1360_Y end - attribute \src "ls180.v:5859.100-5859.144" - cell $eq $eq$ls180.v:5859$1231 + attribute \src "ls180.v:5996.100-5996.144" + cell $eq $eq$ls180.v:5996$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249878,10 +251697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5859$1231_Y + connect \Y $eq$ls180.v:5996$1364_Y end - attribute \src "ls180.v:5861.97-5861.141" - cell $eq $eq$ls180.v:5861$1234 + attribute \src "ls180.v:5998.97-5998.141" + cell $eq $eq$ls180.v:5998$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249889,10 +251708,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5861$1234_Y + connect \Y $eq$ls180.v:5998$1367_Y end - attribute \src "ls180.v:5862.100-5862.144" - cell $eq $eq$ls180.v:5862$1238 + attribute \src "ls180.v:5999.100-5999.144" + cell $eq $eq$ls180.v:5999$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249900,10 +251719,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5862$1238_Y + connect \Y $eq$ls180.v:5999$1371_Y end - attribute \src "ls180.v:5864.98-5864.142" - cell $eq $eq$ls180.v:5864$1241 + attribute \src "ls180.v:6001.98-6001.142" + cell $eq $eq$ls180.v:6001$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249911,10 +251730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5864$1241_Y + connect \Y $eq$ls180.v:6001$1374_Y end - attribute \src "ls180.v:5865.101-5865.145" - cell $eq $eq$ls180.v:5865$1245 + attribute \src "ls180.v:6002.101-6002.145" + cell $eq $eq$ls180.v:6002$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249922,10 +251741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5865$1245_Y + connect \Y $eq$ls180.v:6002$1378_Y end - attribute \src "ls180.v:5867.98-5867.142" - cell $eq $eq$ls180.v:5867$1248 + attribute \src "ls180.v:6004.98-6004.142" + cell $eq $eq$ls180.v:6004$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249933,10 +251752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5867$1248_Y + connect \Y $eq$ls180.v:6004$1381_Y end - attribute \src "ls180.v:5868.101-5868.145" - cell $eq $eq$ls180.v:5868$1252 + attribute \src "ls180.v:6005.101-6005.145" + cell $eq $eq$ls180.v:6005$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249944,10 +251763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5868$1252_Y + connect \Y $eq$ls180.v:6005$1385_Y end - attribute \src "ls180.v:5870.98-5870.142" - cell $eq $eq$ls180.v:5870$1255 + attribute \src "ls180.v:6007.98-6007.142" + cell $eq $eq$ls180.v:6007$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249955,10 +251774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5870$1255_Y + connect \Y $eq$ls180.v:6007$1388_Y end - attribute \src "ls180.v:5871.101-5871.145" - cell $eq $eq$ls180.v:5871$1259 + attribute \src "ls180.v:6008.101-6008.145" + cell $eq $eq$ls180.v:6008$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249966,10 +251785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5871$1259_Y + connect \Y $eq$ls180.v:6008$1392_Y end - attribute \src "ls180.v:5873.98-5873.142" - cell $eq $eq$ls180.v:5873$1262 + attribute \src "ls180.v:6010.98-6010.142" + cell $eq $eq$ls180.v:6010$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249977,10 +251796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5873$1262_Y + connect \Y $eq$ls180.v:6010$1395_Y end - attribute \src "ls180.v:5874.101-5874.145" - cell $eq $eq$ls180.v:5874$1266 + attribute \src "ls180.v:6011.101-6011.145" + cell $eq $eq$ls180.v:6011$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249988,21 +251807,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5874$1266_Y + connect \Y $eq$ls180.v:6011$1399_Y end - attribute \src "ls180.v:5884.32-5884.78" - cell $eq $eq$ls180.v:5884$1268 + attribute \src "ls180.v:6021.32-6021.78" + cell $eq $eq$ls180.v:6021$1401 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:9] + connect \A \builder_interface4_bank_bus_adr [13:8] connect \B 4'1010 - connect \Y $eq$ls180.v:5884$1268_Y + connect \Y $eq$ls180.v:6021$1401_Y end - attribute \src "ls180.v:5886.98-5886.142" - cell $eq $eq$ls180.v:5886$1270 + attribute \src "ls180.v:6023.98-6023.142" + cell $eq $eq$ls180.v:6023$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250010,10 +251829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5886$1270_Y + connect \Y $eq$ls180.v:6023$1403_Y end - attribute \src "ls180.v:5887.101-5887.145" - cell $eq $eq$ls180.v:5887$1274 + attribute \src "ls180.v:6024.101-6024.145" + cell $eq $eq$ls180.v:6024$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250021,10 +251840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5887$1274_Y + connect \Y $eq$ls180.v:6024$1407_Y end - attribute \src "ls180.v:5889.97-5889.141" - cell $eq $eq$ls180.v:5889$1277 + attribute \src "ls180.v:6026.97-6026.141" + cell $eq $eq$ls180.v:6026$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250032,10 +251851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5889$1277_Y + connect \Y $eq$ls180.v:6026$1410_Y end - attribute \src "ls180.v:5890.100-5890.144" - cell $eq $eq$ls180.v:5890$1281 + attribute \src "ls180.v:6027.100-6027.144" + cell $eq $eq$ls180.v:6027$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250043,10 +251862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5890$1281_Y + connect \Y $eq$ls180.v:6027$1414_Y end - attribute \src "ls180.v:5892.97-5892.141" - cell $eq $eq$ls180.v:5892$1284 + attribute \src "ls180.v:6029.97-6029.141" + cell $eq $eq$ls180.v:6029$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250054,10 +251873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5892$1284_Y + connect \Y $eq$ls180.v:6029$1417_Y end - attribute \src "ls180.v:5893.100-5893.144" - cell $eq $eq$ls180.v:5893$1288 + attribute \src "ls180.v:6030.100-6030.144" + cell $eq $eq$ls180.v:6030$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250065,10 +251884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5893$1288_Y + connect \Y $eq$ls180.v:6030$1421_Y end - attribute \src "ls180.v:5895.97-5895.141" - cell $eq $eq$ls180.v:5895$1291 + attribute \src "ls180.v:6032.97-6032.141" + cell $eq $eq$ls180.v:6032$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250076,10 +251895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5895$1291_Y + connect \Y $eq$ls180.v:6032$1424_Y end - attribute \src "ls180.v:5896.100-5896.144" - cell $eq $eq$ls180.v:5896$1295 + attribute \src "ls180.v:6033.100-6033.144" + cell $eq $eq$ls180.v:6033$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250087,10 +251906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5896$1295_Y + connect \Y $eq$ls180.v:6033$1428_Y end - attribute \src "ls180.v:5898.97-5898.141" - cell $eq $eq$ls180.v:5898$1298 + attribute \src "ls180.v:6035.97-6035.141" + cell $eq $eq$ls180.v:6035$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250098,10 +251917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5898$1298_Y + connect \Y $eq$ls180.v:6035$1431_Y end - attribute \src "ls180.v:5899.100-5899.144" - cell $eq $eq$ls180.v:5899$1302 + attribute \src "ls180.v:6036.100-6036.144" + cell $eq $eq$ls180.v:6036$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250109,10 +251928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5899$1302_Y + connect \Y $eq$ls180.v:6036$1435_Y end - attribute \src "ls180.v:5901.98-5901.142" - cell $eq $eq$ls180.v:5901$1305 + attribute \src "ls180.v:6038.98-6038.142" + cell $eq $eq$ls180.v:6038$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250120,10 +251939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5901$1305_Y + connect \Y $eq$ls180.v:6038$1438_Y end - attribute \src "ls180.v:5902.101-5902.145" - cell $eq $eq$ls180.v:5902$1309 + attribute \src "ls180.v:6039.101-6039.145" + cell $eq $eq$ls180.v:6039$1442 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250131,10 +251950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5902$1309_Y + connect \Y $eq$ls180.v:6039$1442_Y end - attribute \src "ls180.v:5904.98-5904.142" - cell $eq $eq$ls180.v:5904$1312 + attribute \src "ls180.v:6041.98-6041.142" + cell $eq $eq$ls180.v:6041$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250142,10 +251961,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5904$1312_Y + connect \Y $eq$ls180.v:6041$1445_Y end - attribute \src "ls180.v:5905.101-5905.145" - cell $eq $eq$ls180.v:5905$1316 + attribute \src "ls180.v:6042.101-6042.145" + cell $eq $eq$ls180.v:6042$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250153,10 +251972,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5905$1316_Y + connect \Y $eq$ls180.v:6042$1449_Y end - attribute \src "ls180.v:5907.98-5907.142" - cell $eq $eq$ls180.v:5907$1319 + attribute \src "ls180.v:6044.98-6044.142" + cell $eq $eq$ls180.v:6044$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250164,10 +251983,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5907$1319_Y + connect \Y $eq$ls180.v:6044$1452_Y end - attribute \src "ls180.v:5908.101-5908.145" - cell $eq $eq$ls180.v:5908$1323 + attribute \src "ls180.v:6045.101-6045.145" + cell $eq $eq$ls180.v:6045$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250175,10 +251994,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5908$1323_Y + connect \Y $eq$ls180.v:6045$1456_Y end - attribute \src "ls180.v:5910.98-5910.142" - cell $eq $eq$ls180.v:5910$1326 + attribute \src "ls180.v:6047.98-6047.142" + cell $eq $eq$ls180.v:6047$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250186,10 +252005,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5910$1326_Y + connect \Y $eq$ls180.v:6047$1459_Y end - attribute \src "ls180.v:5911.101-5911.145" - cell $eq $eq$ls180.v:5911$1330 + attribute \src "ls180.v:6048.101-6048.145" + cell $eq $eq$ls180.v:6048$1463 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250197,21 +252016,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5911$1330_Y + connect \Y $eq$ls180.v:6048$1463_Y end - attribute \src "ls180.v:5921.32-5921.78" - cell $eq $eq$ls180.v:5921$1332 + attribute \src "ls180.v:6058.32-6058.78" + cell $eq $eq$ls180.v:6058$1465 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:9] + connect \A \builder_interface5_bank_bus_adr [13:8] connect \B 4'1110 - connect \Y $eq$ls180.v:5921$1332_Y + connect \Y $eq$ls180.v:6058$1465_Y end - attribute \src "ls180.v:5923.100-5923.144" - cell $eq $eq$ls180.v:5923$1334 + attribute \src "ls180.v:6060.100-6060.144" + cell $eq $eq$ls180.v:6060$1467 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250219,10 +252038,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5923$1334_Y + connect \Y $eq$ls180.v:6060$1467_Y end - attribute \src "ls180.v:5924.103-5924.147" - cell $eq $eq$ls180.v:5924$1338 + attribute \src "ls180.v:6061.103-6061.147" + cell $eq $eq$ls180.v:6061$1471 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250230,10 +252049,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5924$1338_Y + connect \Y $eq$ls180.v:6061$1471_Y end - attribute \src "ls180.v:5926.100-5926.144" - cell $eq $eq$ls180.v:5926$1341 + attribute \src "ls180.v:6063.100-6063.144" + cell $eq $eq$ls180.v:6063$1474 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250241,10 +252060,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5926$1341_Y + connect \Y $eq$ls180.v:6063$1474_Y end - attribute \src "ls180.v:5927.103-5927.147" - cell $eq $eq$ls180.v:5927$1345 + attribute \src "ls180.v:6064.103-6064.147" + cell $eq $eq$ls180.v:6064$1478 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250252,10 +252071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5927$1345_Y + connect \Y $eq$ls180.v:6064$1478_Y end - attribute \src "ls180.v:5929.100-5929.144" - cell $eq $eq$ls180.v:5929$1348 + attribute \src "ls180.v:6066.100-6066.144" + cell $eq $eq$ls180.v:6066$1481 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250263,10 +252082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5929$1348_Y + connect \Y $eq$ls180.v:6066$1481_Y end - attribute \src "ls180.v:5930.103-5930.147" - cell $eq $eq$ls180.v:5930$1352 + attribute \src "ls180.v:6067.103-6067.147" + cell $eq $eq$ls180.v:6067$1485 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250274,10 +252093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5930$1352_Y + connect \Y $eq$ls180.v:6067$1485_Y end - attribute \src "ls180.v:5932.100-5932.144" - cell $eq $eq$ls180.v:5932$1355 + attribute \src "ls180.v:6069.100-6069.144" + cell $eq $eq$ls180.v:6069$1488 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250285,10 +252104,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5932$1355_Y + connect \Y $eq$ls180.v:6069$1488_Y end - attribute \src "ls180.v:5933.103-5933.147" - cell $eq $eq$ls180.v:5933$1359 + attribute \src "ls180.v:6070.103-6070.147" + cell $eq $eq$ls180.v:6070$1492 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250296,10 +252115,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5933$1359_Y + connect \Y $eq$ls180.v:6070$1492_Y end - attribute \src "ls180.v:5935.100-5935.144" - cell $eq $eq$ls180.v:5935$1362 + attribute \src "ls180.v:6072.100-6072.144" + cell $eq $eq$ls180.v:6072$1495 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250307,10 +252126,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5935$1362_Y + connect \Y $eq$ls180.v:6072$1495_Y end - attribute \src "ls180.v:5936.103-5936.147" - cell $eq $eq$ls180.v:5936$1366 + attribute \src "ls180.v:6073.103-6073.147" + cell $eq $eq$ls180.v:6073$1499 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250318,10 +252137,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5936$1366_Y + connect \Y $eq$ls180.v:6073$1499_Y end - attribute \src "ls180.v:5938.100-5938.144" - cell $eq $eq$ls180.v:5938$1369 + attribute \src "ls180.v:6075.100-6075.144" + cell $eq $eq$ls180.v:6075$1502 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250329,10 +252148,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5938$1369_Y + connect \Y $eq$ls180.v:6075$1502_Y end - attribute \src "ls180.v:5939.103-5939.147" - cell $eq $eq$ls180.v:5939$1373 + attribute \src "ls180.v:6076.103-6076.147" + cell $eq $eq$ls180.v:6076$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250340,10 +252159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5939$1373_Y + connect \Y $eq$ls180.v:6076$1506_Y end - attribute \src "ls180.v:5941.100-5941.144" - cell $eq $eq$ls180.v:5941$1376 + attribute \src "ls180.v:6078.100-6078.144" + cell $eq $eq$ls180.v:6078$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250351,10 +252170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5941$1376_Y + connect \Y $eq$ls180.v:6078$1509_Y end - attribute \src "ls180.v:5942.103-5942.147" - cell $eq $eq$ls180.v:5942$1380 + attribute \src "ls180.v:6079.103-6079.147" + cell $eq $eq$ls180.v:6079$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250362,10 +252181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5942$1380_Y + connect \Y $eq$ls180.v:6079$1513_Y end - attribute \src "ls180.v:5944.100-5944.144" - cell $eq $eq$ls180.v:5944$1383 + attribute \src "ls180.v:6081.100-6081.144" + cell $eq $eq$ls180.v:6081$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250373,10 +252192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5944$1383_Y + connect \Y $eq$ls180.v:6081$1516_Y end - attribute \src "ls180.v:5945.103-5945.147" - cell $eq $eq$ls180.v:5945$1387 + attribute \src "ls180.v:6082.103-6082.147" + cell $eq $eq$ls180.v:6082$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250384,10 +252203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5945$1387_Y + connect \Y $eq$ls180.v:6082$1520_Y end - attribute \src "ls180.v:5947.102-5947.146" - cell $eq $eq$ls180.v:5947$1390 + attribute \src "ls180.v:6084.102-6084.146" + cell $eq $eq$ls180.v:6084$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250395,10 +252214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5947$1390_Y + connect \Y $eq$ls180.v:6084$1523_Y end - attribute \src "ls180.v:5948.105-5948.149" - cell $eq $eq$ls180.v:5948$1394 + attribute \src "ls180.v:6085.105-6085.149" + cell $eq $eq$ls180.v:6085$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250406,10 +252225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5948$1394_Y + connect \Y $eq$ls180.v:6085$1527_Y end - attribute \src "ls180.v:5950.102-5950.146" - cell $eq $eq$ls180.v:5950$1397 + attribute \src "ls180.v:6087.102-6087.146" + cell $eq $eq$ls180.v:6087$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250417,10 +252236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5950$1397_Y + connect \Y $eq$ls180.v:6087$1530_Y end - attribute \src "ls180.v:5951.105-5951.149" - cell $eq $eq$ls180.v:5951$1401 + attribute \src "ls180.v:6088.105-6088.149" + cell $eq $eq$ls180.v:6088$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250428,10 +252247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5951$1401_Y + connect \Y $eq$ls180.v:6088$1534_Y end - attribute \src "ls180.v:5953.102-5953.147" - cell $eq $eq$ls180.v:5953$1404 + attribute \src "ls180.v:6090.102-6090.147" + cell $eq $eq$ls180.v:6090$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250439,10 +252258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5953$1404_Y + connect \Y $eq$ls180.v:6090$1537_Y end - attribute \src "ls180.v:5954.105-5954.150" - cell $eq $eq$ls180.v:5954$1408 + attribute \src "ls180.v:6091.105-6091.150" + cell $eq $eq$ls180.v:6091$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250450,10 +252269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5954$1408_Y + connect \Y $eq$ls180.v:6091$1541_Y end - attribute \src "ls180.v:5956.102-5956.147" - cell $eq $eq$ls180.v:5956$1411 + attribute \src "ls180.v:6093.102-6093.147" + cell $eq $eq$ls180.v:6093$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250461,10 +252280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5956$1411_Y + connect \Y $eq$ls180.v:6093$1544_Y end - attribute \src "ls180.v:5957.105-5957.150" - cell $eq $eq$ls180.v:5957$1415 + attribute \src "ls180.v:6094.105-6094.150" + cell $eq $eq$ls180.v:6094$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250472,10 +252291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5957$1415_Y + connect \Y $eq$ls180.v:6094$1548_Y end - attribute \src "ls180.v:5959.102-5959.147" - cell $eq $eq$ls180.v:5959$1418 + attribute \src "ls180.v:6096.102-6096.147" + cell $eq $eq$ls180.v:6096$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250483,10 +252302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5959$1418_Y + connect \Y $eq$ls180.v:6096$1551_Y end - attribute \src "ls180.v:5960.105-5960.150" - cell $eq $eq$ls180.v:5960$1422 + attribute \src "ls180.v:6097.105-6097.150" + cell $eq $eq$ls180.v:6097$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250494,10 +252313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5960$1422_Y + connect \Y $eq$ls180.v:6097$1555_Y end - attribute \src "ls180.v:5962.99-5962.144" - cell $eq $eq$ls180.v:5962$1425 + attribute \src "ls180.v:6099.99-6099.144" + cell $eq $eq$ls180.v:6099$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250505,10 +252324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5962$1425_Y + connect \Y $eq$ls180.v:6099$1558_Y end - attribute \src "ls180.v:5963.102-5963.147" - cell $eq $eq$ls180.v:5963$1429 + attribute \src "ls180.v:6100.102-6100.147" + cell $eq $eq$ls180.v:6100$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250516,10 +252335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5963$1429_Y + connect \Y $eq$ls180.v:6100$1562_Y end - attribute \src "ls180.v:5965.100-5965.145" - cell $eq $eq$ls180.v:5965$1432 + attribute \src "ls180.v:6102.100-6102.145" + cell $eq $eq$ls180.v:6102$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250527,10 +252346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5965$1432_Y + connect \Y $eq$ls180.v:6102$1565_Y end - attribute \src "ls180.v:5966.103-5966.148" - cell $eq $eq$ls180.v:5966$1436 + attribute \src "ls180.v:6103.103-6103.148" + cell $eq $eq$ls180.v:6103$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250538,21 +252357,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5966$1436_Y + connect \Y $eq$ls180.v:6103$1569_Y end - attribute \src "ls180.v:5983.32-5983.78" - cell $eq $eq$ls180.v:5983$1438 + attribute \src "ls180.v:6120.32-6120.78" + cell $eq $eq$ls180.v:6120$1571 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:9] + connect \A \builder_interface6_bank_bus_adr [13:8] connect \B 4'1101 - connect \Y $eq$ls180.v:5983$1438_Y + connect \Y $eq$ls180.v:6120$1571_Y end - attribute \src "ls180.v:5985.104-5985.148" - cell $eq $eq$ls180.v:5985$1440 + attribute \src "ls180.v:6122.104-6122.148" + cell $eq $eq$ls180.v:6122$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250560,10 +252379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:5985$1440_Y + connect \Y $eq$ls180.v:6122$1573_Y end - attribute \src "ls180.v:5986.107-5986.151" - cell $eq $eq$ls180.v:5986$1444 + attribute \src "ls180.v:6123.107-6123.151" + cell $eq $eq$ls180.v:6123$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250571,10 +252390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:5986$1444_Y + connect \Y $eq$ls180.v:6123$1577_Y end - attribute \src "ls180.v:5988.104-5988.148" - cell $eq $eq$ls180.v:5988$1447 + attribute \src "ls180.v:6125.104-6125.148" + cell $eq $eq$ls180.v:6125$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250582,10 +252401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:5988$1447_Y + connect \Y $eq$ls180.v:6125$1580_Y end - attribute \src "ls180.v:5989.107-5989.151" - cell $eq $eq$ls180.v:5989$1451 + attribute \src "ls180.v:6126.107-6126.151" + cell $eq $eq$ls180.v:6126$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250593,10 +252412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:5989$1451_Y + connect \Y $eq$ls180.v:6126$1584_Y end - attribute \src "ls180.v:5991.104-5991.148" - cell $eq $eq$ls180.v:5991$1454 + attribute \src "ls180.v:6128.104-6128.148" + cell $eq $eq$ls180.v:6128$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250604,10 +252423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:5991$1454_Y + connect \Y $eq$ls180.v:6128$1587_Y end - attribute \src "ls180.v:5992.107-5992.151" - cell $eq $eq$ls180.v:5992$1458 + attribute \src "ls180.v:6129.107-6129.151" + cell $eq $eq$ls180.v:6129$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250615,10 +252434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:5992$1458_Y + connect \Y $eq$ls180.v:6129$1591_Y end - attribute \src "ls180.v:5994.104-5994.148" - cell $eq $eq$ls180.v:5994$1461 + attribute \src "ls180.v:6131.104-6131.148" + cell $eq $eq$ls180.v:6131$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250626,10 +252445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:5994$1461_Y + connect \Y $eq$ls180.v:6131$1594_Y end - attribute \src "ls180.v:5995.107-5995.151" - cell $eq $eq$ls180.v:5995$1465 + attribute \src "ls180.v:6132.107-6132.151" + cell $eq $eq$ls180.v:6132$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250637,10 +252456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:5995$1465_Y + connect \Y $eq$ls180.v:6132$1598_Y end - attribute \src "ls180.v:5997.103-5997.147" - cell $eq $eq$ls180.v:5997$1468 + attribute \src "ls180.v:6134.103-6134.147" + cell $eq $eq$ls180.v:6134$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250648,10 +252467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:5997$1468_Y + connect \Y $eq$ls180.v:6134$1601_Y end - attribute \src "ls180.v:5998.106-5998.150" - cell $eq $eq$ls180.v:5998$1472 + attribute \src "ls180.v:6135.106-6135.150" + cell $eq $eq$ls180.v:6135$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250659,10 +252478,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:5998$1472_Y + connect \Y $eq$ls180.v:6135$1605_Y end - attribute \src "ls180.v:6000.103-6000.147" - cell $eq $eq$ls180.v:6000$1475 + attribute \src "ls180.v:6137.103-6137.147" + cell $eq $eq$ls180.v:6137$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250670,10 +252489,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6000$1475_Y + connect \Y $eq$ls180.v:6137$1608_Y end - attribute \src "ls180.v:6001.106-6001.150" - cell $eq $eq$ls180.v:6001$1479 + attribute \src "ls180.v:6138.106-6138.150" + cell $eq $eq$ls180.v:6138$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250681,10 +252500,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6001$1479_Y + connect \Y $eq$ls180.v:6138$1612_Y end - attribute \src "ls180.v:6003.103-6003.147" - cell $eq $eq$ls180.v:6003$1482 + attribute \src "ls180.v:6140.103-6140.147" + cell $eq $eq$ls180.v:6140$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250692,10 +252511,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6003$1482_Y + connect \Y $eq$ls180.v:6140$1615_Y end - attribute \src "ls180.v:6004.106-6004.150" - cell $eq $eq$ls180.v:6004$1486 + attribute \src "ls180.v:6141.106-6141.150" + cell $eq $eq$ls180.v:6141$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250703,10 +252522,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6004$1486_Y + connect \Y $eq$ls180.v:6141$1619_Y end - attribute \src "ls180.v:6006.103-6006.147" - cell $eq $eq$ls180.v:6006$1489 + attribute \src "ls180.v:6143.103-6143.147" + cell $eq $eq$ls180.v:6143$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250714,10 +252533,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6006$1489_Y + connect \Y $eq$ls180.v:6143$1622_Y end - attribute \src "ls180.v:6007.106-6007.150" - cell $eq $eq$ls180.v:6007$1493 + attribute \src "ls180.v:6144.106-6144.150" + cell $eq $eq$ls180.v:6144$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250725,10 +252544,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6007$1493_Y + connect \Y $eq$ls180.v:6144$1626_Y end - attribute \src "ls180.v:6009.94-6009.138" - cell $eq $eq$ls180.v:6009$1496 + attribute \src "ls180.v:6146.94-6146.138" + cell $eq $eq$ls180.v:6146$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250736,10 +252555,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6009$1496_Y + connect \Y $eq$ls180.v:6146$1629_Y end - attribute \src "ls180.v:6010.97-6010.141" - cell $eq $eq$ls180.v:6010$1500 + attribute \src "ls180.v:6147.97-6147.141" + cell $eq $eq$ls180.v:6147$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250747,10 +252566,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6010$1500_Y + connect \Y $eq$ls180.v:6147$1633_Y end - attribute \src "ls180.v:6012.105-6012.149" - cell $eq $eq$ls180.v:6012$1503 + attribute \src "ls180.v:6149.105-6149.149" + cell $eq $eq$ls180.v:6149$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250758,10 +252577,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6012$1503_Y + connect \Y $eq$ls180.v:6149$1636_Y end - attribute \src "ls180.v:6013.108-6013.152" - cell $eq $eq$ls180.v:6013$1507 + attribute \src "ls180.v:6150.108-6150.152" + cell $eq $eq$ls180.v:6150$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250769,10 +252588,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6013$1507_Y + connect \Y $eq$ls180.v:6150$1640_Y end - attribute \src "ls180.v:6015.105-6015.150" - cell $eq $eq$ls180.v:6015$1510 + attribute \src "ls180.v:6152.105-6152.150" + cell $eq $eq$ls180.v:6152$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250780,10 +252599,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6015$1510_Y + connect \Y $eq$ls180.v:6152$1643_Y end - attribute \src "ls180.v:6016.108-6016.153" - cell $eq $eq$ls180.v:6016$1514 + attribute \src "ls180.v:6153.108-6153.153" + cell $eq $eq$ls180.v:6153$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250791,10 +252610,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6016$1514_Y + connect \Y $eq$ls180.v:6153$1647_Y end - attribute \src "ls180.v:6018.105-6018.150" - cell $eq $eq$ls180.v:6018$1517 + attribute \src "ls180.v:6155.105-6155.150" + cell $eq $eq$ls180.v:6155$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250802,10 +252621,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6018$1517_Y + connect \Y $eq$ls180.v:6155$1650_Y end - attribute \src "ls180.v:6019.108-6019.153" - cell $eq $eq$ls180.v:6019$1521 + attribute \src "ls180.v:6156.108-6156.153" + cell $eq $eq$ls180.v:6156$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250813,10 +252632,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6019$1521_Y + connect \Y $eq$ls180.v:6156$1654_Y end - attribute \src "ls180.v:6021.105-6021.150" - cell $eq $eq$ls180.v:6021$1524 + attribute \src "ls180.v:6158.105-6158.150" + cell $eq $eq$ls180.v:6158$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250824,10 +252643,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6021$1524_Y + connect \Y $eq$ls180.v:6158$1657_Y end - attribute \src "ls180.v:6022.108-6022.153" - cell $eq $eq$ls180.v:6022$1528 + attribute \src "ls180.v:6159.108-6159.153" + cell $eq $eq$ls180.v:6159$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250835,10 +252654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6022$1528_Y + connect \Y $eq$ls180.v:6159$1661_Y end - attribute \src "ls180.v:6024.105-6024.150" - cell $eq $eq$ls180.v:6024$1531 + attribute \src "ls180.v:6161.105-6161.150" + cell $eq $eq$ls180.v:6161$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250846,10 +252665,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6024$1531_Y + connect \Y $eq$ls180.v:6161$1664_Y end - attribute \src "ls180.v:6025.108-6025.153" - cell $eq $eq$ls180.v:6025$1535 + attribute \src "ls180.v:6162.108-6162.153" + cell $eq $eq$ls180.v:6162$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250857,10 +252676,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6025$1535_Y + connect \Y $eq$ls180.v:6162$1668_Y end - attribute \src "ls180.v:6027.105-6027.150" - cell $eq $eq$ls180.v:6027$1538 + attribute \src "ls180.v:6164.105-6164.150" + cell $eq $eq$ls180.v:6164$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250868,10 +252687,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6027$1538_Y + connect \Y $eq$ls180.v:6164$1671_Y end - attribute \src "ls180.v:6028.108-6028.153" - cell $eq $eq$ls180.v:6028$1542 + attribute \src "ls180.v:6165.108-6165.153" + cell $eq $eq$ls180.v:6165$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250879,10 +252698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6028$1542_Y + connect \Y $eq$ls180.v:6165$1675_Y end - attribute \src "ls180.v:6030.104-6030.149" - cell $eq $eq$ls180.v:6030$1545 + attribute \src "ls180.v:6167.104-6167.149" + cell $eq $eq$ls180.v:6167$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250890,10 +252709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6030$1545_Y + connect \Y $eq$ls180.v:6167$1678_Y end - attribute \src "ls180.v:6031.107-6031.152" - cell $eq $eq$ls180.v:6031$1549 + attribute \src "ls180.v:6168.107-6168.152" + cell $eq $eq$ls180.v:6168$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250901,10 +252720,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6031$1549_Y + connect \Y $eq$ls180.v:6168$1682_Y end - attribute \src "ls180.v:6033.104-6033.149" - cell $eq $eq$ls180.v:6033$1552 + attribute \src "ls180.v:6170.104-6170.149" + cell $eq $eq$ls180.v:6170$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250912,10 +252731,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6033$1552_Y + connect \Y $eq$ls180.v:6170$1685_Y end - attribute \src "ls180.v:6034.107-6034.152" - cell $eq $eq$ls180.v:6034$1556 + attribute \src "ls180.v:6171.107-6171.152" + cell $eq $eq$ls180.v:6171$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250923,10 +252742,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6034$1556_Y + connect \Y $eq$ls180.v:6171$1689_Y end - attribute \src "ls180.v:6036.104-6036.149" - cell $eq $eq$ls180.v:6036$1559 + attribute \src "ls180.v:6173.104-6173.149" + cell $eq $eq$ls180.v:6173$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250934,10 +252753,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6036$1559_Y + connect \Y $eq$ls180.v:6173$1692_Y end - attribute \src "ls180.v:6037.107-6037.152" - cell $eq $eq$ls180.v:6037$1563 + attribute \src "ls180.v:6174.107-6174.152" + cell $eq $eq$ls180.v:6174$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250945,10 +252764,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6037$1563_Y + connect \Y $eq$ls180.v:6174$1696_Y end - attribute \src "ls180.v:6039.104-6039.149" - cell $eq $eq$ls180.v:6039$1566 + attribute \src "ls180.v:6176.104-6176.149" + cell $eq $eq$ls180.v:6176$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250956,10 +252775,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6039$1566_Y + connect \Y $eq$ls180.v:6176$1699_Y end - attribute \src "ls180.v:6040.107-6040.152" - cell $eq $eq$ls180.v:6040$1570 + attribute \src "ls180.v:6177.107-6177.152" + cell $eq $eq$ls180.v:6177$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250967,10 +252786,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6040$1570_Y + connect \Y $eq$ls180.v:6177$1703_Y end - attribute \src "ls180.v:6042.104-6042.149" - cell $eq $eq$ls180.v:6042$1573 + attribute \src "ls180.v:6179.104-6179.149" + cell $eq $eq$ls180.v:6179$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250978,10 +252797,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6042$1573_Y + connect \Y $eq$ls180.v:6179$1706_Y end - attribute \src "ls180.v:6043.107-6043.152" - cell $eq $eq$ls180.v:6043$1577 + attribute \src "ls180.v:6180.107-6180.152" + cell $eq $eq$ls180.v:6180$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250989,10 +252808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6043$1577_Y + connect \Y $eq$ls180.v:6180$1710_Y end - attribute \src "ls180.v:6045.104-6045.149" - cell $eq $eq$ls180.v:6045$1580 + attribute \src "ls180.v:6182.104-6182.149" + cell $eq $eq$ls180.v:6182$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251000,10 +252819,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6045$1580_Y + connect \Y $eq$ls180.v:6182$1713_Y end - attribute \src "ls180.v:6046.107-6046.152" - cell $eq $eq$ls180.v:6046$1584 + attribute \src "ls180.v:6183.107-6183.152" + cell $eq $eq$ls180.v:6183$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251011,10 +252830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6046$1584_Y + connect \Y $eq$ls180.v:6183$1717_Y end - attribute \src "ls180.v:6048.104-6048.149" - cell $eq $eq$ls180.v:6048$1587 + attribute \src "ls180.v:6185.104-6185.149" + cell $eq $eq$ls180.v:6185$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251022,10 +252841,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6048$1587_Y + connect \Y $eq$ls180.v:6185$1720_Y end - attribute \src "ls180.v:6049.107-6049.152" - cell $eq $eq$ls180.v:6049$1591 + attribute \src "ls180.v:6186.107-6186.152" + cell $eq $eq$ls180.v:6186$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251033,10 +252852,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6049$1591_Y + connect \Y $eq$ls180.v:6186$1724_Y end - attribute \src "ls180.v:6051.104-6051.149" - cell $eq $eq$ls180.v:6051$1594 + attribute \src "ls180.v:6188.104-6188.149" + cell $eq $eq$ls180.v:6188$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251044,10 +252863,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6051$1594_Y + connect \Y $eq$ls180.v:6188$1727_Y end - attribute \src "ls180.v:6052.107-6052.152" - cell $eq $eq$ls180.v:6052$1598 + attribute \src "ls180.v:6189.107-6189.152" + cell $eq $eq$ls180.v:6189$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251055,10 +252874,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6052$1598_Y + connect \Y $eq$ls180.v:6189$1731_Y end - attribute \src "ls180.v:6054.104-6054.149" - cell $eq $eq$ls180.v:6054$1601 + attribute \src "ls180.v:6191.104-6191.149" + cell $eq $eq$ls180.v:6191$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251066,10 +252885,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6054$1601_Y + connect \Y $eq$ls180.v:6191$1734_Y end - attribute \src "ls180.v:6055.107-6055.152" - cell $eq $eq$ls180.v:6055$1605 + attribute \src "ls180.v:6192.107-6192.152" + cell $eq $eq$ls180.v:6192$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251077,10 +252896,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6055$1605_Y + connect \Y $eq$ls180.v:6192$1738_Y end - attribute \src "ls180.v:6057.104-6057.149" - cell $eq $eq$ls180.v:6057$1608 + attribute \src "ls180.v:6194.104-6194.149" + cell $eq $eq$ls180.v:6194$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251088,10 +252907,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6057$1608_Y + connect \Y $eq$ls180.v:6194$1741_Y end - attribute \src "ls180.v:6058.107-6058.152" - cell $eq $eq$ls180.v:6058$1612 + attribute \src "ls180.v:6195.107-6195.152" + cell $eq $eq$ls180.v:6195$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251099,10 +252918,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6058$1612_Y + connect \Y $eq$ls180.v:6195$1745_Y end - attribute \src "ls180.v:6060.100-6060.145" - cell $eq $eq$ls180.v:6060$1615 + attribute \src "ls180.v:6197.100-6197.145" + cell $eq $eq$ls180.v:6197$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251110,10 +252929,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6060$1615_Y + connect \Y $eq$ls180.v:6197$1748_Y end - attribute \src "ls180.v:6061.103-6061.148" - cell $eq $eq$ls180.v:6061$1619 + attribute \src "ls180.v:6198.103-6198.148" + cell $eq $eq$ls180.v:6198$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251121,10 +252940,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6061$1619_Y + connect \Y $eq$ls180.v:6198$1752_Y end - attribute \src "ls180.v:6063.101-6063.146" - cell $eq $eq$ls180.v:6063$1622 + attribute \src "ls180.v:6200.101-6200.146" + cell $eq $eq$ls180.v:6200$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251132,10 +252951,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6063$1622_Y + connect \Y $eq$ls180.v:6200$1755_Y end - attribute \src "ls180.v:6064.104-6064.149" - cell $eq $eq$ls180.v:6064$1626 + attribute \src "ls180.v:6201.104-6201.149" + cell $eq $eq$ls180.v:6201$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251143,10 +252962,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6064$1626_Y + connect \Y $eq$ls180.v:6201$1759_Y end - attribute \src "ls180.v:6066.104-6066.149" - cell $eq $eq$ls180.v:6066$1629 + attribute \src "ls180.v:6203.104-6203.149" + cell $eq $eq$ls180.v:6203$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251154,10 +252973,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6066$1629_Y + connect \Y $eq$ls180.v:6203$1762_Y end - attribute \src "ls180.v:6067.107-6067.152" - cell $eq $eq$ls180.v:6067$1633 + attribute \src "ls180.v:6204.107-6204.152" + cell $eq $eq$ls180.v:6204$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251165,10 +252984,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6067$1633_Y + connect \Y $eq$ls180.v:6204$1766_Y end - attribute \src "ls180.v:6069.104-6069.149" - cell $eq $eq$ls180.v:6069$1636 + attribute \src "ls180.v:6206.104-6206.149" + cell $eq $eq$ls180.v:6206$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251176,10 +252995,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6069$1636_Y + connect \Y $eq$ls180.v:6206$1769_Y end - attribute \src "ls180.v:6070.107-6070.152" - cell $eq $eq$ls180.v:6070$1640 + attribute \src "ls180.v:6207.107-6207.152" + cell $eq $eq$ls180.v:6207$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251187,10 +253006,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6070$1640_Y + connect \Y $eq$ls180.v:6207$1773_Y end - attribute \src "ls180.v:6072.103-6072.148" - cell $eq $eq$ls180.v:6072$1643 + attribute \src "ls180.v:6209.103-6209.148" + cell $eq $eq$ls180.v:6209$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251198,10 +253017,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6072$1643_Y + connect \Y $eq$ls180.v:6209$1776_Y end - attribute \src "ls180.v:6073.106-6073.151" - cell $eq $eq$ls180.v:6073$1647 + attribute \src "ls180.v:6210.106-6210.151" + cell $eq $eq$ls180.v:6210$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251209,10 +253028,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6073$1647_Y + connect \Y $eq$ls180.v:6210$1780_Y end - attribute \src "ls180.v:6075.103-6075.148" - cell $eq $eq$ls180.v:6075$1650 + attribute \src "ls180.v:6212.103-6212.148" + cell $eq $eq$ls180.v:6212$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251220,10 +253039,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6075$1650_Y + connect \Y $eq$ls180.v:6212$1783_Y end - attribute \src "ls180.v:6076.106-6076.151" - cell $eq $eq$ls180.v:6076$1654 + attribute \src "ls180.v:6213.106-6213.151" + cell $eq $eq$ls180.v:6213$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251231,10 +253050,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6076$1654_Y + connect \Y $eq$ls180.v:6213$1787_Y end - attribute \src "ls180.v:6078.103-6078.148" - cell $eq $eq$ls180.v:6078$1657 + attribute \src "ls180.v:6215.103-6215.148" + cell $eq $eq$ls180.v:6215$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251242,10 +253061,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6078$1657_Y + connect \Y $eq$ls180.v:6215$1790_Y end - attribute \src "ls180.v:6079.106-6079.151" - cell $eq $eq$ls180.v:6079$1661 + attribute \src "ls180.v:6216.106-6216.151" + cell $eq $eq$ls180.v:6216$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251253,10 +253072,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6079$1661_Y + connect \Y $eq$ls180.v:6216$1794_Y end - attribute \src "ls180.v:6081.103-6081.148" - cell $eq $eq$ls180.v:6081$1664 + attribute \src "ls180.v:6218.103-6218.148" + cell $eq $eq$ls180.v:6218$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251264,10 +253083,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6081$1664_Y + connect \Y $eq$ls180.v:6218$1797_Y end - attribute \src "ls180.v:6082.106-6082.151" - cell $eq $eq$ls180.v:6082$1668 + attribute \src "ls180.v:6219.106-6219.151" + cell $eq $eq$ls180.v:6219$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251275,21 +253094,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6082$1668_Y + connect \Y $eq$ls180.v:6219$1801_Y end - attribute \src "ls180.v:6118.32-6118.78" - cell $eq $eq$ls180.v:6118$1670 + attribute \src "ls180.v:6255.32-6255.78" + cell $eq $eq$ls180.v:6255$1803 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:9] + connect \A \builder_interface7_bank_bus_adr [13:8] connect \B 4'1111 - connect \Y $eq$ls180.v:6118$1670_Y + connect \Y $eq$ls180.v:6255$1803_Y end - attribute \src "ls180.v:6120.100-6120.144" - cell $eq $eq$ls180.v:6120$1672 + attribute \src "ls180.v:6257.100-6257.144" + cell $eq $eq$ls180.v:6257$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251297,10 +253116,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6120$1672_Y + connect \Y $eq$ls180.v:6257$1805_Y end - attribute \src "ls180.v:6121.103-6121.147" - cell $eq $eq$ls180.v:6121$1676 + attribute \src "ls180.v:6258.103-6258.147" + cell $eq $eq$ls180.v:6258$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251308,10 +253127,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6121$1676_Y + connect \Y $eq$ls180.v:6258$1809_Y end - attribute \src "ls180.v:6123.100-6123.144" - cell $eq $eq$ls180.v:6123$1679 + attribute \src "ls180.v:6260.100-6260.144" + cell $eq $eq$ls180.v:6260$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251319,10 +253138,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6123$1679_Y + connect \Y $eq$ls180.v:6260$1812_Y end - attribute \src "ls180.v:6124.103-6124.147" - cell $eq $eq$ls180.v:6124$1683 + attribute \src "ls180.v:6261.103-6261.147" + cell $eq $eq$ls180.v:6261$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251330,10 +253149,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6124$1683_Y + connect \Y $eq$ls180.v:6261$1816_Y end - attribute \src "ls180.v:6126.100-6126.144" - cell $eq $eq$ls180.v:6126$1686 + attribute \src "ls180.v:6263.100-6263.144" + cell $eq $eq$ls180.v:6263$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251341,10 +253160,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6126$1686_Y + connect \Y $eq$ls180.v:6263$1819_Y end - attribute \src "ls180.v:6127.103-6127.147" - cell $eq $eq$ls180.v:6127$1690 + attribute \src "ls180.v:6264.103-6264.147" + cell $eq $eq$ls180.v:6264$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251352,10 +253171,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6127$1690_Y + connect \Y $eq$ls180.v:6264$1823_Y end - attribute \src "ls180.v:6129.100-6129.144" - cell $eq $eq$ls180.v:6129$1693 + attribute \src "ls180.v:6266.100-6266.144" + cell $eq $eq$ls180.v:6266$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251363,10 +253182,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6129$1693_Y + connect \Y $eq$ls180.v:6266$1826_Y end - attribute \src "ls180.v:6130.103-6130.147" - cell $eq $eq$ls180.v:6130$1697 + attribute \src "ls180.v:6267.103-6267.147" + cell $eq $eq$ls180.v:6267$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251374,10 +253193,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6130$1697_Y + connect \Y $eq$ls180.v:6267$1830_Y end - attribute \src "ls180.v:6132.100-6132.144" - cell $eq $eq$ls180.v:6132$1700 + attribute \src "ls180.v:6269.100-6269.144" + cell $eq $eq$ls180.v:6269$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251385,10 +253204,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6132$1700_Y + connect \Y $eq$ls180.v:6269$1833_Y end - attribute \src "ls180.v:6133.103-6133.147" - cell $eq $eq$ls180.v:6133$1704 + attribute \src "ls180.v:6270.103-6270.147" + cell $eq $eq$ls180.v:6270$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251396,10 +253215,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6133$1704_Y + connect \Y $eq$ls180.v:6270$1837_Y end - attribute \src "ls180.v:6135.100-6135.144" - cell $eq $eq$ls180.v:6135$1707 + attribute \src "ls180.v:6272.100-6272.144" + cell $eq $eq$ls180.v:6272$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251407,10 +253226,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6135$1707_Y + connect \Y $eq$ls180.v:6272$1840_Y end - attribute \src "ls180.v:6136.103-6136.147" - cell $eq $eq$ls180.v:6136$1711 + attribute \src "ls180.v:6273.103-6273.147" + cell $eq $eq$ls180.v:6273$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251418,10 +253237,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6136$1711_Y + connect \Y $eq$ls180.v:6273$1844_Y end - attribute \src "ls180.v:6138.100-6138.144" - cell $eq $eq$ls180.v:6138$1714 + attribute \src "ls180.v:6275.100-6275.144" + cell $eq $eq$ls180.v:6275$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251429,10 +253248,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6138$1714_Y + connect \Y $eq$ls180.v:6275$1847_Y end - attribute \src "ls180.v:6139.103-6139.147" - cell $eq $eq$ls180.v:6139$1718 + attribute \src "ls180.v:6276.103-6276.147" + cell $eq $eq$ls180.v:6276$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251440,10 +253259,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6139$1718_Y + connect \Y $eq$ls180.v:6276$1851_Y end - attribute \src "ls180.v:6141.100-6141.144" - cell $eq $eq$ls180.v:6141$1721 + attribute \src "ls180.v:6278.100-6278.144" + cell $eq $eq$ls180.v:6278$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251451,10 +253270,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6141$1721_Y + connect \Y $eq$ls180.v:6278$1854_Y end - attribute \src "ls180.v:6142.103-6142.147" - cell $eq $eq$ls180.v:6142$1725 + attribute \src "ls180.v:6279.103-6279.147" + cell $eq $eq$ls180.v:6279$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251462,10 +253281,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6142$1725_Y + connect \Y $eq$ls180.v:6279$1858_Y end - attribute \src "ls180.v:6144.102-6144.146" - cell $eq $eq$ls180.v:6144$1728 + attribute \src "ls180.v:6281.102-6281.146" + cell $eq $eq$ls180.v:6281$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251473,10 +253292,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6144$1728_Y + connect \Y $eq$ls180.v:6281$1861_Y end - attribute \src "ls180.v:6145.105-6145.149" - cell $eq $eq$ls180.v:6145$1732 + attribute \src "ls180.v:6282.105-6282.149" + cell $eq $eq$ls180.v:6282$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251484,10 +253303,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6145$1732_Y + connect \Y $eq$ls180.v:6282$1865_Y end - attribute \src "ls180.v:6147.102-6147.146" - cell $eq $eq$ls180.v:6147$1735 + attribute \src "ls180.v:6284.102-6284.146" + cell $eq $eq$ls180.v:6284$1868 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251495,10 +253314,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6147$1735_Y + connect \Y $eq$ls180.v:6284$1868_Y end - attribute \src "ls180.v:6148.105-6148.149" - cell $eq $eq$ls180.v:6148$1739 + attribute \src "ls180.v:6285.105-6285.149" + cell $eq $eq$ls180.v:6285$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251506,10 +253325,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6148$1739_Y + connect \Y $eq$ls180.v:6285$1872_Y end - attribute \src "ls180.v:6150.102-6150.147" - cell $eq $eq$ls180.v:6150$1742 + attribute \src "ls180.v:6287.102-6287.147" + cell $eq $eq$ls180.v:6287$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251517,10 +253336,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6150$1742_Y + connect \Y $eq$ls180.v:6287$1875_Y end - attribute \src "ls180.v:6151.105-6151.150" - cell $eq $eq$ls180.v:6151$1746 + attribute \src "ls180.v:6288.105-6288.150" + cell $eq $eq$ls180.v:6288$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251528,10 +253347,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6151$1746_Y + connect \Y $eq$ls180.v:6288$1879_Y end - attribute \src "ls180.v:6153.102-6153.147" - cell $eq $eq$ls180.v:6153$1749 + attribute \src "ls180.v:6290.102-6290.147" + cell $eq $eq$ls180.v:6290$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251539,10 +253358,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6153$1749_Y + connect \Y $eq$ls180.v:6290$1882_Y end - attribute \src "ls180.v:6154.105-6154.150" - cell $eq $eq$ls180.v:6154$1753 + attribute \src "ls180.v:6291.105-6291.150" + cell $eq $eq$ls180.v:6291$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251550,10 +253369,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6154$1753_Y + connect \Y $eq$ls180.v:6291$1886_Y end - attribute \src "ls180.v:6156.102-6156.147" - cell $eq $eq$ls180.v:6156$1756 + attribute \src "ls180.v:6293.102-6293.147" + cell $eq $eq$ls180.v:6293$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251561,10 +253380,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6156$1756_Y + connect \Y $eq$ls180.v:6293$1889_Y end - attribute \src "ls180.v:6157.105-6157.150" - cell $eq $eq$ls180.v:6157$1760 + attribute \src "ls180.v:6294.105-6294.150" + cell $eq $eq$ls180.v:6294$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251572,10 +253391,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6157$1760_Y + connect \Y $eq$ls180.v:6294$1893_Y end - attribute \src "ls180.v:6159.99-6159.144" - cell $eq $eq$ls180.v:6159$1763 + attribute \src "ls180.v:6296.99-6296.144" + cell $eq $eq$ls180.v:6296$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251583,10 +253402,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6159$1763_Y + connect \Y $eq$ls180.v:6296$1896_Y end - attribute \src "ls180.v:6160.102-6160.147" - cell $eq $eq$ls180.v:6160$1767 + attribute \src "ls180.v:6297.102-6297.147" + cell $eq $eq$ls180.v:6297$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251594,10 +253413,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6160$1767_Y + connect \Y $eq$ls180.v:6297$1900_Y end - attribute \src "ls180.v:6162.100-6162.145" - cell $eq $eq$ls180.v:6162$1770 + attribute \src "ls180.v:6299.100-6299.145" + cell $eq $eq$ls180.v:6299$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251605,10 +253424,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6162$1770_Y + connect \Y $eq$ls180.v:6299$1903_Y end - attribute \src "ls180.v:6163.103-6163.148" - cell $eq $eq$ls180.v:6163$1774 + attribute \src "ls180.v:6300.103-6300.148" + cell $eq $eq$ls180.v:6300$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251616,10 +253435,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6163$1774_Y + connect \Y $eq$ls180.v:6300$1907_Y end - attribute \src "ls180.v:6165.102-6165.147" - cell $eq $eq$ls180.v:6165$1777 + attribute \src "ls180.v:6302.102-6302.147" + cell $eq $eq$ls180.v:6302$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251627,10 +253446,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6165$1777_Y + connect \Y $eq$ls180.v:6302$1910_Y end - attribute \src "ls180.v:6166.105-6166.150" - cell $eq $eq$ls180.v:6166$1781 + attribute \src "ls180.v:6303.105-6303.150" + cell $eq $eq$ls180.v:6303$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251638,10 +253457,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6166$1781_Y + connect \Y $eq$ls180.v:6303$1914_Y end - attribute \src "ls180.v:6168.102-6168.147" - cell $eq $eq$ls180.v:6168$1784 + attribute \src "ls180.v:6305.102-6305.147" + cell $eq $eq$ls180.v:6305$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251649,10 +253468,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6168$1784_Y + connect \Y $eq$ls180.v:6305$1917_Y end - attribute \src "ls180.v:6169.105-6169.150" - cell $eq $eq$ls180.v:6169$1788 + attribute \src "ls180.v:6306.105-6306.150" + cell $eq $eq$ls180.v:6306$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251660,10 +253479,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6169$1788_Y + connect \Y $eq$ls180.v:6306$1921_Y end - attribute \src "ls180.v:6171.102-6171.147" - cell $eq $eq$ls180.v:6171$1791 + attribute \src "ls180.v:6308.102-6308.147" + cell $eq $eq$ls180.v:6308$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251671,10 +253490,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6171$1791_Y + connect \Y $eq$ls180.v:6308$1924_Y end - attribute \src "ls180.v:6172.105-6172.150" - cell $eq $eq$ls180.v:6172$1795 + attribute \src "ls180.v:6309.105-6309.150" + cell $eq $eq$ls180.v:6309$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251682,10 +253501,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6172$1795_Y + connect \Y $eq$ls180.v:6309$1928_Y end - attribute \src "ls180.v:6174.102-6174.147" - cell $eq $eq$ls180.v:6174$1798 + attribute \src "ls180.v:6311.102-6311.147" + cell $eq $eq$ls180.v:6311$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251693,10 +253512,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6174$1798_Y + connect \Y $eq$ls180.v:6311$1931_Y end - attribute \src "ls180.v:6175.105-6175.150" - cell $eq $eq$ls180.v:6175$1802 + attribute \src "ls180.v:6312.105-6312.150" + cell $eq $eq$ls180.v:6312$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -251704,21 +253523,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6175$1802_Y + connect \Y $eq$ls180.v:6312$1935_Y end - attribute \src "ls180.v:6197.32-6197.78" - cell $eq $eq$ls180.v:6197$1804 + attribute \src "ls180.v:6334.32-6334.78" + cell $eq $eq$ls180.v:6334$1937 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:9] + connect \A \builder_interface8_bank_bus_adr [13:8] connect \B 4'1100 - connect \Y $eq$ls180.v:6197$1804_Y + connect \Y $eq$ls180.v:6334$1937_Y end - attribute \src "ls180.v:6199.102-6199.146" - cell $eq $eq$ls180.v:6199$1806 + attribute \src "ls180.v:6336.102-6336.146" + cell $eq $eq$ls180.v:6336$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -251726,10 +253545,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6199$1806_Y + connect \Y $eq$ls180.v:6336$1939_Y end - attribute \src "ls180.v:6200.105-6200.149" - cell $eq $eq$ls180.v:6200$1810 + attribute \src "ls180.v:6337.105-6337.149" + cell $eq $eq$ls180.v:6337$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -251737,10 +253556,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6200$1810_Y + connect \Y $eq$ls180.v:6337$1943_Y end - attribute \src "ls180.v:6202.107-6202.151" - cell $eq $eq$ls180.v:6202$1813 + attribute \src "ls180.v:6339.107-6339.151" + cell $eq $eq$ls180.v:6339$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -251748,10 +253567,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6202$1813_Y + connect \Y $eq$ls180.v:6339$1946_Y end - attribute \src "ls180.v:6203.110-6203.154" - cell $eq $eq$ls180.v:6203$1817 + attribute \src "ls180.v:6340.110-6340.154" + cell $eq $eq$ls180.v:6340$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -251759,10 +253578,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6203$1817_Y + connect \Y $eq$ls180.v:6340$1950_Y end - attribute \src "ls180.v:6205.107-6205.151" - cell $eq $eq$ls180.v:6205$1820 + attribute \src "ls180.v:6342.107-6342.151" + cell $eq $eq$ls180.v:6342$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -251770,10 +253589,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6205$1820_Y + connect \Y $eq$ls180.v:6342$1953_Y end - attribute \src "ls180.v:6206.110-6206.154" - cell $eq $eq$ls180.v:6206$1824 + attribute \src "ls180.v:6343.110-6343.154" + cell $eq $eq$ls180.v:6343$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -251781,10 +253600,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6206$1824_Y + connect \Y $eq$ls180.v:6343$1957_Y end - attribute \src "ls180.v:6208.100-6208.144" - cell $eq $eq$ls180.v:6208$1827 + attribute \src "ls180.v:6345.100-6345.144" + cell $eq $eq$ls180.v:6345$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -251792,10 +253611,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6208$1827_Y + connect \Y $eq$ls180.v:6345$1960_Y end - attribute \src "ls180.v:6209.103-6209.147" - cell $eq $eq$ls180.v:6209$1831 + attribute \src "ls180.v:6346.103-6346.147" + cell $eq $eq$ls180.v:6346$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -251803,21 +253622,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6209$1831_Y + connect \Y $eq$ls180.v:6346$1964_Y end - attribute \src "ls180.v:6214.32-6214.77" - cell $eq $eq$ls180.v:6214$1833 + attribute \src "ls180.v:6351.32-6351.77" + cell $eq $eq$ls180.v:6351$1966 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:9] + connect \A \builder_interface9_bank_bus_adr [13:8] connect \B 2'11 - connect \Y $eq$ls180.v:6214$1833_Y + connect \Y $eq$ls180.v:6351$1966_Y end - attribute \src "ls180.v:6216.104-6216.148" - cell $eq $eq$ls180.v:6216$1835 + attribute \src "ls180.v:6353.104-6353.148" + cell $eq $eq$ls180.v:6353$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251825,10 +253644,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6216$1835_Y + connect \Y $eq$ls180.v:6353$1968_Y end - attribute \src "ls180.v:6217.107-6217.151" - cell $eq $eq$ls180.v:6217$1839 + attribute \src "ls180.v:6354.107-6354.151" + cell $eq $eq$ls180.v:6354$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251836,10 +253655,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6217$1839_Y + connect \Y $eq$ls180.v:6354$1972_Y end - attribute \src "ls180.v:6219.108-6219.152" - cell $eq $eq$ls180.v:6219$1842 + attribute \src "ls180.v:6356.108-6356.152" + cell $eq $eq$ls180.v:6356$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251847,10 +253666,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6219$1842_Y + connect \Y $eq$ls180.v:6356$1975_Y end - attribute \src "ls180.v:6220.111-6220.155" - cell $eq $eq$ls180.v:6220$1846 + attribute \src "ls180.v:6357.111-6357.155" + cell $eq $eq$ls180.v:6357$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251858,10 +253677,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6220$1846_Y + connect \Y $eq$ls180.v:6357$1979_Y end - attribute \src "ls180.v:6222.98-6222.142" - cell $eq $eq$ls180.v:6222$1849 + attribute \src "ls180.v:6359.98-6359.142" + cell $eq $eq$ls180.v:6359$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251869,10 +253688,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6222$1849_Y + connect \Y $eq$ls180.v:6359$1982_Y end - attribute \src "ls180.v:6223.101-6223.145" - cell $eq $eq$ls180.v:6223$1853 + attribute \src "ls180.v:6360.101-6360.145" + cell $eq $eq$ls180.v:6360$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251880,10 +253699,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6223$1853_Y + connect \Y $eq$ls180.v:6360$1986_Y end - attribute \src "ls180.v:6225.108-6225.152" - cell $eq $eq$ls180.v:6225$1856 + attribute \src "ls180.v:6362.108-6362.152" + cell $eq $eq$ls180.v:6362$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251891,10 +253710,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6225$1856_Y + connect \Y $eq$ls180.v:6362$1989_Y end - attribute \src "ls180.v:6226.111-6226.155" - cell $eq $eq$ls180.v:6226$1860 + attribute \src "ls180.v:6363.111-6363.155" + cell $eq $eq$ls180.v:6363$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251902,10 +253721,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6226$1860_Y + connect \Y $eq$ls180.v:6363$1993_Y end - attribute \src "ls180.v:6228.108-6228.152" - cell $eq $eq$ls180.v:6228$1863 + attribute \src "ls180.v:6365.108-6365.152" + cell $eq $eq$ls180.v:6365$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251913,10 +253732,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6228$1863_Y + connect \Y $eq$ls180.v:6365$1996_Y end - attribute \src "ls180.v:6229.111-6229.155" - cell $eq $eq$ls180.v:6229$1867 + attribute \src "ls180.v:6366.111-6366.155" + cell $eq $eq$ls180.v:6366$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251924,10 +253743,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6229$1867_Y + connect \Y $eq$ls180.v:6366$2000_Y end - attribute \src "ls180.v:6231.109-6231.153" - cell $eq $eq$ls180.v:6231$1870 + attribute \src "ls180.v:6368.109-6368.153" + cell $eq $eq$ls180.v:6368$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251935,10 +253754,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6231$1870_Y + connect \Y $eq$ls180.v:6368$2003_Y end - attribute \src "ls180.v:6232.112-6232.156" - cell $eq $eq$ls180.v:6232$1874 + attribute \src "ls180.v:6369.112-6369.156" + cell $eq $eq$ls180.v:6369$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251946,10 +253765,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6232$1874_Y + connect \Y $eq$ls180.v:6369$2007_Y end - attribute \src "ls180.v:6234.107-6234.151" - cell $eq $eq$ls180.v:6234$1877 + attribute \src "ls180.v:6371.107-6371.151" + cell $eq $eq$ls180.v:6371$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251957,10 +253776,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6234$1877_Y + connect \Y $eq$ls180.v:6371$2010_Y end - attribute \src "ls180.v:6235.110-6235.154" - cell $eq $eq$ls180.v:6235$1881 + attribute \src "ls180.v:6372.110-6372.154" + cell $eq $eq$ls180.v:6372$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251968,10 +253787,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6235$1881_Y + connect \Y $eq$ls180.v:6372$2014_Y end - attribute \src "ls180.v:6237.107-6237.151" - cell $eq $eq$ls180.v:6237$1884 + attribute \src "ls180.v:6374.107-6374.151" + cell $eq $eq$ls180.v:6374$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251979,10 +253798,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6237$1884_Y + connect \Y $eq$ls180.v:6374$2017_Y end - attribute \src "ls180.v:6238.110-6238.154" - cell $eq $eq$ls180.v:6238$1888 + attribute \src "ls180.v:6375.110-6375.154" + cell $eq $eq$ls180.v:6375$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251990,10 +253809,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6238$1888_Y + connect \Y $eq$ls180.v:6375$2021_Y end - attribute \src "ls180.v:6240.107-6240.151" - cell $eq $eq$ls180.v:6240$1891 + attribute \src "ls180.v:6377.107-6377.151" + cell $eq $eq$ls180.v:6377$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252001,10 +253820,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6240$1891_Y + connect \Y $eq$ls180.v:6377$2024_Y end - attribute \src "ls180.v:6241.110-6241.154" - cell $eq $eq$ls180.v:6241$1895 + attribute \src "ls180.v:6378.110-6378.154" + cell $eq $eq$ls180.v:6378$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252012,10 +253831,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6241$1895_Y + connect \Y $eq$ls180.v:6378$2028_Y end - attribute \src "ls180.v:6243.107-6243.151" - cell $eq $eq$ls180.v:6243$1898 + attribute \src "ls180.v:6380.107-6380.151" + cell $eq $eq$ls180.v:6380$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252023,10 +253842,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6243$1898_Y + connect \Y $eq$ls180.v:6380$2031_Y end - attribute \src "ls180.v:6244.110-6244.154" - cell $eq $eq$ls180.v:6244$1902 + attribute \src "ls180.v:6381.110-6381.154" + cell $eq $eq$ls180.v:6381$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252034,21 +253853,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6244$1902_Y + connect \Y $eq$ls180.v:6381$2035_Y end - attribute \src "ls180.v:6259.33-6259.79" - cell $eq $eq$ls180.v:6259$1904 + attribute \src "ls180.v:6396.33-6396.79" + cell $eq $eq$ls180.v:6396$2037 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:9] + connect \A \builder_interface10_bank_bus_adr [13:8] connect \B 3'111 - connect \Y $eq$ls180.v:6259$1904_Y + connect \Y $eq$ls180.v:6396$2037_Y end - attribute \src "ls180.v:6261.102-6261.147" - cell $eq $eq$ls180.v:6261$1906 + attribute \src "ls180.v:6398.102-6398.147" + cell $eq $eq$ls180.v:6398$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252056,10 +253875,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6261$1906_Y + connect \Y $eq$ls180.v:6398$2039_Y end - attribute \src "ls180.v:6262.105-6262.150" - cell $eq $eq$ls180.v:6262$1910 + attribute \src "ls180.v:6399.105-6399.150" + cell $eq $eq$ls180.v:6399$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252067,10 +253886,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6262$1910_Y + connect \Y $eq$ls180.v:6399$2043_Y end - attribute \src "ls180.v:6264.102-6264.147" - cell $eq $eq$ls180.v:6264$1913 + attribute \src "ls180.v:6401.102-6401.147" + cell $eq $eq$ls180.v:6401$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252078,10 +253897,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6264$1913_Y + connect \Y $eq$ls180.v:6401$2046_Y end - attribute \src "ls180.v:6265.105-6265.150" - cell $eq $eq$ls180.v:6265$1917 + attribute \src "ls180.v:6402.105-6402.150" + cell $eq $eq$ls180.v:6402$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252089,10 +253908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6265$1917_Y + connect \Y $eq$ls180.v:6402$2050_Y end - attribute \src "ls180.v:6267.100-6267.145" - cell $eq $eq$ls180.v:6267$1920 + attribute \src "ls180.v:6404.100-6404.145" + cell $eq $eq$ls180.v:6404$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252100,10 +253919,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6267$1920_Y + connect \Y $eq$ls180.v:6404$2053_Y end - attribute \src "ls180.v:6268.103-6268.148" - cell $eq $eq$ls180.v:6268$1924 + attribute \src "ls180.v:6405.103-6405.148" + cell $eq $eq$ls180.v:6405$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252111,10 +253930,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6268$1924_Y + connect \Y $eq$ls180.v:6405$2057_Y end - attribute \src "ls180.v:6270.99-6270.144" - cell $eq $eq$ls180.v:6270$1927 + attribute \src "ls180.v:6407.99-6407.144" + cell $eq $eq$ls180.v:6407$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252122,10 +253941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6270$1927_Y + connect \Y $eq$ls180.v:6407$2060_Y end - attribute \src "ls180.v:6271.102-6271.147" - cell $eq $eq$ls180.v:6271$1931 + attribute \src "ls180.v:6408.102-6408.147" + cell $eq $eq$ls180.v:6408$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252133,10 +253952,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6271$1931_Y + connect \Y $eq$ls180.v:6408$2064_Y end - attribute \src "ls180.v:6273.98-6273.143" - cell $eq $eq$ls180.v:6273$1934 + attribute \src "ls180.v:6410.98-6410.143" + cell $eq $eq$ls180.v:6410$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252144,10 +253963,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6273$1934_Y + connect \Y $eq$ls180.v:6410$2067_Y end - attribute \src "ls180.v:6274.101-6274.146" - cell $eq $eq$ls180.v:6274$1938 + attribute \src "ls180.v:6411.101-6411.146" + cell $eq $eq$ls180.v:6411$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252155,10 +253974,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6274$1938_Y + connect \Y $eq$ls180.v:6411$2071_Y end - attribute \src "ls180.v:6276.97-6276.142" - cell $eq $eq$ls180.v:6276$1941 + attribute \src "ls180.v:6413.97-6413.142" + cell $eq $eq$ls180.v:6413$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252166,10 +253985,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6276$1941_Y + connect \Y $eq$ls180.v:6413$2074_Y end - attribute \src "ls180.v:6277.100-6277.145" - cell $eq $eq$ls180.v:6277$1945 + attribute \src "ls180.v:6414.100-6414.145" + cell $eq $eq$ls180.v:6414$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252177,10 +253996,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6277$1945_Y + connect \Y $eq$ls180.v:6414$2078_Y end - attribute \src "ls180.v:6279.103-6279.148" - cell $eq $eq$ls180.v:6279$1948 + attribute \src "ls180.v:6416.103-6416.148" + cell $eq $eq$ls180.v:6416$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252188,10 +254007,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6279$1948_Y + connect \Y $eq$ls180.v:6416$2081_Y end - attribute \src "ls180.v:6280.106-6280.151" - cell $eq $eq$ls180.v:6280$1952 + attribute \src "ls180.v:6417.106-6417.151" + cell $eq $eq$ls180.v:6417$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252199,21 +254018,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6280$1952_Y + connect \Y $eq$ls180.v:6417$2085_Y end - attribute \src "ls180.v:6299.33-6299.79" - cell $eq $eq$ls180.v:6299$1955 + attribute \src "ls180.v:6436.33-6436.79" + cell $eq $eq$ls180.v:6436$2088 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:9] + connect \A \builder_interface11_bank_bus_adr [13:8] connect \B 4'1000 - connect \Y $eq$ls180.v:6299$1955_Y + connect \Y $eq$ls180.v:6436$2088_Y end - attribute \src "ls180.v:6301.102-6301.147" - cell $eq $eq$ls180.v:6301$1957 + attribute \src "ls180.v:6438.102-6438.147" + cell $eq $eq$ls180.v:6438$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252221,10 +254040,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6301$1957_Y + connect \Y $eq$ls180.v:6438$2090_Y end - attribute \src "ls180.v:6302.105-6302.150" - cell $eq $eq$ls180.v:6302$1961 + attribute \src "ls180.v:6439.105-6439.150" + cell $eq $eq$ls180.v:6439$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252232,10 +254051,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6302$1961_Y + connect \Y $eq$ls180.v:6439$2094_Y end - attribute \src "ls180.v:6304.102-6304.147" - cell $eq $eq$ls180.v:6304$1964 + attribute \src "ls180.v:6441.102-6441.147" + cell $eq $eq$ls180.v:6441$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252243,10 +254062,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6304$1964_Y + connect \Y $eq$ls180.v:6441$2097_Y end - attribute \src "ls180.v:6305.105-6305.150" - cell $eq $eq$ls180.v:6305$1968 + attribute \src "ls180.v:6442.105-6442.150" + cell $eq $eq$ls180.v:6442$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252254,10 +254073,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6305$1968_Y + connect \Y $eq$ls180.v:6442$2101_Y end - attribute \src "ls180.v:6307.100-6307.145" - cell $eq $eq$ls180.v:6307$1971 + attribute \src "ls180.v:6444.100-6444.145" + cell $eq $eq$ls180.v:6444$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252265,10 +254084,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6307$1971_Y + connect \Y $eq$ls180.v:6444$2104_Y end - attribute \src "ls180.v:6308.103-6308.148" - cell $eq $eq$ls180.v:6308$1975 + attribute \src "ls180.v:6445.103-6445.148" + cell $eq $eq$ls180.v:6445$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252276,10 +254095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6308$1975_Y + connect \Y $eq$ls180.v:6445$2108_Y end - attribute \src "ls180.v:6310.99-6310.144" - cell $eq $eq$ls180.v:6310$1978 + attribute \src "ls180.v:6447.99-6447.144" + cell $eq $eq$ls180.v:6447$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252287,10 +254106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6310$1978_Y + connect \Y $eq$ls180.v:6447$2111_Y end - attribute \src "ls180.v:6311.102-6311.147" - cell $eq $eq$ls180.v:6311$1982 + attribute \src "ls180.v:6448.102-6448.147" + cell $eq $eq$ls180.v:6448$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252298,10 +254117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6311$1982_Y + connect \Y $eq$ls180.v:6448$2115_Y end - attribute \src "ls180.v:6313.98-6313.143" - cell $eq $eq$ls180.v:6313$1985 + attribute \src "ls180.v:6450.98-6450.143" + cell $eq $eq$ls180.v:6450$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252309,10 +254128,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6313$1985_Y + connect \Y $eq$ls180.v:6450$2118_Y end - attribute \src "ls180.v:6314.101-6314.146" - cell $eq $eq$ls180.v:6314$1989 + attribute \src "ls180.v:6451.101-6451.146" + cell $eq $eq$ls180.v:6451$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252320,10 +254139,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6314$1989_Y + connect \Y $eq$ls180.v:6451$2122_Y end - attribute \src "ls180.v:6316.97-6316.142" - cell $eq $eq$ls180.v:6316$1992 + attribute \src "ls180.v:6453.97-6453.142" + cell $eq $eq$ls180.v:6453$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252331,10 +254150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6316$1992_Y + connect \Y $eq$ls180.v:6453$2125_Y end - attribute \src "ls180.v:6317.100-6317.145" - cell $eq $eq$ls180.v:6317$1996 + attribute \src "ls180.v:6454.100-6454.145" + cell $eq $eq$ls180.v:6454$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252342,10 +254161,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6317$1996_Y + connect \Y $eq$ls180.v:6454$2129_Y end - attribute \src "ls180.v:6319.103-6319.148" - cell $eq $eq$ls180.v:6319$1999 + attribute \src "ls180.v:6456.103-6456.148" + cell $eq $eq$ls180.v:6456$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252353,10 +254172,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6319$1999_Y + connect \Y $eq$ls180.v:6456$2132_Y end - attribute \src "ls180.v:6320.106-6320.151" - cell $eq $eq$ls180.v:6320$2003 + attribute \src "ls180.v:6457.106-6457.151" + cell $eq $eq$ls180.v:6457$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252364,10 +254183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6320$2003_Y + connect \Y $eq$ls180.v:6457$2136_Y end - attribute \src "ls180.v:6322.106-6322.151" - cell $eq $eq$ls180.v:6322$2006 + attribute \src "ls180.v:6459.106-6459.151" + cell $eq $eq$ls180.v:6459$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252375,10 +254194,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6322$2006_Y + connect \Y $eq$ls180.v:6459$2139_Y end - attribute \src "ls180.v:6323.109-6323.154" - cell $eq $eq$ls180.v:6323$2010 + attribute \src "ls180.v:6460.109-6460.154" + cell $eq $eq$ls180.v:6460$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252386,10 +254205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6323$2010_Y + connect \Y $eq$ls180.v:6460$2143_Y end - attribute \src "ls180.v:6325.106-6325.151" - cell $eq $eq$ls180.v:6325$2013 + attribute \src "ls180.v:6462.106-6462.151" + cell $eq $eq$ls180.v:6462$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252397,10 +254216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6325$2013_Y + connect \Y $eq$ls180.v:6462$2146_Y end - attribute \src "ls180.v:6326.109-6326.154" - cell $eq $eq$ls180.v:6326$2017 + attribute \src "ls180.v:6463.109-6463.154" + cell $eq $eq$ls180.v:6463$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252408,21 +254227,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6326$2017_Y + connect \Y $eq$ls180.v:6463$2150_Y end - attribute \src "ls180.v:6347.33-6347.79" - cell $eq $eq$ls180.v:6347$2020 + attribute \src "ls180.v:6484.33-6484.79" + cell $eq $eq$ls180.v:6484$2153 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:9] + connect \A \builder_interface12_bank_bus_adr [13:8] connect \B 2'10 - connect \Y $eq$ls180.v:6347$2020_Y + connect \Y $eq$ls180.v:6484$2153_Y end - attribute \src "ls180.v:6349.99-6349.144" - cell $eq $eq$ls180.v:6349$2022 + attribute \src "ls180.v:6486.99-6486.144" + cell $eq $eq$ls180.v:6486$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252430,10 +254249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6349$2022_Y + connect \Y $eq$ls180.v:6486$2155_Y end - attribute \src "ls180.v:6350.102-6350.147" - cell $eq $eq$ls180.v:6350$2026 + attribute \src "ls180.v:6487.102-6487.147" + cell $eq $eq$ls180.v:6487$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252441,10 +254260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6350$2026_Y + connect \Y $eq$ls180.v:6487$2159_Y end - attribute \src "ls180.v:6352.99-6352.144" - cell $eq $eq$ls180.v:6352$2029 + attribute \src "ls180.v:6489.99-6489.144" + cell $eq $eq$ls180.v:6489$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252452,10 +254271,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6352$2029_Y + connect \Y $eq$ls180.v:6489$2162_Y end - attribute \src "ls180.v:6353.102-6353.147" - cell $eq $eq$ls180.v:6353$2033 + attribute \src "ls180.v:6490.102-6490.147" + cell $eq $eq$ls180.v:6490$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252463,10 +254282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6353$2033_Y + connect \Y $eq$ls180.v:6490$2166_Y end - attribute \src "ls180.v:6355.99-6355.144" - cell $eq $eq$ls180.v:6355$2036 + attribute \src "ls180.v:6492.99-6492.144" + cell $eq $eq$ls180.v:6492$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252474,10 +254293,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6355$2036_Y + connect \Y $eq$ls180.v:6492$2169_Y end - attribute \src "ls180.v:6356.102-6356.147" - cell $eq $eq$ls180.v:6356$2040 + attribute \src "ls180.v:6493.102-6493.147" + cell $eq $eq$ls180.v:6493$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252485,10 +254304,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6356$2040_Y + connect \Y $eq$ls180.v:6493$2173_Y end - attribute \src "ls180.v:6358.99-6358.144" - cell $eq $eq$ls180.v:6358$2043 + attribute \src "ls180.v:6495.99-6495.144" + cell $eq $eq$ls180.v:6495$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252496,10 +254315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6358$2043_Y + connect \Y $eq$ls180.v:6495$2176_Y end - attribute \src "ls180.v:6359.102-6359.147" - cell $eq $eq$ls180.v:6359$2047 + attribute \src "ls180.v:6496.102-6496.147" + cell $eq $eq$ls180.v:6496$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252507,10 +254326,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6359$2047_Y + connect \Y $eq$ls180.v:6496$2180_Y end - attribute \src "ls180.v:6361.101-6361.146" - cell $eq $eq$ls180.v:6361$2050 + attribute \src "ls180.v:6498.101-6498.146" + cell $eq $eq$ls180.v:6498$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252518,10 +254337,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6361$2050_Y + connect \Y $eq$ls180.v:6498$2183_Y end - attribute \src "ls180.v:6362.104-6362.149" - cell $eq $eq$ls180.v:6362$2054 + attribute \src "ls180.v:6499.104-6499.149" + cell $eq $eq$ls180.v:6499$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252529,10 +254348,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6362$2054_Y + connect \Y $eq$ls180.v:6499$2187_Y end - attribute \src "ls180.v:6364.101-6364.146" - cell $eq $eq$ls180.v:6364$2057 + attribute \src "ls180.v:6501.101-6501.146" + cell $eq $eq$ls180.v:6501$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252540,10 +254359,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6364$2057_Y + connect \Y $eq$ls180.v:6501$2190_Y end - attribute \src "ls180.v:6365.104-6365.149" - cell $eq $eq$ls180.v:6365$2061 + attribute \src "ls180.v:6502.104-6502.149" + cell $eq $eq$ls180.v:6502$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252551,10 +254370,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6365$2061_Y + connect \Y $eq$ls180.v:6502$2194_Y end - attribute \src "ls180.v:6367.101-6367.146" - cell $eq $eq$ls180.v:6367$2064 + attribute \src "ls180.v:6504.101-6504.146" + cell $eq $eq$ls180.v:6504$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252562,10 +254381,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6367$2064_Y + connect \Y $eq$ls180.v:6504$2197_Y end - attribute \src "ls180.v:6368.104-6368.149" - cell $eq $eq$ls180.v:6368$2068 + attribute \src "ls180.v:6505.104-6505.149" + cell $eq $eq$ls180.v:6505$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252573,10 +254392,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6368$2068_Y + connect \Y $eq$ls180.v:6505$2201_Y end - attribute \src "ls180.v:6370.101-6370.146" - cell $eq $eq$ls180.v:6370$2071 + attribute \src "ls180.v:6507.101-6507.146" + cell $eq $eq$ls180.v:6507$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252584,10 +254403,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6370$2071_Y + connect \Y $eq$ls180.v:6507$2204_Y end - attribute \src "ls180.v:6371.104-6371.149" - cell $eq $eq$ls180.v:6371$2075 + attribute \src "ls180.v:6508.104-6508.149" + cell $eq $eq$ls180.v:6508$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252595,10 +254414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6371$2075_Y + connect \Y $eq$ls180.v:6508$2208_Y end - attribute \src "ls180.v:6373.97-6373.142" - cell $eq $eq$ls180.v:6373$2078 + attribute \src "ls180.v:6510.97-6510.142" + cell $eq $eq$ls180.v:6510$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252606,10 +254425,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6373$2078_Y + connect \Y $eq$ls180.v:6510$2211_Y end - attribute \src "ls180.v:6374.100-6374.145" - cell $eq $eq$ls180.v:6374$2082 + attribute \src "ls180.v:6511.100-6511.145" + cell $eq $eq$ls180.v:6511$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252617,10 +254436,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6374$2082_Y + connect \Y $eq$ls180.v:6511$2215_Y end - attribute \src "ls180.v:6376.107-6376.152" - cell $eq $eq$ls180.v:6376$2085 + attribute \src "ls180.v:6513.107-6513.152" + cell $eq $eq$ls180.v:6513$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252628,10 +254447,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6376$2085_Y + connect \Y $eq$ls180.v:6513$2218_Y end - attribute \src "ls180.v:6377.110-6377.155" - cell $eq $eq$ls180.v:6377$2089 + attribute \src "ls180.v:6514.110-6514.155" + cell $eq $eq$ls180.v:6514$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252639,10 +254458,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6377$2089_Y + connect \Y $eq$ls180.v:6514$2222_Y end - attribute \src "ls180.v:6379.100-6379.146" - cell $eq $eq$ls180.v:6379$2092 + attribute \src "ls180.v:6516.100-6516.146" + cell $eq $eq$ls180.v:6516$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252650,10 +254469,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6379$2092_Y + connect \Y $eq$ls180.v:6516$2225_Y end - attribute \src "ls180.v:6380.103-6380.149" - cell $eq $eq$ls180.v:6380$2096 + attribute \src "ls180.v:6517.103-6517.149" + cell $eq $eq$ls180.v:6517$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252661,10 +254480,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6380$2096_Y + connect \Y $eq$ls180.v:6517$2229_Y end - attribute \src "ls180.v:6382.100-6382.146" - cell $eq $eq$ls180.v:6382$2099 + attribute \src "ls180.v:6519.100-6519.146" + cell $eq $eq$ls180.v:6519$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252672,10 +254491,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6382$2099_Y + connect \Y $eq$ls180.v:6519$2232_Y end - attribute \src "ls180.v:6383.103-6383.149" - cell $eq $eq$ls180.v:6383$2103 + attribute \src "ls180.v:6520.103-6520.149" + cell $eq $eq$ls180.v:6520$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252683,10 +254502,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6383$2103_Y + connect \Y $eq$ls180.v:6520$2236_Y end - attribute \src "ls180.v:6385.100-6385.146" - cell $eq $eq$ls180.v:6385$2106 + attribute \src "ls180.v:6522.100-6522.146" + cell $eq $eq$ls180.v:6522$2239 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252694,10 +254513,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6385$2106_Y + connect \Y $eq$ls180.v:6522$2239_Y end - attribute \src "ls180.v:6386.103-6386.149" - cell $eq $eq$ls180.v:6386$2110 + attribute \src "ls180.v:6523.103-6523.149" + cell $eq $eq$ls180.v:6523$2243 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252705,10 +254524,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6386$2110_Y + connect \Y $eq$ls180.v:6523$2243_Y end - attribute \src "ls180.v:6388.100-6388.146" - cell $eq $eq$ls180.v:6388$2113 + attribute \src "ls180.v:6525.100-6525.146" + cell $eq $eq$ls180.v:6525$2246 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252716,10 +254535,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6388$2113_Y + connect \Y $eq$ls180.v:6525$2246_Y end - attribute \src "ls180.v:6389.103-6389.149" - cell $eq $eq$ls180.v:6389$2117 + attribute \src "ls180.v:6526.103-6526.149" + cell $eq $eq$ls180.v:6526$2250 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252727,10 +254546,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6389$2117_Y + connect \Y $eq$ls180.v:6526$2250_Y end - attribute \src "ls180.v:6391.112-6391.158" - cell $eq $eq$ls180.v:6391$2120 + attribute \src "ls180.v:6528.112-6528.158" + cell $eq $eq$ls180.v:6528$2253 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252738,10 +254557,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6391$2120_Y + connect \Y $eq$ls180.v:6528$2253_Y end - attribute \src "ls180.v:6392.115-6392.161" - cell $eq $eq$ls180.v:6392$2124 + attribute \src "ls180.v:6529.115-6529.161" + cell $eq $eq$ls180.v:6529$2257 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252749,10 +254568,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6392$2124_Y + connect \Y $eq$ls180.v:6529$2257_Y end - attribute \src "ls180.v:6394.113-6394.159" - cell $eq $eq$ls180.v:6394$2127 + attribute \src "ls180.v:6531.113-6531.159" + cell $eq $eq$ls180.v:6531$2260 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252760,10 +254579,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6394$2127_Y + connect \Y $eq$ls180.v:6531$2260_Y end - attribute \src "ls180.v:6395.116-6395.162" - cell $eq $eq$ls180.v:6395$2131 + attribute \src "ls180.v:6532.116-6532.162" + cell $eq $eq$ls180.v:6532$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252771,10 +254590,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6395$2131_Y + connect \Y $eq$ls180.v:6532$2264_Y end - attribute \src "ls180.v:6397.104-6397.150" - cell $eq $eq$ls180.v:6397$2134 + attribute \src "ls180.v:6534.104-6534.150" + cell $eq $eq$ls180.v:6534$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252782,10 +254601,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6397$2134_Y + connect \Y $eq$ls180.v:6534$2267_Y end - attribute \src "ls180.v:6398.107-6398.153" - cell $eq $eq$ls180.v:6398$2138 + attribute \src "ls180.v:6535.107-6535.153" + cell $eq $eq$ls180.v:6535$2271 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252793,21 +254612,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6398$2138_Y + connect \Y $eq$ls180.v:6535$2271_Y end - attribute \src "ls180.v:6415.33-6415.79" - cell $eq $eq$ls180.v:6415$2140 + attribute \src "ls180.v:6552.33-6552.79" + cell $eq $eq$ls180.v:6552$2273 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:9] + connect \A \builder_interface13_bank_bus_adr [13:8] connect \B 3'101 - connect \Y $eq$ls180.v:6415$2140_Y + connect \Y $eq$ls180.v:6552$2273_Y end - attribute \src "ls180.v:6417.90-6417.135" - cell $eq $eq$ls180.v:6417$2142 + attribute \src "ls180.v:6554.90-6554.135" + cell $eq $eq$ls180.v:6554$2275 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252815,10 +254634,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6417$2142_Y + connect \Y $eq$ls180.v:6554$2275_Y end - attribute \src "ls180.v:6418.93-6418.138" - cell $eq $eq$ls180.v:6418$2146 + attribute \src "ls180.v:6555.93-6555.138" + cell $eq $eq$ls180.v:6555$2279 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252826,10 +254645,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6418$2146_Y + connect \Y $eq$ls180.v:6555$2279_Y end - attribute \src "ls180.v:6420.100-6420.145" - cell $eq $eq$ls180.v:6420$2149 + attribute \src "ls180.v:6557.100-6557.145" + cell $eq $eq$ls180.v:6557$2282 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252837,10 +254656,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6420$2149_Y + connect \Y $eq$ls180.v:6557$2282_Y end - attribute \src "ls180.v:6421.103-6421.148" - cell $eq $eq$ls180.v:6421$2153 + attribute \src "ls180.v:6558.103-6558.148" + cell $eq $eq$ls180.v:6558$2286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252848,10 +254667,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6421$2153_Y + connect \Y $eq$ls180.v:6558$2286_Y end - attribute \src "ls180.v:6423.101-6423.146" - cell $eq $eq$ls180.v:6423$2156 + attribute \src "ls180.v:6560.101-6560.146" + cell $eq $eq$ls180.v:6560$2289 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252859,10 +254678,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6423$2156_Y + connect \Y $eq$ls180.v:6560$2289_Y end - attribute \src "ls180.v:6424.104-6424.149" - cell $eq $eq$ls180.v:6424$2160 + attribute \src "ls180.v:6561.104-6561.149" + cell $eq $eq$ls180.v:6561$2293 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252870,10 +254689,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6424$2160_Y + connect \Y $eq$ls180.v:6561$2293_Y end - attribute \src "ls180.v:6426.105-6426.150" - cell $eq $eq$ls180.v:6426$2163 + attribute \src "ls180.v:6563.105-6563.150" + cell $eq $eq$ls180.v:6563$2296 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252881,10 +254700,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6426$2163_Y + connect \Y $eq$ls180.v:6563$2296_Y end - attribute \src "ls180.v:6427.108-6427.153" - cell $eq $eq$ls180.v:6427$2167 + attribute \src "ls180.v:6564.108-6564.153" + cell $eq $eq$ls180.v:6564$2300 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252892,10 +254711,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6427$2167_Y + connect \Y $eq$ls180.v:6564$2300_Y end - attribute \src "ls180.v:6429.106-6429.151" - cell $eq $eq$ls180.v:6429$2170 + attribute \src "ls180.v:6566.106-6566.151" + cell $eq $eq$ls180.v:6566$2303 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252903,10 +254722,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6429$2170_Y + connect \Y $eq$ls180.v:6566$2303_Y end - attribute \src "ls180.v:6430.109-6430.154" - cell $eq $eq$ls180.v:6430$2174 + attribute \src "ls180.v:6567.109-6567.154" + cell $eq $eq$ls180.v:6567$2307 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252914,10 +254733,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6430$2174_Y + connect \Y $eq$ls180.v:6567$2307_Y end - attribute \src "ls180.v:6432.104-6432.149" - cell $eq $eq$ls180.v:6432$2177 + attribute \src "ls180.v:6569.104-6569.149" + cell $eq $eq$ls180.v:6569$2310 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252925,10 +254744,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6432$2177_Y + connect \Y $eq$ls180.v:6569$2310_Y end - attribute \src "ls180.v:6433.107-6433.152" - cell $eq $eq$ls180.v:6433$2181 + attribute \src "ls180.v:6570.107-6570.152" + cell $eq $eq$ls180.v:6570$2314 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252936,10 +254755,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6433$2181_Y + connect \Y $eq$ls180.v:6570$2314_Y end - attribute \src "ls180.v:6435.101-6435.146" - cell $eq $eq$ls180.v:6435$2184 + attribute \src "ls180.v:6572.101-6572.146" + cell $eq $eq$ls180.v:6572$2317 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252947,10 +254766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6435$2184_Y + connect \Y $eq$ls180.v:6572$2317_Y end - attribute \src "ls180.v:6436.104-6436.149" - cell $eq $eq$ls180.v:6436$2188 + attribute \src "ls180.v:6573.104-6573.149" + cell $eq $eq$ls180.v:6573$2321 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252958,10 +254777,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6436$2188_Y + connect \Y $eq$ls180.v:6573$2321_Y end - attribute \src "ls180.v:6438.100-6438.145" - cell $eq $eq$ls180.v:6438$2191 + attribute \src "ls180.v:6575.100-6575.145" + cell $eq $eq$ls180.v:6575$2324 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252969,10 +254788,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6438$2191_Y + connect \Y $eq$ls180.v:6575$2324_Y end - attribute \src "ls180.v:6439.103-6439.148" - cell $eq $eq$ls180.v:6439$2195 + attribute \src "ls180.v:6576.103-6576.148" + cell $eq $eq$ls180.v:6576$2328 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -252980,21 +254799,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6439$2195_Y + connect \Y $eq$ls180.v:6576$2328_Y end - attribute \src "ls180.v:6449.33-6449.79" - cell $eq $eq$ls180.v:6449$2197 + attribute \src "ls180.v:6586.33-6586.79" + cell $eq $eq$ls180.v:6586$2330 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [13:9] + connect \A \builder_interface14_bank_bus_adr [13:8] connect \B 3'100 - connect \Y $eq$ls180.v:6449$2197_Y + connect \Y $eq$ls180.v:6586$2330_Y end - attribute \src "ls180.v:6451.106-6451.151" - cell $eq $eq$ls180.v:6451$2199 + attribute \src "ls180.v:6588.106-6588.151" + cell $eq $eq$ls180.v:6588$2332 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253002,10 +254821,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6451$2199_Y + connect \Y $eq$ls180.v:6588$2332_Y end - attribute \src "ls180.v:6452.109-6452.154" - cell $eq $eq$ls180.v:6452$2203 + attribute \src "ls180.v:6589.109-6589.154" + cell $eq $eq$ls180.v:6589$2336 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253013,10 +254832,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6452$2203_Y + connect \Y $eq$ls180.v:6589$2336_Y end - attribute \src "ls180.v:6454.106-6454.151" - cell $eq $eq$ls180.v:6454$2206 + attribute \src "ls180.v:6591.106-6591.151" + cell $eq $eq$ls180.v:6591$2339 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253024,10 +254843,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6454$2206_Y + connect \Y $eq$ls180.v:6591$2339_Y end - attribute \src "ls180.v:6455.109-6455.154" - cell $eq $eq$ls180.v:6455$2210 + attribute \src "ls180.v:6592.109-6592.154" + cell $eq $eq$ls180.v:6592$2343 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253035,10 +254854,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6455$2210_Y + connect \Y $eq$ls180.v:6592$2343_Y end - attribute \src "ls180.v:6457.106-6457.151" - cell $eq $eq$ls180.v:6457$2213 + attribute \src "ls180.v:6594.106-6594.151" + cell $eq $eq$ls180.v:6594$2346 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253046,10 +254865,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6457$2213_Y + connect \Y $eq$ls180.v:6594$2346_Y end - attribute \src "ls180.v:6458.109-6458.154" - cell $eq $eq$ls180.v:6458$2217 + attribute \src "ls180.v:6595.109-6595.154" + cell $eq $eq$ls180.v:6595$2350 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253057,10 +254876,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6458$2217_Y + connect \Y $eq$ls180.v:6595$2350_Y end - attribute \src "ls180.v:6460.106-6460.151" - cell $eq $eq$ls180.v:6460$2220 + attribute \src "ls180.v:6597.106-6597.151" + cell $eq $eq$ls180.v:6597$2353 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253068,10 +254887,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6460$2220_Y + connect \Y $eq$ls180.v:6597$2353_Y end - attribute \src "ls180.v:6461.109-6461.154" - cell $eq $eq$ls180.v:6461$2224 + attribute \src "ls180.v:6598.109-6598.154" + cell $eq $eq$ls180.v:6598$2357 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253079,10 +254898,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6461$2224_Y + connect \Y $eq$ls180.v:6598$2357_Y end - attribute \src "ls180.v:6842.41-6842.81" - cell $eq $eq$ls180.v:6842$2261 + attribute \src "ls180.v:6979.41-6979.81" + cell $eq $eq$ls180.v:6979$2394 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253090,10 +254909,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:6842$2261_Y + connect \Y $eq$ls180.v:6979$2394_Y end - attribute \src "ls180.v:6842.144-6842.177" - cell $eq $eq$ls180.v:6842$2262 + attribute \src "ls180.v:6979.144-6979.177" + cell $eq $eq$ls180.v:6979$2395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253101,10 +254920,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6842$2262_Y + connect \Y $eq$ls180.v:6979$2395_Y end - attribute \src "ls180.v:6842.219-6842.252" - cell $eq $eq$ls180.v:6842$2265 + attribute \src "ls180.v:6979.219-6979.252" + cell $eq $eq$ls180.v:6979$2398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253112,10 +254931,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6842$2265_Y + connect \Y $eq$ls180.v:6979$2398_Y end - attribute \src "ls180.v:6842.294-6842.327" - cell $eq $eq$ls180.v:6842$2268 + attribute \src "ls180.v:6979.294-6979.327" + cell $eq $eq$ls180.v:6979$2401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253123,10 +254942,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6842$2268_Y + connect \Y $eq$ls180.v:6979$2401_Y end - attribute \src "ls180.v:6866.41-6866.81" - cell $eq $eq$ls180.v:6866$2277 + attribute \src "ls180.v:7003.41-7003.81" + cell $eq $eq$ls180.v:7003$2410 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253134,10 +254953,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:6866$2277_Y + connect \Y $eq$ls180.v:7003$2410_Y end - attribute \src "ls180.v:6866.144-6866.177" - cell $eq $eq$ls180.v:6866$2278 + attribute \src "ls180.v:7003.144-7003.177" + cell $eq $eq$ls180.v:7003$2411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253145,10 +254964,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6866$2278_Y + connect \Y $eq$ls180.v:7003$2411_Y end - attribute \src "ls180.v:6866.219-6866.252" - cell $eq $eq$ls180.v:6866$2281 + attribute \src "ls180.v:7003.219-7003.252" + cell $eq $eq$ls180.v:7003$2414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253156,10 +254975,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6866$2281_Y + connect \Y $eq$ls180.v:7003$2414_Y end - attribute \src "ls180.v:6866.294-6866.327" - cell $eq $eq$ls180.v:6866$2284 + attribute \src "ls180.v:7003.294-7003.327" + cell $eq $eq$ls180.v:7003$2417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253167,10 +254986,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6866$2284_Y + connect \Y $eq$ls180.v:7003$2417_Y end - attribute \src "ls180.v:6890.41-6890.81" - cell $eq $eq$ls180.v:6890$2293 + attribute \src "ls180.v:7027.41-7027.81" + cell $eq $eq$ls180.v:7027$2426 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253178,10 +254997,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:6890$2293_Y + connect \Y $eq$ls180.v:7027$2426_Y end - attribute \src "ls180.v:6890.144-6890.177" - cell $eq $eq$ls180.v:6890$2294 + attribute \src "ls180.v:7027.144-7027.177" + cell $eq $eq$ls180.v:7027$2427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253189,10 +255008,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6890$2294_Y + connect \Y $eq$ls180.v:7027$2427_Y end - attribute \src "ls180.v:6890.219-6890.252" - cell $eq $eq$ls180.v:6890$2297 + attribute \src "ls180.v:7027.219-7027.252" + cell $eq $eq$ls180.v:7027$2430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253200,10 +255019,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6890$2297_Y + connect \Y $eq$ls180.v:7027$2430_Y end - attribute \src "ls180.v:6890.294-6890.327" - cell $eq $eq$ls180.v:6890$2300 + attribute \src "ls180.v:7027.294-7027.327" + cell $eq $eq$ls180.v:7027$2433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253211,10 +255030,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6890$2300_Y + connect \Y $eq$ls180.v:7027$2433_Y end - attribute \src "ls180.v:6914.41-6914.81" - cell $eq $eq$ls180.v:6914$2309 + attribute \src "ls180.v:7051.41-7051.81" + cell $eq $eq$ls180.v:7051$2442 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253222,10 +255041,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:6914$2309_Y + connect \Y $eq$ls180.v:7051$2442_Y end - attribute \src "ls180.v:6914.144-6914.177" - cell $eq $eq$ls180.v:6914$2310 + attribute \src "ls180.v:7051.144-7051.177" + cell $eq $eq$ls180.v:7051$2443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253233,10 +255052,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6914$2310_Y + connect \Y $eq$ls180.v:7051$2443_Y end - attribute \src "ls180.v:6914.219-6914.252" - cell $eq $eq$ls180.v:6914$2313 + attribute \src "ls180.v:7051.219-7051.252" + cell $eq $eq$ls180.v:7051$2446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253244,10 +255063,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6914$2313_Y + connect \Y $eq$ls180.v:7051$2446_Y end - attribute \src "ls180.v:6914.294-6914.327" - cell $eq $eq$ls180.v:6914$2316 + attribute \src "ls180.v:7051.294-7051.327" + cell $eq $eq$ls180.v:7051$2449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253255,10 +255074,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6914$2316_Y + connect \Y $eq$ls180.v:7051$2449_Y end - attribute \src "ls180.v:7495.8-7495.38" - cell $eq $eq$ls180.v:7495$2407 + attribute \src "ls180.v:7632.8-7632.38" + cell $eq $eq$ls180.v:7632$2540 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -253266,10 +255085,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7495$2407_Y + connect \Y $eq$ls180.v:7632$2540_Y end - attribute \src "ls180.v:7526.8-7526.42" - cell $eq $eq$ls180.v:7526$2415 + attribute \src "ls180.v:7675.8-7675.42" + cell $eq $eq$ls180.v:7675$2557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253277,10 +255096,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7526$2415_Y + connect \Y $eq$ls180.v:7675$2557_Y end - attribute \src "ls180.v:7546.38-7546.74" - cell $eq $eq$ls180.v:7546$2418 + attribute \src "ls180.v:7695.38-7695.74" + cell $eq $eq$ls180.v:7695$2560 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253288,10 +255107,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7546$2418_Y + connect \Y $eq$ls180.v:7695$2560_Y end - attribute \src "ls180.v:7553.7-7553.43" - cell $eq $eq$ls180.v:7553$2420 + attribute \src "ls180.v:7702.7-7702.43" + cell $eq $eq$ls180.v:7702$2562 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253299,10 +255118,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7553$2420_Y + connect \Y $eq$ls180.v:7702$2562_Y end - attribute \src "ls180.v:7560.7-7560.43" - cell $eq $eq$ls180.v:7560$2421 + attribute \src "ls180.v:7709.7-7709.43" + cell $eq $eq$ls180.v:7709$2563 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253310,10 +255129,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7560$2421_Y + connect \Y $eq$ls180.v:7709$2563_Y end - attribute \src "ls180.v:7568.7-7568.43" - cell $eq $eq$ls180.v:7568$2422 + attribute \src "ls180.v:7717.7-7717.43" + cell $eq $eq$ls180.v:7717$2564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253321,10 +255140,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7568$2422_Y + connect \Y $eq$ls180.v:7717$2564_Y end - attribute \src "ls180.v:7620.9-7620.54" - cell $eq $eq$ls180.v:7620$2440 + attribute \src "ls180.v:7769.9-7769.54" + cell $eq $eq$ls180.v:7769$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253332,10 +255151,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7620$2440_Y + connect \Y $eq$ls180.v:7769$2582_Y end - attribute \src "ls180.v:7666.9-7666.54" - cell $eq $eq$ls180.v:7666$2456 + attribute \src "ls180.v:7815.9-7815.54" + cell $eq $eq$ls180.v:7815$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253343,10 +255162,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7666$2456_Y + connect \Y $eq$ls180.v:7815$2598_Y end - attribute \src "ls180.v:7712.9-7712.54" - cell $eq $eq$ls180.v:7712$2472 + attribute \src "ls180.v:7861.9-7861.54" + cell $eq $eq$ls180.v:7861$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253354,10 +255173,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7712$2472_Y + connect \Y $eq$ls180.v:7861$2614_Y end - attribute \src "ls180.v:7758.9-7758.54" - cell $eq $eq$ls180.v:7758$2488 + attribute \src "ls180.v:7907.9-7907.54" + cell $eq $eq$ls180.v:7907$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253365,10 +255184,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7758$2488_Y + connect \Y $eq$ls180.v:7907$2630_Y end - attribute \src "ls180.v:7908.9-7908.41" - cell $eq $eq$ls180.v:7908$2500 + attribute \src "ls180.v:8057.9-8057.41" + cell $eq $eq$ls180.v:8057$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253376,10 +255195,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7908$2500_Y + connect \Y $eq$ls180.v:8057$2642_Y end - attribute \src "ls180.v:7923.9-7923.41" - cell $eq $eq$ls180.v:7923$2503 + attribute \src "ls180.v:8072.9-8072.41" + cell $eq $eq$ls180.v:8072$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253387,10 +255206,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7923$2503_Y + connect \Y $eq$ls180.v:8072$2645_Y end - attribute \src "ls180.v:7929.49-7929.82" - cell $eq $eq$ls180.v:7929$2504 + attribute \src "ls180.v:8078.49-8078.82" + cell $eq $eq$ls180.v:8078$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253398,10 +255217,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7929$2504_Y + connect \Y $eq$ls180.v:8078$2646_Y end - attribute \src "ls180.v:7929.131-7929.164" - cell $eq $eq$ls180.v:7929$2507 + attribute \src "ls180.v:8078.131-8078.164" + cell $eq $eq$ls180.v:8078$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253409,10 +255228,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7929$2507_Y + connect \Y $eq$ls180.v:8078$2649_Y end - attribute \src "ls180.v:7929.213-7929.246" - cell $eq $eq$ls180.v:7929$2510 + attribute \src "ls180.v:8078.213-8078.246" + cell $eq $eq$ls180.v:8078$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253420,10 +255239,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7929$2510_Y + connect \Y $eq$ls180.v:8078$2652_Y end - attribute \src "ls180.v:7929.295-7929.328" - cell $eq $eq$ls180.v:7929$2513 + attribute \src "ls180.v:8078.295-8078.328" + cell $eq $eq$ls180.v:8078$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253431,10 +255250,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7929$2513_Y + connect \Y $eq$ls180.v:8078$2655_Y end - attribute \src "ls180.v:7930.50-7930.83" - cell $eq $eq$ls180.v:7930$2516 + attribute \src "ls180.v:8079.50-8079.83" + cell $eq $eq$ls180.v:8079$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253442,10 +255261,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7930$2516_Y + connect \Y $eq$ls180.v:8079$2658_Y end - attribute \src "ls180.v:7930.132-7930.165" - cell $eq $eq$ls180.v:7930$2519 + attribute \src "ls180.v:8079.132-8079.165" + cell $eq $eq$ls180.v:8079$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253453,10 +255272,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7930$2519_Y + connect \Y $eq$ls180.v:8079$2661_Y end - attribute \src "ls180.v:7930.214-7930.247" - cell $eq $eq$ls180.v:7930$2522 + attribute \src "ls180.v:8079.214-8079.247" + cell $eq $eq$ls180.v:8079$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253464,10 +255283,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7930$2522_Y + connect \Y $eq$ls180.v:8079$2664_Y end - attribute \src "ls180.v:7930.296-7930.329" - cell $eq $eq$ls180.v:7930$2525 + attribute \src "ls180.v:8079.296-8079.329" + cell $eq $eq$ls180.v:8079$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253475,10 +255294,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7930$2525_Y + connect \Y $eq$ls180.v:8079$2667_Y end - attribute \src "ls180.v:7965.9-7965.42" - cell $eq $eq$ls180.v:7965$2537 + attribute \src "ls180.v:8114.9-8114.42" + cell $eq $eq$ls180.v:8114$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253486,10 +255305,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:7965$2537_Y + connect \Y $eq$ls180.v:8114$2679_Y end - attribute \src "ls180.v:7968.10-7968.43" - cell $eq $eq$ls180.v:7968$2538 + attribute \src "ls180.v:8117.10-8117.43" + cell $eq $eq$ls180.v:8117$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253497,10 +255316,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:7968$2538_Y + connect \Y $eq$ls180.v:8117$2680_Y end - attribute \src "ls180.v:7994.9-7994.42" - cell $eq $eq$ls180.v:7994$2544 + attribute \src "ls180.v:8143.9-8143.42" + cell $eq $eq$ls180.v:8143$2686 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253508,10 +255327,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:7994$2544_Y + connect \Y $eq$ls180.v:8143$2686_Y end - attribute \src "ls180.v:7999.10-7999.43" - cell $eq $eq$ls180.v:7999$2545 + attribute \src "ls180.v:8148.10-8148.43" + cell $eq $eq$ls180.v:8148$2687 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253519,10 +255338,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:7999$2545_Y + connect \Y $eq$ls180.v:8148$2687_Y end - attribute \src "ls180.v:8206.9-8206.53" - cell $eq $eq$ls180.v:8206$2594 + attribute \src "ls180.v:8355.9-8355.53" + cell $eq $eq$ls180.v:8355$2736 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253530,10 +255349,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8206$2594_Y + connect \Y $eq$ls180.v:8355$2736_Y end - attribute \src "ls180.v:8287.9-8287.54" - cell $eq $eq$ls180.v:8287$2606 + attribute \src "ls180.v:8436.9-8436.54" + cell $eq $eq$ls180.v:8436$2748 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253541,10 +255360,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8287$2606_Y + connect \Y $eq$ls180.v:8436$2748_Y end - attribute \src "ls180.v:8366.9-8366.55" - cell $eq $eq$ls180.v:8366$2618 + attribute \src "ls180.v:8515.9-8515.55" + cell $eq $eq$ls180.v:8515$2760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253552,43 +255371,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8366$2618_Y + connect \Y $eq$ls180.v:8515$2760_Y end - attribute \src "ls180.v:8589.9-8589.49" - cell $eq $eq$ls180.v:8589$2651 + attribute \src "ls180.v:8738.9-8738.49" + cell $eq $eq$ls180.v:8738$2793 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux - connect \B 2'11 - connect \Y $eq$ls180.v:8589$2651_Y + connect \B 3'111 + connect \Y $eq$ls180.v:8738$2793_Y end - attribute \src "ls180.v:8165.8-8165.54" - cell $ge $ge$ls180.v:8165$2586 + attribute \src "ls180.v:8314.8-8314.54" + cell $ge $ge$ls180.v:8314$2728 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8165$2585_Y - connect \Y $ge$ls180.v:8165$2586_Y + connect \B $sub$ls180.v:8314$2727_Y + connect \Y $ge$ls180.v:8314$2728_Y end - attribute \src "ls180.v:8179.8-8179.54" - cell $ge $ge$ls180.v:8179$2590 + attribute \src "ls180.v:8328.8-8328.54" + cell $ge $ge$ls180.v:8328$2732 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8179$2589_Y - connect \Y $ge$ls180.v:8179$2590_Y + connect \B $sub$ls180.v:8328$2731_Y + connect \Y $ge$ls180.v:8328$2732_Y end - attribute \src "ls180.v:5151.47-5151.83" - cell $gt $gt$ls180.v:5151$914 + attribute \src "ls180.v:5249.47-5249.83" + cell $gt $gt$ls180.v:5249$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253596,10 +255415,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $gt$ls180.v:5151$914_Y + connect \Y $gt$ls180.v:5249$1029_Y end - attribute \src "ls180.v:5157.7-5157.43" - cell $lt $lt$ls180.v:5157$917 + attribute \src "ls180.v:5255.7-5255.43" + cell $lt $lt$ls180.v:5255$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253607,10 +255426,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1000 - connect \Y $lt$ls180.v:5157$917_Y + connect \Y $lt$ls180.v:5255$1032_Y end - attribute \src "ls180.v:8160.8-8160.43" - cell $lt $lt$ls180.v:8160$2584 + attribute \src "ls180.v:8309.8-8309.43" + cell $lt $lt$ls180.v:8309$2726 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -253618,10 +255437,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8160$2584_Y + connect \Y $lt$ls180.v:8309$2726_Y end - attribute \src "ls180.v:8174.8-8174.43" - cell $lt $lt$ls180.v:8174$2588 + attribute \src "ls180.v:8323.8-8323.43" + cell $lt $lt$ls180.v:8323$2730 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -253629,23 +255448,62 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8174$2588_Y + connect \Y $lt$ls180.v:8323$2730_Y end - attribute \src "ls180.v:10055.33-10055.36" - cell $memrd $memrd$\mem$ls180.v:10055$2693 - parameter \ABITS 7 + attribute \src "ls180.v:10227.33-10227.36" + cell $memrd $memrd$\mem$ls180.v:10227$2847 + parameter \ABITS 9 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10055$2693_DATA + connect \DATA $memrd$\mem$ls180.v:10227$2847_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10255.27-10255.32" + cell $memrd $memrd$\mem_1$ls180.v:10255$2873 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_1 + connect \CLK 1'x + connect \DATA $memrd$\mem_1$ls180.v:10255$2873_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10283.27-10283.32" + cell $memrd $memrd$\mem_2$ls180.v:10283$2899 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_2 + connect \CLK 1'x + connect \DATA $memrd$\mem_2$ls180.v:10283$2899_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10311.27-10311.32" + cell $memrd $memrd$\mem_3$ls180.v:10311$2925 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_3 + connect \CLK 1'x + connect \DATA $memrd$\mem_3$ls180.v:10311$2925_DATA connect \EN 1'x end - attribute \src "ls180.v:10066.12-10066.19" - cell $memrd $memrd$\storage$ls180.v:10066$2698 + attribute \src "ls180.v:10322.12-10322.19" + cell $memrd $memrd$\storage$ls180.v:10322$2930 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253654,11 +255512,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10066$2698_DATA + connect \DATA $memrd$\storage$ls180.v:10322$2930_DATA connect \EN 1'x end - attribute \src "ls180.v:10073.68-10073.75" - cell $memrd $memrd$\storage$ls180.v:10073$2700 + attribute \src "ls180.v:10329.68-10329.75" + cell $memrd $memrd$\storage$ls180.v:10329$2932 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253667,11 +255525,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10073$2700_DATA + connect \DATA $memrd$\storage$ls180.v:10329$2932_DATA connect \EN 1'x end - attribute \src "ls180.v:10080.14-10080.23" - cell $memrd $memrd$\storage_1$ls180.v:10080$2705 + attribute \src "ls180.v:10336.14-10336.23" + cell $memrd $memrd$\storage_1$ls180.v:10336$2937 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253680,11 +255538,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10080$2705_DATA + connect \DATA $memrd$\storage_1$ls180.v:10336$2937_DATA connect \EN 1'x end - attribute \src "ls180.v:10087.68-10087.77" - cell $memrd $memrd$\storage_1$ls180.v:10087$2707 + attribute \src "ls180.v:10343.68-10343.77" + cell $memrd $memrd$\storage_1$ls180.v:10343$2939 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253693,11 +255551,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10087$2707_DATA + connect \DATA $memrd$\storage_1$ls180.v:10343$2939_DATA connect \EN 1'x end - attribute \src "ls180.v:10094.14-10094.23" - cell $memrd $memrd$\storage_2$ls180.v:10094$2712 + attribute \src "ls180.v:10350.14-10350.23" + cell $memrd $memrd$\storage_2$ls180.v:10350$2944 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253706,11 +255564,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10094$2712_DATA + connect \DATA $memrd$\storage_2$ls180.v:10350$2944_DATA connect \EN 1'x end - attribute \src "ls180.v:10101.68-10101.77" - cell $memrd $memrd$\storage_2$ls180.v:10101$2714 + attribute \src "ls180.v:10357.68-10357.77" + cell $memrd $memrd$\storage_2$ls180.v:10357$2946 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253719,11 +255577,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10101$2714_DATA + connect \DATA $memrd$\storage_2$ls180.v:10357$2946_DATA connect \EN 1'x end - attribute \src "ls180.v:10108.14-10108.23" - cell $memrd $memrd$\storage_3$ls180.v:10108$2719 + attribute \src "ls180.v:10364.14-10364.23" + cell $memrd $memrd$\storage_3$ls180.v:10364$2951 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253732,11 +255590,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10108$2719_DATA + connect \DATA $memrd$\storage_3$ls180.v:10364$2951_DATA connect \EN 1'x end - attribute \src "ls180.v:10115.68-10115.77" - cell $memrd $memrd$\storage_3$ls180.v:10115$2721 + attribute \src "ls180.v:10371.68-10371.77" + cell $memrd $memrd$\storage_3$ls180.v:10371$2953 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253745,11 +255603,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10115$2721_DATA + connect \DATA $memrd$\storage_3$ls180.v:10371$2953_DATA connect \EN 1'x end - attribute \src "ls180.v:10123.14-10123.23" - cell $memrd $memrd$\storage_4$ls180.v:10123$2726 + attribute \src "ls180.v:10379.14-10379.23" + cell $memrd $memrd$\storage_4$ls180.v:10379$2958 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253758,11 +255616,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10123$2726_DATA + connect \DATA $memrd$\storage_4$ls180.v:10379$2958_DATA connect \EN 1'x end - attribute \src "ls180.v:10128.15-10128.24" - cell $memrd $memrd$\storage_4$ls180.v:10128$2728 + attribute \src "ls180.v:10384.15-10384.24" + cell $memrd $memrd$\storage_4$ls180.v:10384$2960 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253771,11 +255629,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10128$2728_DATA + connect \DATA $memrd$\storage_4$ls180.v:10384$2960_DATA connect \EN 1'x end - attribute \src "ls180.v:10140.14-10140.23" - cell $memrd $memrd$\storage_5$ls180.v:10140$2733 + attribute \src "ls180.v:10396.14-10396.23" + cell $memrd $memrd$\storage_5$ls180.v:10396$2965 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253784,11 +255642,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10140$2733_DATA + connect \DATA $memrd$\storage_5$ls180.v:10396$2965_DATA connect \EN 1'x end - attribute \src "ls180.v:10145.15-10145.24" - cell $memrd $memrd$\storage_5$ls180.v:10145$2735 + attribute \src "ls180.v:10401.15-10401.24" + cell $memrd $memrd$\storage_5$ls180.v:10401$2967 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253797,11 +255655,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10145$2735_DATA + connect \DATA $memrd$\storage_5$ls180.v:10401$2967_DATA connect \EN 1'x end - attribute \src "ls180.v:10156.14-10156.23" - cell $memrd $memrd$\storage_6$ls180.v:10156$2740 + attribute \src "ls180.v:10412.14-10412.23" + cell $memrd $memrd$\storage_6$ls180.v:10412$2972 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253810,11 +255668,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10156$2740_DATA + connect \DATA $memrd$\storage_6$ls180.v:10412$2972_DATA connect \EN 1'x end - attribute \src "ls180.v:10163.45-10163.54" - cell $memrd $memrd$\storage_6$ls180.v:10163$2742 + attribute \src "ls180.v:10419.45-10419.54" + cell $memrd $memrd$\storage_6$ls180.v:10419$2974 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253823,11 +255681,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10163$2742_DATA + connect \DATA $memrd$\storage_6$ls180.v:10419$2974_DATA connect \EN 1'x end - attribute \src "ls180.v:10170.14-10170.23" - cell $memrd $memrd$\storage_7$ls180.v:10170$2747 + attribute \src "ls180.v:10426.14-10426.23" + cell $memrd $memrd$\storage_7$ls180.v:10426$2979 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253836,11 +255694,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10170$2747_DATA + connect \DATA $memrd$\storage_7$ls180.v:10426$2979_DATA connect \EN 1'x end - attribute \src "ls180.v:10177.45-10177.54" - cell $memrd $memrd$\storage_7$ls180.v:10177$2749 + attribute \src "ls180.v:10433.45-10433.54" + cell $memrd $memrd$\storage_7$ls180.v:10433$2981 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -253849,167 +255707,531 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10177$2749_DATA + connect \DATA $memrd$\storage_7$ls180.v:10433$2981_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2751 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2983 + parameter \ABITS 9 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2751 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10045$1_ADDR + parameter \PRIORITY 2983 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10209$1_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10045$1_DATA - connect \EN $memwr$\mem$ls180.v:10045$1_EN + connect \DATA $memwr$\mem$ls180.v:10209$1_DATA + connect \EN $memwr$\mem$ls180.v:10209$1_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2752 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2984 + parameter \ABITS 9 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2752 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10047$2_ADDR + parameter \PRIORITY 2984 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10211$2_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10047$2_DATA - connect \EN $memwr$\mem$ls180.v:10047$2_EN + connect \DATA $memwr$\mem$ls180.v:10211$2_DATA + connect \EN $memwr$\mem$ls180.v:10211$2_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2753 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2985 + parameter \ABITS 9 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2753 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10049$3_ADDR + parameter \PRIORITY 2985 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10213$3_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10049$3_DATA - connect \EN $memwr$\mem$ls180.v:10049$3_EN + connect \DATA $memwr$\mem$ls180.v:10213$3_DATA + connect \EN $memwr$\mem$ls180.v:10213$3_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2754 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2986 + parameter \ABITS 9 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2754 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10051$4_ADDR + parameter \PRIORITY 2986 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10215$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10215$4_DATA + connect \EN $memwr$\mem$ls180.v:10215$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2987 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2987 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10217$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10217$5_DATA + connect \EN $memwr$\mem$ls180.v:10217$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2988 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2988 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10219$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10219$6_DATA + connect \EN $memwr$\mem$ls180.v:10219$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2989 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2989 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10221$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10221$7_DATA + connect \EN $memwr$\mem$ls180.v:10221$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2990 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2990 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10223$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10223$8_DATA + connect \EN $memwr$\mem$ls180.v:10223$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2991 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2991 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10237$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10237$9_DATA + connect \EN $memwr$\mem_1$ls180.v:10237$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2992 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2992 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10239$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10239$10_DATA + connect \EN $memwr$\mem_1$ls180.v:10239$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2993 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2993 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10241$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10241$11_DATA + connect \EN $memwr$\mem_1$ls180.v:10241$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2994 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2994 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10243$12_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10051$4_DATA - connect \EN $memwr$\mem$ls180.v:10051$4_EN + connect \DATA $memwr$\mem_1$ls180.v:10243$12_DATA + connect \EN $memwr$\mem_1$ls180.v:10243$12_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2755 + cell $memwr $memwr$\mem_1$ls180.v:0$2995 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2995 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10245$13_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10245$13_DATA + connect \EN $memwr$\mem_1$ls180.v:10245$13_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2996 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2996 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10247$14_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10247$14_DATA + connect \EN $memwr$\mem_1$ls180.v:10247$14_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2997 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2997 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10249$15_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10249$15_DATA + connect \EN $memwr$\mem_1$ls180.v:10249$15_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2998 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2998 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10251$16_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10251$16_DATA + connect \EN $memwr$\mem_1$ls180.v:10251$16_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$2999 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 2999 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10265$17_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10265$17_DATA + connect \EN $memwr$\mem_2$ls180.v:10265$17_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3000 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3000 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10267$18_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10267$18_DATA + connect \EN $memwr$\mem_2$ls180.v:10267$18_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3001 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3001 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10269$19_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10269$19_DATA + connect \EN $memwr$\mem_2$ls180.v:10269$19_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3002 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3002 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10271$20_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10271$20_DATA + connect \EN $memwr$\mem_2$ls180.v:10271$20_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3003 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3003 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10273$21_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10273$21_DATA + connect \EN $memwr$\mem_2$ls180.v:10273$21_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3004 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3004 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10275$22_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10275$22_DATA + connect \EN $memwr$\mem_2$ls180.v:10275$22_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3005 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3005 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10277$23_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10277$23_DATA + connect \EN $memwr$\mem_2$ls180.v:10277$23_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3006 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3006 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10279$24_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10279$24_DATA + connect \EN $memwr$\mem_2$ls180.v:10279$24_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3007 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3007 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10293$25_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10293$25_DATA + connect \EN $memwr$\mem_3$ls180.v:10293$25_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3008 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3008 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10295$26_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10295$26_DATA + connect \EN $memwr$\mem_3$ls180.v:10295$26_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3009 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3009 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10297$27_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10297$27_DATA + connect \EN $memwr$\mem_3$ls180.v:10297$27_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3010 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3010 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10299$28_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10299$28_DATA + connect \EN $memwr$\mem_3$ls180.v:10299$28_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3011 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3011 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10301$29_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10301$29_DATA + connect \EN $memwr$\mem_3$ls180.v:10301$29_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3012 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3012 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10303$30_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10303$30_DATA + connect \EN $memwr$\mem_3$ls180.v:10303$30_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3013 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3013 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10305$31_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10305$31_DATA + connect \EN $memwr$\mem_3$ls180.v:10305$31_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3014 + parameter \ABITS 9 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3014 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10307$32_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10307$32_DATA + connect \EN $memwr$\mem_3$ls180.v:10307$32_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$3015 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" - parameter \PRIORITY 2755 + parameter \PRIORITY 3015 parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10065$5_ADDR + connect \ADDR $memwr$\storage$ls180.v:10321$33_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10065$5_DATA - connect \EN $memwr$\storage$ls180.v:10065$5_EN + connect \DATA $memwr$\storage$ls180.v:10321$33_DATA + connect \EN $memwr$\storage$ls180.v:10321$33_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2756 + cell $memwr $memwr$\storage_1$ls180.v:0$3016 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" - parameter \PRIORITY 2756 + parameter \PRIORITY 3016 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10079$6_ADDR + connect \ADDR $memwr$\storage_1$ls180.v:10335$34_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10079$6_DATA - connect \EN $memwr$\storage_1$ls180.v:10079$6_EN + connect \DATA $memwr$\storage_1$ls180.v:10335$34_DATA + connect \EN $memwr$\storage_1$ls180.v:10335$34_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2757 + cell $memwr $memwr$\storage_2$ls180.v:0$3017 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" - parameter \PRIORITY 2757 + parameter \PRIORITY 3017 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10093$7_ADDR + connect \ADDR $memwr$\storage_2$ls180.v:10349$35_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10093$7_DATA - connect \EN $memwr$\storage_2$ls180.v:10093$7_EN + connect \DATA $memwr$\storage_2$ls180.v:10349$35_DATA + connect \EN $memwr$\storage_2$ls180.v:10349$35_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2758 + cell $memwr $memwr$\storage_3$ls180.v:0$3018 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" - parameter \PRIORITY 2758 + parameter \PRIORITY 3018 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10107$8_ADDR + connect \ADDR $memwr$\storage_3$ls180.v:10363$36_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10107$8_DATA - connect \EN $memwr$\storage_3$ls180.v:10107$8_EN + connect \DATA $memwr$\storage_3$ls180.v:10363$36_DATA + connect \EN $memwr$\storage_3$ls180.v:10363$36_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2759 + cell $memwr $memwr$\storage_4$ls180.v:0$3019 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" - parameter \PRIORITY 2759 + parameter \PRIORITY 3019 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10122$9_ADDR + connect \ADDR $memwr$\storage_4$ls180.v:10378$37_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10122$9_DATA - connect \EN $memwr$\storage_4$ls180.v:10122$9_EN + connect \DATA $memwr$\storage_4$ls180.v:10378$37_DATA + connect \EN $memwr$\storage_4$ls180.v:10378$37_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2760 + cell $memwr $memwr$\storage_5$ls180.v:0$3020 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" - parameter \PRIORITY 2760 + parameter \PRIORITY 3020 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10139$10_ADDR + connect \ADDR $memwr$\storage_5$ls180.v:10395$38_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10139$10_DATA - connect \EN $memwr$\storage_5$ls180.v:10139$10_EN + connect \DATA $memwr$\storage_5$ls180.v:10395$38_DATA + connect \EN $memwr$\storage_5$ls180.v:10395$38_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2761 + cell $memwr $memwr$\storage_6$ls180.v:0$3021 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_6" - parameter \PRIORITY 2761 + parameter \PRIORITY 3021 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10155$11_ADDR + connect \ADDR $memwr$\storage_6$ls180.v:10411$39_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10155$11_DATA - connect \EN $memwr$\storage_6$ls180.v:10155$11_EN + connect \DATA $memwr$\storage_6$ls180.v:10411$39_DATA + connect \EN $memwr$\storage_6$ls180.v:10411$39_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2762 + cell $memwr $memwr$\storage_7$ls180.v:0$3022 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_7" - parameter \PRIORITY 2762 + parameter \PRIORITY 3022 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10169$12_ADDR + connect \ADDR $memwr$\storage_7$ls180.v:10425$40_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10169$12_DATA - connect \EN $memwr$\storage_7$ls180.v:10169$12_EN + connect \DATA $memwr$\storage_7$ls180.v:10425$40_DATA + connect \EN $memwr$\storage_7$ls180.v:10425$40_EN end - attribute \src "ls180.v:2965.41-2965.71" - cell $ne $ne$ls180.v:2965$60 + attribute \src "ls180.v:3021.41-3021.71" + cell $ne $ne$ls180.v:3021$100 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254017,10 +256239,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $ne$ls180.v:2965$60_Y + connect \Y $ne$ls180.v:3021$100_Y end - attribute \src "ls180.v:3126.70-3126.104" - cell $ne $ne$ls180.v:3126$74 + attribute \src "ls180.v:3224.70-3224.104" + cell $ne $ne$ls180.v:3224$189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254028,10 +256250,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:3126$74_Y + connect \Y $ne$ls180.v:3224$189_Y end - attribute \src "ls180.v:3187.8-3187.142" - cell $ne $ne$ls180.v:3187$93 + attribute \src "ls180.v:3285.8-3285.142" + cell $ne $ne$ls180.v:3285$208 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -254039,10 +256261,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3187$93_Y + connect \Y $ne$ls180.v:3285$208_Y end - attribute \src "ls180.v:3219.75-3219.133" - cell $ne $ne$ls180.v:3219$100 + attribute \src "ls180.v:3317.75-3317.133" + cell $ne $ne$ls180.v:3317$215 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254050,10 +256272,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3219$100_Y + connect \Y $ne$ls180.v:3317$215_Y end - attribute \src "ls180.v:3220.75-3220.133" - cell $ne $ne$ls180.v:3220$101 + attribute \src "ls180.v:3318.75-3318.133" + cell $ne $ne$ls180.v:3318$216 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254061,10 +256283,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3220$101_Y + connect \Y $ne$ls180.v:3318$216_Y end - attribute \src "ls180.v:3344.8-3344.142" - cell $ne $ne$ls180.v:3344$123 + attribute \src "ls180.v:3442.8-3442.142" + cell $ne $ne$ls180.v:3442$238 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -254072,10 +256294,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3344$123_Y + connect \Y $ne$ls180.v:3442$238_Y end - attribute \src "ls180.v:3376.75-3376.133" - cell $ne $ne$ls180.v:3376$130 + attribute \src "ls180.v:3474.75-3474.133" + cell $ne $ne$ls180.v:3474$245 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254083,10 +256305,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3376$130_Y + connect \Y $ne$ls180.v:3474$245_Y end - attribute \src "ls180.v:3377.75-3377.133" - cell $ne $ne$ls180.v:3377$131 + attribute \src "ls180.v:3475.75-3475.133" + cell $ne $ne$ls180.v:3475$246 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254094,10 +256316,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3377$131_Y + connect \Y $ne$ls180.v:3475$246_Y end - attribute \src "ls180.v:3501.8-3501.142" - cell $ne $ne$ls180.v:3501$153 + attribute \src "ls180.v:3599.8-3599.142" + cell $ne $ne$ls180.v:3599$268 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -254105,10 +256327,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3501$153_Y + connect \Y $ne$ls180.v:3599$268_Y end - attribute \src "ls180.v:3533.75-3533.133" - cell $ne $ne$ls180.v:3533$160 + attribute \src "ls180.v:3631.75-3631.133" + cell $ne $ne$ls180.v:3631$275 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254116,10 +256338,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3533$160_Y + connect \Y $ne$ls180.v:3631$275_Y end - attribute \src "ls180.v:3534.75-3534.133" - cell $ne $ne$ls180.v:3534$161 + attribute \src "ls180.v:3632.75-3632.133" + cell $ne $ne$ls180.v:3632$276 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254127,10 +256349,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3534$161_Y + connect \Y $ne$ls180.v:3632$276_Y end - attribute \src "ls180.v:3658.8-3658.142" - cell $ne $ne$ls180.v:3658$183 + attribute \src "ls180.v:3756.8-3756.142" + cell $ne $ne$ls180.v:3756$298 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -254138,10 +256360,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3658$183_Y + connect \Y $ne$ls180.v:3756$298_Y end - attribute \src "ls180.v:3690.75-3690.133" - cell $ne $ne$ls180.v:3690$190 + attribute \src "ls180.v:3788.75-3788.133" + cell $ne $ne$ls180.v:3788$305 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254149,10 +256371,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3690$190_Y + connect \Y $ne$ls180.v:3788$305_Y end - attribute \src "ls180.v:3691.75-3691.133" - cell $ne $ne$ls180.v:3691$191 + attribute \src "ls180.v:3789.75-3789.133" + cell $ne $ne$ls180.v:3789$306 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254160,10 +256382,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3691$191_Y + connect \Y $ne$ls180.v:3789$306_Y end - attribute \src "ls180.v:4183.47-4183.80" - cell $ne $ne$ls180.v:4183$589 + attribute \src "ls180.v:4281.47-4281.80" + cell $ne $ne$ls180.v:4281$704 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254171,10 +256393,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4183$589_Y + connect \Y $ne$ls180.v:4281$704_Y end - attribute \src "ls180.v:4184.47-4184.79" - cell $ne $ne$ls180.v:4184$590 + attribute \src "ls180.v:4282.47-4282.79" + cell $ne $ne$ls180.v:4282$705 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254182,10 +256404,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4184$590_Y + connect \Y $ne$ls180.v:4282$705_Y end - attribute \src "ls180.v:4213.47-4213.80" - cell $ne $ne$ls180.v:4213$600 + attribute \src "ls180.v:4311.47-4311.80" + cell $ne $ne$ls180.v:4311$715 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254193,10 +256415,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4213$600_Y + connect \Y $ne$ls180.v:4311$715_Y end - attribute \src "ls180.v:4214.47-4214.79" - cell $ne $ne$ls180.v:4214$601 + attribute \src "ls180.v:4312.47-4312.79" + cell $ne $ne$ls180.v:4312$716 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254204,10 +256426,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4214$601_Y + connect \Y $ne$ls180.v:4312$716_Y end - attribute \src "ls180.v:4683.32-4683.89" - cell $ne $ne$ls180.v:4683$681 + attribute \src "ls180.v:4781.32-4781.89" + cell $ne $ne$ls180.v:4781$796 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -254215,10 +256437,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $ne$ls180.v:4683$681_Y + connect \Y $ne$ls180.v:4781$796_Y end - attribute \src "ls180.v:5330.10-5330.56" - cell $ne $ne$ls180.v:5330$978 + attribute \src "ls180.v:5428.10-5428.56" + cell $ne $ne$ls180.v:5428$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254226,10 +256448,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 2'10 - connect \Y $ne$ls180.v:5330$978_Y + connect \Y $ne$ls180.v:5428$1093_Y end - attribute \src "ls180.v:5435.51-5435.87" - cell $ne $ne$ls180.v:5435$992 + attribute \src "ls180.v:5533.51-5533.87" + cell $ne $ne$ls180.v:5533$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -254237,10 +256459,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5435$992_Y + connect \Y $ne$ls180.v:5533$1107_Y end - attribute \src "ls180.v:5436.51-5436.86" - cell $ne $ne$ls180.v:5436$993 + attribute \src "ls180.v:5534.51-5534.86" + cell $ne $ne$ls180.v:5534$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -254248,10 +256470,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5436$993_Y + connect \Y $ne$ls180.v:5534$1108_Y end - attribute \src "ls180.v:5643.51-5643.87" - cell $ne $ne$ls180.v:5643$1023 + attribute \src "ls180.v:5753.51-5753.87" + cell $ne $ne$ls180.v:5753$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -254259,10 +256481,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5643$1023_Y + connect \Y $ne$ls180.v:5753$1138_Y end - attribute \src "ls180.v:5644.51-5644.86" - cell $ne $ne$ls180.v:5644$1024 + attribute \src "ls180.v:5754.51-5754.86" + cell $ne $ne$ls180.v:5754$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -254270,10 +256492,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5644$1024_Y + connect \Y $ne$ls180.v:5754$1139_Y end - attribute \src "ls180.v:5675.79-5675.119" - cell $ne $ne$ls180.v:5675$1027 + attribute \src "ls180.v:5785.79-5785.119" + cell $ne $ne$ls180.v:5785$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254281,10 +256503,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_sel connect \B 1'0 - connect \Y $ne$ls180.v:5675$1027_Y + connect \Y $ne$ls180.v:5785$1142_Y end - attribute \src "ls180.v:7485.7-7485.52" - cell $ne $ne$ls180.v:7485$2402 + attribute \src "ls180.v:7622.7-7622.52" + cell $ne $ne$ls180.v:7622$2535 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254292,10 +256514,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7485$2402_Y + connect \Y $ne$ls180.v:7622$2535_Y end - attribute \src "ls180.v:7535.9-7535.43" - cell $ne $ne$ls180.v:7535$2416 + attribute \src "ls180.v:7684.9-7684.43" + cell $ne $ne$ls180.v:7684$2558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254303,10 +256525,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7535$2416_Y + connect \Y $ne$ls180.v:7684$2558_Y end - attribute \src "ls180.v:7571.8-7571.44" - cell $ne $ne$ls180.v:7571$2423 + attribute \src "ls180.v:7720.8-7720.44" + cell $ne $ne$ls180.v:7720$2565 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254314,10 +256536,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7571$2423_Y + connect \Y $ne$ls180.v:7720$2565_Y end - attribute \src "ls180.v:8509.9-8509.47" - cell $ne $ne$ls180.v:8509$2638 + attribute \src "ls180.v:8658.9-8658.47" + cell $ne $ne$ls180.v:8658$2780 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254325,2706 +256547,2730 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8509$2638_Y + connect \Y $ne$ls180.v:8658$2780_Y end - attribute \src "ls180.v:2773.45-2773.80" - cell $not $not$ls180.v:2773$14 + attribute \src "ls180.v:2825.33-2825.73" + cell $not $not$ls180.v:2825$42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:2773$14_Y + connect \A \main_interface0_converted_interface_cyc + connect \Y $not$ls180.v:2825$42_Y end - attribute \src "ls180.v:2812.61-2812.94" - cell $not $not$ls180.v:2812$19 + attribute \src "ls180.v:2864.48-2864.69" + cell $not $not$ls180.v:2864$47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2812$19_Y + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2864$47_Y end - attribute \src "ls180.v:2813.61-2813.94" - cell $not $not$ls180.v:2813$20 + attribute \src "ls180.v:2865.48-2865.69" + cell $not $not$ls180.v:2865$48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2813$20_Y + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2865$48_Y end - attribute \src "ls180.v:2833.45-2833.80" - cell $not $not$ls180.v:2833$25 + attribute \src "ls180.v:2885.33-2885.73" + cell $not $not$ls180.v:2885$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:2833$25_Y + connect \A \main_interface1_converted_interface_cyc + connect \Y $not$ls180.v:2885$53_Y end - attribute \src "ls180.v:2872.61-2872.94" - cell $not $not$ls180.v:2872$30 + attribute \src "ls180.v:2924.48-2924.69" + cell $not $not$ls180.v:2924$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2872$30_Y + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2924$58_Y end - attribute \src "ls180.v:2873.61-2873.94" - cell $not $not$ls180.v:2873$31 + attribute \src "ls180.v:2925.48-2925.69" + cell $not $not$ls180.v:2925$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2873$31_Y + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2925$59_Y end - attribute \src "ls180.v:2893.45-2893.83" - cell $not $not$ls180.v:2893$36 + attribute \src "ls180.v:2945.36-2945.79" + cell $not $not$ls180.v:2945$64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $not$ls180.v:2893$36_Y + connect \A \main_socbushandler_converted_interface_cyc + connect \Y $not$ls180.v:2945$64_Y end - attribute \src "ls180.v:2932.61-2932.94" - cell $not $not$ls180.v:2932$41 + attribute \src "ls180.v:2984.27-2984.51" + cell $not $not$ls180.v:2984$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2932$41_Y + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:2984$69_Y end - attribute \src "ls180.v:2933.61-2933.94" - cell $not $not$ls180.v:2933$42 + attribute \src "ls180.v:2985.27-2985.51" + cell $not $not$ls180.v:2985$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2933$42_Y + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:2985$70_Y end - attribute \src "ls180.v:3075.34-3075.64" - cell $not $not$ls180.v:3075$66 + attribute \src "ls180.v:3173.34-3173.64" + cell $not $not$ls180.v:3173$181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3075$66_Y + connect \Y $not$ls180.v:3173$181_Y end - attribute \src "ls180.v:3076.31-3076.61" - cell $not $not$ls180.v:3076$67 + attribute \src "ls180.v:3174.31-3174.61" + cell $not $not$ls180.v:3174$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3076$67_Y + connect \Y $not$ls180.v:3174$182_Y end - attribute \src "ls180.v:3077.32-3077.62" - cell $not $not$ls180.v:3077$68 + attribute \src "ls180.v:3175.32-3175.62" + cell $not $not$ls180.v:3175$183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3077$68_Y + connect \Y $not$ls180.v:3175$183_Y end - attribute \src "ls180.v:3078.32-3078.62" - cell $not $not$ls180.v:3078$69 + attribute \src "ls180.v:3176.32-3176.62" + cell $not $not$ls180.v:3176$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3078$69_Y + connect \Y $not$ls180.v:3176$184_Y end - attribute \src "ls180.v:3120.33-3120.56" - cell $not $not$ls180.v:3120$72 + attribute \src "ls180.v:3218.33-3218.56" + cell $not $not$ls180.v:3218$187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3120$72_Y + connect \Y $not$ls180.v:3218$187_Y end - attribute \src "ls180.v:3221.58-3221.106" - cell $not $not$ls180.v:3221$102 + attribute \src "ls180.v:3319.58-3319.106" + cell $not $not$ls180.v:3319$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3221$102_Y + connect \Y $not$ls180.v:3319$217_Y end - attribute \src "ls180.v:3275.9-3275.45" - cell $not $not$ls180.v:3275$107 + attribute \src "ls180.v:3373.9-3373.45" + cell $not $not$ls180.v:3373$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3275$107_Y + connect \Y $not$ls180.v:3373$222_Y end - attribute \src "ls180.v:3378.58-3378.106" - cell $not $not$ls180.v:3378$132 + attribute \src "ls180.v:3476.58-3476.106" + cell $not $not$ls180.v:3476$247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3378$132_Y + connect \Y $not$ls180.v:3476$247_Y end - attribute \src "ls180.v:3432.9-3432.45" - cell $not $not$ls180.v:3432$137 + attribute \src "ls180.v:3530.9-3530.45" + cell $not $not$ls180.v:3530$252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3432$137_Y + connect \Y $not$ls180.v:3530$252_Y end - attribute \src "ls180.v:3535.58-3535.106" - cell $not $not$ls180.v:3535$162 + attribute \src "ls180.v:3633.58-3633.106" + cell $not $not$ls180.v:3633$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3535$162_Y + connect \Y $not$ls180.v:3633$277_Y end - attribute \src "ls180.v:3589.9-3589.45" - cell $not $not$ls180.v:3589$167 + attribute \src "ls180.v:3687.9-3687.45" + cell $not $not$ls180.v:3687$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3589$167_Y + connect \Y $not$ls180.v:3687$282_Y end - attribute \src "ls180.v:3692.58-3692.106" - cell $not $not$ls180.v:3692$192 + attribute \src "ls180.v:3790.58-3790.106" + cell $not $not$ls180.v:3790$307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3692$192_Y + connect \Y $not$ls180.v:3790$307_Y end - attribute \src "ls180.v:3746.9-3746.45" - cell $not $not$ls180.v:3746$197 + attribute \src "ls180.v:3844.9-3844.45" + cell $not $not$ls180.v:3844$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3746$197_Y + connect \Y $not$ls180.v:3844$312_Y end - attribute \src "ls180.v:3788.149-3788.187" - cell $not $not$ls180.v:3788$200 + attribute \src "ls180.v:3886.149-3886.187" + cell $not $not$ls180.v:3886$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3788$200_Y + connect \Y $not$ls180.v:3886$315_Y end - attribute \src "ls180.v:3788.193-3788.230" - cell $not $not$ls180.v:3788$202 + attribute \src "ls180.v:3886.193-3886.230" + cell $not $not$ls180.v:3886$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3788$202_Y + connect \Y $not$ls180.v:3886$317_Y end - attribute \src "ls180.v:3789.149-3789.187" - cell $not $not$ls180.v:3789$206 + attribute \src "ls180.v:3887.149-3887.187" + cell $not $not$ls180.v:3887$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3789$206_Y + connect \Y $not$ls180.v:3887$321_Y end - attribute \src "ls180.v:3789.193-3789.230" - cell $not $not$ls180.v:3789$208 + attribute \src "ls180.v:3887.193-3887.230" + cell $not $not$ls180.v:3887$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3789$208_Y + connect \Y $not$ls180.v:3887$323_Y end - attribute \src "ls180.v:3805.43-3805.73" - cell $not $not$ls180.v:3805$236 + attribute \src "ls180.v:3903.43-3903.73" + cell $not $not$ls180.v:3903$351 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3805$236_Y + connect \Y $not$ls180.v:3903$351_Y end - attribute \src "ls180.v:3808.205-3808.245" - cell $not $not$ls180.v:3808$239 + attribute \src "ls180.v:3906.205-3906.245" + cell $not $not$ls180.v:3906$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3808$239_Y + connect \Y $not$ls180.v:3906$354_Y end - attribute \src "ls180.v:3808.251-3808.290" - cell $not $not$ls180.v:3808$241 + attribute \src "ls180.v:3906.251-3906.290" + cell $not $not$ls180.v:3906$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3808$241_Y + connect \Y $not$ls180.v:3906$356_Y end - attribute \src "ls180.v:3808.159-3808.292" - cell $not $not$ls180.v:3808$243 + attribute \src "ls180.v:3906.159-3906.292" + cell $not $not$ls180.v:3906$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3808$242_Y - connect \Y $not$ls180.v:3808$243_Y + connect \A $and$ls180.v:3906$357_Y + connect \Y $not$ls180.v:3906$358_Y end - attribute \src "ls180.v:3809.205-3809.245" - cell $not $not$ls180.v:3809$252 + attribute \src "ls180.v:3907.205-3907.245" + cell $not $not$ls180.v:3907$367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3809$252_Y + connect \Y $not$ls180.v:3907$367_Y end - attribute \src "ls180.v:3809.251-3809.290" - cell $not $not$ls180.v:3809$254 + attribute \src "ls180.v:3907.251-3907.290" + cell $not $not$ls180.v:3907$369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3809$254_Y + connect \Y $not$ls180.v:3907$369_Y end - attribute \src "ls180.v:3809.159-3809.292" - cell $not $not$ls180.v:3809$256 + attribute \src "ls180.v:3907.159-3907.292" + cell $not $not$ls180.v:3907$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$255_Y - connect \Y $not$ls180.v:3809$256_Y + connect \A $and$ls180.v:3907$370_Y + connect \Y $not$ls180.v:3907$371_Y end - attribute \src "ls180.v:3810.205-3810.245" - cell $not $not$ls180.v:3810$265 + attribute \src "ls180.v:3908.205-3908.245" + cell $not $not$ls180.v:3908$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3810$265_Y + connect \Y $not$ls180.v:3908$380_Y end - attribute \src "ls180.v:3810.251-3810.290" - cell $not $not$ls180.v:3810$267 + attribute \src "ls180.v:3908.251-3908.290" + cell $not $not$ls180.v:3908$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3810$267_Y + connect \Y $not$ls180.v:3908$382_Y end - attribute \src "ls180.v:3810.159-3810.292" - cell $not $not$ls180.v:3810$269 + attribute \src "ls180.v:3908.159-3908.292" + cell $not $not$ls180.v:3908$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3810$268_Y - connect \Y $not$ls180.v:3810$269_Y + connect \A $and$ls180.v:3908$383_Y + connect \Y $not$ls180.v:3908$384_Y end - attribute \src "ls180.v:3811.205-3811.245" - cell $not $not$ls180.v:3811$278 + attribute \src "ls180.v:3909.205-3909.245" + cell $not $not$ls180.v:3909$393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3811$278_Y + connect \Y $not$ls180.v:3909$393_Y end - attribute \src "ls180.v:3811.251-3811.290" - cell $not $not$ls180.v:3811$280 + attribute \src "ls180.v:3909.251-3909.290" + cell $not $not$ls180.v:3909$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3811$280_Y + connect \Y $not$ls180.v:3909$395_Y end - attribute \src "ls180.v:3811.159-3811.292" - cell $not $not$ls180.v:3811$282 + attribute \src "ls180.v:3909.159-3909.292" + cell $not $not$ls180.v:3909$397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3811$281_Y - connect \Y $not$ls180.v:3811$282_Y + connect \A $and$ls180.v:3909$396_Y + connect \Y $not$ls180.v:3909$397_Y end - attribute \src "ls180.v:3838.71-3838.103" - cell $not $not$ls180.v:3838$293 + attribute \src "ls180.v:3936.71-3936.103" + cell $not $not$ls180.v:3936$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3838$293_Y + connect \Y $not$ls180.v:3936$408_Y end - attribute \src "ls180.v:3841.205-3841.245" - cell $not $not$ls180.v:3841$297 + attribute \src "ls180.v:3939.205-3939.245" + cell $not $not$ls180.v:3939$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3841$297_Y + connect \Y $not$ls180.v:3939$412_Y end - attribute \src "ls180.v:3841.251-3841.290" - cell $not $not$ls180.v:3841$299 + attribute \src "ls180.v:3939.251-3939.290" + cell $not $not$ls180.v:3939$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3841$299_Y + connect \Y $not$ls180.v:3939$414_Y end - attribute \src "ls180.v:3841.159-3841.292" - cell $not $not$ls180.v:3841$301 + attribute \src "ls180.v:3939.159-3939.292" + cell $not $not$ls180.v:3939$416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3841$300_Y - connect \Y $not$ls180.v:3841$301_Y + connect \A $and$ls180.v:3939$415_Y + connect \Y $not$ls180.v:3939$416_Y end - attribute \src "ls180.v:3842.205-3842.245" - cell $not $not$ls180.v:3842$310 + attribute \src "ls180.v:3940.205-3940.245" + cell $not $not$ls180.v:3940$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3842$310_Y + connect \Y $not$ls180.v:3940$425_Y end - attribute \src "ls180.v:3842.251-3842.290" - cell $not $not$ls180.v:3842$312 + attribute \src "ls180.v:3940.251-3940.290" + cell $not $not$ls180.v:3940$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3842$312_Y + connect \Y $not$ls180.v:3940$427_Y end - attribute \src "ls180.v:3842.159-3842.292" - cell $not $not$ls180.v:3842$314 + attribute \src "ls180.v:3940.159-3940.292" + cell $not $not$ls180.v:3940$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$313_Y - connect \Y $not$ls180.v:3842$314_Y + connect \A $and$ls180.v:3940$428_Y + connect \Y $not$ls180.v:3940$429_Y end - attribute \src "ls180.v:3843.205-3843.245" - cell $not $not$ls180.v:3843$323 + attribute \src "ls180.v:3941.205-3941.245" + cell $not $not$ls180.v:3941$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3843$323_Y + connect \Y $not$ls180.v:3941$438_Y end - attribute \src "ls180.v:3843.251-3843.290" - cell $not $not$ls180.v:3843$325 + attribute \src "ls180.v:3941.251-3941.290" + cell $not $not$ls180.v:3941$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3843$325_Y + connect \Y $not$ls180.v:3941$440_Y end - attribute \src "ls180.v:3843.159-3843.292" - cell $not $not$ls180.v:3843$327 + attribute \src "ls180.v:3941.159-3941.292" + cell $not $not$ls180.v:3941$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$326_Y - connect \Y $not$ls180.v:3843$327_Y + connect \A $and$ls180.v:3941$441_Y + connect \Y $not$ls180.v:3941$442_Y end - attribute \src "ls180.v:3844.205-3844.245" - cell $not $not$ls180.v:3844$336 + attribute \src "ls180.v:3942.205-3942.245" + cell $not $not$ls180.v:3942$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3844$336_Y + connect \Y $not$ls180.v:3942$451_Y end - attribute \src "ls180.v:3844.251-3844.290" - cell $not $not$ls180.v:3844$338 + attribute \src "ls180.v:3942.251-3942.290" + cell $not $not$ls180.v:3942$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3844$338_Y + connect \Y $not$ls180.v:3942$453_Y end - attribute \src "ls180.v:3844.159-3844.292" - cell $not $not$ls180.v:3844$340 + attribute \src "ls180.v:3942.159-3942.292" + cell $not $not$ls180.v:3942$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$339_Y - connect \Y $not$ls180.v:3844$340_Y + connect \A $and$ls180.v:3942$454_Y + connect \Y $not$ls180.v:3942$455_Y end - attribute \src "ls180.v:3907.71-3907.103" - cell $not $not$ls180.v:3907$379 + attribute \src "ls180.v:4005.71-4005.103" + cell $not $not$ls180.v:4005$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3907$379_Y + connect \Y $not$ls180.v:4005$494_Y end - attribute \src "ls180.v:3928.112-3928.150" - cell $not $not$ls180.v:3928$382 + attribute \src "ls180.v:4026.112-4026.150" + cell $not $not$ls180.v:4026$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3928$382_Y + connect \Y $not$ls180.v:4026$497_Y end - attribute \src "ls180.v:3928.156-3928.193" - cell $not $not$ls180.v:3928$384 + attribute \src "ls180.v:4026.156-4026.193" + cell $not $not$ls180.v:4026$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3928$384_Y + connect \Y $not$ls180.v:4026$499_Y end - attribute \src "ls180.v:3928.68-3928.195" - cell $not $not$ls180.v:3928$386 + attribute \src "ls180.v:4026.68-4026.195" + cell $not $not$ls180.v:4026$501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3928$385_Y - connect \Y $not$ls180.v:3928$386_Y + connect \A $and$ls180.v:4026$500_Y + connect \Y $not$ls180.v:4026$501_Y end - attribute \src "ls180.v:3936.11-3936.38" - cell $not $not$ls180.v:3936$389 + attribute \src "ls180.v:4034.11-4034.38" + cell $not $not$ls180.v:4034$504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_write_available - connect \Y $not$ls180.v:3936$389_Y + connect \Y $not$ls180.v:4034$504_Y end - attribute \src "ls180.v:3966.112-3966.150" - cell $not $not$ls180.v:3966$391 + attribute \src "ls180.v:4064.112-4064.150" + cell $not $not$ls180.v:4064$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3966$391_Y + connect \Y $not$ls180.v:4064$506_Y end - attribute \src "ls180.v:3966.156-3966.193" - cell $not $not$ls180.v:3966$393 + attribute \src "ls180.v:4064.156-4064.193" + cell $not $not$ls180.v:4064$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3966$393_Y + connect \Y $not$ls180.v:4064$508_Y end - attribute \src "ls180.v:3966.68-3966.195" - cell $not $not$ls180.v:3966$395 + attribute \src "ls180.v:4064.68-4064.195" + cell $not $not$ls180.v:4064$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3966$394_Y - connect \Y $not$ls180.v:3966$395_Y + connect \A $and$ls180.v:4064$509_Y + connect \Y $not$ls180.v:4064$510_Y end - attribute \src "ls180.v:3974.11-3974.37" - cell $not $not$ls180.v:3974$398 + attribute \src "ls180.v:4072.11-4072.37" + cell $not $not$ls180.v:4072$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_read_available - connect \Y $not$ls180.v:3974$398_Y + connect \Y $not$ls180.v:4072$513_Y end - attribute \src "ls180.v:3984.87-3984.331" - cell $not $not$ls180.v:3984$410 + attribute \src "ls180.v:4082.87-4082.331" + cell $not $not$ls180.v:4082$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3984$409_Y - connect \Y $not$ls180.v:3984$410_Y + connect \A $or$ls180.v:4082$524_Y + connect \Y $not$ls180.v:4082$525_Y end - attribute \src "ls180.v:3985.35-3985.68" - cell $not $not$ls180.v:3985$413 + attribute \src "ls180.v:4083.35-4083.68" + cell $not $not$ls180.v:4083$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:3985$413_Y + connect \Y $not$ls180.v:4083$528_Y end - attribute \src "ls180.v:3985.73-3985.105" - cell $not $not$ls180.v:3985$414 + attribute \src "ls180.v:4083.73-4083.105" + cell $not $not$ls180.v:4083$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:3985$414_Y + connect \Y $not$ls180.v:4083$529_Y end - attribute \src "ls180.v:3989.87-3989.331" - cell $not $not$ls180.v:3989$426 + attribute \src "ls180.v:4087.87-4087.331" + cell $not $not$ls180.v:4087$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3989$425_Y - connect \Y $not$ls180.v:3989$426_Y + connect \A $or$ls180.v:4087$540_Y + connect \Y $not$ls180.v:4087$541_Y end - attribute \src "ls180.v:3990.35-3990.68" - cell $not $not$ls180.v:3990$429 + attribute \src "ls180.v:4088.35-4088.68" + cell $not $not$ls180.v:4088$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:3990$429_Y + connect \Y $not$ls180.v:4088$544_Y end - attribute \src "ls180.v:3990.73-3990.105" - cell $not $not$ls180.v:3990$430 + attribute \src "ls180.v:4088.73-4088.105" + cell $not $not$ls180.v:4088$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:3990$430_Y + connect \Y $not$ls180.v:4088$545_Y end - attribute \src "ls180.v:3994.87-3994.331" - cell $not $not$ls180.v:3994$442 + attribute \src "ls180.v:4092.87-4092.331" + cell $not $not$ls180.v:4092$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3994$441_Y - connect \Y $not$ls180.v:3994$442_Y + connect \A $or$ls180.v:4092$556_Y + connect \Y $not$ls180.v:4092$557_Y end - attribute \src "ls180.v:3995.35-3995.68" - cell $not $not$ls180.v:3995$445 + attribute \src "ls180.v:4093.35-4093.68" + cell $not $not$ls180.v:4093$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:3995$445_Y + connect \Y $not$ls180.v:4093$560_Y end - attribute \src "ls180.v:3995.73-3995.105" - cell $not $not$ls180.v:3995$446 + attribute \src "ls180.v:4093.73-4093.105" + cell $not $not$ls180.v:4093$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:3995$446_Y + connect \Y $not$ls180.v:4093$561_Y end - attribute \src "ls180.v:3999.87-3999.331" - cell $not $not$ls180.v:3999$458 + attribute \src "ls180.v:4097.87-4097.331" + cell $not $not$ls180.v:4097$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3999$457_Y - connect \Y $not$ls180.v:3999$458_Y + connect \A $or$ls180.v:4097$572_Y + connect \Y $not$ls180.v:4097$573_Y end - attribute \src "ls180.v:4000.35-4000.68" - cell $not $not$ls180.v:4000$461 + attribute \src "ls180.v:4098.35-4098.68" + cell $not $not$ls180.v:4098$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4000$461_Y + connect \Y $not$ls180.v:4098$576_Y end - attribute \src "ls180.v:4000.73-4000.105" - cell $not $not$ls180.v:4000$462 + attribute \src "ls180.v:4098.73-4098.105" + cell $not $not$ls180.v:4098$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4000$462_Y + connect \Y $not$ls180.v:4098$577_Y end - attribute \src "ls180.v:4004.128-4004.372" - cell $not $not$ls180.v:4004$475 + attribute \src "ls180.v:4102.128-4102.372" + cell $not $not$ls180.v:4102$590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$474_Y - connect \Y $not$ls180.v:4004$475_Y + connect \A $or$ls180.v:4102$589_Y + connect \Y $not$ls180.v:4102$590_Y end - attribute \src "ls180.v:4004.502-4004.746" - cell $not $not$ls180.v:4004$491 + attribute \src "ls180.v:4102.502-4102.746" + cell $not $not$ls180.v:4102$606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$490_Y - connect \Y $not$ls180.v:4004$491_Y + connect \A $or$ls180.v:4102$605_Y + connect \Y $not$ls180.v:4102$606_Y end - attribute \src "ls180.v:4004.876-4004.1120" - cell $not $not$ls180.v:4004$507 + attribute \src "ls180.v:4102.876-4102.1120" + cell $not $not$ls180.v:4102$622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$506_Y - connect \Y $not$ls180.v:4004$507_Y + connect \A $or$ls180.v:4102$621_Y + connect \Y $not$ls180.v:4102$622_Y end - attribute \src "ls180.v:4004.1250-4004.1494" - cell $not $not$ls180.v:4004$523 + attribute \src "ls180.v:4102.1250-4102.1494" + cell $not $not$ls180.v:4102$638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$522_Y - connect \Y $not$ls180.v:4004$523_Y + connect \A $or$ls180.v:4102$637_Y + connect \Y $not$ls180.v:4102$638_Y end - attribute \src "ls180.v:4026.32-4026.50" - cell $not $not$ls180.v:4026$529 + attribute \src "ls180.v:4124.32-4124.50" + cell $not $not$ls180.v:4124$644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4026$529_Y + connect \Y $not$ls180.v:4124$644_Y end - attribute \src "ls180.v:4065.30-4065.50" - cell $not $not$ls180.v:4065$534 + attribute \src "ls180.v:4163.30-4163.50" + cell $not $not$ls180.v:4163$649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4065$534_Y + connect \Y $not$ls180.v:4163$649_Y end - attribute \src "ls180.v:4066.30-4066.50" - cell $not $not$ls180.v:4066$535 + attribute \src "ls180.v:4164.30-4164.50" + cell $not $not$ls180.v:4164$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4066$535_Y + connect \Y $not$ls180.v:4164$650_Y end - attribute \src "ls180.v:4091.27-4091.48" - cell $not $not$ls180.v:4091$541 + attribute \src "ls180.v:4189.27-4189.48" + cell $not $not$ls180.v:4189$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4091$541_Y + connect \Y $not$ls180.v:4189$656_Y end - attribute \src "ls180.v:4092.30-4092.50" - cell $not $not$ls180.v:4092$542 + attribute \src "ls180.v:4190.30-4190.50" + cell $not $not$ls180.v:4190$657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4092$542_Y + connect \Y $not$ls180.v:4190$657_Y end - attribute \src "ls180.v:4093.80-4093.98" - cell $not $not$ls180.v:4093$544 + attribute \src "ls180.v:4191.80-4191.98" + cell $not $not$ls180.v:4191$659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4093$544_Y + connect \Y $not$ls180.v:4191$659_Y end - attribute \src "ls180.v:4094.107-4094.127" - cell $not $not$ls180.v:4094$548 + attribute \src "ls180.v:4192.107-4192.127" + cell $not $not$ls180.v:4192$663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4094$548_Y + connect \Y $not$ls180.v:4192$663_Y end - attribute \src "ls180.v:4095.78-4095.103" - cell $not $not$ls180.v:4095$551 + attribute \src "ls180.v:4193.78-4193.103" + cell $not $not$ls180.v:4193$666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4095$551_Y + connect \Y $not$ls180.v:4193$666_Y end - attribute \src "ls180.v:4096.91-4096.111" - cell $not $not$ls180.v:4096$554 + attribute \src "ls180.v:4194.91-4194.111" + cell $not $not$ls180.v:4194$669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4096$554_Y + connect \Y $not$ls180.v:4194$669_Y end - attribute \src "ls180.v:4112.35-4112.64" - cell $not $not$ls180.v:4112$563 + attribute \src "ls180.v:4210.35-4210.64" + cell $not $not$ls180.v:4210$678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4112$563_Y + connect \Y $not$ls180.v:4210$678_Y end - attribute \src "ls180.v:4113.36-4113.67" - cell $not $not$ls180.v:4113$564 + attribute \src "ls180.v:4211.36-4211.67" + cell $not $not$ls180.v:4211$679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4113$564_Y + connect \Y $not$ls180.v:4211$679_Y end - attribute \src "ls180.v:4119.32-4119.61" - cell $not $not$ls180.v:4119$565 + attribute \src "ls180.v:4217.32-4217.61" + cell $not $not$ls180.v:4217$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4119$565_Y + connect \Y $not$ls180.v:4217$680_Y end - attribute \src "ls180.v:4125.36-4125.67" - cell $not $not$ls180.v:4125$566 + attribute \src "ls180.v:4223.36-4223.67" + cell $not $not$ls180.v:4223$681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4125$566_Y + connect \Y $not$ls180.v:4223$681_Y end - attribute \src "ls180.v:4126.35-4126.64" - cell $not $not$ls180.v:4126$567 + attribute \src "ls180.v:4224.35-4224.64" + cell $not $not$ls180.v:4224$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4126$567_Y + connect \Y $not$ls180.v:4224$682_Y end - attribute \src "ls180.v:4129.32-4129.63" - cell $not $not$ls180.v:4129$570 + attribute \src "ls180.v:4227.32-4227.63" + cell $not $not$ls180.v:4227$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4129$570_Y + connect \Y $not$ls180.v:4227$685_Y end - attribute \src "ls180.v:4167.81-4167.108" - cell $not $not$ls180.v:4167$580 + attribute \src "ls180.v:4265.81-4265.108" + cell $not $not$ls180.v:4265$695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4167$580_Y + connect \Y $not$ls180.v:4265$695_Y end - attribute \src "ls180.v:4197.81-4197.108" - cell $not $not$ls180.v:4197$591 + attribute \src "ls180.v:4295.81-4295.108" + cell $not $not$ls180.v:4295$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4197$591_Y + connect \Y $not$ls180.v:4295$706_Y end - attribute \src "ls180.v:4397.60-4397.85" - cell $not $not$ls180.v:4397$640 + attribute \src "ls180.v:4495.60-4495.85" + cell $not $not$ls180.v:4495$755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4397$640_Y + connect \Y $not$ls180.v:4495$755_Y end - attribute \src "ls180.v:4538.54-4538.96" - cell $not $not$ls180.v:4538$654 + attribute \src "ls180.v:4636.54-4636.96" + cell $not $not$ls180.v:4636$769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4538$654_Y + connect \Y $not$ls180.v:4636$769_Y end - attribute \src "ls180.v:4541.48-4541.86" - cell $not $not$ls180.v:4541$657 + attribute \src "ls180.v:4639.48-4639.86" + cell $not $not$ls180.v:4639$772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4541$657_Y + connect \Y $not$ls180.v:4639$772_Y end - attribute \src "ls180.v:4665.55-4665.98" - cell $not $not$ls180.v:4665$675 + attribute \src "ls180.v:4763.55-4763.98" + cell $not $not$ls180.v:4763$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4665$675_Y + connect \Y $not$ls180.v:4763$790_Y end - attribute \src "ls180.v:4668.49-4668.88" - cell $not $not$ls180.v:4668$678 + attribute \src "ls180.v:4766.49-4766.88" + cell $not $not$ls180.v:4766$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4668$678_Y + connect \Y $not$ls180.v:4766$793_Y end - attribute \src "ls180.v:4718.30-4718.58" - cell $not $not$ls180.v:4718$684 + attribute \src "ls180.v:4816.30-4816.58" + cell $not $not$ls180.v:4816$799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4718$684_Y + connect \Y $not$ls180.v:4816$799_Y end - attribute \src "ls180.v:4799.56-4799.100" - cell $not $not$ls180.v:4799$690 + attribute \src "ls180.v:4897.56-4897.100" + cell $not $not$ls180.v:4897$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4799$690_Y + connect \Y $not$ls180.v:4897$805_Y end - attribute \src "ls180.v:4802.50-4802.90" - cell $not $not$ls180.v:4802$693 + attribute \src "ls180.v:4900.50-4900.90" + cell $not $not$ls180.v:4900$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4802$693_Y + connect \Y $not$ls180.v:4900$808_Y end - attribute \src "ls180.v:4918.42-4918.74" - cell $not $not$ls180.v:4918$709 + attribute \src "ls180.v:5016.42-5016.74" + cell $not $not$ls180.v:5016$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4918$709_Y + connect \Y $not$ls180.v:5016$824_Y end - attribute \src "ls180.v:5442.50-5442.88" - cell $not $not$ls180.v:5442$994 + attribute \src "ls180.v:5540.50-5540.88" + cell $not $not$ls180.v:5540$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5442$994_Y + connect \Y $not$ls180.v:5540$1109_Y end - attribute \src "ls180.v:5454.52-5454.102" - cell $not $not$ls180.v:5454$997 + attribute \src "ls180.v:5552.52-5552.102" + cell $not $not$ls180.v:5552$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5454$997_Y + connect \Y $not$ls180.v:5552$1112_Y end - attribute \src "ls180.v:5513.38-5513.74" - cell $not $not$ls180.v:5513$1004 + attribute \src "ls180.v:5611.38-5611.74" + cell $not $not$ls180.v:5611$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5513$1004_Y + connect \Y $not$ls180.v:5611$1119_Y end - attribute \src "ls180.v:5755.69-5755.88" - cell $not $not$ls180.v:5755$1065 + attribute \src "ls180.v:5892.69-5892.88" + cell $not $not$ls180.v:5892$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \Y $not$ls180.v:5755$1065_Y + connect \Y $not$ls180.v:5892$1189_Y end - attribute \src "ls180.v:5772.63-5772.94" - cell $not $not$ls180.v:5772$1086 + attribute \src "ls180.v:5909.63-5909.94" + cell $not $not$ls180.v:5909$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5772$1086_Y + connect \Y $not$ls180.v:5909$1219_Y end - attribute \src "ls180.v:5775.65-5775.96" - cell $not $not$ls180.v:5775$1093 + attribute \src "ls180.v:5912.65-5912.96" + cell $not $not$ls180.v:5912$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5775$1093_Y + connect \Y $not$ls180.v:5912$1226_Y end - attribute \src "ls180.v:5778.65-5778.96" - cell $not $not$ls180.v:5778$1100 + attribute \src "ls180.v:5915.65-5915.96" + cell $not $not$ls180.v:5915$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5778$1100_Y + connect \Y $not$ls180.v:5915$1233_Y end - attribute \src "ls180.v:5781.65-5781.96" - cell $not $not$ls180.v:5781$1107 + attribute \src "ls180.v:5918.65-5918.96" + cell $not $not$ls180.v:5918$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5781$1107_Y + connect \Y $not$ls180.v:5918$1240_Y end - attribute \src "ls180.v:5784.65-5784.96" - cell $not $not$ls180.v:5784$1114 + attribute \src "ls180.v:5921.65-5921.96" + cell $not $not$ls180.v:5921$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5784$1114_Y + connect \Y $not$ls180.v:5921$1247_Y end - attribute \src "ls180.v:5787.68-5787.99" - cell $not $not$ls180.v:5787$1121 + attribute \src "ls180.v:5924.68-5924.99" + cell $not $not$ls180.v:5924$1254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5787$1121_Y + connect \Y $not$ls180.v:5924$1254_Y end - attribute \src "ls180.v:5790.68-5790.99" - cell $not $not$ls180.v:5790$1128 + attribute \src "ls180.v:5927.68-5927.99" + cell $not $not$ls180.v:5927$1261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5790$1128_Y + connect \Y $not$ls180.v:5927$1261_Y end - attribute \src "ls180.v:5793.68-5793.99" - cell $not $not$ls180.v:5793$1135 + attribute \src "ls180.v:5930.68-5930.99" + cell $not $not$ls180.v:5930$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5793$1135_Y + connect \Y $not$ls180.v:5930$1268_Y end - attribute \src "ls180.v:5796.68-5796.99" - cell $not $not$ls180.v:5796$1142 + attribute \src "ls180.v:5933.68-5933.99" + cell $not $not$ls180.v:5933$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5796$1142_Y + connect \Y $not$ls180.v:5933$1275_Y end - attribute \src "ls180.v:5810.60-5810.91" - cell $not $not$ls180.v:5810$1150 + attribute \src "ls180.v:5947.60-5947.91" + cell $not $not$ls180.v:5947$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5810$1150_Y + connect \Y $not$ls180.v:5947$1283_Y end - attribute \src "ls180.v:5813.60-5813.91" - cell $not $not$ls180.v:5813$1157 + attribute \src "ls180.v:5950.60-5950.91" + cell $not $not$ls180.v:5950$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5813$1157_Y + connect \Y $not$ls180.v:5950$1290_Y end - attribute \src "ls180.v:5816.60-5816.91" - cell $not $not$ls180.v:5816$1164 + attribute \src "ls180.v:5953.60-5953.91" + cell $not $not$ls180.v:5953$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5816$1164_Y + connect \Y $not$ls180.v:5953$1297_Y end - attribute \src "ls180.v:5819.60-5819.91" - cell $not $not$ls180.v:5819$1171 + attribute \src "ls180.v:5956.60-5956.91" + cell $not $not$ls180.v:5956$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5819$1171_Y + connect \Y $not$ls180.v:5956$1304_Y end - attribute \src "ls180.v:5822.61-5822.92" - cell $not $not$ls180.v:5822$1178 + attribute \src "ls180.v:5959.61-5959.92" + cell $not $not$ls180.v:5959$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5822$1178_Y + connect \Y $not$ls180.v:5959$1311_Y end - attribute \src "ls180.v:5825.61-5825.92" - cell $not $not$ls180.v:5825$1185 + attribute \src "ls180.v:5962.61-5962.92" + cell $not $not$ls180.v:5962$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5825$1185_Y + connect \Y $not$ls180.v:5962$1318_Y end - attribute \src "ls180.v:5836.59-5836.90" - cell $not $not$ls180.v:5836$1193 + attribute \src "ls180.v:5973.59-5973.90" + cell $not $not$ls180.v:5973$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5836$1193_Y + connect \Y $not$ls180.v:5973$1326_Y end - attribute \src "ls180.v:5839.58-5839.89" - cell $not $not$ls180.v:5839$1200 + attribute \src "ls180.v:5976.58-5976.89" + cell $not $not$ls180.v:5976$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5839$1200_Y + connect \Y $not$ls180.v:5976$1333_Y end - attribute \src "ls180.v:5850.64-5850.95" - cell $not $not$ls180.v:5850$1208 + attribute \src "ls180.v:5987.64-5987.95" + cell $not $not$ls180.v:5987$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5850$1208_Y + connect \Y $not$ls180.v:5987$1341_Y end - attribute \src "ls180.v:5853.63-5853.94" - cell $not $not$ls180.v:5853$1215 + attribute \src "ls180.v:5990.63-5990.94" + cell $not $not$ls180.v:5990$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5853$1215_Y + connect \Y $not$ls180.v:5990$1348_Y end - attribute \src "ls180.v:5856.63-5856.94" - cell $not $not$ls180.v:5856$1222 + attribute \src "ls180.v:5993.63-5993.94" + cell $not $not$ls180.v:5993$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5856$1222_Y + connect \Y $not$ls180.v:5993$1355_Y end - attribute \src "ls180.v:5859.63-5859.94" - cell $not $not$ls180.v:5859$1229 + attribute \src "ls180.v:5996.63-5996.94" + cell $not $not$ls180.v:5996$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5859$1229_Y + connect \Y $not$ls180.v:5996$1362_Y end - attribute \src "ls180.v:5862.63-5862.94" - cell $not $not$ls180.v:5862$1236 + attribute \src "ls180.v:5999.63-5999.94" + cell $not $not$ls180.v:5999$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5862$1236_Y + connect \Y $not$ls180.v:5999$1369_Y end - attribute \src "ls180.v:5865.64-5865.95" - cell $not $not$ls180.v:5865$1243 + attribute \src "ls180.v:6002.64-6002.95" + cell $not $not$ls180.v:6002$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5865$1243_Y + connect \Y $not$ls180.v:6002$1376_Y end - attribute \src "ls180.v:5868.64-5868.95" - cell $not $not$ls180.v:5868$1250 + attribute \src "ls180.v:6005.64-6005.95" + cell $not $not$ls180.v:6005$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5868$1250_Y + connect \Y $not$ls180.v:6005$1383_Y end - attribute \src "ls180.v:5871.64-5871.95" - cell $not $not$ls180.v:5871$1257 + attribute \src "ls180.v:6008.64-6008.95" + cell $not $not$ls180.v:6008$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5871$1257_Y + connect \Y $not$ls180.v:6008$1390_Y end - attribute \src "ls180.v:5874.64-5874.95" - cell $not $not$ls180.v:5874$1264 + attribute \src "ls180.v:6011.64-6011.95" + cell $not $not$ls180.v:6011$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5874$1264_Y + connect \Y $not$ls180.v:6011$1397_Y end - attribute \src "ls180.v:5887.64-5887.95" - cell $not $not$ls180.v:5887$1272 + attribute \src "ls180.v:6024.64-6024.95" + cell $not $not$ls180.v:6024$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5887$1272_Y + connect \Y $not$ls180.v:6024$1405_Y end - attribute \src "ls180.v:5890.63-5890.94" - cell $not $not$ls180.v:5890$1279 + attribute \src "ls180.v:6027.63-6027.94" + cell $not $not$ls180.v:6027$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5890$1279_Y + connect \Y $not$ls180.v:6027$1412_Y end - attribute \src "ls180.v:5893.63-5893.94" - cell $not $not$ls180.v:5893$1286 + attribute \src "ls180.v:6030.63-6030.94" + cell $not $not$ls180.v:6030$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5893$1286_Y + connect \Y $not$ls180.v:6030$1419_Y end - attribute \src "ls180.v:5896.63-5896.94" - cell $not $not$ls180.v:5896$1293 + attribute \src "ls180.v:6033.63-6033.94" + cell $not $not$ls180.v:6033$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5896$1293_Y + connect \Y $not$ls180.v:6033$1426_Y end - attribute \src "ls180.v:5899.63-5899.94" - cell $not $not$ls180.v:5899$1300 + attribute \src "ls180.v:6036.63-6036.94" + cell $not $not$ls180.v:6036$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5899$1300_Y + connect \Y $not$ls180.v:6036$1433_Y end - attribute \src "ls180.v:5902.64-5902.95" - cell $not $not$ls180.v:5902$1307 + attribute \src "ls180.v:6039.64-6039.95" + cell $not $not$ls180.v:6039$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5902$1307_Y + connect \Y $not$ls180.v:6039$1440_Y end - attribute \src "ls180.v:5905.64-5905.95" - cell $not $not$ls180.v:5905$1314 + attribute \src "ls180.v:6042.64-6042.95" + cell $not $not$ls180.v:6042$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5905$1314_Y + connect \Y $not$ls180.v:6042$1447_Y end - attribute \src "ls180.v:5908.64-5908.95" - cell $not $not$ls180.v:5908$1321 + attribute \src "ls180.v:6045.64-6045.95" + cell $not $not$ls180.v:6045$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5908$1321_Y + connect \Y $not$ls180.v:6045$1454_Y end - attribute \src "ls180.v:5911.64-5911.95" - cell $not $not$ls180.v:5911$1328 + attribute \src "ls180.v:6048.64-6048.95" + cell $not $not$ls180.v:6048$1461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5911$1328_Y + connect \Y $not$ls180.v:6048$1461_Y end - attribute \src "ls180.v:5924.66-5924.97" - cell $not $not$ls180.v:5924$1336 + attribute \src "ls180.v:6061.66-6061.97" + cell $not $not$ls180.v:6061$1469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5924$1336_Y + connect \Y $not$ls180.v:6061$1469_Y end - attribute \src "ls180.v:5927.66-5927.97" - cell $not $not$ls180.v:5927$1343 + attribute \src "ls180.v:6064.66-6064.97" + cell $not $not$ls180.v:6064$1476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5927$1343_Y + connect \Y $not$ls180.v:6064$1476_Y end - attribute \src "ls180.v:5930.66-5930.97" - cell $not $not$ls180.v:5930$1350 + attribute \src "ls180.v:6067.66-6067.97" + cell $not $not$ls180.v:6067$1483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5930$1350_Y + connect \Y $not$ls180.v:6067$1483_Y end - attribute \src "ls180.v:5933.66-5933.97" - cell $not $not$ls180.v:5933$1357 + attribute \src "ls180.v:6070.66-6070.97" + cell $not $not$ls180.v:6070$1490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5933$1357_Y + connect \Y $not$ls180.v:6070$1490_Y end - attribute \src "ls180.v:5936.66-5936.97" - cell $not $not$ls180.v:5936$1364 + attribute \src "ls180.v:6073.66-6073.97" + cell $not $not$ls180.v:6073$1497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5936$1364_Y + connect \Y $not$ls180.v:6073$1497_Y end - attribute \src "ls180.v:5939.66-5939.97" - cell $not $not$ls180.v:5939$1371 + attribute \src "ls180.v:6076.66-6076.97" + cell $not $not$ls180.v:6076$1504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5939$1371_Y + connect \Y $not$ls180.v:6076$1504_Y end - attribute \src "ls180.v:5942.66-5942.97" - cell $not $not$ls180.v:5942$1378 + attribute \src "ls180.v:6079.66-6079.97" + cell $not $not$ls180.v:6079$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5942$1378_Y + connect \Y $not$ls180.v:6079$1511_Y end - attribute \src "ls180.v:5945.66-5945.97" - cell $not $not$ls180.v:5945$1385 + attribute \src "ls180.v:6082.66-6082.97" + cell $not $not$ls180.v:6082$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5945$1385_Y + connect \Y $not$ls180.v:6082$1518_Y end - attribute \src "ls180.v:5948.68-5948.99" - cell $not $not$ls180.v:5948$1392 + attribute \src "ls180.v:6085.68-6085.99" + cell $not $not$ls180.v:6085$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5948$1392_Y + connect \Y $not$ls180.v:6085$1525_Y end - attribute \src "ls180.v:5951.68-5951.99" - cell $not $not$ls180.v:5951$1399 + attribute \src "ls180.v:6088.68-6088.99" + cell $not $not$ls180.v:6088$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5951$1399_Y + connect \Y $not$ls180.v:6088$1532_Y end - attribute \src "ls180.v:5954.68-5954.99" - cell $not $not$ls180.v:5954$1406 + attribute \src "ls180.v:6091.68-6091.99" + cell $not $not$ls180.v:6091$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5954$1406_Y + connect \Y $not$ls180.v:6091$1539_Y end - attribute \src "ls180.v:5957.68-5957.99" - cell $not $not$ls180.v:5957$1413 + attribute \src "ls180.v:6094.68-6094.99" + cell $not $not$ls180.v:6094$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5957$1413_Y + connect \Y $not$ls180.v:6094$1546_Y end - attribute \src "ls180.v:5960.68-5960.99" - cell $not $not$ls180.v:5960$1420 + attribute \src "ls180.v:6097.68-6097.99" + cell $not $not$ls180.v:6097$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5960$1420_Y + connect \Y $not$ls180.v:6097$1553_Y end - attribute \src "ls180.v:5963.65-5963.96" - cell $not $not$ls180.v:5963$1427 + attribute \src "ls180.v:6100.65-6100.96" + cell $not $not$ls180.v:6100$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5963$1427_Y + connect \Y $not$ls180.v:6100$1560_Y end - attribute \src "ls180.v:5966.66-5966.97" - cell $not $not$ls180.v:5966$1434 + attribute \src "ls180.v:6103.66-6103.97" + cell $not $not$ls180.v:6103$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5966$1434_Y + connect \Y $not$ls180.v:6103$1567_Y end - attribute \src "ls180.v:5986.70-5986.101" - cell $not $not$ls180.v:5986$1442 + attribute \src "ls180.v:6123.70-6123.101" + cell $not $not$ls180.v:6123$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5986$1442_Y + connect \Y $not$ls180.v:6123$1575_Y end - attribute \src "ls180.v:5989.70-5989.101" - cell $not $not$ls180.v:5989$1449 + attribute \src "ls180.v:6126.70-6126.101" + cell $not $not$ls180.v:6126$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5989$1449_Y + connect \Y $not$ls180.v:6126$1582_Y end - attribute \src "ls180.v:5992.70-5992.101" - cell $not $not$ls180.v:5992$1456 + attribute \src "ls180.v:6129.70-6129.101" + cell $not $not$ls180.v:6129$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5992$1456_Y + connect \Y $not$ls180.v:6129$1589_Y end - attribute \src "ls180.v:5995.70-5995.101" - cell $not $not$ls180.v:5995$1463 + attribute \src "ls180.v:6132.70-6132.101" + cell $not $not$ls180.v:6132$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5995$1463_Y + connect \Y $not$ls180.v:6132$1596_Y end - attribute \src "ls180.v:5998.69-5998.100" - cell $not $not$ls180.v:5998$1470 + attribute \src "ls180.v:6135.69-6135.100" + cell $not $not$ls180.v:6135$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5998$1470_Y + connect \Y $not$ls180.v:6135$1603_Y end - attribute \src "ls180.v:6001.69-6001.100" - cell $not $not$ls180.v:6001$1477 + attribute \src "ls180.v:6138.69-6138.100" + cell $not $not$ls180.v:6138$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6001$1477_Y + connect \Y $not$ls180.v:6138$1610_Y end - attribute \src "ls180.v:6004.69-6004.100" - cell $not $not$ls180.v:6004$1484 + attribute \src "ls180.v:6141.69-6141.100" + cell $not $not$ls180.v:6141$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6004$1484_Y + connect \Y $not$ls180.v:6141$1617_Y end - attribute \src "ls180.v:6007.69-6007.100" - cell $not $not$ls180.v:6007$1491 + attribute \src "ls180.v:6144.69-6144.100" + cell $not $not$ls180.v:6144$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6007$1491_Y + connect \Y $not$ls180.v:6144$1624_Y end - attribute \src "ls180.v:6010.60-6010.91" - cell $not $not$ls180.v:6010$1498 + attribute \src "ls180.v:6147.60-6147.91" + cell $not $not$ls180.v:6147$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6010$1498_Y + connect \Y $not$ls180.v:6147$1631_Y end - attribute \src "ls180.v:6013.71-6013.102" - cell $not $not$ls180.v:6013$1505 + attribute \src "ls180.v:6150.71-6150.102" + cell $not $not$ls180.v:6150$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6013$1505_Y + connect \Y $not$ls180.v:6150$1638_Y end - attribute \src "ls180.v:6016.71-6016.102" - cell $not $not$ls180.v:6016$1512 + attribute \src "ls180.v:6153.71-6153.102" + cell $not $not$ls180.v:6153$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6016$1512_Y + connect \Y $not$ls180.v:6153$1645_Y end - attribute \src "ls180.v:6019.71-6019.102" - cell $not $not$ls180.v:6019$1519 + attribute \src "ls180.v:6156.71-6156.102" + cell $not $not$ls180.v:6156$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6019$1519_Y + connect \Y $not$ls180.v:6156$1652_Y end - attribute \src "ls180.v:6022.71-6022.102" - cell $not $not$ls180.v:6022$1526 + attribute \src "ls180.v:6159.71-6159.102" + cell $not $not$ls180.v:6159$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6022$1526_Y + connect \Y $not$ls180.v:6159$1659_Y end - attribute \src "ls180.v:6025.71-6025.102" - cell $not $not$ls180.v:6025$1533 + attribute \src "ls180.v:6162.71-6162.102" + cell $not $not$ls180.v:6162$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6025$1533_Y + connect \Y $not$ls180.v:6162$1666_Y end - attribute \src "ls180.v:6028.71-6028.102" - cell $not $not$ls180.v:6028$1540 + attribute \src "ls180.v:6165.71-6165.102" + cell $not $not$ls180.v:6165$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6028$1540_Y + connect \Y $not$ls180.v:6165$1673_Y end - attribute \src "ls180.v:6031.70-6031.101" - cell $not $not$ls180.v:6031$1547 + attribute \src "ls180.v:6168.70-6168.101" + cell $not $not$ls180.v:6168$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6031$1547_Y + connect \Y $not$ls180.v:6168$1680_Y end - attribute \src "ls180.v:6034.70-6034.101" - cell $not $not$ls180.v:6034$1554 + attribute \src "ls180.v:6171.70-6171.101" + cell $not $not$ls180.v:6171$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6034$1554_Y + connect \Y $not$ls180.v:6171$1687_Y end - attribute \src "ls180.v:6037.70-6037.101" - cell $not $not$ls180.v:6037$1561 + attribute \src "ls180.v:6174.70-6174.101" + cell $not $not$ls180.v:6174$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6037$1561_Y + connect \Y $not$ls180.v:6174$1694_Y end - attribute \src "ls180.v:6040.70-6040.101" - cell $not $not$ls180.v:6040$1568 + attribute \src "ls180.v:6177.70-6177.101" + cell $not $not$ls180.v:6177$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6040$1568_Y + connect \Y $not$ls180.v:6177$1701_Y end - attribute \src "ls180.v:6043.70-6043.101" - cell $not $not$ls180.v:6043$1575 + attribute \src "ls180.v:6180.70-6180.101" + cell $not $not$ls180.v:6180$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6043$1575_Y + connect \Y $not$ls180.v:6180$1708_Y end - attribute \src "ls180.v:6046.70-6046.101" - cell $not $not$ls180.v:6046$1582 + attribute \src "ls180.v:6183.70-6183.101" + cell $not $not$ls180.v:6183$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6046$1582_Y + connect \Y $not$ls180.v:6183$1715_Y end - attribute \src "ls180.v:6049.70-6049.101" - cell $not $not$ls180.v:6049$1589 + attribute \src "ls180.v:6186.70-6186.101" + cell $not $not$ls180.v:6186$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6049$1589_Y + connect \Y $not$ls180.v:6186$1722_Y end - attribute \src "ls180.v:6052.70-6052.101" - cell $not $not$ls180.v:6052$1596 + attribute \src "ls180.v:6189.70-6189.101" + cell $not $not$ls180.v:6189$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6052$1596_Y + connect \Y $not$ls180.v:6189$1729_Y end - attribute \src "ls180.v:6055.70-6055.101" - cell $not $not$ls180.v:6055$1603 + attribute \src "ls180.v:6192.70-6192.101" + cell $not $not$ls180.v:6192$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6055$1603_Y + connect \Y $not$ls180.v:6192$1736_Y end - attribute \src "ls180.v:6058.70-6058.101" - cell $not $not$ls180.v:6058$1610 + attribute \src "ls180.v:6195.70-6195.101" + cell $not $not$ls180.v:6195$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6058$1610_Y + connect \Y $not$ls180.v:6195$1743_Y end - attribute \src "ls180.v:6061.66-6061.97" - cell $not $not$ls180.v:6061$1617 + attribute \src "ls180.v:6198.66-6198.97" + cell $not $not$ls180.v:6198$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6061$1617_Y + connect \Y $not$ls180.v:6198$1750_Y end - attribute \src "ls180.v:6064.67-6064.98" - cell $not $not$ls180.v:6064$1624 + attribute \src "ls180.v:6201.67-6201.98" + cell $not $not$ls180.v:6201$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6064$1624_Y + connect \Y $not$ls180.v:6201$1757_Y end - attribute \src "ls180.v:6067.70-6067.101" - cell $not $not$ls180.v:6067$1631 + attribute \src "ls180.v:6204.70-6204.101" + cell $not $not$ls180.v:6204$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6067$1631_Y + connect \Y $not$ls180.v:6204$1764_Y end - attribute \src "ls180.v:6070.70-6070.101" - cell $not $not$ls180.v:6070$1638 + attribute \src "ls180.v:6207.70-6207.101" + cell $not $not$ls180.v:6207$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6070$1638_Y + connect \Y $not$ls180.v:6207$1771_Y end - attribute \src "ls180.v:6073.69-6073.100" - cell $not $not$ls180.v:6073$1645 + attribute \src "ls180.v:6210.69-6210.100" + cell $not $not$ls180.v:6210$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6073$1645_Y + connect \Y $not$ls180.v:6210$1778_Y end - attribute \src "ls180.v:6076.69-6076.100" - cell $not $not$ls180.v:6076$1652 + attribute \src "ls180.v:6213.69-6213.100" + cell $not $not$ls180.v:6213$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6076$1652_Y + connect \Y $not$ls180.v:6213$1785_Y end - attribute \src "ls180.v:6079.69-6079.100" - cell $not $not$ls180.v:6079$1659 + attribute \src "ls180.v:6216.69-6216.100" + cell $not $not$ls180.v:6216$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6079$1659_Y + connect \Y $not$ls180.v:6216$1792_Y end - attribute \src "ls180.v:6082.69-6082.100" - cell $not $not$ls180.v:6082$1666 + attribute \src "ls180.v:6219.69-6219.100" + cell $not $not$ls180.v:6219$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6082$1666_Y + connect \Y $not$ls180.v:6219$1799_Y end - attribute \src "ls180.v:6121.66-6121.97" - cell $not $not$ls180.v:6121$1674 + attribute \src "ls180.v:6258.66-6258.97" + cell $not $not$ls180.v:6258$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6121$1674_Y + connect \Y $not$ls180.v:6258$1807_Y end - attribute \src "ls180.v:6124.66-6124.97" - cell $not $not$ls180.v:6124$1681 + attribute \src "ls180.v:6261.66-6261.97" + cell $not $not$ls180.v:6261$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6124$1681_Y + connect \Y $not$ls180.v:6261$1814_Y end - attribute \src "ls180.v:6127.66-6127.97" - cell $not $not$ls180.v:6127$1688 + attribute \src "ls180.v:6264.66-6264.97" + cell $not $not$ls180.v:6264$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6127$1688_Y + connect \Y $not$ls180.v:6264$1821_Y end - attribute \src "ls180.v:6130.66-6130.97" - cell $not $not$ls180.v:6130$1695 + attribute \src "ls180.v:6267.66-6267.97" + cell $not $not$ls180.v:6267$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6130$1695_Y + connect \Y $not$ls180.v:6267$1828_Y end - attribute \src "ls180.v:6133.66-6133.97" - cell $not $not$ls180.v:6133$1702 + attribute \src "ls180.v:6270.66-6270.97" + cell $not $not$ls180.v:6270$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6133$1702_Y + connect \Y $not$ls180.v:6270$1835_Y end - attribute \src "ls180.v:6136.66-6136.97" - cell $not $not$ls180.v:6136$1709 + attribute \src "ls180.v:6273.66-6273.97" + cell $not $not$ls180.v:6273$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6136$1709_Y + connect \Y $not$ls180.v:6273$1842_Y end - attribute \src "ls180.v:6139.66-6139.97" - cell $not $not$ls180.v:6139$1716 + attribute \src "ls180.v:6276.66-6276.97" + cell $not $not$ls180.v:6276$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6139$1716_Y + connect \Y $not$ls180.v:6276$1849_Y end - attribute \src "ls180.v:6142.66-6142.97" - cell $not $not$ls180.v:6142$1723 + attribute \src "ls180.v:6279.66-6279.97" + cell $not $not$ls180.v:6279$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6142$1723_Y + connect \Y $not$ls180.v:6279$1856_Y end - attribute \src "ls180.v:6145.68-6145.99" - cell $not $not$ls180.v:6145$1730 + attribute \src "ls180.v:6282.68-6282.99" + cell $not $not$ls180.v:6282$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6145$1730_Y + connect \Y $not$ls180.v:6282$1863_Y end - attribute \src "ls180.v:6148.68-6148.99" - cell $not $not$ls180.v:6148$1737 + attribute \src "ls180.v:6285.68-6285.99" + cell $not $not$ls180.v:6285$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6148$1737_Y + connect \Y $not$ls180.v:6285$1870_Y end - attribute \src "ls180.v:6151.68-6151.99" - cell $not $not$ls180.v:6151$1744 + attribute \src "ls180.v:6288.68-6288.99" + cell $not $not$ls180.v:6288$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6151$1744_Y + connect \Y $not$ls180.v:6288$1877_Y end - attribute \src "ls180.v:6154.68-6154.99" - cell $not $not$ls180.v:6154$1751 + attribute \src "ls180.v:6291.68-6291.99" + cell $not $not$ls180.v:6291$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6154$1751_Y + connect \Y $not$ls180.v:6291$1884_Y end - attribute \src "ls180.v:6157.68-6157.99" - cell $not $not$ls180.v:6157$1758 + attribute \src "ls180.v:6294.68-6294.99" + cell $not $not$ls180.v:6294$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6157$1758_Y + connect \Y $not$ls180.v:6294$1891_Y end - attribute \src "ls180.v:6160.65-6160.96" - cell $not $not$ls180.v:6160$1765 + attribute \src "ls180.v:6297.65-6297.96" + cell $not $not$ls180.v:6297$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6160$1765_Y + connect \Y $not$ls180.v:6297$1898_Y end - attribute \src "ls180.v:6163.66-6163.97" - cell $not $not$ls180.v:6163$1772 + attribute \src "ls180.v:6300.66-6300.97" + cell $not $not$ls180.v:6300$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6163$1772_Y + connect \Y $not$ls180.v:6300$1905_Y end - attribute \src "ls180.v:6166.68-6166.99" - cell $not $not$ls180.v:6166$1779 + attribute \src "ls180.v:6303.68-6303.99" + cell $not $not$ls180.v:6303$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6166$1779_Y + connect \Y $not$ls180.v:6303$1912_Y end - attribute \src "ls180.v:6169.68-6169.99" - cell $not $not$ls180.v:6169$1786 + attribute \src "ls180.v:6306.68-6306.99" + cell $not $not$ls180.v:6306$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6169$1786_Y + connect \Y $not$ls180.v:6306$1919_Y end - attribute \src "ls180.v:6172.68-6172.99" - cell $not $not$ls180.v:6172$1793 + attribute \src "ls180.v:6309.68-6309.99" + cell $not $not$ls180.v:6309$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6172$1793_Y + connect \Y $not$ls180.v:6309$1926_Y end - attribute \src "ls180.v:6175.68-6175.99" - cell $not $not$ls180.v:6175$1800 + attribute \src "ls180.v:6312.68-6312.99" + cell $not $not$ls180.v:6312$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6175$1800_Y + connect \Y $not$ls180.v:6312$1933_Y end - attribute \src "ls180.v:6200.68-6200.99" - cell $not $not$ls180.v:6200$1808 + attribute \src "ls180.v:6337.68-6337.99" + cell $not $not$ls180.v:6337$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6200$1808_Y + connect \Y $not$ls180.v:6337$1941_Y end - attribute \src "ls180.v:6203.73-6203.104" - cell $not $not$ls180.v:6203$1815 + attribute \src "ls180.v:6340.73-6340.104" + cell $not $not$ls180.v:6340$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6203$1815_Y + connect \Y $not$ls180.v:6340$1948_Y end - attribute \src "ls180.v:6206.73-6206.104" - cell $not $not$ls180.v:6206$1822 + attribute \src "ls180.v:6343.73-6343.104" + cell $not $not$ls180.v:6343$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6206$1822_Y + connect \Y $not$ls180.v:6343$1955_Y end - attribute \src "ls180.v:6209.66-6209.97" - cell $not $not$ls180.v:6209$1829 + attribute \src "ls180.v:6346.66-6346.97" + cell $not $not$ls180.v:6346$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6209$1829_Y + connect \Y $not$ls180.v:6346$1962_Y end - attribute \src "ls180.v:6217.70-6217.101" - cell $not $not$ls180.v:6217$1837 + attribute \src "ls180.v:6354.70-6354.101" + cell $not $not$ls180.v:6354$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6217$1837_Y + connect \Y $not$ls180.v:6354$1970_Y end - attribute \src "ls180.v:6220.74-6220.105" - cell $not $not$ls180.v:6220$1844 + attribute \src "ls180.v:6357.74-6357.105" + cell $not $not$ls180.v:6357$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6220$1844_Y + connect \Y $not$ls180.v:6357$1977_Y end - attribute \src "ls180.v:6223.64-6223.95" - cell $not $not$ls180.v:6223$1851 + attribute \src "ls180.v:6360.64-6360.95" + cell $not $not$ls180.v:6360$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6223$1851_Y + connect \Y $not$ls180.v:6360$1984_Y end - attribute \src "ls180.v:6226.74-6226.105" - cell $not $not$ls180.v:6226$1858 + attribute \src "ls180.v:6363.74-6363.105" + cell $not $not$ls180.v:6363$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6226$1858_Y + connect \Y $not$ls180.v:6363$1991_Y end - attribute \src "ls180.v:6229.74-6229.105" - cell $not $not$ls180.v:6229$1865 + attribute \src "ls180.v:6366.74-6366.105" + cell $not $not$ls180.v:6366$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6229$1865_Y + connect \Y $not$ls180.v:6366$1998_Y end - attribute \src "ls180.v:6232.75-6232.106" - cell $not $not$ls180.v:6232$1872 + attribute \src "ls180.v:6369.75-6369.106" + cell $not $not$ls180.v:6369$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6232$1872_Y + connect \Y $not$ls180.v:6369$2005_Y end - attribute \src "ls180.v:6235.73-6235.104" - cell $not $not$ls180.v:6235$1879 + attribute \src "ls180.v:6372.73-6372.104" + cell $not $not$ls180.v:6372$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6235$1879_Y + connect \Y $not$ls180.v:6372$2012_Y end - attribute \src "ls180.v:6238.73-6238.104" - cell $not $not$ls180.v:6238$1886 + attribute \src "ls180.v:6375.73-6375.104" + cell $not $not$ls180.v:6375$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6238$1886_Y + connect \Y $not$ls180.v:6375$2019_Y end - attribute \src "ls180.v:6241.73-6241.104" - cell $not $not$ls180.v:6241$1893 + attribute \src "ls180.v:6378.73-6378.104" + cell $not $not$ls180.v:6378$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6241$1893_Y + connect \Y $not$ls180.v:6378$2026_Y end - attribute \src "ls180.v:6244.73-6244.104" - cell $not $not$ls180.v:6244$1900 + attribute \src "ls180.v:6381.73-6381.104" + cell $not $not$ls180.v:6381$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6244$1900_Y + connect \Y $not$ls180.v:6381$2033_Y end - attribute \src "ls180.v:6262.67-6262.99" - cell $not $not$ls180.v:6262$1908 + attribute \src "ls180.v:6399.67-6399.99" + cell $not $not$ls180.v:6399$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6262$1908_Y + connect \Y $not$ls180.v:6399$2041_Y end - attribute \src "ls180.v:6265.67-6265.99" - cell $not $not$ls180.v:6265$1915 + attribute \src "ls180.v:6402.67-6402.99" + cell $not $not$ls180.v:6402$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6265$1915_Y + connect \Y $not$ls180.v:6402$2048_Y end - attribute \src "ls180.v:6268.65-6268.97" - cell $not $not$ls180.v:6268$1922 + attribute \src "ls180.v:6405.65-6405.97" + cell $not $not$ls180.v:6405$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6268$1922_Y + connect \Y $not$ls180.v:6405$2055_Y end - attribute \src "ls180.v:6271.64-6271.96" - cell $not $not$ls180.v:6271$1929 + attribute \src "ls180.v:6408.64-6408.96" + cell $not $not$ls180.v:6408$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6271$1929_Y + connect \Y $not$ls180.v:6408$2062_Y end - attribute \src "ls180.v:6274.63-6274.95" - cell $not $not$ls180.v:6274$1936 + attribute \src "ls180.v:6411.63-6411.95" + cell $not $not$ls180.v:6411$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6274$1936_Y + connect \Y $not$ls180.v:6411$2069_Y end - attribute \src "ls180.v:6277.62-6277.94" - cell $not $not$ls180.v:6277$1943 + attribute \src "ls180.v:6414.62-6414.94" + cell $not $not$ls180.v:6414$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6277$1943_Y + connect \Y $not$ls180.v:6414$2076_Y end - attribute \src "ls180.v:6280.68-6280.100" - cell $not $not$ls180.v:6280$1950 + attribute \src "ls180.v:6417.68-6417.100" + cell $not $not$ls180.v:6417$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6280$1950_Y + connect \Y $not$ls180.v:6417$2083_Y end - attribute \src "ls180.v:6302.67-6302.99" - cell $not $not$ls180.v:6302$1959 + attribute \src "ls180.v:6439.67-6439.99" + cell $not $not$ls180.v:6439$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6302$1959_Y + connect \Y $not$ls180.v:6439$2092_Y end - attribute \src "ls180.v:6305.67-6305.99" - cell $not $not$ls180.v:6305$1966 + attribute \src "ls180.v:6442.67-6442.99" + cell $not $not$ls180.v:6442$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6305$1966_Y + connect \Y $not$ls180.v:6442$2099_Y end - attribute \src "ls180.v:6308.65-6308.97" - cell $not $not$ls180.v:6308$1973 + attribute \src "ls180.v:6445.65-6445.97" + cell $not $not$ls180.v:6445$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6308$1973_Y + connect \Y $not$ls180.v:6445$2106_Y end - attribute \src "ls180.v:6311.64-6311.96" - cell $not $not$ls180.v:6311$1980 + attribute \src "ls180.v:6448.64-6448.96" + cell $not $not$ls180.v:6448$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6311$1980_Y + connect \Y $not$ls180.v:6448$2113_Y end - attribute \src "ls180.v:6314.63-6314.95" - cell $not $not$ls180.v:6314$1987 + attribute \src "ls180.v:6451.63-6451.95" + cell $not $not$ls180.v:6451$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6314$1987_Y + connect \Y $not$ls180.v:6451$2120_Y end - attribute \src "ls180.v:6317.62-6317.94" - cell $not $not$ls180.v:6317$1994 + attribute \src "ls180.v:6454.62-6454.94" + cell $not $not$ls180.v:6454$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6317$1994_Y + connect \Y $not$ls180.v:6454$2127_Y end - attribute \src "ls180.v:6320.68-6320.100" - cell $not $not$ls180.v:6320$2001 + attribute \src "ls180.v:6457.68-6457.100" + cell $not $not$ls180.v:6457$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6320$2001_Y + connect \Y $not$ls180.v:6457$2134_Y end - attribute \src "ls180.v:6323.71-6323.103" - cell $not $not$ls180.v:6323$2008 + attribute \src "ls180.v:6460.71-6460.103" + cell $not $not$ls180.v:6460$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6323$2008_Y + connect \Y $not$ls180.v:6460$2141_Y end - attribute \src "ls180.v:6326.71-6326.103" - cell $not $not$ls180.v:6326$2015 + attribute \src "ls180.v:6463.71-6463.103" + cell $not $not$ls180.v:6463$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6326$2015_Y + connect \Y $not$ls180.v:6463$2148_Y end - attribute \src "ls180.v:6350.64-6350.96" - cell $not $not$ls180.v:6350$2024 + attribute \src "ls180.v:6487.64-6487.96" + cell $not $not$ls180.v:6487$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6350$2024_Y + connect \Y $not$ls180.v:6487$2157_Y end - attribute \src "ls180.v:6353.64-6353.96" - cell $not $not$ls180.v:6353$2031 + attribute \src "ls180.v:6490.64-6490.96" + cell $not $not$ls180.v:6490$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6353$2031_Y + connect \Y $not$ls180.v:6490$2164_Y end - attribute \src "ls180.v:6356.64-6356.96" - cell $not $not$ls180.v:6356$2038 + attribute \src "ls180.v:6493.64-6493.96" + cell $not $not$ls180.v:6493$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6356$2038_Y + connect \Y $not$ls180.v:6493$2171_Y end - attribute \src "ls180.v:6359.64-6359.96" - cell $not $not$ls180.v:6359$2045 + attribute \src "ls180.v:6496.64-6496.96" + cell $not $not$ls180.v:6496$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6359$2045_Y + connect \Y $not$ls180.v:6496$2178_Y end - attribute \src "ls180.v:6362.66-6362.98" - cell $not $not$ls180.v:6362$2052 + attribute \src "ls180.v:6499.66-6499.98" + cell $not $not$ls180.v:6499$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6362$2052_Y + connect \Y $not$ls180.v:6499$2185_Y end - attribute \src "ls180.v:6365.66-6365.98" - cell $not $not$ls180.v:6365$2059 + attribute \src "ls180.v:6502.66-6502.98" + cell $not $not$ls180.v:6502$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6365$2059_Y + connect \Y $not$ls180.v:6502$2192_Y end - attribute \src "ls180.v:6368.66-6368.98" - cell $not $not$ls180.v:6368$2066 + attribute \src "ls180.v:6505.66-6505.98" + cell $not $not$ls180.v:6505$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6368$2066_Y + connect \Y $not$ls180.v:6505$2199_Y end - attribute \src "ls180.v:6371.66-6371.98" - cell $not $not$ls180.v:6371$2073 + attribute \src "ls180.v:6508.66-6508.98" + cell $not $not$ls180.v:6508$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6371$2073_Y + connect \Y $not$ls180.v:6508$2206_Y end - attribute \src "ls180.v:6374.62-6374.94" - cell $not $not$ls180.v:6374$2080 + attribute \src "ls180.v:6511.62-6511.94" + cell $not $not$ls180.v:6511$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6374$2080_Y + connect \Y $not$ls180.v:6511$2213_Y end - attribute \src "ls180.v:6377.72-6377.104" - cell $not $not$ls180.v:6377$2087 + attribute \src "ls180.v:6514.72-6514.104" + cell $not $not$ls180.v:6514$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6377$2087_Y + connect \Y $not$ls180.v:6514$2220_Y end - attribute \src "ls180.v:6380.65-6380.97" - cell $not $not$ls180.v:6380$2094 + attribute \src "ls180.v:6517.65-6517.97" + cell $not $not$ls180.v:6517$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6380$2094_Y + connect \Y $not$ls180.v:6517$2227_Y end - attribute \src "ls180.v:6383.65-6383.97" - cell $not $not$ls180.v:6383$2101 + attribute \src "ls180.v:6520.65-6520.97" + cell $not $not$ls180.v:6520$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6383$2101_Y + connect \Y $not$ls180.v:6520$2234_Y end - attribute \src "ls180.v:6386.65-6386.97" - cell $not $not$ls180.v:6386$2108 + attribute \src "ls180.v:6523.65-6523.97" + cell $not $not$ls180.v:6523$2241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6386$2108_Y + connect \Y $not$ls180.v:6523$2241_Y end - attribute \src "ls180.v:6389.65-6389.97" - cell $not $not$ls180.v:6389$2115 + attribute \src "ls180.v:6526.65-6526.97" + cell $not $not$ls180.v:6526$2248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6389$2115_Y + connect \Y $not$ls180.v:6526$2248_Y end - attribute \src "ls180.v:6392.77-6392.109" - cell $not $not$ls180.v:6392$2122 + attribute \src "ls180.v:6529.77-6529.109" + cell $not $not$ls180.v:6529$2255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6392$2122_Y + connect \Y $not$ls180.v:6529$2255_Y end - attribute \src "ls180.v:6395.78-6395.110" - cell $not $not$ls180.v:6395$2129 + attribute \src "ls180.v:6532.78-6532.110" + cell $not $not$ls180.v:6532$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6395$2129_Y + connect \Y $not$ls180.v:6532$2262_Y end - attribute \src "ls180.v:6398.69-6398.101" - cell $not $not$ls180.v:6398$2136 + attribute \src "ls180.v:6535.69-6535.101" + cell $not $not$ls180.v:6535$2269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6398$2136_Y + connect \Y $not$ls180.v:6535$2269_Y end - attribute \src "ls180.v:6418.55-6418.87" - cell $not $not$ls180.v:6418$2144 + attribute \src "ls180.v:6555.55-6555.87" + cell $not $not$ls180.v:6555$2277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6418$2144_Y + connect \Y $not$ls180.v:6555$2277_Y end - attribute \src "ls180.v:6421.65-6421.97" - cell $not $not$ls180.v:6421$2151 + attribute \src "ls180.v:6558.65-6558.97" + cell $not $not$ls180.v:6558$2284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6421$2151_Y + connect \Y $not$ls180.v:6558$2284_Y end - attribute \src "ls180.v:6424.66-6424.98" - cell $not $not$ls180.v:6424$2158 + attribute \src "ls180.v:6561.66-6561.98" + cell $not $not$ls180.v:6561$2291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6424$2158_Y + connect \Y $not$ls180.v:6561$2291_Y end - attribute \src "ls180.v:6427.70-6427.102" - cell $not $not$ls180.v:6427$2165 + attribute \src "ls180.v:6564.70-6564.102" + cell $not $not$ls180.v:6564$2298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6427$2165_Y + connect \Y $not$ls180.v:6564$2298_Y end - attribute \src "ls180.v:6430.71-6430.103" - cell $not $not$ls180.v:6430$2172 + attribute \src "ls180.v:6567.71-6567.103" + cell $not $not$ls180.v:6567$2305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6430$2172_Y + connect \Y $not$ls180.v:6567$2305_Y end - attribute \src "ls180.v:6433.69-6433.101" - cell $not $not$ls180.v:6433$2179 + attribute \src "ls180.v:6570.69-6570.101" + cell $not $not$ls180.v:6570$2312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6433$2179_Y + connect \Y $not$ls180.v:6570$2312_Y end - attribute \src "ls180.v:6436.66-6436.98" - cell $not $not$ls180.v:6436$2186 + attribute \src "ls180.v:6573.66-6573.98" + cell $not $not$ls180.v:6573$2319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6436$2186_Y + connect \Y $not$ls180.v:6573$2319_Y end - attribute \src "ls180.v:6439.65-6439.97" - cell $not $not$ls180.v:6439$2193 + attribute \src "ls180.v:6576.65-6576.97" + cell $not $not$ls180.v:6576$2326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6439$2193_Y + connect \Y $not$ls180.v:6576$2326_Y end - attribute \src "ls180.v:6452.71-6452.103" - cell $not $not$ls180.v:6452$2201 + attribute \src "ls180.v:6589.71-6589.103" + cell $not $not$ls180.v:6589$2334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6452$2201_Y + connect \Y $not$ls180.v:6589$2334_Y end - attribute \src "ls180.v:6455.71-6455.103" - cell $not $not$ls180.v:6455$2208 + attribute \src "ls180.v:6592.71-6592.103" + cell $not $not$ls180.v:6592$2341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6455$2208_Y + connect \Y $not$ls180.v:6592$2341_Y end - attribute \src "ls180.v:6458.71-6458.103" - cell $not $not$ls180.v:6458$2215 + attribute \src "ls180.v:6595.71-6595.103" + cell $not $not$ls180.v:6595$2348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6458$2215_Y + connect \Y $not$ls180.v:6595$2348_Y end - attribute \src "ls180.v:6461.71-6461.103" - cell $not $not$ls180.v:6461$2222 + attribute \src "ls180.v:6598.71-6598.103" + cell $not $not$ls180.v:6598$2355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6461$2222_Y + connect \Y $not$ls180.v:6598$2355_Y end - attribute \src "ls180.v:6842.86-6842.330" - cell $not $not$ls180.v:6842$2271 + attribute \src "ls180.v:6979.86-6979.330" + cell $not $not$ls180.v:6979$2404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6842$2270_Y - connect \Y $not$ls180.v:6842$2271_Y + connect \A $or$ls180.v:6979$2403_Y + connect \Y $not$ls180.v:6979$2404_Y end - attribute \src "ls180.v:6866.86-6866.330" - cell $not $not$ls180.v:6866$2287 + attribute \src "ls180.v:7003.86-7003.330" + cell $not $not$ls180.v:7003$2420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6866$2286_Y - connect \Y $not$ls180.v:6866$2287_Y + connect \A $or$ls180.v:7003$2419_Y + connect \Y $not$ls180.v:7003$2420_Y end - attribute \src "ls180.v:6890.86-6890.330" - cell $not $not$ls180.v:6890$2303 + attribute \src "ls180.v:7027.86-7027.330" + cell $not $not$ls180.v:7027$2436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6890$2302_Y - connect \Y $not$ls180.v:6890$2303_Y + connect \A $or$ls180.v:7027$2435_Y + connect \Y $not$ls180.v:7027$2436_Y end - attribute \src "ls180.v:6914.86-6914.330" - cell $not $not$ls180.v:6914$2319 + attribute \src "ls180.v:7051.86-7051.330" + cell $not $not$ls180.v:7051$2452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6914$2318_Y - connect \Y $not$ls180.v:6914$2319_Y + connect \A $or$ls180.v:7051$2451_Y + connect \Y $not$ls180.v:7051$2452_Y end - attribute \src "ls180.v:7412.18-7412.42" - cell $not $not$ls180.v:7412$2372 + attribute \src "ls180.v:7549.18-7549.42" + cell $not $not$ls180.v:7549$2505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7412$2372_Y + connect \Y $not$ls180.v:7549$2505_Y end - attribute \src "ls180.v:7491.72-7491.101" - cell $not $not$ls180.v:7491$2405 + attribute \src "ls180.v:7628.72-7628.101" + cell $not $not$ls180.v:7628$2538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7491$2405_Y + connect \Y $not$ls180.v:7628$2538_Y end - attribute \src "ls180.v:7510.8-7510.38" - cell $not $not$ls180.v:7510$2409 + attribute \src "ls180.v:7647.8-7647.38" + cell $not $not$ls180.v:7647$2542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7510$2409_Y + connect \Y $not$ls180.v:7647$2542_Y + end + attribute \src "ls180.v:7651.70-7651.98" + cell $not $not$ls180.v:7651$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_ack + connect \Y $not$ls180.v:7651$2545_Y end - attribute \src "ls180.v:7518.32-7518.55" - cell $not $not$ls180.v:7518$2411 + attribute \src "ls180.v:7655.70-7655.98" + cell $not $not$ls180.v:7655$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_ack + connect \Y $not$ls180.v:7655$2548_Y + end + attribute \src "ls180.v:7659.70-7659.98" + cell $not $not$ls180.v:7659$2551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_ack + connect \Y $not$ls180.v:7659$2551_Y + end + attribute \src "ls180.v:7667.32-7667.55" + cell $not $not$ls180.v:7667$2553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7518$2411_Y + connect \Y $not$ls180.v:7667$2553_Y end - attribute \src "ls180.v:7588.136-7588.189" - cell $not $not$ls180.v:7588$2426 + attribute \src "ls180.v:7737.136-7737.189" + cell $not $not$ls180.v:7737$2568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7588$2426_Y + connect \Y $not$ls180.v:7737$2568_Y end - attribute \src "ls180.v:7594.136-7594.189" - cell $not $not$ls180.v:7594$2431 + attribute \src "ls180.v:7743.136-7743.189" + cell $not $not$ls180.v:7743$2573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7594$2431_Y + connect \Y $not$ls180.v:7743$2573_Y end - attribute \src "ls180.v:7595.8-7595.61" - cell $not $not$ls180.v:7595$2433 + attribute \src "ls180.v:7744.8-7744.61" + cell $not $not$ls180.v:7744$2575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7595$2433_Y + connect \Y $not$ls180.v:7744$2575_Y end - attribute \src "ls180.v:7603.8-7603.56" - cell $not $not$ls180.v:7603$2436 + attribute \src "ls180.v:7752.8-7752.56" + cell $not $not$ls180.v:7752$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7603$2436_Y + connect \Y $not$ls180.v:7752$2578_Y end - attribute \src "ls180.v:7618.8-7618.46" - cell $not $not$ls180.v:7618$2438 + attribute \src "ls180.v:7767.8-7767.46" + cell $not $not$ls180.v:7767$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7618$2438_Y + connect \Y $not$ls180.v:7767$2580_Y end - attribute \src "ls180.v:7634.136-7634.189" - cell $not $not$ls180.v:7634$2442 + attribute \src "ls180.v:7783.136-7783.189" + cell $not $not$ls180.v:7783$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7634$2442_Y + connect \Y $not$ls180.v:7783$2584_Y end - attribute \src "ls180.v:7640.136-7640.189" - cell $not $not$ls180.v:7640$2447 + attribute \src "ls180.v:7789.136-7789.189" + cell $not $not$ls180.v:7789$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7640$2447_Y + connect \Y $not$ls180.v:7789$2589_Y end - attribute \src "ls180.v:7641.8-7641.61" - cell $not $not$ls180.v:7641$2449 + attribute \src "ls180.v:7790.8-7790.61" + cell $not $not$ls180.v:7790$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7641$2449_Y + connect \Y $not$ls180.v:7790$2591_Y end - attribute \src "ls180.v:7649.8-7649.56" - cell $not $not$ls180.v:7649$2452 + attribute \src "ls180.v:7798.8-7798.56" + cell $not $not$ls180.v:7798$2594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7649$2452_Y + connect \Y $not$ls180.v:7798$2594_Y end - attribute \src "ls180.v:7664.8-7664.46" - cell $not $not$ls180.v:7664$2454 + attribute \src "ls180.v:7813.8-7813.46" + cell $not $not$ls180.v:7813$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7664$2454_Y + connect \Y $not$ls180.v:7813$2596_Y end - attribute \src "ls180.v:7680.136-7680.189" - cell $not $not$ls180.v:7680$2458 + attribute \src "ls180.v:7829.136-7829.189" + cell $not $not$ls180.v:7829$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7680$2458_Y + connect \Y $not$ls180.v:7829$2600_Y end - attribute \src "ls180.v:7686.136-7686.189" - cell $not $not$ls180.v:7686$2463 + attribute \src "ls180.v:7835.136-7835.189" + cell $not $not$ls180.v:7835$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7686$2463_Y + connect \Y $not$ls180.v:7835$2605_Y end - attribute \src "ls180.v:7687.8-7687.61" - cell $not $not$ls180.v:7687$2465 + attribute \src "ls180.v:7836.8-7836.61" + cell $not $not$ls180.v:7836$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7687$2465_Y + connect \Y $not$ls180.v:7836$2607_Y end - attribute \src "ls180.v:7695.8-7695.56" - cell $not $not$ls180.v:7695$2468 + attribute \src "ls180.v:7844.8-7844.56" + cell $not $not$ls180.v:7844$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7695$2468_Y + connect \Y $not$ls180.v:7844$2610_Y end - attribute \src "ls180.v:7710.8-7710.46" - cell $not $not$ls180.v:7710$2470 + attribute \src "ls180.v:7859.8-7859.46" + cell $not $not$ls180.v:7859$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7710$2470_Y + connect \Y $not$ls180.v:7859$2612_Y end - attribute \src "ls180.v:7726.136-7726.189" - cell $not $not$ls180.v:7726$2474 + attribute \src "ls180.v:7875.136-7875.189" + cell $not $not$ls180.v:7875$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7726$2474_Y + connect \Y $not$ls180.v:7875$2616_Y end - attribute \src "ls180.v:7732.136-7732.189" - cell $not $not$ls180.v:7732$2479 + attribute \src "ls180.v:7881.136-7881.189" + cell $not $not$ls180.v:7881$2621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7732$2479_Y + connect \Y $not$ls180.v:7881$2621_Y end - attribute \src "ls180.v:7733.8-7733.61" - cell $not $not$ls180.v:7733$2481 + attribute \src "ls180.v:7882.8-7882.61" + cell $not $not$ls180.v:7882$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7733$2481_Y + connect \Y $not$ls180.v:7882$2623_Y end - attribute \src "ls180.v:7741.8-7741.56" - cell $not $not$ls180.v:7741$2484 + attribute \src "ls180.v:7890.8-7890.56" + cell $not $not$ls180.v:7890$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7741$2484_Y + connect \Y $not$ls180.v:7890$2626_Y end - attribute \src "ls180.v:7756.8-7756.46" - cell $not $not$ls180.v:7756$2486 + attribute \src "ls180.v:7905.8-7905.46" + cell $not $not$ls180.v:7905$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7756$2486_Y + connect \Y $not$ls180.v:7905$2628_Y end - attribute \src "ls180.v:7764.7-7764.22" - cell $not $not$ls180.v:7764$2489 + attribute \src "ls180.v:7913.7-7913.22" + cell $not $not$ls180.v:7913$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7764$2489_Y + connect \Y $not$ls180.v:7913$2631_Y end - attribute \src "ls180.v:7767.8-7767.29" - cell $not $not$ls180.v:7767$2490 + attribute \src "ls180.v:7916.8-7916.29" + cell $not $not$ls180.v:7916$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7767$2490_Y + connect \Y $not$ls180.v:7916$2632_Y end - attribute \src "ls180.v:7771.7-7771.22" - cell $not $not$ls180.v:7771$2492 + attribute \src "ls180.v:7920.7-7920.22" + cell $not $not$ls180.v:7920$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7771$2492_Y + connect \Y $not$ls180.v:7920$2634_Y end - attribute \src "ls180.v:7774.8-7774.29" - cell $not $not$ls180.v:7774$2493 + attribute \src "ls180.v:7923.8-7923.29" + cell $not $not$ls180.v:7923$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7774$2493_Y + connect \Y $not$ls180.v:7923$2635_Y end - attribute \src "ls180.v:7893.30-7893.60" - cell $not $not$ls180.v:7893$2495 + attribute \src "ls180.v:8042.30-8042.60" + cell $not $not$ls180.v:8042$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:7893$2495_Y + connect \Y $not$ls180.v:8042$2637_Y end - attribute \src "ls180.v:7894.30-7894.60" - cell $not $not$ls180.v:7894$2496 + attribute \src "ls180.v:8043.30-8043.60" + cell $not $not$ls180.v:8043$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:7894$2496_Y + connect \Y $not$ls180.v:8043$2638_Y end - attribute \src "ls180.v:7895.29-7895.59" - cell $not $not$ls180.v:7895$2497 + attribute \src "ls180.v:8044.29-8044.59" + cell $not $not$ls180.v:8044$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:7895$2497_Y + connect \Y $not$ls180.v:8044$2639_Y end - attribute \src "ls180.v:7906.8-7906.33" - cell $not $not$ls180.v:7906$2498 + attribute \src "ls180.v:8055.8-8055.33" + cell $not $not$ls180.v:8055$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:7906$2498_Y + connect \Y $not$ls180.v:8055$2640_Y end - attribute \src "ls180.v:7921.8-7921.33" - cell $not $not$ls180.v:7921$2501 + attribute \src "ls180.v:8070.8-8070.33" + cell $not $not$ls180.v:8070$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:7921$2501_Y + connect \Y $not$ls180.v:8070$2643_Y end - attribute \src "ls180.v:7957.36-7957.58" - cell $not $not$ls180.v:7957$2531 + attribute \src "ls180.v:8106.36-8106.58" + cell $not $not$ls180.v:8106$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:7957$2531_Y + connect \Y $not$ls180.v:8106$2673_Y end - attribute \src "ls180.v:7957.64-7957.89" - cell $not $not$ls180.v:7957$2533 + attribute \src "ls180.v:8106.64-8106.89" + cell $not $not$ls180.v:8106$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:7957$2533_Y + connect \Y $not$ls180.v:8106$2675_Y end - attribute \src "ls180.v:7986.7-7986.29" - cell $not $not$ls180.v:7986$2540 + attribute \src "ls180.v:8135.7-8135.29" + cell $not $not$ls180.v:8135$2682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:7986$2540_Y + connect \Y $not$ls180.v:8135$2682_Y end - attribute \src "ls180.v:7987.9-7987.26" - cell $not $not$ls180.v:7987$2541 + attribute \src "ls180.v:8136.9-8136.26" + cell $not $not$ls180.v:8136$2683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:7987$2541_Y + connect \Y $not$ls180.v:8136$2683_Y end - attribute \src "ls180.v:8020.8-8020.29" - cell $not $not$ls180.v:8020$2547 + attribute \src "ls180.v:8169.8-8169.29" + cell $not $not$ls180.v:8169$2689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8020$2547_Y + connect \Y $not$ls180.v:8169$2689_Y end - attribute \src "ls180.v:8027.8-8027.29" - cell $not $not$ls180.v:8027$2549 + attribute \src "ls180.v:8176.8-8176.29" + cell $not $not$ls180.v:8176$2691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8027$2549_Y + connect \Y $not$ls180.v:8176$2691_Y end - attribute \src "ls180.v:8037.80-8037.106" - cell $not $not$ls180.v:8037$2552 + attribute \src "ls180.v:8186.80-8186.106" + cell $not $not$ls180.v:8186$2694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8037$2552_Y + connect \Y $not$ls180.v:8186$2694_Y end - attribute \src "ls180.v:8043.80-8043.106" - cell $not $not$ls180.v:8043$2557 + attribute \src "ls180.v:8192.80-8192.106" + cell $not $not$ls180.v:8192$2699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8043$2557_Y + connect \Y $not$ls180.v:8192$2699_Y end - attribute \src "ls180.v:8044.8-8044.34" - cell $not $not$ls180.v:8044$2559 + attribute \src "ls180.v:8193.8-8193.34" + cell $not $not$ls180.v:8193$2701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8044$2559_Y + connect \Y $not$ls180.v:8193$2701_Y end - attribute \src "ls180.v:8059.80-8059.106" - cell $not $not$ls180.v:8059$2563 + attribute \src "ls180.v:8208.80-8208.106" + cell $not $not$ls180.v:8208$2705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8059$2563_Y + connect \Y $not$ls180.v:8208$2705_Y end - attribute \src "ls180.v:8065.80-8065.106" - cell $not $not$ls180.v:8065$2568 + attribute \src "ls180.v:8214.80-8214.106" + cell $not $not$ls180.v:8214$2710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8065$2568_Y + connect \Y $not$ls180.v:8214$2710_Y end - attribute \src "ls180.v:8066.8-8066.34" - cell $not $not$ls180.v:8066$2570 + attribute \src "ls180.v:8215.8-8215.34" + cell $not $not$ls180.v:8215$2712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8066$2570_Y + connect \Y $not$ls180.v:8215$2712_Y end - attribute \src "ls180.v:8097.22-8097.41" - cell $not $not$ls180.v:8097$2574 + attribute \src "ls180.v:8246.22-8246.41" + cell $not $not$ls180.v:8246$2716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8097$2574_Y + connect \Y $not$ls180.v:8246$2716_Y end - attribute \src "ls180.v:8097.46-8097.73" - cell $not $not$ls180.v:8097$2575 + attribute \src "ls180.v:8246.46-8246.73" + cell $not $not$ls180.v:8246$2717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8097$2575_Y + connect \Y $not$ls180.v:8246$2717_Y end - attribute \src "ls180.v:8132.22-8132.40" - cell $not $not$ls180.v:8132$2579 + attribute \src "ls180.v:8281.22-8281.40" + cell $not $not$ls180.v:8281$2721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8132$2579_Y + connect \Y $not$ls180.v:8281$2721_Y end - attribute \src "ls180.v:8132.45-8132.70" - cell $not $not$ls180.v:8132$2580 + attribute \src "ls180.v:8281.45-8281.70" + cell $not $not$ls180.v:8281$2722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8132$2580_Y + connect \Y $not$ls180.v:8281$2722_Y end - attribute \src "ls180.v:8186.7-8186.31" - cell $not $not$ls180.v:8186$2591 + attribute \src "ls180.v:8335.7-8335.31" + cell $not $not$ls180.v:8335$2733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8186$2591_Y + connect \Y $not$ls180.v:8335$2733_Y end - attribute \src "ls180.v:8258.8-8258.46" - cell $not $not$ls180.v:8258$2603 + attribute \src "ls180.v:8407.8-8407.46" + cell $not $not$ls180.v:8407$2745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8258$2603_Y + connect \Y $not$ls180.v:8407$2745_Y end - attribute \src "ls180.v:8339.8-8339.47" - cell $not $not$ls180.v:8339$2615 + attribute \src "ls180.v:8488.8-8488.47" + cell $not $not$ls180.v:8488$2757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8339$2615_Y + connect \Y $not$ls180.v:8488$2757_Y end - attribute \src "ls180.v:8400.8-8400.48" - cell $not $not$ls180.v:8400$2627 + attribute \src "ls180.v:8549.8-8549.48" + cell $not $not$ls180.v:8549$2769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8400$2627_Y + connect \Y $not$ls180.v:8549$2769_Y end - attribute \src "ls180.v:8570.88-8570.118" - cell $not $not$ls180.v:8570$2641 + attribute \src "ls180.v:8719.88-8719.118" + cell $not $not$ls180.v:8719$2783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8570$2641_Y + connect \Y $not$ls180.v:8719$2783_Y end - attribute \src "ls180.v:8576.88-8576.118" - cell $not $not$ls180.v:8576$2646 + attribute \src "ls180.v:8725.88-8725.118" + cell $not $not$ls180.v:8725$2788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8576$2646_Y + connect \Y $not$ls180.v:8725$2788_Y end - attribute \src "ls180.v:8577.8-8577.38" - cell $not $not$ls180.v:8577$2648 + attribute \src "ls180.v:8726.8-8726.38" + cell $not $not$ls180.v:8726$2790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8577$2648_Y + connect \Y $not$ls180.v:8726$2790_Y end - attribute \src "ls180.v:8656.88-8656.118" - cell $not $not$ls180.v:8656$2663 + attribute \src "ls180.v:8817.88-8817.118" + cell $not $not$ls180.v:8817$2805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8656$2663_Y + connect \Y $not$ls180.v:8817$2805_Y end - attribute \src "ls180.v:8662.88-8662.118" - cell $not $not$ls180.v:8662$2668 + attribute \src "ls180.v:8823.88-8823.118" + cell $not $not$ls180.v:8823$2810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8662$2668_Y + connect \Y $not$ls180.v:8823$2810_Y end - attribute \src "ls180.v:8663.8-8663.38" - cell $not $not$ls180.v:8663$2670 + attribute \src "ls180.v:8824.8-8824.38" + cell $not $not$ls180.v:8824$2812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8663$2670_Y + connect \Y $not$ls180.v:8824$2812_Y end - attribute \src "ls180.v:8683.9-8683.28" - cell $not $not$ls180.v:8683$2673 + attribute \src "ls180.v:8844.9-8844.28" + cell $not $not$ls180.v:8844$2815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8683$2673_Y + connect \Y $not$ls180.v:8844$2815_Y end - attribute \src "ls180.v:8702.9-8702.28" - cell $not $not$ls180.v:8702$2674 + attribute \src "ls180.v:8863.9-8863.28" + cell $not $not$ls180.v:8863$2816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:8702$2674_Y + connect \Y $not$ls180.v:8863$2816_Y end - attribute \src "ls180.v:8721.9-8721.28" - cell $not $not$ls180.v:8721$2675 + attribute \src "ls180.v:8882.9-8882.28" + cell $not $not$ls180.v:8882$2817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:8721$2675_Y + connect \Y $not$ls180.v:8882$2817_Y end - attribute \src "ls180.v:8740.9-8740.28" - cell $not $not$ls180.v:8740$2676 + attribute \src "ls180.v:8901.9-8901.28" + cell $not $not$ls180.v:8901$2818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:8740$2676_Y + connect \Y $not$ls180.v:8901$2818_Y end - attribute \src "ls180.v:8759.9-8759.28" - cell $not $not$ls180.v:8759$2677 + attribute \src "ls180.v:8920.9-8920.28" + cell $not $not$ls180.v:8920$2819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:8759$2677_Y + connect \Y $not$ls180.v:8920$2819_Y end - attribute \src "ls180.v:8780.8-8780.21" - cell $not $not$ls180.v:8780$2678 + attribute \src "ls180.v:8941.8-8941.21" + cell $not $not$ls180.v:8941$2820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:8780$2678_Y + connect \Y $not$ls180.v:8941$2820_Y end - attribute \src "ls180.v:10279.8-10279.51" - cell $or $or$ls180.v:10279$2750 + attribute \src "ls180.v:10535.8-10535.51" + cell $or $or$ls180.v:10535$2982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257032,54 +259278,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10279$2750_Y + connect \Y $or$ls180.v:10535$2982_Y end - attribute \src "ls180.v:2814.10-2814.96" - cell $or $or$ls180.v:2814$21 + attribute \src "ls180.v:2866.10-2866.71" + cell $or $or$ls180.v:2866$49 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:2814$21_Y + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:2866$49_Y end - attribute \src "ls180.v:2874.10-2874.96" - cell $or $or$ls180.v:2874$32 + attribute \src "ls180.v:2926.10-2926.71" + cell $or $or$ls180.v:2926$60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:2874$32_Y + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:2926$60_Y end - attribute \src "ls180.v:2934.10-2934.96" - cell $or $or$ls180.v:2934$43 + attribute \src "ls180.v:2986.10-2986.53" + cell $or $or$ls180.v:2986$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:2934$43_Y + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:2986$71_Y end - attribute \src "ls180.v:3126.39-3126.105" - cell $or $or$ls180.v:3126$75 + attribute \src "ls180.v:3224.39-3224.105" + cell $or $or$ls180.v:3224$190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3126$74_Y - connect \Y $or$ls180.v:3126$75_Y + connect \B $ne$ls180.v:3224$189_Y + connect \Y $or$ls180.v:3224$190_Y end - attribute \src "ls180.v:3169.59-3169.140" - cell $or $or$ls180.v:3169$79 + attribute \src "ls180.v:3267.59-3267.140" + cell $or $or$ls180.v:3267$194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257087,10 +259333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_req_wdata_ready connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3169$79_Y + connect \Y $or$ls180.v:3267$194_Y end - attribute \src "ls180.v:3170.44-3170.151" - cell $or $or$ls180.v:3170$80 + attribute \src "ls180.v:3268.44-3268.151" + cell $or $or$ls180.v:3268$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257098,21 +259344,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3170$80_Y + connect \Y $or$ls180.v:3268$195_Y end - attribute \src "ls180.v:3178.45-3178.170" - cell $or $or$ls180.v:3178$84 + attribute \src "ls180.v:3276.45-3276.170" + cell $or $or$ls180.v:3276$199 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3178$83_Y + connect \A $sshl$ls180.v:3276$198_Y connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3178$84_Y + connect \Y $or$ls180.v:3276$199_Y end - attribute \src "ls180.v:3215.127-3215.245" - cell $or $or$ls180.v:3215$97 + attribute \src "ls180.v:3313.127-3313.245" + cell $or $or$ls180.v:3313$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257120,21 +259366,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3215$97_Y + connect \Y $or$ls180.v:3313$212_Y end - attribute \src "ls180.v:3221.57-3221.157" - cell $or $or$ls180.v:3221$103 + attribute \src "ls180.v:3319.57-3319.157" + cell $or $or$ls180.v:3319$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3221$102_Y + connect \A $not$ls180.v:3319$217_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3221$103_Y + connect \Y $or$ls180.v:3319$218_Y end - attribute \src "ls180.v:3326.59-3326.140" - cell $or $or$ls180.v:3326$109 + attribute \src "ls180.v:3424.59-3424.140" + cell $or $or$ls180.v:3424$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257142,10 +259388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_req_wdata_ready connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3326$109_Y + connect \Y $or$ls180.v:3424$224_Y end - attribute \src "ls180.v:3327.44-3327.151" - cell $or $or$ls180.v:3327$110 + attribute \src "ls180.v:3425.44-3425.151" + cell $or $or$ls180.v:3425$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257153,21 +259399,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3327$110_Y + connect \Y $or$ls180.v:3425$225_Y end - attribute \src "ls180.v:3335.45-3335.170" - cell $or $or$ls180.v:3335$114 + attribute \src "ls180.v:3433.45-3433.170" + cell $or $or$ls180.v:3433$229 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3335$113_Y + connect \A $sshl$ls180.v:3433$228_Y connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3335$114_Y + connect \Y $or$ls180.v:3433$229_Y end - attribute \src "ls180.v:3372.127-3372.245" - cell $or $or$ls180.v:3372$127 + attribute \src "ls180.v:3470.127-3470.245" + cell $or $or$ls180.v:3470$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257175,21 +259421,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3372$127_Y + connect \Y $or$ls180.v:3470$242_Y end - attribute \src "ls180.v:3378.57-3378.157" - cell $or $or$ls180.v:3378$133 + attribute \src "ls180.v:3476.57-3476.157" + cell $or $or$ls180.v:3476$248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3378$132_Y + connect \A $not$ls180.v:3476$247_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3378$133_Y + connect \Y $or$ls180.v:3476$248_Y end - attribute \src "ls180.v:3483.59-3483.140" - cell $or $or$ls180.v:3483$139 + attribute \src "ls180.v:3581.59-3581.140" + cell $or $or$ls180.v:3581$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257197,10 +259443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_req_wdata_ready connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3483$139_Y + connect \Y $or$ls180.v:3581$254_Y end - attribute \src "ls180.v:3484.44-3484.151" - cell $or $or$ls180.v:3484$140 + attribute \src "ls180.v:3582.44-3582.151" + cell $or $or$ls180.v:3582$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257208,21 +259454,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3484$140_Y + connect \Y $or$ls180.v:3582$255_Y end - attribute \src "ls180.v:3492.45-3492.170" - cell $or $or$ls180.v:3492$144 + attribute \src "ls180.v:3590.45-3590.170" + cell $or $or$ls180.v:3590$259 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3492$143_Y + connect \A $sshl$ls180.v:3590$258_Y connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3492$144_Y + connect \Y $or$ls180.v:3590$259_Y end - attribute \src "ls180.v:3529.127-3529.245" - cell $or $or$ls180.v:3529$157 + attribute \src "ls180.v:3627.127-3627.245" + cell $or $or$ls180.v:3627$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257230,21 +259476,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3529$157_Y + connect \Y $or$ls180.v:3627$272_Y end - attribute \src "ls180.v:3535.57-3535.157" - cell $or $or$ls180.v:3535$163 + attribute \src "ls180.v:3633.57-3633.157" + cell $or $or$ls180.v:3633$278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3535$162_Y + connect \A $not$ls180.v:3633$277_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3535$163_Y + connect \Y $or$ls180.v:3633$278_Y end - attribute \src "ls180.v:3640.59-3640.140" - cell $or $or$ls180.v:3640$169 + attribute \src "ls180.v:3738.59-3738.140" + cell $or $or$ls180.v:3738$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257252,10 +259498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_req_wdata_ready connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3640$169_Y + connect \Y $or$ls180.v:3738$284_Y end - attribute \src "ls180.v:3641.44-3641.151" - cell $or $or$ls180.v:3641$170 + attribute \src "ls180.v:3739.44-3739.151" + cell $or $or$ls180.v:3739$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257263,21 +259509,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3641$170_Y + connect \Y $or$ls180.v:3739$285_Y end - attribute \src "ls180.v:3649.45-3649.170" - cell $or $or$ls180.v:3649$174 + attribute \src "ls180.v:3747.45-3747.170" + cell $or $or$ls180.v:3747$289 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3649$173_Y + connect \A $sshl$ls180.v:3747$288_Y connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3649$174_Y + connect \Y $or$ls180.v:3747$289_Y end - attribute \src "ls180.v:3686.127-3686.245" - cell $or $or$ls180.v:3686$187 + attribute \src "ls180.v:3784.127-3784.245" + cell $or $or$ls180.v:3784$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257285,21 +259531,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3686$187_Y + connect \Y $or$ls180.v:3784$302_Y end - attribute \src "ls180.v:3692.57-3692.157" - cell $or $or$ls180.v:3692$193 + attribute \src "ls180.v:3790.57-3790.157" + cell $or $or$ls180.v:3790$308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3692$192_Y + connect \A $not$ls180.v:3790$307_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3692$193_Y + connect \Y $or$ls180.v:3790$308_Y end - attribute \src "ls180.v:3791.107-3791.193" - cell $or $or$ls180.v:3791$213 + attribute \src "ls180.v:3889.107-3889.193" + cell $or $or$ls180.v:3889$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257307,626 +259553,626 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_is_write connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3791$213_Y + connect \Y $or$ls180.v:3889$328_Y end - attribute \src "ls180.v:3794.39-3794.204" - cell $or $or$ls180.v:3794$219 + attribute \src "ls180.v:3892.39-3892.204" + cell $or $or$ls180.v:3892$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$217_Y - connect \B $and$ls180.v:3794$218_Y - connect \Y $or$ls180.v:3794$219_Y + connect \A $and$ls180.v:3892$332_Y + connect \B $and$ls180.v:3892$333_Y + connect \Y $or$ls180.v:3892$334_Y end - attribute \src "ls180.v:3794.38-3794.289" - cell $or $or$ls180.v:3794$221 + attribute \src "ls180.v:3892.38-3892.289" + cell $or $or$ls180.v:3892$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3794$219_Y - connect \B $and$ls180.v:3794$220_Y - connect \Y $or$ls180.v:3794$221_Y + connect \A $or$ls180.v:3892$334_Y + connect \B $and$ls180.v:3892$335_Y + connect \Y $or$ls180.v:3892$336_Y end - attribute \src "ls180.v:3794.37-3794.374" - cell $or $or$ls180.v:3794$223 + attribute \src "ls180.v:3892.37-3892.374" + cell $or $or$ls180.v:3892$338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3794$221_Y - connect \B $and$ls180.v:3794$222_Y - connect \Y $or$ls180.v:3794$223_Y + connect \A $or$ls180.v:3892$336_Y + connect \B $and$ls180.v:3892$337_Y + connect \Y $or$ls180.v:3892$338_Y end - attribute \src "ls180.v:3795.40-3795.207" - cell $or $or$ls180.v:3795$226 + attribute \src "ls180.v:3893.40-3893.207" + cell $or $or$ls180.v:3893$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$224_Y - connect \B $and$ls180.v:3795$225_Y - connect \Y $or$ls180.v:3795$226_Y + connect \A $and$ls180.v:3893$339_Y + connect \B $and$ls180.v:3893$340_Y + connect \Y $or$ls180.v:3893$341_Y end - attribute \src "ls180.v:3795.39-3795.293" - cell $or $or$ls180.v:3795$228 + attribute \src "ls180.v:3893.39-3893.293" + cell $or $or$ls180.v:3893$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3795$226_Y - connect \B $and$ls180.v:3795$227_Y - connect \Y $or$ls180.v:3795$228_Y + connect \A $or$ls180.v:3893$341_Y + connect \B $and$ls180.v:3893$342_Y + connect \Y $or$ls180.v:3893$343_Y end - attribute \src "ls180.v:3795.38-3795.379" - cell $or $or$ls180.v:3795$230 + attribute \src "ls180.v:3893.38-3893.379" + cell $or $or$ls180.v:3893$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3795$228_Y - connect \B $and$ls180.v:3795$229_Y - connect \Y $or$ls180.v:3795$230_Y + connect \A $or$ls180.v:3893$343_Y + connect \B $and$ls180.v:3893$344_Y + connect \Y $or$ls180.v:3893$345_Y end - attribute \src "ls180.v:3808.158-3808.332" - cell $or $or$ls180.v:3808$244 + attribute \src "ls180.v:3906.158-3906.332" + cell $or $or$ls180.v:3906$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3808$243_Y + connect \A $not$ls180.v:3906$358_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3808$244_Y + connect \Y $or$ls180.v:3906$359_Y end - attribute \src "ls180.v:3808.75-3808.506" - cell $or $or$ls180.v:3808$249 + attribute \src "ls180.v:3906.75-3906.506" + cell $or $or$ls180.v:3906$364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3808$245_Y - connect \B $and$ls180.v:3808$248_Y - connect \Y $or$ls180.v:3808$249_Y + connect \A $and$ls180.v:3906$360_Y + connect \B $and$ls180.v:3906$363_Y + connect \Y $or$ls180.v:3906$364_Y end - attribute \src "ls180.v:3809.158-3809.332" - cell $or $or$ls180.v:3809$257 + attribute \src "ls180.v:3907.158-3907.332" + cell $or $or$ls180.v:3907$372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3809$256_Y + connect \A $not$ls180.v:3907$371_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3809$257_Y + connect \Y $or$ls180.v:3907$372_Y end - attribute \src "ls180.v:3809.75-3809.506" - cell $or $or$ls180.v:3809$262 + attribute \src "ls180.v:3907.75-3907.506" + cell $or $or$ls180.v:3907$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$258_Y - connect \B $and$ls180.v:3809$261_Y - connect \Y $or$ls180.v:3809$262_Y + connect \A $and$ls180.v:3907$373_Y + connect \B $and$ls180.v:3907$376_Y + connect \Y $or$ls180.v:3907$377_Y end - attribute \src "ls180.v:3810.158-3810.332" - cell $or $or$ls180.v:3810$270 + attribute \src "ls180.v:3908.158-3908.332" + cell $or $or$ls180.v:3908$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3810$269_Y + connect \A $not$ls180.v:3908$384_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3810$270_Y + connect \Y $or$ls180.v:3908$385_Y end - attribute \src "ls180.v:3810.75-3810.506" - cell $or $or$ls180.v:3810$275 + attribute \src "ls180.v:3908.75-3908.506" + cell $or $or$ls180.v:3908$390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3810$271_Y - connect \B $and$ls180.v:3810$274_Y - connect \Y $or$ls180.v:3810$275_Y + connect \A $and$ls180.v:3908$386_Y + connect \B $and$ls180.v:3908$389_Y + connect \Y $or$ls180.v:3908$390_Y end - attribute \src "ls180.v:3811.158-3811.332" - cell $or $or$ls180.v:3811$283 + attribute \src "ls180.v:3909.158-3909.332" + cell $or $or$ls180.v:3909$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3811$282_Y + connect \A $not$ls180.v:3909$397_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3811$283_Y + connect \Y $or$ls180.v:3909$398_Y end - attribute \src "ls180.v:3811.75-3811.506" - cell $or $or$ls180.v:3811$288 + attribute \src "ls180.v:3909.75-3909.506" + cell $or $or$ls180.v:3909$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3811$284_Y - connect \B $and$ls180.v:3811$287_Y - connect \Y $or$ls180.v:3811$288_Y + connect \A $and$ls180.v:3909$399_Y + connect \B $and$ls180.v:3909$402_Y + connect \Y $or$ls180.v:3909$403_Y end - attribute \src "ls180.v:3838.36-3838.104" - cell $or $or$ls180.v:3838$294 + attribute \src "ls180.v:3936.36-3936.104" + cell $or $or$ls180.v:3936$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3838$293_Y - connect \Y $or$ls180.v:3838$294_Y + connect \B $not$ls180.v:3936$408_Y + connect \Y $or$ls180.v:3936$409_Y end - attribute \src "ls180.v:3841.158-3841.332" - cell $or $or$ls180.v:3841$302 + attribute \src "ls180.v:3939.158-3939.332" + cell $or $or$ls180.v:3939$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3841$301_Y + connect \A $not$ls180.v:3939$416_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3841$302_Y + connect \Y $or$ls180.v:3939$417_Y end - attribute \src "ls180.v:3841.75-3841.506" - cell $or $or$ls180.v:3841$307 + attribute \src "ls180.v:3939.75-3939.506" + cell $or $or$ls180.v:3939$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3841$303_Y - connect \B $and$ls180.v:3841$306_Y - connect \Y $or$ls180.v:3841$307_Y + connect \A $and$ls180.v:3939$418_Y + connect \B $and$ls180.v:3939$421_Y + connect \Y $or$ls180.v:3939$422_Y end - attribute \src "ls180.v:3842.158-3842.332" - cell $or $or$ls180.v:3842$315 + attribute \src "ls180.v:3940.158-3940.332" + cell $or $or$ls180.v:3940$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3842$314_Y + connect \A $not$ls180.v:3940$429_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3842$315_Y + connect \Y $or$ls180.v:3940$430_Y end - attribute \src "ls180.v:3842.75-3842.506" - cell $or $or$ls180.v:3842$320 + attribute \src "ls180.v:3940.75-3940.506" + cell $or $or$ls180.v:3940$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$316_Y - connect \B $and$ls180.v:3842$319_Y - connect \Y $or$ls180.v:3842$320_Y + connect \A $and$ls180.v:3940$431_Y + connect \B $and$ls180.v:3940$434_Y + connect \Y $or$ls180.v:3940$435_Y end - attribute \src "ls180.v:3843.158-3843.332" - cell $or $or$ls180.v:3843$328 + attribute \src "ls180.v:3941.158-3941.332" + cell $or $or$ls180.v:3941$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3843$327_Y + connect \A $not$ls180.v:3941$442_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3843$328_Y + connect \Y $or$ls180.v:3941$443_Y end - attribute \src "ls180.v:3843.75-3843.506" - cell $or $or$ls180.v:3843$333 + attribute \src "ls180.v:3941.75-3941.506" + cell $or $or$ls180.v:3941$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$329_Y - connect \B $and$ls180.v:3843$332_Y - connect \Y $or$ls180.v:3843$333_Y + connect \A $and$ls180.v:3941$444_Y + connect \B $and$ls180.v:3941$447_Y + connect \Y $or$ls180.v:3941$448_Y end - attribute \src "ls180.v:3844.158-3844.332" - cell $or $or$ls180.v:3844$341 + attribute \src "ls180.v:3942.158-3942.332" + cell $or $or$ls180.v:3942$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3844$340_Y + connect \A $not$ls180.v:3942$455_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3844$341_Y + connect \Y $or$ls180.v:3942$456_Y end - attribute \src "ls180.v:3844.75-3844.506" - cell $or $or$ls180.v:3844$346 + attribute \src "ls180.v:3942.75-3942.506" + cell $or $or$ls180.v:3942$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$342_Y - connect \B $and$ls180.v:3844$345_Y - connect \Y $or$ls180.v:3844$346_Y + connect \A $and$ls180.v:3942$457_Y + connect \B $and$ls180.v:3942$460_Y + connect \Y $or$ls180.v:3942$461_Y end - attribute \src "ls180.v:3907.36-3907.104" - cell $or $or$ls180.v:3907$380 + attribute \src "ls180.v:4005.36-4005.104" + cell $or $or$ls180.v:4005$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3907$379_Y - connect \Y $or$ls180.v:3907$380_Y + connect \B $not$ls180.v:4005$494_Y + connect \Y $or$ls180.v:4005$495_Y end - attribute \src "ls180.v:3928.67-3928.221" - cell $or $or$ls180.v:3928$387 + attribute \src "ls180.v:4026.67-4026.221" + cell $or $or$ls180.v:4026$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3928$386_Y + connect \A $not$ls180.v:4026$501_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3928$387_Y + connect \Y $or$ls180.v:4026$502_Y end - attribute \src "ls180.v:3936.10-3936.62" - cell $or $or$ls180.v:3936$390 + attribute \src "ls180.v:4034.10-4034.62" + cell $or $or$ls180.v:4034$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3936$389_Y + connect \A $not$ls180.v:4034$504_Y connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:3936$390_Y + connect \Y $or$ls180.v:4034$505_Y end - attribute \src "ls180.v:3966.67-3966.221" - cell $or $or$ls180.v:3966$396 + attribute \src "ls180.v:4064.67-4064.221" + cell $or $or$ls180.v:4064$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3966$395_Y + connect \A $not$ls180.v:4064$510_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3966$396_Y + connect \Y $or$ls180.v:4064$511_Y end - attribute \src "ls180.v:3974.10-3974.61" - cell $or $or$ls180.v:3974$399 + attribute \src "ls180.v:4072.10-4072.61" + cell $or $or$ls180.v:4072$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3974$398_Y + connect \A $not$ls180.v:4072$513_Y connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:3974$399_Y + connect \Y $or$ls180.v:4072$514_Y end - attribute \src "ls180.v:3984.91-3984.180" - cell $or $or$ls180.v:3984$403 + attribute \src "ls180.v:4082.91-4082.180" + cell $or $or$ls180.v:4082$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:3984$402_Y - connect \Y $or$ls180.v:3984$403_Y + connect \B $and$ls180.v:4082$517_Y + connect \Y $or$ls180.v:4082$518_Y end - attribute \src "ls180.v:3984.90-3984.255" - cell $or $or$ls180.v:3984$406 + attribute \src "ls180.v:4082.90-4082.255" + cell $or $or$ls180.v:4082$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3984$403_Y - connect \B $and$ls180.v:3984$405_Y - connect \Y $or$ls180.v:3984$406_Y + connect \A $or$ls180.v:4082$518_Y + connect \B $and$ls180.v:4082$520_Y + connect \Y $or$ls180.v:4082$521_Y end - attribute \src "ls180.v:3984.89-3984.330" - cell $or $or$ls180.v:3984$409 + attribute \src "ls180.v:4082.89-4082.330" + cell $or $or$ls180.v:4082$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3984$406_Y - connect \B $and$ls180.v:3984$408_Y - connect \Y $or$ls180.v:3984$409_Y + connect \A $or$ls180.v:4082$521_Y + connect \B $and$ls180.v:4082$523_Y + connect \Y $or$ls180.v:4082$524_Y end - attribute \src "ls180.v:3989.91-3989.180" - cell $or $or$ls180.v:3989$419 + attribute \src "ls180.v:4087.91-4087.180" + cell $or $or$ls180.v:4087$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:3989$418_Y - connect \Y $or$ls180.v:3989$419_Y + connect \B $and$ls180.v:4087$533_Y + connect \Y $or$ls180.v:4087$534_Y end - attribute \src "ls180.v:3989.90-3989.255" - cell $or $or$ls180.v:3989$422 + attribute \src "ls180.v:4087.90-4087.255" + cell $or $or$ls180.v:4087$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3989$419_Y - connect \B $and$ls180.v:3989$421_Y - connect \Y $or$ls180.v:3989$422_Y + connect \A $or$ls180.v:4087$534_Y + connect \B $and$ls180.v:4087$536_Y + connect \Y $or$ls180.v:4087$537_Y end - attribute \src "ls180.v:3989.89-3989.330" - cell $or $or$ls180.v:3989$425 + attribute \src "ls180.v:4087.89-4087.330" + cell $or $or$ls180.v:4087$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3989$422_Y - connect \B $and$ls180.v:3989$424_Y - connect \Y $or$ls180.v:3989$425_Y + connect \A $or$ls180.v:4087$537_Y + connect \B $and$ls180.v:4087$539_Y + connect \Y $or$ls180.v:4087$540_Y end - attribute \src "ls180.v:3994.91-3994.180" - cell $or $or$ls180.v:3994$435 + attribute \src "ls180.v:4092.91-4092.180" + cell $or $or$ls180.v:4092$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:3994$434_Y - connect \Y $or$ls180.v:3994$435_Y + connect \B $and$ls180.v:4092$549_Y + connect \Y $or$ls180.v:4092$550_Y end - attribute \src "ls180.v:3994.90-3994.255" - cell $or $or$ls180.v:3994$438 + attribute \src "ls180.v:4092.90-4092.255" + cell $or $or$ls180.v:4092$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3994$435_Y - connect \B $and$ls180.v:3994$437_Y - connect \Y $or$ls180.v:3994$438_Y + connect \A $or$ls180.v:4092$550_Y + connect \B $and$ls180.v:4092$552_Y + connect \Y $or$ls180.v:4092$553_Y end - attribute \src "ls180.v:3994.89-3994.330" - cell $or $or$ls180.v:3994$441 + attribute \src "ls180.v:4092.89-4092.330" + cell $or $or$ls180.v:4092$556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3994$438_Y - connect \B $and$ls180.v:3994$440_Y - connect \Y $or$ls180.v:3994$441_Y + connect \A $or$ls180.v:4092$553_Y + connect \B $and$ls180.v:4092$555_Y + connect \Y $or$ls180.v:4092$556_Y end - attribute \src "ls180.v:3999.91-3999.180" - cell $or $or$ls180.v:3999$451 + attribute \src "ls180.v:4097.91-4097.180" + cell $or $or$ls180.v:4097$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:3999$450_Y - connect \Y $or$ls180.v:3999$451_Y + connect \B $and$ls180.v:4097$565_Y + connect \Y $or$ls180.v:4097$566_Y end - attribute \src "ls180.v:3999.90-3999.255" - cell $or $or$ls180.v:3999$454 + attribute \src "ls180.v:4097.90-4097.255" + cell $or $or$ls180.v:4097$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3999$451_Y - connect \B $and$ls180.v:3999$453_Y - connect \Y $or$ls180.v:3999$454_Y + connect \A $or$ls180.v:4097$566_Y + connect \B $and$ls180.v:4097$568_Y + connect \Y $or$ls180.v:4097$569_Y end - attribute \src "ls180.v:3999.89-3999.330" - cell $or $or$ls180.v:3999$457 + attribute \src "ls180.v:4097.89-4097.330" + cell $or $or$ls180.v:4097$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3999$454_Y - connect \B $and$ls180.v:3999$456_Y - connect \Y $or$ls180.v:3999$457_Y + connect \A $or$ls180.v:4097$569_Y + connect \B $and$ls180.v:4097$571_Y + connect \Y $or$ls180.v:4097$572_Y end - attribute \src "ls180.v:4004.132-4004.221" - cell $or $or$ls180.v:4004$468 + attribute \src "ls180.v:4102.132-4102.221" + cell $or $or$ls180.v:4102$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4004$467_Y - connect \Y $or$ls180.v:4004$468_Y + connect \B $and$ls180.v:4102$582_Y + connect \Y $or$ls180.v:4102$583_Y end - attribute \src "ls180.v:4004.131-4004.296" - cell $or $or$ls180.v:4004$471 + attribute \src "ls180.v:4102.131-4102.296" + cell $or $or$ls180.v:4102$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$468_Y - connect \B $and$ls180.v:4004$470_Y - connect \Y $or$ls180.v:4004$471_Y + connect \A $or$ls180.v:4102$583_Y + connect \B $and$ls180.v:4102$585_Y + connect \Y $or$ls180.v:4102$586_Y end - attribute \src "ls180.v:4004.130-4004.371" - cell $or $or$ls180.v:4004$474 + attribute \src "ls180.v:4102.130-4102.371" + cell $or $or$ls180.v:4102$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$471_Y - connect \B $and$ls180.v:4004$473_Y - connect \Y $or$ls180.v:4004$474_Y + connect \A $or$ls180.v:4102$586_Y + connect \B $and$ls180.v:4102$588_Y + connect \Y $or$ls180.v:4102$589_Y end - attribute \src "ls180.v:4004.34-4004.411" - cell $or $or$ls180.v:4004$479 + attribute \src "ls180.v:4102.34-4102.411" + cell $or $or$ls180.v:4102$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:4004$478_Y - connect \Y $or$ls180.v:4004$479_Y + connect \B $and$ls180.v:4102$593_Y + connect \Y $or$ls180.v:4102$594_Y end - attribute \src "ls180.v:4004.506-4004.595" - cell $or $or$ls180.v:4004$484 + attribute \src "ls180.v:4102.506-4102.595" + cell $or $or$ls180.v:4102$599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4004$483_Y - connect \Y $or$ls180.v:4004$484_Y + connect \B $and$ls180.v:4102$598_Y + connect \Y $or$ls180.v:4102$599_Y end - attribute \src "ls180.v:4004.505-4004.670" - cell $or $or$ls180.v:4004$487 + attribute \src "ls180.v:4102.505-4102.670" + cell $or $or$ls180.v:4102$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$484_Y - connect \B $and$ls180.v:4004$486_Y - connect \Y $or$ls180.v:4004$487_Y + connect \A $or$ls180.v:4102$599_Y + connect \B $and$ls180.v:4102$601_Y + connect \Y $or$ls180.v:4102$602_Y end - attribute \src "ls180.v:4004.504-4004.745" - cell $or $or$ls180.v:4004$490 + attribute \src "ls180.v:4102.504-4102.745" + cell $or $or$ls180.v:4102$605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$487_Y - connect \B $and$ls180.v:4004$489_Y - connect \Y $or$ls180.v:4004$490_Y + connect \A $or$ls180.v:4102$602_Y + connect \B $and$ls180.v:4102$604_Y + connect \Y $or$ls180.v:4102$605_Y end - attribute \src "ls180.v:4004.33-4004.785" - cell $or $or$ls180.v:4004$495 + attribute \src "ls180.v:4102.33-4102.785" + cell $or $or$ls180.v:4102$610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$479_Y - connect \B $and$ls180.v:4004$494_Y - connect \Y $or$ls180.v:4004$495_Y + connect \A $or$ls180.v:4102$594_Y + connect \B $and$ls180.v:4102$609_Y + connect \Y $or$ls180.v:4102$610_Y end - attribute \src "ls180.v:4004.880-4004.969" - cell $or $or$ls180.v:4004$500 + attribute \src "ls180.v:4102.880-4102.969" + cell $or $or$ls180.v:4102$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4004$499_Y - connect \Y $or$ls180.v:4004$500_Y + connect \B $and$ls180.v:4102$614_Y + connect \Y $or$ls180.v:4102$615_Y end - attribute \src "ls180.v:4004.879-4004.1044" - cell $or $or$ls180.v:4004$503 + attribute \src "ls180.v:4102.879-4102.1044" + cell $or $or$ls180.v:4102$618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$500_Y - connect \B $and$ls180.v:4004$502_Y - connect \Y $or$ls180.v:4004$503_Y + connect \A $or$ls180.v:4102$615_Y + connect \B $and$ls180.v:4102$617_Y + connect \Y $or$ls180.v:4102$618_Y end - attribute \src "ls180.v:4004.878-4004.1119" - cell $or $or$ls180.v:4004$506 + attribute \src "ls180.v:4102.878-4102.1119" + cell $or $or$ls180.v:4102$621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$503_Y - connect \B $and$ls180.v:4004$505_Y - connect \Y $or$ls180.v:4004$506_Y + connect \A $or$ls180.v:4102$618_Y + connect \B $and$ls180.v:4102$620_Y + connect \Y $or$ls180.v:4102$621_Y end - attribute \src "ls180.v:4004.32-4004.1159" - cell $or $or$ls180.v:4004$511 + attribute \src "ls180.v:4102.32-4102.1159" + cell $or $or$ls180.v:4102$626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$495_Y - connect \B $and$ls180.v:4004$510_Y - connect \Y $or$ls180.v:4004$511_Y + connect \A $or$ls180.v:4102$610_Y + connect \B $and$ls180.v:4102$625_Y + connect \Y $or$ls180.v:4102$626_Y end - attribute \src "ls180.v:4004.1254-4004.1343" - cell $or $or$ls180.v:4004$516 + attribute \src "ls180.v:4102.1254-4102.1343" + cell $or $or$ls180.v:4102$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4004$515_Y - connect \Y $or$ls180.v:4004$516_Y + connect \B $and$ls180.v:4102$630_Y + connect \Y $or$ls180.v:4102$631_Y end - attribute \src "ls180.v:4004.1253-4004.1418" - cell $or $or$ls180.v:4004$519 + attribute \src "ls180.v:4102.1253-4102.1418" + cell $or $or$ls180.v:4102$634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$516_Y - connect \B $and$ls180.v:4004$518_Y - connect \Y $or$ls180.v:4004$519_Y + connect \A $or$ls180.v:4102$631_Y + connect \B $and$ls180.v:4102$633_Y + connect \Y $or$ls180.v:4102$634_Y end - attribute \src "ls180.v:4004.1252-4004.1493" - cell $or $or$ls180.v:4004$522 + attribute \src "ls180.v:4102.1252-4102.1493" + cell $or $or$ls180.v:4102$637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$519_Y - connect \B $and$ls180.v:4004$521_Y - connect \Y $or$ls180.v:4004$522_Y + connect \A $or$ls180.v:4102$634_Y + connect \B $and$ls180.v:4102$636_Y + connect \Y $or$ls180.v:4102$637_Y end - attribute \src "ls180.v:4004.31-4004.1533" - cell $or $or$ls180.v:4004$527 + attribute \src "ls180.v:4102.31-4102.1533" + cell $or $or$ls180.v:4102$642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4004$511_Y - connect \B $and$ls180.v:4004$526_Y - connect \Y $or$ls180.v:4004$527_Y + connect \A $or$ls180.v:4102$626_Y + connect \B $and$ls180.v:4102$641_Y + connect \Y $or$ls180.v:4102$642_Y end - attribute \src "ls180.v:4067.10-4067.52" - cell $or $or$ls180.v:4067$536 + attribute \src "ls180.v:4165.10-4165.52" + cell $or $or$ls180.v:4165$651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257934,10 +260180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:4067$536_Y + connect \Y $or$ls180.v:4165$651_Y end - attribute \src "ls180.v:4094.35-4094.74" - cell $or $or$ls180.v:4094$546 + attribute \src "ls180.v:4192.35-4192.74" + cell $or $or$ls180.v:4192$661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257945,10 +260191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4094$546_Y + connect \Y $or$ls180.v:4192$661_Y end - attribute \src "ls180.v:4095.34-4095.73" - cell $or $or$ls180.v:4095$550 + attribute \src "ls180.v:4193.34-4193.73" + cell $or $or$ls180.v:4193$665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257956,76 +260202,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4095$550_Y + connect \Y $or$ls180.v:4193$665_Y end - attribute \src "ls180.v:4096.48-4096.130" - cell $or $or$ls180.v:4096$556 + attribute \src "ls180.v:4194.48-4194.130" + cell $or $or$ls180.v:4194$671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4096$553_Y - connect \B $and$ls180.v:4096$555_Y - connect \Y $or$ls180.v:4096$556_Y + connect \A $and$ls180.v:4194$668_Y + connect \B $and$ls180.v:4194$670_Y + connect \Y $or$ls180.v:4194$671_Y end - attribute \src "ls180.v:4097.24-4097.87" - cell $or $or$ls180.v:4097$559 + attribute \src "ls180.v:4195.24-4195.87" + cell $or $or$ls180.v:4195$674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4097$558_Y + connect \A $and$ls180.v:4195$673_Y connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4097$559_Y + connect \Y $or$ls180.v:4195$674_Y end - attribute \src "ls180.v:4098.26-4098.95" - cell $or $or$ls180.v:4098$561 + attribute \src "ls180.v:4196.26-4196.95" + cell $or $or$ls180.v:4196$676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4098$560_Y + connect \A $and$ls180.v:4196$675_Y connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4098$561_Y + connect \Y $or$ls180.v:4196$676_Y end - attribute \src "ls180.v:4128.42-4128.89" - cell $or $or$ls180.v:4128$569 + attribute \src "ls180.v:4226.42-4226.89" + cell $or $or$ls180.v:4226$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4128$568_Y - connect \Y $or$ls180.v:4128$569_Y + connect \B $and$ls180.v:4226$683_Y + connect \Y $or$ls180.v:4226$684_Y end - attribute \src "ls180.v:4152.25-4152.174" - cell $or $or$ls180.v:4152$579 + attribute \src "ls180.v:4250.25-4250.174" + cell $or $or$ls180.v:4250$694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4152$577_Y - connect \B $and$ls180.v:4152$578_Y - connect \Y $or$ls180.v:4152$579_Y + connect \A $and$ls180.v:4250$692_Y + connect \B $and$ls180.v:4250$693_Y + connect \Y $or$ls180.v:4250$694_Y end - attribute \src "ls180.v:4167.80-4167.132" - cell $or $or$ls180.v:4167$581 + attribute \src "ls180.v:4265.80-4265.132" + cell $or $or$ls180.v:4265$696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4167$580_Y + connect \A $not$ls180.v:4265$695_Y connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4167$581_Y + connect \Y $or$ls180.v:4265$696_Y end - attribute \src "ls180.v:4178.72-4178.135" - cell $or $or$ls180.v:4178$586 + attribute \src "ls180.v:4276.72-4276.135" + cell $or $or$ls180.v:4276$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258033,21 +260279,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_writable connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4178$586_Y + connect \Y $or$ls180.v:4276$701_Y end - attribute \src "ls180.v:4197.80-4197.132" - cell $or $or$ls180.v:4197$592 + attribute \src "ls180.v:4295.80-4295.132" + cell $or $or$ls180.v:4295$707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4197$591_Y + connect \A $not$ls180.v:4295$706_Y connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4197$592_Y + connect \Y $or$ls180.v:4295$707_Y end - attribute \src "ls180.v:4208.72-4208.135" - cell $or $or$ls180.v:4208$597 + attribute \src "ls180.v:4306.72-4306.135" + cell $or $or$ls180.v:4306$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258055,10 +260301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_writable connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4208$597_Y + connect \Y $or$ls180.v:4306$712_Y end - attribute \src "ls180.v:4342.36-4342.111" - cell $or $or$ls180.v:4342$618 + attribute \src "ls180.v:4440.36-4440.111" + cell $or $or$ls180.v:4440$733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258066,43 +260312,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_clk connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4342$618_Y + connect \Y $or$ls180.v:4440$733_Y end - attribute \src "ls180.v:4342.35-4342.151" - cell $or $or$ls180.v:4342$619 + attribute \src "ls180.v:4440.35-4440.151" + cell $or $or$ls180.v:4440$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4342$618_Y + connect \A $or$ls180.v:4440$733_Y connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4342$619_Y + connect \Y $or$ls180.v:4440$734_Y end - attribute \src "ls180.v:4342.34-4342.192" - cell $or $or$ls180.v:4342$620 + attribute \src "ls180.v:4440.34-4440.192" + cell $or $or$ls180.v:4440$735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4342$619_Y + connect \A $or$ls180.v:4440$734_Y connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4342$620_Y + connect \Y $or$ls180.v:4440$735_Y end - attribute \src "ls180.v:4342.33-4342.233" - cell $or $or$ls180.v:4342$621 + attribute \src "ls180.v:4440.33-4440.233" + cell $or $or$ls180.v:4440$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4342$620_Y + connect \A $or$ls180.v:4440$735_Y connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4342$621_Y + connect \Y $or$ls180.v:4440$736_Y end - attribute \src "ls180.v:4343.39-4343.120" - cell $or $or$ls180.v:4343$622 + attribute \src "ls180.v:4441.39-4441.120" + cell $or $or$ls180.v:4441$737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258110,43 +260356,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_oe connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4343$622_Y + connect \Y $or$ls180.v:4441$737_Y end - attribute \src "ls180.v:4343.38-4343.163" - cell $or $or$ls180.v:4343$623 + attribute \src "ls180.v:4441.38-4441.163" + cell $or $or$ls180.v:4441$738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4343$622_Y + connect \A $or$ls180.v:4441$737_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4343$623_Y + connect \Y $or$ls180.v:4441$738_Y end - attribute \src "ls180.v:4343.37-4343.207" - cell $or $or$ls180.v:4343$624 + attribute \src "ls180.v:4441.37-4441.207" + cell $or $or$ls180.v:4441$739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4343$623_Y + connect \A $or$ls180.v:4441$738_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4343$624_Y + connect \Y $or$ls180.v:4441$739_Y end - attribute \src "ls180.v:4343.36-4343.251" - cell $or $or$ls180.v:4343$625 + attribute \src "ls180.v:4441.36-4441.251" + cell $or $or$ls180.v:4441$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4343$624_Y + connect \A $or$ls180.v:4441$739_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4343$625_Y + connect \Y $or$ls180.v:4441$740_Y end - attribute \src "ls180.v:4344.38-4344.117" - cell $or $or$ls180.v:4344$626 + attribute \src "ls180.v:4442.38-4442.117" + cell $or $or$ls180.v:4442$741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258154,43 +260400,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_o connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4344$626_Y + connect \Y $or$ls180.v:4442$741_Y end - attribute \src "ls180.v:4344.37-4344.159" - cell $or $or$ls180.v:4344$627 + attribute \src "ls180.v:4442.37-4442.159" + cell $or $or$ls180.v:4442$742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4344$626_Y + connect \A $or$ls180.v:4442$741_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4344$627_Y + connect \Y $or$ls180.v:4442$742_Y end - attribute \src "ls180.v:4344.36-4344.202" - cell $or $or$ls180.v:4344$628 + attribute \src "ls180.v:4442.36-4442.202" + cell $or $or$ls180.v:4442$743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4344$627_Y + connect \A $or$ls180.v:4442$742_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4344$628_Y + connect \Y $or$ls180.v:4442$743_Y end - attribute \src "ls180.v:4344.35-4344.245" - cell $or $or$ls180.v:4344$629 + attribute \src "ls180.v:4442.35-4442.245" + cell $or $or$ls180.v:4442$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4344$628_Y + connect \A $or$ls180.v:4442$743_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4344$629_Y + connect \Y $or$ls180.v:4442$744_Y end - attribute \src "ls180.v:4345.40-4345.123" - cell $or $or$ls180.v:4345$630 + attribute \src "ls180.v:4443.40-4443.123" + cell $or $or$ls180.v:4443$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258198,43 +260444,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_data_oe connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4345$630_Y + connect \Y $or$ls180.v:4443$745_Y end - attribute \src "ls180.v:4345.39-4345.167" - cell $or $or$ls180.v:4345$631 + attribute \src "ls180.v:4443.39-4443.167" + cell $or $or$ls180.v:4443$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4345$630_Y + connect \A $or$ls180.v:4443$745_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4345$631_Y + connect \Y $or$ls180.v:4443$746_Y end - attribute \src "ls180.v:4345.38-4345.212" - cell $or $or$ls180.v:4345$632 + attribute \src "ls180.v:4443.38-4443.212" + cell $or $or$ls180.v:4443$747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4345$631_Y + connect \A $or$ls180.v:4443$746_Y connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4345$632_Y + connect \Y $or$ls180.v:4443$747_Y end - attribute \src "ls180.v:4345.37-4345.257" - cell $or $or$ls180.v:4345$633 + attribute \src "ls180.v:4443.37-4443.257" + cell $or $or$ls180.v:4443$748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4345$632_Y + connect \A $or$ls180.v:4443$747_Y connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4345$633_Y + connect \Y $or$ls180.v:4443$748_Y end - attribute \src "ls180.v:4346.39-4346.120" - cell $or $or$ls180.v:4346$634 + attribute \src "ls180.v:4444.39-4444.120" + cell $or $or$ls180.v:4444$749 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -258242,43 +260488,43 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_init_pads_out_payload_data_o connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4346$634_Y + connect \Y $or$ls180.v:4444$749_Y end - attribute \src "ls180.v:4346.38-4346.163" - cell $or $or$ls180.v:4346$635 + attribute \src "ls180.v:4444.38-4444.163" + cell $or $or$ls180.v:4444$750 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4346$634_Y + connect \A $or$ls180.v:4444$749_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4346$635_Y + connect \Y $or$ls180.v:4444$750_Y end - attribute \src "ls180.v:4346.37-4346.207" - cell $or $or$ls180.v:4346$636 + attribute \src "ls180.v:4444.37-4444.207" + cell $or $or$ls180.v:4444$751 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4346$635_Y + connect \A $or$ls180.v:4444$750_Y connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4346$636_Y + connect \Y $or$ls180.v:4444$751_Y end - attribute \src "ls180.v:4346.36-4346.251" - cell $or $or$ls180.v:4346$637 + attribute \src "ls180.v:4444.36-4444.251" + cell $or $or$ls180.v:4444$752 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4346$636_Y + connect \A $or$ls180.v:4444$751_Y connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4346$637_Y + connect \Y $or$ls180.v:4444$752_Y end - attribute \src "ls180.v:4367.35-4367.80" - cell $or $or$ls180.v:4367$638 + attribute \src "ls180.v:4465.35-4465.80" + cell $or $or$ls180.v:4465$753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258286,10 +260532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_stop connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4367$638_Y + connect \Y $or$ls180.v:4465$753_Y end - attribute \src "ls180.v:4521.91-4521.144" - cell $or $or$ls180.v:4521$652 + attribute \src "ls180.v:4619.91-4619.144" + cell $or $or$ls180.v:4619$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258297,76 +260543,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4521$652_Y + connect \Y $or$ls180.v:4619$767_Y end - attribute \src "ls180.v:4538.53-4538.143" - cell $or $or$ls180.v:4538$655 + attribute \src "ls180.v:4636.53-4636.143" + cell $or $or$ls180.v:4636$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4538$654_Y + connect \A $not$ls180.v:4636$769_Y connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4538$655_Y + connect \Y $or$ls180.v:4636$770_Y end - attribute \src "ls180.v:4541.47-4541.127" - cell $or $or$ls180.v:4541$658 + attribute \src "ls180.v:4639.47-4639.127" + cell $or $or$ls180.v:4639$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4541$657_Y + connect \A $not$ls180.v:4639$772_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4541$658_Y + connect \Y $or$ls180.v:4639$773_Y end - attribute \src "ls180.v:4665.54-4665.146" - cell $or $or$ls180.v:4665$676 + attribute \src "ls180.v:4763.54-4763.146" + cell $or $or$ls180.v:4763$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4665$675_Y + connect \A $not$ls180.v:4763$790_Y connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4665$676_Y + connect \Y $or$ls180.v:4763$791_Y end - attribute \src "ls180.v:4668.48-4668.130" - cell $or $or$ls180.v:4668$679 + attribute \src "ls180.v:4766.48-4766.130" + cell $or $or$ls180.v:4766$794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4668$678_Y + connect \A $not$ls180.v:4766$793_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4668$679_Y + connect \Y $or$ls180.v:4766$794_Y end - attribute \src "ls180.v:4799.55-4799.149" - cell $or $or$ls180.v:4799$691 + attribute \src "ls180.v:4897.55-4897.149" + cell $or $or$ls180.v:4897$806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4799$690_Y + connect \A $not$ls180.v:4897$805_Y connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4799$691_Y + connect \Y $or$ls180.v:4897$806_Y end - attribute \src "ls180.v:4802.49-4802.133" - cell $or $or$ls180.v:4802$694 + attribute \src "ls180.v:4900.49-4900.133" + cell $or $or$ls180.v:4900$809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4802$693_Y + connect \A $not$ls180.v:4900$808_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4802$694_Y + connect \Y $or$ls180.v:4900$809_Y end - attribute \src "ls180.v:5431.80-5431.151" - cell $or $or$ls180.v:5431$989 + attribute \src "ls180.v:5529.80-5529.151" + cell $or $or$ls180.v:5529$1104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258374,21 +260620,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_writable connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5431$989_Y + connect \Y $or$ls180.v:5529$1104_Y end - attribute \src "ls180.v:5442.49-5442.131" - cell $or $or$ls180.v:5442$995 + attribute \src "ls180.v:5540.49-5540.131" + cell $or $or$ls180.v:5540$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5442$994_Y + connect \A $not$ls180.v:5540$1109_Y connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5442$995_Y + connect \Y $or$ls180.v:5540$1110_Y end - attribute \src "ls180.v:5639.80-5639.151" - cell $or $or$ls180.v:5639$1020 + attribute \src "ls180.v:5749.80-5749.151" + cell $or $or$ls180.v:5749$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258396,142 +260642,241 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_writable connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5639$1020_Y + connect \Y $or$ls180.v:5749$1135_Y end - attribute \src "ls180.v:5754.33-5754.102" - cell $or $or$ls180.v:5754$1060 + attribute \src "ls180.v:5891.36-5891.94" + cell $or $or$ls180.v:5891$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_err - connect \B \main_libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:5754$1060_Y + connect \B \main_interface0_ram_bus_err + connect \Y $or$ls180.v:5891$1181_Y + end + attribute \src "ls180.v:5891.35-5891.125" + cell $or $or$ls180.v:5891$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5891$1181_Y + connect \B \main_interface1_ram_bus_err + connect \Y $or$ls180.v:5891$1182_Y + end + attribute \src "ls180.v:5891.34-5891.156" + cell $or $or$ls180.v:5891$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5891$1182_Y + connect \B \main_interface2_ram_bus_err + connect \Y $or$ls180.v:5891$1183_Y + end + attribute \src "ls180.v:5891.33-5891.199" + cell $or $or$ls180.v:5891$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5891$1183_Y + connect \B \main_interface0_converted_interface_err + connect \Y $or$ls180.v:5891$1184_Y end - attribute \src "ls180.v:5754.32-5754.144" - cell $or $or$ls180.v:5754$1061 + attribute \src "ls180.v:5891.32-5891.242" + cell $or $or$ls180.v:5891$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5754$1060_Y - connect \B \main_libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:5754$1061_Y + connect \A $or$ls180.v:5891$1184_Y + connect \B \main_interface1_converted_interface_err + connect \Y $or$ls180.v:5891$1185_Y end - attribute \src "ls180.v:5754.31-5754.165" - cell $or $or$ls180.v:5754$1062 + attribute \src "ls180.v:5891.31-5891.288" + cell $or $or$ls180.v:5891$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5754$1061_Y - connect \B \main_wb_sdram_err - connect \Y $or$ls180.v:5754$1062_Y + connect \A $or$ls180.v:5891$1185_Y + connect \B \main_socbushandler_converted_interface_err + connect \Y $or$ls180.v:5891$1186_Y end - attribute \src "ls180.v:5754.30-5754.201" - cell $or $or$ls180.v:5754$1063 + attribute \src "ls180.v:5891.30-5891.335" + cell $or $or$ls180.v:5891$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5754$1062_Y - connect \B \builder_libresocsim_wishbone_err - connect \Y $or$ls180.v:5754$1063_Y + connect \A $or$ls180.v:5891$1186_Y + connect \B \builder_libresocsim_converted_interface_err + connect \Y $or$ls180.v:5891$1187_Y end - attribute \src "ls180.v:5760.28-5760.97" - cell $or $or$ls180.v:5760$1068 + attribute \src "ls180.v:5897.31-5897.89" + cell $or $or$ls180.v:5897$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \B \main_libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:5760$1068_Y + connect \B \main_interface0_ram_bus_ack + connect \Y $or$ls180.v:5897$1192_Y end - attribute \src "ls180.v:5760.27-5760.139" - cell $or $or$ls180.v:5760$1069 + attribute \src "ls180.v:5897.30-5897.120" + cell $or $or$ls180.v:5897$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5760$1068_Y - connect \B \main_libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:5760$1069_Y + connect \A $or$ls180.v:5897$1192_Y + connect \B \main_interface1_ram_bus_ack + connect \Y $or$ls180.v:5897$1193_Y end - attribute \src "ls180.v:5760.26-5760.160" - cell $or $or$ls180.v:5760$1070 + attribute \src "ls180.v:5897.29-5897.151" + cell $or $or$ls180.v:5897$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5760$1069_Y - connect \B \main_wb_sdram_ack - connect \Y $or$ls180.v:5760$1070_Y + connect \A $or$ls180.v:5897$1193_Y + connect \B \main_interface2_ram_bus_ack + connect \Y $or$ls180.v:5897$1194_Y end - attribute \src "ls180.v:5760.25-5760.196" - cell $or $or$ls180.v:5760$1071 + attribute \src "ls180.v:5897.28-5897.194" + cell $or $or$ls180.v:5897$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5760$1070_Y - connect \B \builder_libresocsim_wishbone_ack - connect \Y $or$ls180.v:5760$1071_Y + connect \A $or$ls180.v:5897$1194_Y + connect \B \main_interface0_converted_interface_ack + connect \Y $or$ls180.v:5897$1195_Y end - attribute \src "ls180.v:5761.30-5761.169" - cell $or $or$ls180.v:5761$1074 + attribute \src "ls180.v:5897.27-5897.237" + cell $or $or$ls180.v:5897$1196 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $and$ls180.v:5761$1072_Y - connect \B $and$ls180.v:5761$1073_Y - connect \Y $or$ls180.v:5761$1074_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5897$1195_Y + connect \B \main_interface1_converted_interface_ack + connect \Y $or$ls180.v:5897$1196_Y end - attribute \src "ls180.v:5761.29-5761.246" - cell $or $or$ls180.v:5761$1076 + attribute \src "ls180.v:5897.26-5897.283" + cell $or $or$ls180.v:5897$1197 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5761$1074_Y - connect \B $and$ls180.v:5761$1075_Y - connect \Y $or$ls180.v:5761$1076_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5897$1196_Y + connect \B \main_socbushandler_converted_interface_ack + connect \Y $or$ls180.v:5897$1197_Y end - attribute \src "ls180.v:5761.28-5761.302" - cell $or $or$ls180.v:5761$1078 + attribute \src "ls180.v:5897.25-5897.330" + cell $or $or$ls180.v:5897$1198 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5761$1076_Y - connect \B $and$ls180.v:5761$1077_Y - connect \Y $or$ls180.v:5761$1078_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5897$1197_Y + connect \B \builder_libresocsim_converted_interface_ack + connect \Y $or$ls180.v:5897$1198_Y end - attribute \src "ls180.v:5761.27-5761.373" - cell $or $or$ls180.v:5761$1080 + attribute \src "ls180.v:5898.33-5898.161" + cell $or $or$ls180.v:5898$1201 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5761$1078_Y - connect \B $and$ls180.v:5761$1079_Y - connect \Y $or$ls180.v:5761$1080_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $and$ls180.v:5898$1199_Y + connect \B $and$ls180.v:5898$1200_Y + connect \Y $or$ls180.v:5898$1201_Y + end + attribute \src "ls180.v:5898.32-5898.227" + cell $or $or$ls180.v:5898$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5898$1201_Y + connect \B $and$ls180.v:5898$1202_Y + connect \Y $or$ls180.v:5898$1203_Y end - attribute \src "ls180.v:6515.55-6515.124" - cell $or $or$ls180.v:6515$2226 + attribute \src "ls180.v:5898.31-5898.293" + cell $or $or$ls180.v:5898$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5898$1203_Y + connect \B $and$ls180.v:5898$1204_Y + connect \Y $or$ls180.v:5898$1205_Y + end + attribute \src "ls180.v:5898.30-5898.371" + cell $or $or$ls180.v:5898$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5898$1205_Y + connect \B $and$ls180.v:5898$1206_Y + connect \Y $or$ls180.v:5898$1207_Y + end + attribute \src "ls180.v:5898.29-5898.449" + cell $or $or$ls180.v:5898$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5898$1207_Y + connect \B $and$ls180.v:5898$1208_Y + connect \Y $or$ls180.v:5898$1209_Y + end + attribute \src "ls180.v:5898.28-5898.530" + cell $or $or$ls180.v:5898$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5898$1209_Y + connect \B $and$ls180.v:5898$1210_Y + connect \Y $or$ls180.v:5898$1211_Y + end + attribute \src "ls180.v:5898.27-5898.612" + cell $or $or$ls180.v:5898$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5898$1211_Y + connect \B $and$ls180.v:5898$1212_Y + connect \Y $or$ls180.v:5898$1213_Y + end + attribute \src "ls180.v:6652.55-6652.124" + cell $or $or$ls180.v:6652$2359 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -258539,285 +260884,285 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \builder_interface0_bank_bus_dat_r connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2226_Y + connect \Y $or$ls180.v:6652$2359_Y end - attribute \src "ls180.v:6515.54-6515.161" - cell $or $or$ls180.v:6515$2227 + attribute \src "ls180.v:6652.54-6652.161" + cell $or $or$ls180.v:6652$2360 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2226_Y + connect \A $or$ls180.v:6652$2359_Y connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2227_Y + connect \Y $or$ls180.v:6652$2360_Y end - attribute \src "ls180.v:6515.53-6515.198" - cell $or $or$ls180.v:6515$2228 + attribute \src "ls180.v:6652.53-6652.198" + cell $or $or$ls180.v:6652$2361 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2227_Y + connect \A $or$ls180.v:6652$2360_Y connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2228_Y + connect \Y $or$ls180.v:6652$2361_Y end - attribute \src "ls180.v:6515.52-6515.235" - cell $or $or$ls180.v:6515$2229 + attribute \src "ls180.v:6652.52-6652.235" + cell $or $or$ls180.v:6652$2362 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2228_Y + connect \A $or$ls180.v:6652$2361_Y connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2229_Y + connect \Y $or$ls180.v:6652$2362_Y end - attribute \src "ls180.v:6515.51-6515.272" - cell $or $or$ls180.v:6515$2230 + attribute \src "ls180.v:6652.51-6652.272" + cell $or $or$ls180.v:6652$2363 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2229_Y + connect \A $or$ls180.v:6652$2362_Y connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2230_Y + connect \Y $or$ls180.v:6652$2363_Y end - attribute \src "ls180.v:6515.50-6515.309" - cell $or $or$ls180.v:6515$2231 + attribute \src "ls180.v:6652.50-6652.309" + cell $or $or$ls180.v:6652$2364 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2230_Y + connect \A $or$ls180.v:6652$2363_Y connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2231_Y + connect \Y $or$ls180.v:6652$2364_Y end - attribute \src "ls180.v:6515.49-6515.346" - cell $or $or$ls180.v:6515$2232 + attribute \src "ls180.v:6652.49-6652.346" + cell $or $or$ls180.v:6652$2365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2231_Y + connect \A $or$ls180.v:6652$2364_Y connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2232_Y + connect \Y $or$ls180.v:6652$2365_Y end - attribute \src "ls180.v:6515.48-6515.383" - cell $or $or$ls180.v:6515$2233 + attribute \src "ls180.v:6652.48-6652.383" + cell $or $or$ls180.v:6652$2366 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2232_Y + connect \A $or$ls180.v:6652$2365_Y connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2233_Y + connect \Y $or$ls180.v:6652$2366_Y end - attribute \src "ls180.v:6515.47-6515.420" - cell $or $or$ls180.v:6515$2234 + attribute \src "ls180.v:6652.47-6652.420" + cell $or $or$ls180.v:6652$2367 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2233_Y + connect \A $or$ls180.v:6652$2366_Y connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2234_Y + connect \Y $or$ls180.v:6652$2367_Y end - attribute \src "ls180.v:6515.46-6515.458" - cell $or $or$ls180.v:6515$2235 + attribute \src "ls180.v:6652.46-6652.458" + cell $or $or$ls180.v:6652$2368 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2234_Y + connect \A $or$ls180.v:6652$2367_Y connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2235_Y + connect \Y $or$ls180.v:6652$2368_Y end - attribute \src "ls180.v:6515.45-6515.496" - cell $or $or$ls180.v:6515$2236 + attribute \src "ls180.v:6652.45-6652.496" + cell $or $or$ls180.v:6652$2369 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2235_Y + connect \A $or$ls180.v:6652$2368_Y connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2236_Y + connect \Y $or$ls180.v:6652$2369_Y end - attribute \src "ls180.v:6515.44-6515.534" - cell $or $or$ls180.v:6515$2237 + attribute \src "ls180.v:6652.44-6652.534" + cell $or $or$ls180.v:6652$2370 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2236_Y + connect \A $or$ls180.v:6652$2369_Y connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2237_Y + connect \Y $or$ls180.v:6652$2370_Y end - attribute \src "ls180.v:6515.43-6515.572" - cell $or $or$ls180.v:6515$2238 + attribute \src "ls180.v:6652.43-6652.572" + cell $or $or$ls180.v:6652$2371 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2237_Y + connect \A $or$ls180.v:6652$2370_Y connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2238_Y + connect \Y $or$ls180.v:6652$2371_Y end - attribute \src "ls180.v:6515.42-6515.610" - cell $or $or$ls180.v:6515$2239 + attribute \src "ls180.v:6652.42-6652.610" + cell $or $or$ls180.v:6652$2372 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6515$2238_Y + connect \A $or$ls180.v:6652$2371_Y connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6515$2239_Y + connect \Y $or$ls180.v:6652$2372_Y end - attribute \src "ls180.v:6842.90-6842.179" - cell $or $or$ls180.v:6842$2264 + attribute \src "ls180.v:6979.90-6979.179" + cell $or $or$ls180.v:6979$2397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:6842$2263_Y - connect \Y $or$ls180.v:6842$2264_Y + connect \B $and$ls180.v:6979$2396_Y + connect \Y $or$ls180.v:6979$2397_Y end - attribute \src "ls180.v:6842.89-6842.254" - cell $or $or$ls180.v:6842$2267 + attribute \src "ls180.v:6979.89-6979.254" + cell $or $or$ls180.v:6979$2400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6842$2264_Y - connect \B $and$ls180.v:6842$2266_Y - connect \Y $or$ls180.v:6842$2267_Y + connect \A $or$ls180.v:6979$2397_Y + connect \B $and$ls180.v:6979$2399_Y + connect \Y $or$ls180.v:6979$2400_Y end - attribute \src "ls180.v:6842.88-6842.329" - cell $or $or$ls180.v:6842$2270 + attribute \src "ls180.v:6979.88-6979.329" + cell $or $or$ls180.v:6979$2403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6842$2267_Y - connect \B $and$ls180.v:6842$2269_Y - connect \Y $or$ls180.v:6842$2270_Y + connect \A $or$ls180.v:6979$2400_Y + connect \B $and$ls180.v:6979$2402_Y + connect \Y $or$ls180.v:6979$2403_Y end - attribute \src "ls180.v:6866.90-6866.179" - cell $or $or$ls180.v:6866$2280 + attribute \src "ls180.v:7003.90-7003.179" + cell $or $or$ls180.v:7003$2413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:6866$2279_Y - connect \Y $or$ls180.v:6866$2280_Y + connect \B $and$ls180.v:7003$2412_Y + connect \Y $or$ls180.v:7003$2413_Y end - attribute \src "ls180.v:6866.89-6866.254" - cell $or $or$ls180.v:6866$2283 + attribute \src "ls180.v:7003.89-7003.254" + cell $or $or$ls180.v:7003$2416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6866$2280_Y - connect \B $and$ls180.v:6866$2282_Y - connect \Y $or$ls180.v:6866$2283_Y + connect \A $or$ls180.v:7003$2413_Y + connect \B $and$ls180.v:7003$2415_Y + connect \Y $or$ls180.v:7003$2416_Y end - attribute \src "ls180.v:6866.88-6866.329" - cell $or $or$ls180.v:6866$2286 + attribute \src "ls180.v:7003.88-7003.329" + cell $or $or$ls180.v:7003$2419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6866$2283_Y - connect \B $and$ls180.v:6866$2285_Y - connect \Y $or$ls180.v:6866$2286_Y + connect \A $or$ls180.v:7003$2416_Y + connect \B $and$ls180.v:7003$2418_Y + connect \Y $or$ls180.v:7003$2419_Y end - attribute \src "ls180.v:6890.90-6890.179" - cell $or $or$ls180.v:6890$2296 + attribute \src "ls180.v:7027.90-7027.179" + cell $or $or$ls180.v:7027$2429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:6890$2295_Y - connect \Y $or$ls180.v:6890$2296_Y + connect \B $and$ls180.v:7027$2428_Y + connect \Y $or$ls180.v:7027$2429_Y end - attribute \src "ls180.v:6890.89-6890.254" - cell $or $or$ls180.v:6890$2299 + attribute \src "ls180.v:7027.89-7027.254" + cell $or $or$ls180.v:7027$2432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6890$2296_Y - connect \B $and$ls180.v:6890$2298_Y - connect \Y $or$ls180.v:6890$2299_Y + connect \A $or$ls180.v:7027$2429_Y + connect \B $and$ls180.v:7027$2431_Y + connect \Y $or$ls180.v:7027$2432_Y end - attribute \src "ls180.v:6890.88-6890.329" - cell $or $or$ls180.v:6890$2302 + attribute \src "ls180.v:7027.88-7027.329" + cell $or $or$ls180.v:7027$2435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6890$2299_Y - connect \B $and$ls180.v:6890$2301_Y - connect \Y $or$ls180.v:6890$2302_Y + connect \A $or$ls180.v:7027$2432_Y + connect \B $and$ls180.v:7027$2434_Y + connect \Y $or$ls180.v:7027$2435_Y end - attribute \src "ls180.v:6914.90-6914.179" - cell $or $or$ls180.v:6914$2312 + attribute \src "ls180.v:7051.90-7051.179" + cell $or $or$ls180.v:7051$2445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:6914$2311_Y - connect \Y $or$ls180.v:6914$2312_Y + connect \B $and$ls180.v:7051$2444_Y + connect \Y $or$ls180.v:7051$2445_Y end - attribute \src "ls180.v:6914.89-6914.254" - cell $or $or$ls180.v:6914$2315 + attribute \src "ls180.v:7051.89-7051.254" + cell $or $or$ls180.v:7051$2448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6914$2312_Y - connect \B $and$ls180.v:6914$2314_Y - connect \Y $or$ls180.v:6914$2315_Y + connect \A $or$ls180.v:7051$2445_Y + connect \B $and$ls180.v:7051$2447_Y + connect \Y $or$ls180.v:7051$2448_Y end - attribute \src "ls180.v:6914.88-6914.329" - cell $or $or$ls180.v:6914$2318 + attribute \src "ls180.v:7051.88-7051.329" + cell $or $or$ls180.v:7051$2451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6914$2315_Y - connect \B $and$ls180.v:6914$2317_Y - connect \Y $or$ls180.v:6914$2318_Y + connect \A $or$ls180.v:7051$2448_Y + connect \B $and$ls180.v:7051$2450_Y + connect \Y $or$ls180.v:7051$2451_Y end - attribute \src "ls180.v:7428.20-7428.71" - cell $or $or$ls180.v:7428$2375 + attribute \src "ls180.v:7565.20-7565.71" + cell $or $or$ls180.v:7565$2508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258825,10 +261170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7428$2375_Y + connect \Y $or$ls180.v:7565$2508_Y end - attribute \src "ls180.v:7429.20-7429.71" - cell $or $or$ls180.v:7429$2376 + attribute \src "ls180.v:7566.20-7566.71" + cell $or $or$ls180.v:7566$2509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258836,10 +261181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7429$2376_Y + connect \Y $or$ls180.v:7566$2509_Y end - attribute \src "ls180.v:7430.20-7430.71" - cell $or $or$ls180.v:7430$2377 + attribute \src "ls180.v:7567.20-7567.71" + cell $or $or$ls180.v:7567$2510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258847,10 +261192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7430$2377_Y + connect \Y $or$ls180.v:7567$2510_Y end - attribute \src "ls180.v:7431.20-7431.71" - cell $or $or$ls180.v:7431$2378 + attribute \src "ls180.v:7568.20-7568.71" + cell $or $or$ls180.v:7568$2511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258858,10 +261203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7431$2378_Y + connect \Y $or$ls180.v:7568$2511_Y end - attribute \src "ls180.v:7432.20-7432.71" - cell $or $or$ls180.v:7432$2379 + attribute \src "ls180.v:7569.20-7569.71" + cell $or $or$ls180.v:7569$2512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258869,10 +261214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7432$2379_Y + connect \Y $or$ls180.v:7569$2512_Y end - attribute \src "ls180.v:7433.20-7433.71" - cell $or $or$ls180.v:7433$2380 + attribute \src "ls180.v:7570.20-7570.71" + cell $or $or$ls180.v:7570$2513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258880,10 +261225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7433$2380_Y + connect \Y $or$ls180.v:7570$2513_Y end - attribute \src "ls180.v:7434.20-7434.71" - cell $or $or$ls180.v:7434$2381 + attribute \src "ls180.v:7571.20-7571.71" + cell $or $or$ls180.v:7571$2514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258891,10 +261236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7434$2381_Y + connect \Y $or$ls180.v:7571$2514_Y end - attribute \src "ls180.v:7435.20-7435.71" - cell $or $or$ls180.v:7435$2382 + attribute \src "ls180.v:7572.20-7572.71" + cell $or $or$ls180.v:7572$2515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258902,10 +261247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7435$2382_Y + connect \Y $or$ls180.v:7572$2515_Y end - attribute \src "ls180.v:7436.20-7436.71" - cell $or $or$ls180.v:7436$2383 + attribute \src "ls180.v:7573.20-7573.71" + cell $or $or$ls180.v:7573$2516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258913,10 +261258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7436$2383_Y + connect \Y $or$ls180.v:7573$2516_Y end - attribute \src "ls180.v:7437.20-7437.71" - cell $or $or$ls180.v:7437$2384 + attribute \src "ls180.v:7574.20-7574.71" + cell $or $or$ls180.v:7574$2517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258924,10 +261269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7437$2384_Y + connect \Y $or$ls180.v:7574$2517_Y end - attribute \src "ls180.v:7438.21-7438.73" - cell $or $or$ls180.v:7438$2385 + attribute \src "ls180.v:7575.21-7575.73" + cell $or $or$ls180.v:7575$2518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258935,10 +261280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7438$2385_Y + connect \Y $or$ls180.v:7575$2518_Y end - attribute \src "ls180.v:7439.21-7439.73" - cell $or $or$ls180.v:7439$2386 + attribute \src "ls180.v:7576.21-7576.73" + cell $or $or$ls180.v:7576$2519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258946,10 +261291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7439$2386_Y + connect \Y $or$ls180.v:7576$2519_Y end - attribute \src "ls180.v:7440.21-7440.73" - cell $or $or$ls180.v:7440$2387 + attribute \src "ls180.v:7577.21-7577.73" + cell $or $or$ls180.v:7577$2520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258957,10 +261302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7440$2387_Y + connect \Y $or$ls180.v:7577$2520_Y end - attribute \src "ls180.v:7441.21-7441.73" - cell $or $or$ls180.v:7441$2388 + attribute \src "ls180.v:7578.21-7578.73" + cell $or $or$ls180.v:7578$2521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258968,10 +261313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7441$2388_Y + connect \Y $or$ls180.v:7578$2521_Y end - attribute \src "ls180.v:7442.21-7442.73" - cell $or $or$ls180.v:7442$2389 + attribute \src "ls180.v:7579.21-7579.73" + cell $or $or$ls180.v:7579$2522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258979,10 +261324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7442$2389_Y + connect \Y $or$ls180.v:7579$2522_Y end - attribute \src "ls180.v:7443.21-7443.73" - cell $or $or$ls180.v:7443$2390 + attribute \src "ls180.v:7580.21-7580.73" + cell $or $or$ls180.v:7580$2523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258990,10 +261335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7443$2390_Y + connect \Y $or$ls180.v:7580$2523_Y end - attribute \src "ls180.v:7444.21-7444.73" - cell $or $or$ls180.v:7444$2391 + attribute \src "ls180.v:7581.21-7581.73" + cell $or $or$ls180.v:7581$2524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259001,10 +261346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7444$2391_Y + connect \Y $or$ls180.v:7581$2524_Y end - attribute \src "ls180.v:7445.21-7445.73" - cell $or $or$ls180.v:7445$2392 + attribute \src "ls180.v:7582.21-7582.73" + cell $or $or$ls180.v:7582$2525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259012,10 +261357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7445$2392_Y + connect \Y $or$ls180.v:7582$2525_Y end - attribute \src "ls180.v:7446.21-7446.73" - cell $or $or$ls180.v:7446$2393 + attribute \src "ls180.v:7583.21-7583.73" + cell $or $or$ls180.v:7583$2526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259023,10 +261368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7446$2393_Y + connect \Y $or$ls180.v:7583$2526_Y end - attribute \src "ls180.v:7447.21-7447.73" - cell $or $or$ls180.v:7447$2394 + attribute \src "ls180.v:7584.21-7584.73" + cell $or $or$ls180.v:7584$2527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259034,10 +261379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7447$2394_Y + connect \Y $or$ls180.v:7584$2527_Y end - attribute \src "ls180.v:7448.21-7448.73" - cell $or $or$ls180.v:7448$2395 + attribute \src "ls180.v:7585.21-7585.73" + cell $or $or$ls180.v:7585$2528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259045,10 +261390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7448$2395_Y + connect \Y $or$ls180.v:7585$2528_Y end - attribute \src "ls180.v:7449.21-7449.73" - cell $or $or$ls180.v:7449$2396 + attribute \src "ls180.v:7586.21-7586.73" + cell $or $or$ls180.v:7586$2529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259056,10 +261401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7449$2396_Y + connect \Y $or$ls180.v:7586$2529_Y end - attribute \src "ls180.v:7450.21-7450.73" - cell $or $or$ls180.v:7450$2397 + attribute \src "ls180.v:7587.21-7587.73" + cell $or $or$ls180.v:7587$2530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259067,10 +261412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7450$2397_Y + connect \Y $or$ls180.v:7587$2530_Y end - attribute \src "ls180.v:7451.21-7451.73" - cell $or $or$ls180.v:7451$2398 + attribute \src "ls180.v:7588.21-7588.73" + cell $or $or$ls180.v:7588$2531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259078,175 +261423,175 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7451$2398_Y + connect \Y $or$ls180.v:7588$2531_Y end - attribute \src "ls180.v:7452.7-7452.93" - cell $or $or$ls180.v:7452$2399 + attribute \src "ls180.v:7589.7-7589.68" + cell $or $or$ls180.v:7589$2532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:7452$2399_Y + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:7589$2532_Y end - attribute \src "ls180.v:7463.7-7463.93" - cell $or $or$ls180.v:7463$2400 + attribute \src "ls180.v:7600.7-7600.68" + cell $or $or$ls180.v:7600$2533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:7463$2400_Y + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:7600$2533_Y end - attribute \src "ls180.v:7474.7-7474.93" - cell $or $or$ls180.v:7474$2401 + attribute \src "ls180.v:7611.7-7611.50" + cell $or $or$ls180.v:7611$2534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:7474$2401_Y + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:7611$2534_Y end - attribute \src "ls180.v:7603.7-7603.107" - cell $or $or$ls180.v:7603$2437 + attribute \src "ls180.v:7752.7-7752.107" + cell $or $or$ls180.v:7752$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7603$2436_Y + connect \A $not$ls180.v:7752$2578_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7603$2437_Y + connect \Y $or$ls180.v:7752$2579_Y end - attribute \src "ls180.v:7649.7-7649.107" - cell $or $or$ls180.v:7649$2453 + attribute \src "ls180.v:7798.7-7798.107" + cell $or $or$ls180.v:7798$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7649$2452_Y + connect \A $not$ls180.v:7798$2594_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7649$2453_Y + connect \Y $or$ls180.v:7798$2595_Y end - attribute \src "ls180.v:7695.7-7695.107" - cell $or $or$ls180.v:7695$2469 + attribute \src "ls180.v:7844.7-7844.107" + cell $or $or$ls180.v:7844$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7695$2468_Y + connect \A $not$ls180.v:7844$2610_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7695$2469_Y + connect \Y $or$ls180.v:7844$2611_Y end - attribute \src "ls180.v:7741.7-7741.107" - cell $or $or$ls180.v:7741$2485 + attribute \src "ls180.v:7890.7-7890.107" + cell $or $or$ls180.v:7890$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7741$2484_Y + connect \A $not$ls180.v:7890$2626_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7741$2485_Y + connect \Y $or$ls180.v:7890$2627_Y end - attribute \src "ls180.v:7929.40-7929.125" - cell $or $or$ls180.v:7929$2506 + attribute \src "ls180.v:8078.40-8078.125" + cell $or $or$ls180.v:8078$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:7929$2505_Y - connect \Y $or$ls180.v:7929$2506_Y + connect \B $and$ls180.v:8078$2647_Y + connect \Y $or$ls180.v:8078$2648_Y end - attribute \src "ls180.v:7929.39-7929.207" - cell $or $or$ls180.v:7929$2509 + attribute \src "ls180.v:8078.39-8078.207" + cell $or $or$ls180.v:8078$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7929$2506_Y - connect \B $and$ls180.v:7929$2508_Y - connect \Y $or$ls180.v:7929$2509_Y + connect \A $or$ls180.v:8078$2648_Y + connect \B $and$ls180.v:8078$2650_Y + connect \Y $or$ls180.v:8078$2651_Y end - attribute \src "ls180.v:7929.38-7929.289" - cell $or $or$ls180.v:7929$2512 + attribute \src "ls180.v:8078.38-8078.289" + cell $or $or$ls180.v:8078$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7929$2509_Y - connect \B $and$ls180.v:7929$2511_Y - connect \Y $or$ls180.v:7929$2512_Y + connect \A $or$ls180.v:8078$2651_Y + connect \B $and$ls180.v:8078$2653_Y + connect \Y $or$ls180.v:8078$2654_Y end - attribute \src "ls180.v:7929.37-7929.371" - cell $or $or$ls180.v:7929$2515 + attribute \src "ls180.v:8078.37-8078.371" + cell $or $or$ls180.v:8078$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7929$2512_Y - connect \B $and$ls180.v:7929$2514_Y - connect \Y $or$ls180.v:7929$2515_Y + connect \A $or$ls180.v:8078$2654_Y + connect \B $and$ls180.v:8078$2656_Y + connect \Y $or$ls180.v:8078$2657_Y end - attribute \src "ls180.v:7930.41-7930.126" - cell $or $or$ls180.v:7930$2518 + attribute \src "ls180.v:8079.41-8079.126" + cell $or $or$ls180.v:8079$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:7930$2517_Y - connect \Y $or$ls180.v:7930$2518_Y + connect \B $and$ls180.v:8079$2659_Y + connect \Y $or$ls180.v:8079$2660_Y end - attribute \src "ls180.v:7930.40-7930.208" - cell $or $or$ls180.v:7930$2521 + attribute \src "ls180.v:8079.40-8079.208" + cell $or $or$ls180.v:8079$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7930$2518_Y - connect \B $and$ls180.v:7930$2520_Y - connect \Y $or$ls180.v:7930$2521_Y + connect \A $or$ls180.v:8079$2660_Y + connect \B $and$ls180.v:8079$2662_Y + connect \Y $or$ls180.v:8079$2663_Y end - attribute \src "ls180.v:7930.39-7930.290" - cell $or $or$ls180.v:7930$2524 + attribute \src "ls180.v:8079.39-8079.290" + cell $or $or$ls180.v:8079$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7930$2521_Y - connect \B $and$ls180.v:7930$2523_Y - connect \Y $or$ls180.v:7930$2524_Y + connect \A $or$ls180.v:8079$2663_Y + connect \B $and$ls180.v:8079$2665_Y + connect \Y $or$ls180.v:8079$2666_Y end - attribute \src "ls180.v:7930.38-7930.372" - cell $or $or$ls180.v:7930$2527 + attribute \src "ls180.v:8079.38-8079.372" + cell $or $or$ls180.v:8079$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7930$2524_Y - connect \B $and$ls180.v:7930$2526_Y - connect \Y $or$ls180.v:7930$2527_Y + connect \A $or$ls180.v:8079$2666_Y + connect \B $and$ls180.v:8079$2668_Y + connect \Y $or$ls180.v:8079$2669_Y end - attribute \src "ls180.v:7934.7-7934.49" - cell $or $or$ls180.v:7934$2528 + attribute \src "ls180.v:8083.7-8083.49" + cell $or $or$ls180.v:8083$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259254,32 +261599,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:7934$2528_Y + connect \Y $or$ls180.v:8083$2670_Y end - attribute \src "ls180.v:8097.21-8097.74" - cell $or $or$ls180.v:8097$2576 + attribute \src "ls180.v:8246.21-8246.74" + cell $or $or$ls180.v:8246$2718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8097$2574_Y - connect \B $not$ls180.v:8097$2575_Y - connect \Y $or$ls180.v:8097$2576_Y + connect \A $not$ls180.v:8246$2716_Y + connect \B $not$ls180.v:8246$2717_Y + connect \Y $or$ls180.v:8246$2718_Y end - attribute \src "ls180.v:8132.21-8132.71" - cell $or $or$ls180.v:8132$2581 + attribute \src "ls180.v:8281.21-8281.71" + cell $or $or$ls180.v:8281$2723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8132$2579_Y - connect \B $not$ls180.v:8132$2580_Y - connect \Y $or$ls180.v:8132$2581_Y + connect \A $not$ls180.v:8281$2721_Y + connect \B $not$ls180.v:8281$2722_Y + connect \Y $or$ls180.v:8281$2723_Y end - attribute \src "ls180.v:8200.32-8200.85" - cell $or $or$ls180.v:8200$2593 + attribute \src "ls180.v:8349.32-8349.85" + cell $or $or$ls180.v:8349$2735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259287,21 +261632,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8200$2593_Y + connect \Y $or$ls180.v:8349$2735_Y end - attribute \src "ls180.v:8206.8-8206.97" - cell $or $or$ls180.v:8206$2595 + attribute \src "ls180.v:8355.8-8355.97" + cell $or $or$ls180.v:8355$2737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8206$2594_Y + connect \A $eq$ls180.v:8355$2736_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8206$2595_Y + connect \Y $or$ls180.v:8355$2737_Y end - attribute \src "ls180.v:8223.52-8223.139" - cell $or $or$ls180.v:8223$2600 + attribute \src "ls180.v:8372.52-8372.139" + cell $or $or$ls180.v:8372$2742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259309,10 +261654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8223$2600_Y + connect \Y $or$ls180.v:8372$2742_Y end - attribute \src "ls180.v:8224.51-8224.136" - cell $or $or$ls180.v:8224$2601 + attribute \src "ls180.v:8373.51-8373.136" + cell $or $or$ls180.v:8373$2743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259320,21 +261665,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8224$2601_Y + connect \Y $or$ls180.v:8373$2743_Y end - attribute \src "ls180.v:8258.7-8258.87" - cell $or $or$ls180.v:8258$2604 + attribute \src "ls180.v:8407.7-8407.87" + cell $or $or$ls180.v:8407$2746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8258$2603_Y + connect \A $not$ls180.v:8407$2745_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8258$2604_Y + connect \Y $or$ls180.v:8407$2746_Y end - attribute \src "ls180.v:8281.33-8281.88" - cell $or $or$ls180.v:8281$2605 + attribute \src "ls180.v:8430.33-8430.88" + cell $or $or$ls180.v:8430$2747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259342,21 +261687,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8281$2605_Y + connect \Y $or$ls180.v:8430$2747_Y end - attribute \src "ls180.v:8287.8-8287.99" - cell $or $or$ls180.v:8287$2607 + attribute \src "ls180.v:8436.8-8436.99" + cell $or $or$ls180.v:8436$2749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8287$2606_Y + connect \A $eq$ls180.v:8436$2748_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8287$2607_Y + connect \Y $or$ls180.v:8436$2749_Y end - attribute \src "ls180.v:8304.53-8304.142" - cell $or $or$ls180.v:8304$2612 + attribute \src "ls180.v:8453.53-8453.142" + cell $or $or$ls180.v:8453$2754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259364,10 +261709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8304$2612_Y + connect \Y $or$ls180.v:8453$2754_Y end - attribute \src "ls180.v:8305.52-8305.139" - cell $or $or$ls180.v:8305$2613 + attribute \src "ls180.v:8454.52-8454.139" + cell $or $or$ls180.v:8454$2755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259375,21 +261720,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8305$2613_Y + connect \Y $or$ls180.v:8454$2755_Y end - attribute \src "ls180.v:8339.7-8339.89" - cell $or $or$ls180.v:8339$2616 + attribute \src "ls180.v:8488.7-8488.89" + cell $or $or$ls180.v:8488$2758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8339$2615_Y + connect \A $not$ls180.v:8488$2757_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8339$2616_Y + connect \Y $or$ls180.v:8488$2758_Y end - attribute \src "ls180.v:8360.34-8360.91" - cell $or $or$ls180.v:8360$2617 + attribute \src "ls180.v:8509.34-8509.91" + cell $or $or$ls180.v:8509$2759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259397,21 +261742,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8360$2617_Y + connect \Y $or$ls180.v:8509$2759_Y end - attribute \src "ls180.v:8366.8-8366.101" - cell $or $or$ls180.v:8366$2619 + attribute \src "ls180.v:8515.8-8515.101" + cell $or $or$ls180.v:8515$2761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8366$2618_Y + connect \A $eq$ls180.v:8515$2760_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8366$2619_Y + connect \Y $or$ls180.v:8515$2761_Y end - attribute \src "ls180.v:8383.54-8383.145" - cell $or $or$ls180.v:8383$2624 + attribute \src "ls180.v:8532.54-8532.145" + cell $or $or$ls180.v:8532$2766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259419,10 +261764,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8383$2624_Y + connect \Y $or$ls180.v:8532$2766_Y end - attribute \src "ls180.v:8384.53-8384.142" - cell $or $or$ls180.v:8384$2625 + attribute \src "ls180.v:8533.53-8533.142" + cell $or $or$ls180.v:8533$2767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259430,32 +261775,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8384$2625_Y + connect \Y $or$ls180.v:8533$2767_Y end - attribute \src "ls180.v:8400.7-8400.91" - cell $or $or$ls180.v:8400$2628 + attribute \src "ls180.v:8549.7-8549.91" + cell $or $or$ls180.v:8549$2770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8400$2627_Y + connect \A $not$ls180.v:8549$2769_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8400$2628_Y + connect \Y $or$ls180.v:8549$2770_Y end - attribute \src "ls180.v:8589.8-8589.89" - cell $or $or$ls180.v:8589$2652 + attribute \src "ls180.v:8738.8-8738.89" + cell $or $or$ls180.v:8738$2794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8589$2651_Y + connect \A $eq$ls180.v:8738$2793_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8589$2652_Y + connect \Y $or$ls180.v:8738$2794_Y end - attribute \src "ls180.v:8606.48-8606.127" - cell $or $or$ls180.v:8606$2657 + attribute \src "ls180.v:8755.48-8755.127" + cell $or $or$ls180.v:8755$2799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259463,10 +261808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8606$2657_Y + connect \Y $or$ls180.v:8755$2799_Y end - attribute \src "ls180.v:8607.47-8607.124" - cell $or $or$ls180.v:8607$2658 + attribute \src "ls180.v:8756.47-8756.124" + cell $or $or$ls180.v:8756$2800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259474,10 +261819,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8607$2658_Y + connect \Y $or$ls180.v:8756$2800_Y end - attribute \src "ls180.v:3178.46-3178.94" - cell $sshl $sshl$ls180.v:3178$83 + attribute \src "ls180.v:3276.46-3276.94" + cell $sshl $sshl$ls180.v:3276$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259485,10 +261830,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine0_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3178$83_Y + connect \Y $sshl$ls180.v:3276$198_Y end - attribute \src "ls180.v:3335.46-3335.94" - cell $sshl $sshl$ls180.v:3335$113 + attribute \src "ls180.v:3433.46-3433.94" + cell $sshl $sshl$ls180.v:3433$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259496,10 +261841,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine1_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3335$113_Y + connect \Y $sshl$ls180.v:3433$228_Y end - attribute \src "ls180.v:3492.46-3492.94" - cell $sshl $sshl$ls180.v:3492$143 + attribute \src "ls180.v:3590.46-3590.94" + cell $sshl $sshl$ls180.v:3590$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259507,10 +261852,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine2_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3492$143_Y + connect \Y $sshl$ls180.v:3590$258_Y end - attribute \src "ls180.v:3649.46-3649.94" - cell $sshl $sshl$ls180.v:3649$173 + attribute \src "ls180.v:3747.46-3747.94" + cell $sshl $sshl$ls180.v:3747$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259518,10 +261863,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine3_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3649$173_Y + connect \Y $sshl$ls180.v:3747$288_Y end - attribute \src "ls180.v:3209.63-3209.122" - cell $sub $sub$ls180.v:3209$96 + attribute \src "ls180.v:3307.63-3307.122" + cell $sub $sub$ls180.v:3307$211 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259529,10 +261874,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3209$96_Y + connect \Y $sub$ls180.v:3307$211_Y end - attribute \src "ls180.v:3366.63-3366.122" - cell $sub $sub$ls180.v:3366$126 + attribute \src "ls180.v:3464.63-3464.122" + cell $sub $sub$ls180.v:3464$241 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259540,10 +261885,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3366$126_Y + connect \Y $sub$ls180.v:3464$241_Y end - attribute \src "ls180.v:3523.63-3523.122" - cell $sub $sub$ls180.v:3523$156 + attribute \src "ls180.v:3621.63-3621.122" + cell $sub $sub$ls180.v:3621$271 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259551,10 +261896,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3523$156_Y + connect \Y $sub$ls180.v:3621$271_Y end - attribute \src "ls180.v:3680.63-3680.122" - cell $sub $sub$ls180.v:3680$186 + attribute \src "ls180.v:3778.63-3778.122" + cell $sub $sub$ls180.v:3778$301 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259562,10 +261907,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3680$186_Y + connect \Y $sub$ls180.v:3778$301_Y end - attribute \src "ls180.v:4086.38-4086.75" - cell $sub $sub$ls180.v:4086$540 + attribute \src "ls180.v:4184.38-4184.75" + cell $sub $sub$ls180.v:4184$655 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 @@ -259573,10 +261918,10 @@ module \ls180 parameter \Y_WIDTH 31 connect \A \main_litedram_wb_adr connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4086$540_Y + connect \Y $sub$ls180.v:4184$655_Y end - attribute \src "ls180.v:4172.36-4172.68" - cell $sub $sub$ls180.v:4172$585 + attribute \src "ls180.v:4270.36-4270.68" + cell $sub $sub$ls180.v:4270$700 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259584,10 +261929,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4172$585_Y + connect \Y $sub$ls180.v:4270$700_Y end - attribute \src "ls180.v:4202.36-4202.68" - cell $sub $sub$ls180.v:4202$596 + attribute \src "ls180.v:4300.36-4300.68" + cell $sub $sub$ls180.v:4300$711 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259595,10 +261940,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4202$596_Y + connect \Y $sub$ls180.v:4300$711_Y end - attribute \src "ls180.v:4227.70-4227.110" - cell $sub $sub$ls180.v:4227$602 + attribute \src "ls180.v:4325.70-4325.110" + cell $sub $sub$ls180.v:4325$717 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -259606,10 +261951,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4227$602_Y + connect \Y $sub$ls180.v:4325$717_Y end - attribute \src "ls180.v:4228.70-4228.104" - cell $sub $sub$ls180.v:4228$604 + attribute \src "ls180.v:4326.70-4326.104" + cell $sub $sub$ls180.v:4326$719 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -259617,10 +261962,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider connect \B 1'1 - connect \Y $sub$ls180.v:4228$604_Y + connect \Y $sub$ls180.v:4326$719_Y end - attribute \src "ls180.v:4255.37-4255.66" - cell $sub $sub$ls180.v:4255$608 + attribute \src "ls180.v:4353.37-4353.66" + cell $sub $sub$ls180.v:4353$723 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -259628,10 +261973,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spimaster1_length connect \B 1'1 - connect \Y $sub$ls180.v:4255$608_Y + connect \Y $sub$ls180.v:4353$723_Y end - attribute \src "ls180.v:4285.67-4285.107" - cell $sub $sub$ls180.v:4285$610 + attribute \src "ls180.v:4383.67-4383.107" + cell $sub $sub$ls180.v:4383$725 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -259639,10 +261984,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4285$610_Y + connect \Y $sub$ls180.v:4383$725_Y end - attribute \src "ls180.v:4286.67-4286.101" - cell $sub $sub$ls180.v:4286$612 + attribute \src "ls180.v:4384.67-4384.101" + cell $sub $sub$ls180.v:4384$727 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -259650,10 +261995,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 connect \B 1'1 - connect \Y $sub$ls180.v:4286$612_Y + connect \Y $sub$ls180.v:4384$727_Y end - attribute \src "ls180.v:4314.35-4314.64" - cell $sub $sub$ls180.v:4314$616 + attribute \src "ls180.v:4412.35-4412.64" + cell $sub $sub$ls180.v:4412$731 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -259661,10 +262006,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spisdcard_length0 connect \B 1'1 - connect \Y $sub$ls180.v:4314$616_Y + connect \Y $sub$ls180.v:4412$731_Y end - attribute \src "ls180.v:4568.60-4568.90" - cell $sub $sub$ls180.v:4568$660 + attribute \src "ls180.v:4666.60-4666.90" + cell $sub $sub$ls180.v:4666$775 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259672,10 +262017,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4568$660_Y + connect \Y $sub$ls180.v:4666$775_Y end - attribute \src "ls180.v:4579.62-4579.104" - cell $sub $sub$ls180.v:4579$662 + attribute \src "ls180.v:4677.62-4677.104" + cell $sub $sub$ls180.v:4677$777 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -259683,10 +262028,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_sink_payload_length connect \B 1'1 - connect \Y $sub$ls180.v:4579$662_Y + connect \Y $sub$ls180.v:4677$777_Y end - attribute \src "ls180.v:4596.60-4596.90" - cell $sub $sub$ls180.v:4596$666 + attribute \src "ls180.v:4694.60-4694.90" + cell $sub $sub$ls180.v:4694$781 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259694,10 +262039,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4596$666_Y + connect \Y $sub$ls180.v:4694$781_Y end - attribute \src "ls180.v:4825.62-4825.93" - cell $sub $sub$ls180.v:4825$696 + attribute \src "ls180.v:4923.62-4923.93" + cell $sub $sub$ls180.v:4923$811 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259705,10 +262050,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4825$696_Y + connect \Y $sub$ls180.v:4923$811_Y end - attribute \src "ls180.v:4830.62-4830.93" - cell $sub $sub$ls180.v:4830$697 + attribute \src "ls180.v:4928.62-4928.93" + cell $sub $sub$ls180.v:4928$812 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259716,21 +262061,21 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4830$697_Y + connect \Y $sub$ls180.v:4928$812_Y end - attribute \src "ls180.v:4841.64-4841.122" - cell $sub $sub$ls180.v:4841$700 + attribute \src "ls180.v:4939.64-4939.122" + cell $sub $sub$ls180.v:4939$815 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4841$699_Y + connect \A $add$ls180.v:4939$814_Y connect \B 1'1 - connect \Y $sub$ls180.v:4841$700_Y + connect \Y $sub$ls180.v:4939$815_Y end - attribute \src "ls180.v:4862.62-4862.93" - cell $sub $sub$ls180.v:4862$703 + attribute \src "ls180.v:4960.62-4960.93" + cell $sub $sub$ls180.v:4960$818 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259738,10 +262083,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4862$703_Y + connect \Y $sub$ls180.v:4960$818_Y end - attribute \src "ls180.v:5324.37-5324.75" - cell $sub $sub$ls180.v:5324$976 + attribute \src "ls180.v:5422.37-5422.75" + cell $sub $sub$ls180.v:5422$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259749,10 +262094,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5324$976_Y + connect \Y $sub$ls180.v:5422$1091_Y end - attribute \src "ls180.v:5339.62-5339.100" - cell $sub $sub$ls180.v:5339$979 + attribute \src "ls180.v:5437.62-5437.100" + cell $sub $sub$ls180.v:5437$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259760,10 +262105,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5339$979_Y + connect \Y $sub$ls180.v:5437$1094_Y end - attribute \src "ls180.v:5350.39-5350.77" - cell $sub $sub$ls180.v:5350$984 + attribute \src "ls180.v:5448.39-5448.77" + cell $sub $sub$ls180.v:5448$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259771,10 +262116,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5350$984_Y + connect \Y $sub$ls180.v:5448$1099_Y end - attribute \src "ls180.v:5425.40-5425.76" - cell $sub $sub$ls180.v:5425$988 + attribute \src "ls180.v:5523.40-5523.76" + cell $sub $sub$ls180.v:5523$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -259782,10 +262127,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5425$988_Y + connect \Y $sub$ls180.v:5523$1103_Y end - attribute \src "ls180.v:5474.56-5474.104" - cell $sub $sub$ls180.v:5474$1002 + attribute \src "ls180.v:5572.56-5572.104" + cell $sub $sub$ls180.v:5572$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259793,10 +262138,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_length connect \B 1'1 - connect \Y $sub$ls180.v:5474$1002_Y + connect \Y $sub$ls180.v:5572$1117_Y end - attribute \src "ls180.v:5564.71-5564.105" - cell $sub $sub$ls180.v:5564$1008 + attribute \src "ls180.v:5662.71-5662.105" + cell $sub $sub$ls180.v:5662$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259804,10 +262149,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_length connect \B 1'1 - connect \Y $sub$ls180.v:5564$1008_Y + connect \Y $sub$ls180.v:5662$1123_Y end - attribute \src "ls180.v:5633.40-5633.76" - cell $sub $sub$ls180.v:5633$1019 + attribute \src "ls180.v:5743.40-5743.76" + cell $sub $sub$ls180.v:5743$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -259815,10 +262160,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5633$1019_Y + connect \Y $sub$ls180.v:5743$1134_Y end - attribute \src "ls180.v:7498.31-7498.60" - cell $sub $sub$ls180.v:7498$2408 + attribute \src "ls180.v:7635.31-7635.60" + cell $sub $sub$ls180.v:7635$2541 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -259826,10 +262171,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7498$2408_Y + connect \Y $sub$ls180.v:7635$2541_Y end - attribute \src "ls180.v:7519.31-7519.61" - cell $sub $sub$ls180.v:7519$2413 + attribute \src "ls180.v:7668.31-7668.61" + cell $sub $sub$ls180.v:7668$2555 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -259837,10 +262182,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7519$2413_Y + connect \Y $sub$ls180.v:7668$2555_Y end - attribute \src "ls180.v:7525.34-7525.67" - cell $sub $sub$ls180.v:7525$2414 + attribute \src "ls180.v:7674.34-7674.67" + cell $sub $sub$ls180.v:7674$2556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259848,10 +262193,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7525$2414_Y + connect \Y $sub$ls180.v:7674$2556_Y end - attribute \src "ls180.v:7536.36-7536.69" - cell $sub $sub$ls180.v:7536$2417 + attribute \src "ls180.v:7685.36-7685.69" + cell $sub $sub$ls180.v:7685$2559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259859,10 +262204,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7536$2417_Y + connect \Y $sub$ls180.v:7685$2559_Y end - attribute \src "ls180.v:7600.59-7600.116" - cell $sub $sub$ls180.v:7600$2435 + attribute \src "ls180.v:7749.59-7749.116" + cell $sub $sub$ls180.v:7749$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259870,10 +262215,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7600$2435_Y + connect \Y $sub$ls180.v:7749$2577_Y end - attribute \src "ls180.v:7619.46-7619.90" - cell $sub $sub$ls180.v:7619$2439 + attribute \src "ls180.v:7768.46-7768.90" + cell $sub $sub$ls180.v:7768$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259881,10 +262226,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7619$2439_Y + connect \Y $sub$ls180.v:7768$2581_Y end - attribute \src "ls180.v:7646.59-7646.116" - cell $sub $sub$ls180.v:7646$2451 + attribute \src "ls180.v:7795.59-7795.116" + cell $sub $sub$ls180.v:7795$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259892,10 +262237,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7646$2451_Y + connect \Y $sub$ls180.v:7795$2593_Y end - attribute \src "ls180.v:7665.46-7665.90" - cell $sub $sub$ls180.v:7665$2455 + attribute \src "ls180.v:7814.46-7814.90" + cell $sub $sub$ls180.v:7814$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259903,10 +262248,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7665$2455_Y + connect \Y $sub$ls180.v:7814$2597_Y end - attribute \src "ls180.v:7692.59-7692.116" - cell $sub $sub$ls180.v:7692$2467 + attribute \src "ls180.v:7841.59-7841.116" + cell $sub $sub$ls180.v:7841$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259914,10 +262259,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7692$2467_Y + connect \Y $sub$ls180.v:7841$2609_Y end - attribute \src "ls180.v:7711.46-7711.90" - cell $sub $sub$ls180.v:7711$2471 + attribute \src "ls180.v:7860.46-7860.90" + cell $sub $sub$ls180.v:7860$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259925,10 +262270,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7711$2471_Y + connect \Y $sub$ls180.v:7860$2613_Y end - attribute \src "ls180.v:7738.59-7738.116" - cell $sub $sub$ls180.v:7738$2483 + attribute \src "ls180.v:7887.59-7887.116" + cell $sub $sub$ls180.v:7887$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259936,10 +262281,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7738$2483_Y + connect \Y $sub$ls180.v:7887$2625_Y end - attribute \src "ls180.v:7757.46-7757.90" - cell $sub $sub$ls180.v:7757$2487 + attribute \src "ls180.v:7906.46-7906.90" + cell $sub $sub$ls180.v:7906$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259947,10 +262292,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7757$2487_Y + connect \Y $sub$ls180.v:7906$2629_Y end - attribute \src "ls180.v:7768.25-7768.48" - cell $sub $sub$ls180.v:7768$2491 + attribute \src "ls180.v:7917.25-7917.48" + cell $sub $sub$ls180.v:7917$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -259958,10 +262303,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:7768$2491_Y + connect \Y $sub$ls180.v:7917$2633_Y end - attribute \src "ls180.v:7775.25-7775.48" - cell $sub $sub$ls180.v:7775$2494 + attribute \src "ls180.v:7924.25-7924.48" + cell $sub $sub$ls180.v:7924$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259969,10 +262314,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:7775$2494_Y + connect \Y $sub$ls180.v:7924$2636_Y end - attribute \src "ls180.v:7907.33-7907.64" - cell $sub $sub$ls180.v:7907$2499 + attribute \src "ls180.v:8056.33-8056.64" + cell $sub $sub$ls180.v:8056$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259980,10 +262325,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7907$2499_Y + connect \Y $sub$ls180.v:8056$2641_Y end - attribute \src "ls180.v:7922.33-7922.64" - cell $sub $sub$ls180.v:7922$2502 + attribute \src "ls180.v:8071.33-8071.64" + cell $sub $sub$ls180.v:8071$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -259991,10 +262336,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7922$2502_Y + connect \Y $sub$ls180.v:8071$2644_Y end - attribute \src "ls180.v:8049.33-8049.64" - cell $sub $sub$ls180.v:8049$2561 + attribute \src "ls180.v:8198.33-8198.64" + cell $sub $sub$ls180.v:8198$2703 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -260002,10 +262347,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8049$2561_Y + connect \Y $sub$ls180.v:8198$2703_Y end - attribute \src "ls180.v:8071.33-8071.64" - cell $sub $sub$ls180.v:8071$2572 + attribute \src "ls180.v:8220.33-8220.64" + cell $sub $sub$ls180.v:8220$2714 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -260013,10 +262358,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8071$2572_Y + connect \Y $sub$ls180.v:8220$2714_Y end - attribute \src "ls180.v:8106.34-8106.66" - cell $sub $sub$ls180.v:8106$2577 + attribute \src "ls180.v:8255.34-8255.66" + cell $sub $sub$ls180.v:8255$2719 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260024,10 +262369,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster34_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8106$2577_Y + connect \Y $sub$ls180.v:8255$2719_Y end - attribute \src "ls180.v:8141.32-8141.62" - cell $sub $sub$ls180.v:8141$2582 + attribute \src "ls180.v:8290.32-8290.62" + cell $sub $sub$ls180.v:8290$2724 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260035,10 +262380,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8141$2582_Y + connect \Y $sub$ls180.v:8290$2724_Y end - attribute \src "ls180.v:8165.30-8165.53" - cell $sub $sub$ls180.v:8165$2585 + attribute \src "ls180.v:8314.30-8314.53" + cell $sub $sub$ls180.v:8314$2727 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260046,10 +262391,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8165$2585_Y + connect \Y $sub$ls180.v:8314$2727_Y end - attribute \src "ls180.v:8179.30-8179.53" - cell $sub $sub$ls180.v:8179$2589 + attribute \src "ls180.v:8328.30-8328.53" + cell $sub $sub$ls180.v:8328$2731 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260057,10 +262402,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8179$2589_Y + connect \Y $sub$ls180.v:8328$2731_Y end - attribute \src "ls180.v:8582.36-8582.70" - cell $sub $sub$ls180.v:8582$2650 + attribute \src "ls180.v:8731.36-8731.70" + cell $sub $sub$ls180.v:8731$2792 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -260068,10 +262413,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8582$2650_Y + connect \Y $sub$ls180.v:8731$2792_Y end - attribute \src "ls180.v:8668.36-8668.70" - cell $sub $sub$ls180.v:8668$2672 + attribute \src "ls180.v:8829.36-8829.70" + cell $sub $sub$ls180.v:8829$2814 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -260079,10 +262424,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8668$2672_Y + connect \Y $sub$ls180.v:8829$2814_Y end - attribute \src "ls180.v:8781.22-8781.42" - cell $sub $sub$ls180.v:8781$2679 + attribute \src "ls180.v:8942.22-8942.42" + cell $sub $sub$ls180.v:8942$2821 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -260090,10 +262435,10 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:8781$2679_Y + connect \Y $sub$ls180.v:8942$2821_Y end - attribute \src "ls180.v:4922.353-4922.425" - cell $xor $xor$ls180.v:4922$710 + attribute \src "ls180.v:5020.353-5020.425" + cell $xor $xor$ls180.v:5020$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260101,10 +262446,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4922$710_Y + connect \Y $xor$ls180.v:5020$825_Y end - attribute \src "ls180.v:4922.200-4922.272" - cell $xor $xor$ls180.v:4922$711 + attribute \src "ls180.v:5020.200-5020.272" + cell $xor $xor$ls180.v:5020$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260112,21 +262457,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4922$711_Y + connect \Y $xor$ls180.v:5020$826_Y end - attribute \src "ls180.v:4922.160-4922.273" - cell $xor $xor$ls180.v:4922$712 + attribute \src "ls180.v:5020.160-5020.273" + cell $xor $xor$ls180.v:5020$827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4922$711_Y - connect \Y $xor$ls180.v:4922$712_Y + connect \B $xor$ls180.v:5020$826_Y + connect \Y $xor$ls180.v:5020$827_Y end - attribute \src "ls180.v:4923.353-4923.425" - cell $xor $xor$ls180.v:4923$713 + attribute \src "ls180.v:5021.353-5021.425" + cell $xor $xor$ls180.v:5021$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260134,10 +262479,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4923$713_Y + connect \Y $xor$ls180.v:5021$828_Y end - attribute \src "ls180.v:4923.200-4923.272" - cell $xor $xor$ls180.v:4923$714 + attribute \src "ls180.v:5021.200-5021.272" + cell $xor $xor$ls180.v:5021$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260145,21 +262490,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4923$714_Y + connect \Y $xor$ls180.v:5021$829_Y end - attribute \src "ls180.v:4923.160-4923.273" - cell $xor $xor$ls180.v:4923$715 + attribute \src "ls180.v:5021.160-5021.273" + cell $xor $xor$ls180.v:5021$830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4923$714_Y - connect \Y $xor$ls180.v:4923$715_Y + connect \B $xor$ls180.v:5021$829_Y + connect \Y $xor$ls180.v:5021$830_Y end - attribute \src "ls180.v:4924.353-4924.425" - cell $xor $xor$ls180.v:4924$716 + attribute \src "ls180.v:5022.353-5022.425" + cell $xor $xor$ls180.v:5022$831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260167,10 +262512,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4924$716_Y + connect \Y $xor$ls180.v:5022$831_Y end - attribute \src "ls180.v:4924.200-4924.272" - cell $xor $xor$ls180.v:4924$717 + attribute \src "ls180.v:5022.200-5022.272" + cell $xor $xor$ls180.v:5022$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260178,21 +262523,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4924$717_Y + connect \Y $xor$ls180.v:5022$832_Y end - attribute \src "ls180.v:4924.160-4924.273" - cell $xor $xor$ls180.v:4924$718 + attribute \src "ls180.v:5022.160-5022.273" + cell $xor $xor$ls180.v:5022$833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4924$717_Y - connect \Y $xor$ls180.v:4924$718_Y + connect \B $xor$ls180.v:5022$832_Y + connect \Y $xor$ls180.v:5022$833_Y end - attribute \src "ls180.v:4925.353-4925.425" - cell $xor $xor$ls180.v:4925$719 + attribute \src "ls180.v:5023.353-5023.425" + cell $xor $xor$ls180.v:5023$834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260200,10 +262545,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4925$719_Y + connect \Y $xor$ls180.v:5023$834_Y end - attribute \src "ls180.v:4925.200-4925.272" - cell $xor $xor$ls180.v:4925$720 + attribute \src "ls180.v:5023.200-5023.272" + cell $xor $xor$ls180.v:5023$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260211,21 +262556,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4925$720_Y + connect \Y $xor$ls180.v:5023$835_Y end - attribute \src "ls180.v:4925.160-4925.273" - cell $xor $xor$ls180.v:4925$721 + attribute \src "ls180.v:5023.160-5023.273" + cell $xor $xor$ls180.v:5023$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:4925$720_Y - connect \Y $xor$ls180.v:4925$721_Y + connect \B $xor$ls180.v:5023$835_Y + connect \Y $xor$ls180.v:5023$836_Y end - attribute \src "ls180.v:4926.353-4926.425" - cell $xor $xor$ls180.v:4926$722 + attribute \src "ls180.v:5024.353-5024.425" + cell $xor $xor$ls180.v:5024$837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260233,10 +262578,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4926$722_Y + connect \Y $xor$ls180.v:5024$837_Y end - attribute \src "ls180.v:4926.200-4926.272" - cell $xor $xor$ls180.v:4926$723 + attribute \src "ls180.v:5024.200-5024.272" + cell $xor $xor$ls180.v:5024$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260244,21 +262589,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4926$723_Y + connect \Y $xor$ls180.v:5024$838_Y end - attribute \src "ls180.v:4926.160-4926.273" - cell $xor $xor$ls180.v:4926$724 + attribute \src "ls180.v:5024.160-5024.273" + cell $xor $xor$ls180.v:5024$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:4926$723_Y - connect \Y $xor$ls180.v:4926$724_Y + connect \B $xor$ls180.v:5024$838_Y + connect \Y $xor$ls180.v:5024$839_Y end - attribute \src "ls180.v:4927.353-4927.425" - cell $xor $xor$ls180.v:4927$725 + attribute \src "ls180.v:5025.353-5025.425" + cell $xor $xor$ls180.v:5025$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260266,10 +262611,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4927$725_Y + connect \Y $xor$ls180.v:5025$840_Y end - attribute \src "ls180.v:4927.200-4927.272" - cell $xor $xor$ls180.v:4927$726 + attribute \src "ls180.v:5025.200-5025.272" + cell $xor $xor$ls180.v:5025$841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260277,21 +262622,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4927$726_Y + connect \Y $xor$ls180.v:5025$841_Y end - attribute \src "ls180.v:4927.160-4927.273" - cell $xor $xor$ls180.v:4927$727 + attribute \src "ls180.v:5025.160-5025.273" + cell $xor $xor$ls180.v:5025$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:4927$726_Y - connect \Y $xor$ls180.v:4927$727_Y + connect \B $xor$ls180.v:5025$841_Y + connect \Y $xor$ls180.v:5025$842_Y end - attribute \src "ls180.v:4928.353-4928.425" - cell $xor $xor$ls180.v:4928$728 + attribute \src "ls180.v:5026.353-5026.425" + cell $xor $xor$ls180.v:5026$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260299,10 +262644,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4928$728_Y + connect \Y $xor$ls180.v:5026$843_Y end - attribute \src "ls180.v:4928.200-4928.272" - cell $xor $xor$ls180.v:4928$729 + attribute \src "ls180.v:5026.200-5026.272" + cell $xor $xor$ls180.v:5026$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260310,21 +262655,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4928$729_Y + connect \Y $xor$ls180.v:5026$844_Y end - attribute \src "ls180.v:4928.160-4928.273" - cell $xor $xor$ls180.v:4928$730 + attribute \src "ls180.v:5026.160-5026.273" + cell $xor $xor$ls180.v:5026$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:4928$729_Y - connect \Y $xor$ls180.v:4928$730_Y + connect \B $xor$ls180.v:5026$844_Y + connect \Y $xor$ls180.v:5026$845_Y end - attribute \src "ls180.v:4929.353-4929.425" - cell $xor $xor$ls180.v:4929$731 + attribute \src "ls180.v:5027.353-5027.425" + cell $xor $xor$ls180.v:5027$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260332,10 +262677,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4929$731_Y + connect \Y $xor$ls180.v:5027$846_Y end - attribute \src "ls180.v:4929.200-4929.272" - cell $xor $xor$ls180.v:4929$732 + attribute \src "ls180.v:5027.200-5027.272" + cell $xor $xor$ls180.v:5027$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260343,21 +262688,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4929$732_Y + connect \Y $xor$ls180.v:5027$847_Y end - attribute \src "ls180.v:4929.160-4929.273" - cell $xor $xor$ls180.v:4929$733 + attribute \src "ls180.v:5027.160-5027.273" + cell $xor $xor$ls180.v:5027$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:4929$732_Y - connect \Y $xor$ls180.v:4929$733_Y + connect \B $xor$ls180.v:5027$847_Y + connect \Y $xor$ls180.v:5027$848_Y end - attribute \src "ls180.v:4930.353-4930.425" - cell $xor $xor$ls180.v:4930$734 + attribute \src "ls180.v:5028.353-5028.425" + cell $xor $xor$ls180.v:5028$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260365,10 +262710,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4930$734_Y + connect \Y $xor$ls180.v:5028$849_Y end - attribute \src "ls180.v:4930.200-4930.272" - cell $xor $xor$ls180.v:4930$735 + attribute \src "ls180.v:5028.200-5028.272" + cell $xor $xor$ls180.v:5028$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260376,21 +262721,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4930$735_Y + connect \Y $xor$ls180.v:5028$850_Y end - attribute \src "ls180.v:4930.160-4930.273" - cell $xor $xor$ls180.v:4930$736 + attribute \src "ls180.v:5028.160-5028.273" + cell $xor $xor$ls180.v:5028$851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:4930$735_Y - connect \Y $xor$ls180.v:4930$736_Y + connect \B $xor$ls180.v:5028$850_Y + connect \Y $xor$ls180.v:5028$851_Y end - attribute \src "ls180.v:4931.354-4931.426" - cell $xor $xor$ls180.v:4931$737 + attribute \src "ls180.v:5029.354-5029.426" + cell $xor $xor$ls180.v:5029$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260398,10 +262743,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4931$737_Y + connect \Y $xor$ls180.v:5029$852_Y end - attribute \src "ls180.v:4931.201-4931.273" - cell $xor $xor$ls180.v:4931$738 + attribute \src "ls180.v:5029.201-5029.273" + cell $xor $xor$ls180.v:5029$853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260409,21 +262754,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4931$738_Y + connect \Y $xor$ls180.v:5029$853_Y end - attribute \src "ls180.v:4931.161-4931.274" - cell $xor $xor$ls180.v:4931$739 + attribute \src "ls180.v:5029.161-5029.274" + cell $xor $xor$ls180.v:5029$854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:4931$738_Y - connect \Y $xor$ls180.v:4931$739_Y + connect \B $xor$ls180.v:5029$853_Y + connect \Y $xor$ls180.v:5029$854_Y end - attribute \src "ls180.v:4932.361-4932.434" - cell $xor $xor$ls180.v:4932$740 + attribute \src "ls180.v:5030.361-5030.434" + cell $xor $xor$ls180.v:5030$855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260431,10 +262776,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4932$740_Y + connect \Y $xor$ls180.v:5030$855_Y end - attribute \src "ls180.v:4932.205-4932.278" - cell $xor $xor$ls180.v:4932$741 + attribute \src "ls180.v:5030.205-5030.278" + cell $xor $xor$ls180.v:5030$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260442,21 +262787,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4932$741_Y + connect \Y $xor$ls180.v:5030$856_Y end - attribute \src "ls180.v:4932.164-4932.279" - cell $xor $xor$ls180.v:4932$742 + attribute \src "ls180.v:5030.164-5030.279" + cell $xor $xor$ls180.v:5030$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:4932$741_Y - connect \Y $xor$ls180.v:4932$742_Y + connect \B $xor$ls180.v:5030$856_Y + connect \Y $xor$ls180.v:5030$857_Y end - attribute \src "ls180.v:4933.361-4933.434" - cell $xor $xor$ls180.v:4933$743 + attribute \src "ls180.v:5031.361-5031.434" + cell $xor $xor$ls180.v:5031$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260464,10 +262809,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4933$743_Y + connect \Y $xor$ls180.v:5031$858_Y end - attribute \src "ls180.v:4933.205-4933.278" - cell $xor $xor$ls180.v:4933$744 + attribute \src "ls180.v:5031.205-5031.278" + cell $xor $xor$ls180.v:5031$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260475,21 +262820,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4933$744_Y + connect \Y $xor$ls180.v:5031$859_Y end - attribute \src "ls180.v:4933.164-4933.279" - cell $xor $xor$ls180.v:4933$745 + attribute \src "ls180.v:5031.164-5031.279" + cell $xor $xor$ls180.v:5031$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:4933$744_Y - connect \Y $xor$ls180.v:4933$745_Y + connect \B $xor$ls180.v:5031$859_Y + connect \Y $xor$ls180.v:5031$860_Y end - attribute \src "ls180.v:4934.361-4934.434" - cell $xor $xor$ls180.v:4934$746 + attribute \src "ls180.v:5032.361-5032.434" + cell $xor $xor$ls180.v:5032$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260497,10 +262842,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4934$746_Y + connect \Y $xor$ls180.v:5032$861_Y end - attribute \src "ls180.v:4934.205-4934.278" - cell $xor $xor$ls180.v:4934$747 + attribute \src "ls180.v:5032.205-5032.278" + cell $xor $xor$ls180.v:5032$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260508,21 +262853,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4934$747_Y + connect \Y $xor$ls180.v:5032$862_Y end - attribute \src "ls180.v:4934.164-4934.279" - cell $xor $xor$ls180.v:4934$748 + attribute \src "ls180.v:5032.164-5032.279" + cell $xor $xor$ls180.v:5032$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:4934$747_Y - connect \Y $xor$ls180.v:4934$748_Y + connect \B $xor$ls180.v:5032$862_Y + connect \Y $xor$ls180.v:5032$863_Y end - attribute \src "ls180.v:4935.361-4935.434" - cell $xor $xor$ls180.v:4935$749 + attribute \src "ls180.v:5033.361-5033.434" + cell $xor $xor$ls180.v:5033$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260530,10 +262875,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4935$749_Y + connect \Y $xor$ls180.v:5033$864_Y end - attribute \src "ls180.v:4935.205-4935.278" - cell $xor $xor$ls180.v:4935$750 + attribute \src "ls180.v:5033.205-5033.278" + cell $xor $xor$ls180.v:5033$865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260541,21 +262886,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4935$750_Y + connect \Y $xor$ls180.v:5033$865_Y end - attribute \src "ls180.v:4935.164-4935.279" - cell $xor $xor$ls180.v:4935$751 + attribute \src "ls180.v:5033.164-5033.279" + cell $xor $xor$ls180.v:5033$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:4935$750_Y - connect \Y $xor$ls180.v:4935$751_Y + connect \B $xor$ls180.v:5033$865_Y + connect \Y $xor$ls180.v:5033$866_Y end - attribute \src "ls180.v:4936.361-4936.434" - cell $xor $xor$ls180.v:4936$752 + attribute \src "ls180.v:5034.361-5034.434" + cell $xor $xor$ls180.v:5034$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260563,10 +262908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4936$752_Y + connect \Y $xor$ls180.v:5034$867_Y end - attribute \src "ls180.v:4936.205-4936.278" - cell $xor $xor$ls180.v:4936$753 + attribute \src "ls180.v:5034.205-5034.278" + cell $xor $xor$ls180.v:5034$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260574,21 +262919,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4936$753_Y + connect \Y $xor$ls180.v:5034$868_Y end - attribute \src "ls180.v:4936.164-4936.279" - cell $xor $xor$ls180.v:4936$754 + attribute \src "ls180.v:5034.164-5034.279" + cell $xor $xor$ls180.v:5034$869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:4936$753_Y - connect \Y $xor$ls180.v:4936$754_Y + connect \B $xor$ls180.v:5034$868_Y + connect \Y $xor$ls180.v:5034$869_Y end - attribute \src "ls180.v:4937.361-4937.434" - cell $xor $xor$ls180.v:4937$755 + attribute \src "ls180.v:5035.361-5035.434" + cell $xor $xor$ls180.v:5035$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260596,10 +262941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4937$755_Y + connect \Y $xor$ls180.v:5035$870_Y end - attribute \src "ls180.v:4937.205-4937.278" - cell $xor $xor$ls180.v:4937$756 + attribute \src "ls180.v:5035.205-5035.278" + cell $xor $xor$ls180.v:5035$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260607,21 +262952,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4937$756_Y + connect \Y $xor$ls180.v:5035$871_Y end - attribute \src "ls180.v:4937.164-4937.279" - cell $xor $xor$ls180.v:4937$757 + attribute \src "ls180.v:5035.164-5035.279" + cell $xor $xor$ls180.v:5035$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:4937$756_Y - connect \Y $xor$ls180.v:4937$757_Y + connect \B $xor$ls180.v:5035$871_Y + connect \Y $xor$ls180.v:5035$872_Y end - attribute \src "ls180.v:4938.361-4938.434" - cell $xor $xor$ls180.v:4938$758 + attribute \src "ls180.v:5036.361-5036.434" + cell $xor $xor$ls180.v:5036$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260629,10 +262974,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4938$758_Y + connect \Y $xor$ls180.v:5036$873_Y end - attribute \src "ls180.v:4938.205-4938.278" - cell $xor $xor$ls180.v:4938$759 + attribute \src "ls180.v:5036.205-5036.278" + cell $xor $xor$ls180.v:5036$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260640,21 +262985,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4938$759_Y + connect \Y $xor$ls180.v:5036$874_Y end - attribute \src "ls180.v:4938.164-4938.279" - cell $xor $xor$ls180.v:4938$760 + attribute \src "ls180.v:5036.164-5036.279" + cell $xor $xor$ls180.v:5036$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:4938$759_Y - connect \Y $xor$ls180.v:4938$760_Y + connect \B $xor$ls180.v:5036$874_Y + connect \Y $xor$ls180.v:5036$875_Y end - attribute \src "ls180.v:4939.361-4939.434" - cell $xor $xor$ls180.v:4939$761 + attribute \src "ls180.v:5037.361-5037.434" + cell $xor $xor$ls180.v:5037$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260662,10 +263007,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4939$761_Y + connect \Y $xor$ls180.v:5037$876_Y end - attribute \src "ls180.v:4939.205-4939.278" - cell $xor $xor$ls180.v:4939$762 + attribute \src "ls180.v:5037.205-5037.278" + cell $xor $xor$ls180.v:5037$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260673,21 +263018,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4939$762_Y + connect \Y $xor$ls180.v:5037$877_Y end - attribute \src "ls180.v:4939.164-4939.279" - cell $xor $xor$ls180.v:4939$763 + attribute \src "ls180.v:5037.164-5037.279" + cell $xor $xor$ls180.v:5037$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:4939$762_Y - connect \Y $xor$ls180.v:4939$763_Y + connect \B $xor$ls180.v:5037$877_Y + connect \Y $xor$ls180.v:5037$878_Y end - attribute \src "ls180.v:4940.361-4940.434" - cell $xor $xor$ls180.v:4940$764 + attribute \src "ls180.v:5038.361-5038.434" + cell $xor $xor$ls180.v:5038$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260695,10 +263040,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4940$764_Y + connect \Y $xor$ls180.v:5038$879_Y end - attribute \src "ls180.v:4940.205-4940.278" - cell $xor $xor$ls180.v:4940$765 + attribute \src "ls180.v:5038.205-5038.278" + cell $xor $xor$ls180.v:5038$880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260706,21 +263051,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4940$765_Y + connect \Y $xor$ls180.v:5038$880_Y end - attribute \src "ls180.v:4940.164-4940.279" - cell $xor $xor$ls180.v:4940$766 + attribute \src "ls180.v:5038.164-5038.279" + cell $xor $xor$ls180.v:5038$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:4940$765_Y - connect \Y $xor$ls180.v:4940$766_Y + connect \B $xor$ls180.v:5038$880_Y + connect \Y $xor$ls180.v:5038$881_Y end - attribute \src "ls180.v:4941.361-4941.434" - cell $xor $xor$ls180.v:4941$767 + attribute \src "ls180.v:5039.361-5039.434" + cell $xor $xor$ls180.v:5039$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260728,10 +263073,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4941$767_Y + connect \Y $xor$ls180.v:5039$882_Y end - attribute \src "ls180.v:4941.205-4941.278" - cell $xor $xor$ls180.v:4941$768 + attribute \src "ls180.v:5039.205-5039.278" + cell $xor $xor$ls180.v:5039$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260739,21 +263084,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4941$768_Y + connect \Y $xor$ls180.v:5039$883_Y end - attribute \src "ls180.v:4941.164-4941.279" - cell $xor $xor$ls180.v:4941$769 + attribute \src "ls180.v:5039.164-5039.279" + cell $xor $xor$ls180.v:5039$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:4941$768_Y - connect \Y $xor$ls180.v:4941$769_Y + connect \B $xor$ls180.v:5039$883_Y + connect \Y $xor$ls180.v:5039$884_Y end - attribute \src "ls180.v:4942.361-4942.434" - cell $xor $xor$ls180.v:4942$770 + attribute \src "ls180.v:5040.361-5040.434" + cell $xor $xor$ls180.v:5040$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260761,10 +263106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4942$770_Y + connect \Y $xor$ls180.v:5040$885_Y end - attribute \src "ls180.v:4942.205-4942.278" - cell $xor $xor$ls180.v:4942$771 + attribute \src "ls180.v:5040.205-5040.278" + cell $xor $xor$ls180.v:5040$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260772,21 +263117,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4942$771_Y + connect \Y $xor$ls180.v:5040$886_Y end - attribute \src "ls180.v:4942.164-4942.279" - cell $xor $xor$ls180.v:4942$772 + attribute \src "ls180.v:5040.164-5040.279" + cell $xor $xor$ls180.v:5040$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:4942$771_Y - connect \Y $xor$ls180.v:4942$772_Y + connect \B $xor$ls180.v:5040$886_Y + connect \Y $xor$ls180.v:5040$887_Y end - attribute \src "ls180.v:4943.361-4943.434" - cell $xor $xor$ls180.v:4943$773 + attribute \src "ls180.v:5041.361-5041.434" + cell $xor $xor$ls180.v:5041$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260794,10 +263139,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4943$773_Y + connect \Y $xor$ls180.v:5041$888_Y end - attribute \src "ls180.v:4943.205-4943.278" - cell $xor $xor$ls180.v:4943$774 + attribute \src "ls180.v:5041.205-5041.278" + cell $xor $xor$ls180.v:5041$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260805,21 +263150,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4943$774_Y + connect \Y $xor$ls180.v:5041$889_Y end - attribute \src "ls180.v:4943.164-4943.279" - cell $xor $xor$ls180.v:4943$775 + attribute \src "ls180.v:5041.164-5041.279" + cell $xor $xor$ls180.v:5041$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:4943$774_Y - connect \Y $xor$ls180.v:4943$775_Y + connect \B $xor$ls180.v:5041$889_Y + connect \Y $xor$ls180.v:5041$890_Y end - attribute \src "ls180.v:4944.361-4944.434" - cell $xor $xor$ls180.v:4944$776 + attribute \src "ls180.v:5042.361-5042.434" + cell $xor $xor$ls180.v:5042$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260827,10 +263172,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4944$776_Y + connect \Y $xor$ls180.v:5042$891_Y end - attribute \src "ls180.v:4944.205-4944.278" - cell $xor $xor$ls180.v:4944$777 + attribute \src "ls180.v:5042.205-5042.278" + cell $xor $xor$ls180.v:5042$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260838,21 +263183,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4944$777_Y + connect \Y $xor$ls180.v:5042$892_Y end - attribute \src "ls180.v:4944.164-4944.279" - cell $xor $xor$ls180.v:4944$778 + attribute \src "ls180.v:5042.164-5042.279" + cell $xor $xor$ls180.v:5042$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:4944$777_Y - connect \Y $xor$ls180.v:4944$778_Y + connect \B $xor$ls180.v:5042$892_Y + connect \Y $xor$ls180.v:5042$893_Y end - attribute \src "ls180.v:4945.361-4945.434" - cell $xor $xor$ls180.v:4945$779 + attribute \src "ls180.v:5043.361-5043.434" + cell $xor $xor$ls180.v:5043$894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260860,10 +263205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4945$779_Y + connect \Y $xor$ls180.v:5043$894_Y end - attribute \src "ls180.v:4945.205-4945.278" - cell $xor $xor$ls180.v:4945$780 + attribute \src "ls180.v:5043.205-5043.278" + cell $xor $xor$ls180.v:5043$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260871,21 +263216,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4945$780_Y + connect \Y $xor$ls180.v:5043$895_Y end - attribute \src "ls180.v:4945.164-4945.279" - cell $xor $xor$ls180.v:4945$781 + attribute \src "ls180.v:5043.164-5043.279" + cell $xor $xor$ls180.v:5043$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:4945$780_Y - connect \Y $xor$ls180.v:4945$781_Y + connect \B $xor$ls180.v:5043$895_Y + connect \Y $xor$ls180.v:5043$896_Y end - attribute \src "ls180.v:4946.361-4946.434" - cell $xor $xor$ls180.v:4946$782 + attribute \src "ls180.v:5044.361-5044.434" + cell $xor $xor$ls180.v:5044$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260893,10 +263238,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4946$782_Y + connect \Y $xor$ls180.v:5044$897_Y end - attribute \src "ls180.v:4946.205-4946.278" - cell $xor $xor$ls180.v:4946$783 + attribute \src "ls180.v:5044.205-5044.278" + cell $xor $xor$ls180.v:5044$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260904,21 +263249,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4946$783_Y + connect \Y $xor$ls180.v:5044$898_Y end - attribute \src "ls180.v:4946.164-4946.279" - cell $xor $xor$ls180.v:4946$784 + attribute \src "ls180.v:5044.164-5044.279" + cell $xor $xor$ls180.v:5044$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:4946$783_Y - connect \Y $xor$ls180.v:4946$784_Y + connect \B $xor$ls180.v:5044$898_Y + connect \Y $xor$ls180.v:5044$899_Y end - attribute \src "ls180.v:4947.361-4947.434" - cell $xor $xor$ls180.v:4947$785 + attribute \src "ls180.v:5045.361-5045.434" + cell $xor $xor$ls180.v:5045$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260926,10 +263271,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4947$785_Y + connect \Y $xor$ls180.v:5045$900_Y end - attribute \src "ls180.v:4947.205-4947.278" - cell $xor $xor$ls180.v:4947$786 + attribute \src "ls180.v:5045.205-5045.278" + cell $xor $xor$ls180.v:5045$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260937,21 +263282,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4947$786_Y + connect \Y $xor$ls180.v:5045$901_Y end - attribute \src "ls180.v:4947.164-4947.279" - cell $xor $xor$ls180.v:4947$787 + attribute \src "ls180.v:5045.164-5045.279" + cell $xor $xor$ls180.v:5045$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:4947$786_Y - connect \Y $xor$ls180.v:4947$787_Y + connect \B $xor$ls180.v:5045$901_Y + connect \Y $xor$ls180.v:5045$902_Y end - attribute \src "ls180.v:4948.361-4948.434" - cell $xor $xor$ls180.v:4948$788 + attribute \src "ls180.v:5046.361-5046.434" + cell $xor $xor$ls180.v:5046$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260959,10 +263304,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4948$788_Y + connect \Y $xor$ls180.v:5046$903_Y end - attribute \src "ls180.v:4948.205-4948.278" - cell $xor $xor$ls180.v:4948$789 + attribute \src "ls180.v:5046.205-5046.278" + cell $xor $xor$ls180.v:5046$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260970,21 +263315,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4948$789_Y + connect \Y $xor$ls180.v:5046$904_Y end - attribute \src "ls180.v:4948.164-4948.279" - cell $xor $xor$ls180.v:4948$790 + attribute \src "ls180.v:5046.164-5046.279" + cell $xor $xor$ls180.v:5046$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:4948$789_Y - connect \Y $xor$ls180.v:4948$790_Y + connect \B $xor$ls180.v:5046$904_Y + connect \Y $xor$ls180.v:5046$905_Y end - attribute \src "ls180.v:4949.361-4949.434" - cell $xor $xor$ls180.v:4949$791 + attribute \src "ls180.v:5047.361-5047.434" + cell $xor $xor$ls180.v:5047$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260992,10 +263337,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4949$791_Y + connect \Y $xor$ls180.v:5047$906_Y end - attribute \src "ls180.v:4949.205-4949.278" - cell $xor $xor$ls180.v:4949$792 + attribute \src "ls180.v:5047.205-5047.278" + cell $xor $xor$ls180.v:5047$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261003,21 +263348,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4949$792_Y + connect \Y $xor$ls180.v:5047$907_Y end - attribute \src "ls180.v:4949.164-4949.279" - cell $xor $xor$ls180.v:4949$793 + attribute \src "ls180.v:5047.164-5047.279" + cell $xor $xor$ls180.v:5047$908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:4949$792_Y - connect \Y $xor$ls180.v:4949$793_Y + connect \B $xor$ls180.v:5047$907_Y + connect \Y $xor$ls180.v:5047$908_Y end - attribute \src "ls180.v:4950.361-4950.434" - cell $xor $xor$ls180.v:4950$794 + attribute \src "ls180.v:5048.361-5048.434" + cell $xor $xor$ls180.v:5048$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261025,10 +263370,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4950$794_Y + connect \Y $xor$ls180.v:5048$909_Y end - attribute \src "ls180.v:4950.205-4950.278" - cell $xor $xor$ls180.v:4950$795 + attribute \src "ls180.v:5048.205-5048.278" + cell $xor $xor$ls180.v:5048$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261036,21 +263381,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4950$795_Y + connect \Y $xor$ls180.v:5048$910_Y end - attribute \src "ls180.v:4950.164-4950.279" - cell $xor $xor$ls180.v:4950$796 + attribute \src "ls180.v:5048.164-5048.279" + cell $xor $xor$ls180.v:5048$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:4950$795_Y - connect \Y $xor$ls180.v:4950$796_Y + connect \B $xor$ls180.v:5048$910_Y + connect \Y $xor$ls180.v:5048$911_Y end - attribute \src "ls180.v:4951.361-4951.434" - cell $xor $xor$ls180.v:4951$797 + attribute \src "ls180.v:5049.361-5049.434" + cell $xor $xor$ls180.v:5049$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261058,10 +263403,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4951$797_Y + connect \Y $xor$ls180.v:5049$912_Y end - attribute \src "ls180.v:4951.205-4951.278" - cell $xor $xor$ls180.v:4951$798 + attribute \src "ls180.v:5049.205-5049.278" + cell $xor $xor$ls180.v:5049$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261069,21 +263414,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4951$798_Y + connect \Y $xor$ls180.v:5049$913_Y end - attribute \src "ls180.v:4951.164-4951.279" - cell $xor $xor$ls180.v:4951$799 + attribute \src "ls180.v:5049.164-5049.279" + cell $xor $xor$ls180.v:5049$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:4951$798_Y - connect \Y $xor$ls180.v:4951$799_Y + connect \B $xor$ls180.v:5049$913_Y + connect \Y $xor$ls180.v:5049$914_Y end - attribute \src "ls180.v:4952.360-4952.432" - cell $xor $xor$ls180.v:4952$800 + attribute \src "ls180.v:5050.360-5050.432" + cell $xor $xor$ls180.v:5050$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261091,10 +263436,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4952$800_Y + connect \Y $xor$ls180.v:5050$915_Y end - attribute \src "ls180.v:4952.205-4952.277" - cell $xor $xor$ls180.v:4952$801 + attribute \src "ls180.v:5050.205-5050.277" + cell $xor $xor$ls180.v:5050$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261102,21 +263447,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4952$801_Y + connect \Y $xor$ls180.v:5050$916_Y end - attribute \src "ls180.v:4952.164-4952.278" - cell $xor $xor$ls180.v:4952$802 + attribute \src "ls180.v:5050.164-5050.278" + cell $xor $xor$ls180.v:5050$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:4952$801_Y - connect \Y $xor$ls180.v:4952$802_Y + connect \B $xor$ls180.v:5050$916_Y + connect \Y $xor$ls180.v:5050$917_Y end - attribute \src "ls180.v:4953.360-4953.432" - cell $xor $xor$ls180.v:4953$803 + attribute \src "ls180.v:5051.360-5051.432" + cell $xor $xor$ls180.v:5051$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261124,10 +263469,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4953$803_Y + connect \Y $xor$ls180.v:5051$918_Y end - attribute \src "ls180.v:4953.205-4953.277" - cell $xor $xor$ls180.v:4953$804 + attribute \src "ls180.v:5051.205-5051.277" + cell $xor $xor$ls180.v:5051$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261135,21 +263480,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4953$804_Y + connect \Y $xor$ls180.v:5051$919_Y end - attribute \src "ls180.v:4953.164-4953.278" - cell $xor $xor$ls180.v:4953$805 + attribute \src "ls180.v:5051.164-5051.278" + cell $xor $xor$ls180.v:5051$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:4953$804_Y - connect \Y $xor$ls180.v:4953$805_Y + connect \B $xor$ls180.v:5051$919_Y + connect \Y $xor$ls180.v:5051$920_Y end - attribute \src "ls180.v:4954.360-4954.432" - cell $xor $xor$ls180.v:4954$806 + attribute \src "ls180.v:5052.360-5052.432" + cell $xor $xor$ls180.v:5052$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261157,10 +263502,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4954$806_Y + connect \Y $xor$ls180.v:5052$921_Y end - attribute \src "ls180.v:4954.205-4954.277" - cell $xor $xor$ls180.v:4954$807 + attribute \src "ls180.v:5052.205-5052.277" + cell $xor $xor$ls180.v:5052$922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261168,21 +263513,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4954$807_Y + connect \Y $xor$ls180.v:5052$922_Y end - attribute \src "ls180.v:4954.164-4954.278" - cell $xor $xor$ls180.v:4954$808 + attribute \src "ls180.v:5052.164-5052.278" + cell $xor $xor$ls180.v:5052$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:4954$807_Y - connect \Y $xor$ls180.v:4954$808_Y + connect \B $xor$ls180.v:5052$922_Y + connect \Y $xor$ls180.v:5052$923_Y end - attribute \src "ls180.v:4955.360-4955.432" - cell $xor $xor$ls180.v:4955$809 + attribute \src "ls180.v:5053.360-5053.432" + cell $xor $xor$ls180.v:5053$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261190,10 +263535,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4955$809_Y + connect \Y $xor$ls180.v:5053$924_Y end - attribute \src "ls180.v:4955.205-4955.277" - cell $xor $xor$ls180.v:4955$810 + attribute \src "ls180.v:5053.205-5053.277" + cell $xor $xor$ls180.v:5053$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261201,21 +263546,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4955$810_Y + connect \Y $xor$ls180.v:5053$925_Y end - attribute \src "ls180.v:4955.164-4955.278" - cell $xor $xor$ls180.v:4955$811 + attribute \src "ls180.v:5053.164-5053.278" + cell $xor $xor$ls180.v:5053$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:4955$810_Y - connect \Y $xor$ls180.v:4955$811_Y + connect \B $xor$ls180.v:5053$925_Y + connect \Y $xor$ls180.v:5053$926_Y end - attribute \src "ls180.v:4956.360-4956.432" - cell $xor $xor$ls180.v:4956$812 + attribute \src "ls180.v:5054.360-5054.432" + cell $xor $xor$ls180.v:5054$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261223,10 +263568,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4956$812_Y + connect \Y $xor$ls180.v:5054$927_Y end - attribute \src "ls180.v:4956.205-4956.277" - cell $xor $xor$ls180.v:4956$813 + attribute \src "ls180.v:5054.205-5054.277" + cell $xor $xor$ls180.v:5054$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261234,21 +263579,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4956$813_Y + connect \Y $xor$ls180.v:5054$928_Y end - attribute \src "ls180.v:4956.164-4956.278" - cell $xor $xor$ls180.v:4956$814 + attribute \src "ls180.v:5054.164-5054.278" + cell $xor $xor$ls180.v:5054$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:4956$813_Y - connect \Y $xor$ls180.v:4956$814_Y + connect \B $xor$ls180.v:5054$928_Y + connect \Y $xor$ls180.v:5054$929_Y end - attribute \src "ls180.v:4957.360-4957.432" - cell $xor $xor$ls180.v:4957$815 + attribute \src "ls180.v:5055.360-5055.432" + cell $xor $xor$ls180.v:5055$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261256,10 +263601,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4957$815_Y + connect \Y $xor$ls180.v:5055$930_Y end - attribute \src "ls180.v:4957.205-4957.277" - cell $xor $xor$ls180.v:4957$816 + attribute \src "ls180.v:5055.205-5055.277" + cell $xor $xor$ls180.v:5055$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261267,21 +263612,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4957$816_Y + connect \Y $xor$ls180.v:5055$931_Y end - attribute \src "ls180.v:4957.164-4957.278" - cell $xor $xor$ls180.v:4957$817 + attribute \src "ls180.v:5055.164-5055.278" + cell $xor $xor$ls180.v:5055$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:4957$816_Y - connect \Y $xor$ls180.v:4957$817_Y + connect \B $xor$ls180.v:5055$931_Y + connect \Y $xor$ls180.v:5055$932_Y end - attribute \src "ls180.v:4958.360-4958.432" - cell $xor $xor$ls180.v:4958$818 + attribute \src "ls180.v:5056.360-5056.432" + cell $xor $xor$ls180.v:5056$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261289,10 +263634,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4958$818_Y + connect \Y $xor$ls180.v:5056$933_Y end - attribute \src "ls180.v:4958.205-4958.277" - cell $xor $xor$ls180.v:4958$819 + attribute \src "ls180.v:5056.205-5056.277" + cell $xor $xor$ls180.v:5056$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261300,21 +263645,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4958$819_Y + connect \Y $xor$ls180.v:5056$934_Y end - attribute \src "ls180.v:4958.164-4958.278" - cell $xor $xor$ls180.v:4958$820 + attribute \src "ls180.v:5056.164-5056.278" + cell $xor $xor$ls180.v:5056$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:4958$819_Y - connect \Y $xor$ls180.v:4958$820_Y + connect \B $xor$ls180.v:5056$934_Y + connect \Y $xor$ls180.v:5056$935_Y end - attribute \src "ls180.v:4959.360-4959.432" - cell $xor $xor$ls180.v:4959$821 + attribute \src "ls180.v:5057.360-5057.432" + cell $xor $xor$ls180.v:5057$936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261322,10 +263667,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4959$821_Y + connect \Y $xor$ls180.v:5057$936_Y end - attribute \src "ls180.v:4959.205-4959.277" - cell $xor $xor$ls180.v:4959$822 + attribute \src "ls180.v:5057.205-5057.277" + cell $xor $xor$ls180.v:5057$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261333,21 +263678,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4959$822_Y + connect \Y $xor$ls180.v:5057$937_Y end - attribute \src "ls180.v:4959.164-4959.278" - cell $xor $xor$ls180.v:4959$823 + attribute \src "ls180.v:5057.164-5057.278" + cell $xor $xor$ls180.v:5057$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:4959$822_Y - connect \Y $xor$ls180.v:4959$823_Y + connect \B $xor$ls180.v:5057$937_Y + connect \Y $xor$ls180.v:5057$938_Y end - attribute \src "ls180.v:4960.360-4960.432" - cell $xor $xor$ls180.v:4960$824 + attribute \src "ls180.v:5058.360-5058.432" + cell $xor $xor$ls180.v:5058$939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261355,10 +263700,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4960$824_Y + connect \Y $xor$ls180.v:5058$939_Y end - attribute \src "ls180.v:4960.205-4960.277" - cell $xor $xor$ls180.v:4960$825 + attribute \src "ls180.v:5058.205-5058.277" + cell $xor $xor$ls180.v:5058$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261366,21 +263711,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4960$825_Y + connect \Y $xor$ls180.v:5058$940_Y end - attribute \src "ls180.v:4960.164-4960.278" - cell $xor $xor$ls180.v:4960$826 + attribute \src "ls180.v:5058.164-5058.278" + cell $xor $xor$ls180.v:5058$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:4960$825_Y - connect \Y $xor$ls180.v:4960$826_Y + connect \B $xor$ls180.v:5058$940_Y + connect \Y $xor$ls180.v:5058$941_Y end - attribute \src "ls180.v:4961.360-4961.432" - cell $xor $xor$ls180.v:4961$827 + attribute \src "ls180.v:5059.360-5059.432" + cell $xor $xor$ls180.v:5059$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261388,10 +263733,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4961$827_Y + connect \Y $xor$ls180.v:5059$942_Y end - attribute \src "ls180.v:4961.205-4961.277" - cell $xor $xor$ls180.v:4961$828 + attribute \src "ls180.v:5059.205-5059.277" + cell $xor $xor$ls180.v:5059$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261399,21 +263744,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4961$828_Y + connect \Y $xor$ls180.v:5059$943_Y end - attribute \src "ls180.v:4961.164-4961.278" - cell $xor $xor$ls180.v:4961$829 + attribute \src "ls180.v:5059.164-5059.278" + cell $xor $xor$ls180.v:5059$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:4961$828_Y - connect \Y $xor$ls180.v:4961$829_Y + connect \B $xor$ls180.v:5059$943_Y + connect \Y $xor$ls180.v:5059$944_Y end - attribute \src "ls180.v:4982.899-4982.983" - cell $xor $xor$ls180.v:4982$843 + attribute \src "ls180.v:5080.899-5080.983" + cell $xor $xor$ls180.v:5080$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261421,10 +263766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4982$843_Y + connect \Y $xor$ls180.v:5080$958_Y end - attribute \src "ls180.v:4982.634-4982.718" - cell $xor $xor$ls180.v:4982$844 + attribute \src "ls180.v:5080.634-5080.718" + cell $xor $xor$ls180.v:5080$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261432,21 +263777,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4982$844_Y + connect \Y $xor$ls180.v:5080$959_Y end - attribute \src "ls180.v:4982.588-4982.719" - cell $xor $xor$ls180.v:4982$845 + attribute \src "ls180.v:5080.588-5080.719" + cell $xor $xor$ls180.v:5080$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:4982$844_Y - connect \Y $xor$ls180.v:4982$845_Y + connect \B $xor$ls180.v:5080$959_Y + connect \Y $xor$ls180.v:5080$960_Y end - attribute \src "ls180.v:4982.234-4982.318" - cell $xor $xor$ls180.v:4982$846 + attribute \src "ls180.v:5080.234-5080.318" + cell $xor $xor$ls180.v:5080$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261454,21 +263799,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4982$846_Y + connect \Y $xor$ls180.v:5080$961_Y end - attribute \src "ls180.v:4982.187-4982.319" - cell $xor $xor$ls180.v:4982$847 + attribute \src "ls180.v:5080.187-5080.319" + cell $xor $xor$ls180.v:5080$962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:4982$846_Y - connect \Y $xor$ls180.v:4982$847_Y + connect \B $xor$ls180.v:5080$961_Y + connect \Y $xor$ls180.v:5080$962_Y end - attribute \src "ls180.v:4983.899-4983.983" - cell $xor $xor$ls180.v:4983$848 + attribute \src "ls180.v:5081.899-5081.983" + cell $xor $xor$ls180.v:5081$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261476,10 +263821,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4983$848_Y + connect \Y $xor$ls180.v:5081$963_Y end - attribute \src "ls180.v:4983.634-4983.718" - cell $xor $xor$ls180.v:4983$849 + attribute \src "ls180.v:5081.634-5081.718" + cell $xor $xor$ls180.v:5081$964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261487,21 +263832,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4983$849_Y + connect \Y $xor$ls180.v:5081$964_Y end - attribute \src "ls180.v:4983.588-4983.719" - cell $xor $xor$ls180.v:4983$850 + attribute \src "ls180.v:5081.588-5081.719" + cell $xor $xor$ls180.v:5081$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:4983$849_Y - connect \Y $xor$ls180.v:4983$850_Y + connect \B $xor$ls180.v:5081$964_Y + connect \Y $xor$ls180.v:5081$965_Y end - attribute \src "ls180.v:4983.234-4983.318" - cell $xor $xor$ls180.v:4983$851 + attribute \src "ls180.v:5081.234-5081.318" + cell $xor $xor$ls180.v:5081$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261509,21 +263854,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4983$851_Y + connect \Y $xor$ls180.v:5081$966_Y end - attribute \src "ls180.v:4983.187-4983.319" - cell $xor $xor$ls180.v:4983$852 + attribute \src "ls180.v:5081.187-5081.319" + cell $xor $xor$ls180.v:5081$967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:4983$851_Y - connect \Y $xor$ls180.v:4983$852_Y + connect \B $xor$ls180.v:5081$966_Y + connect \Y $xor$ls180.v:5081$967_Y end - attribute \src "ls180.v:4992.899-4992.983" - cell $xor $xor$ls180.v:4992$854 + attribute \src "ls180.v:5090.899-5090.983" + cell $xor $xor$ls180.v:5090$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261531,10 +263876,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4992$854_Y + connect \Y $xor$ls180.v:5090$969_Y end - attribute \src "ls180.v:4992.634-4992.718" - cell $xor $xor$ls180.v:4992$855 + attribute \src "ls180.v:5090.634-5090.718" + cell $xor $xor$ls180.v:5090$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261542,21 +263887,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4992$855_Y + connect \Y $xor$ls180.v:5090$970_Y end - attribute \src "ls180.v:4992.588-4992.719" - cell $xor $xor$ls180.v:4992$856 + attribute \src "ls180.v:5090.588-5090.719" + cell $xor $xor$ls180.v:5090$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:4992$855_Y - connect \Y $xor$ls180.v:4992$856_Y + connect \B $xor$ls180.v:5090$970_Y + connect \Y $xor$ls180.v:5090$971_Y end - attribute \src "ls180.v:4992.234-4992.318" - cell $xor $xor$ls180.v:4992$857 + attribute \src "ls180.v:5090.234-5090.318" + cell $xor $xor$ls180.v:5090$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261564,21 +263909,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4992$857_Y + connect \Y $xor$ls180.v:5090$972_Y end - attribute \src "ls180.v:4992.187-4992.319" - cell $xor $xor$ls180.v:4992$858 + attribute \src "ls180.v:5090.187-5090.319" + cell $xor $xor$ls180.v:5090$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:4992$857_Y - connect \Y $xor$ls180.v:4992$858_Y + connect \B $xor$ls180.v:5090$972_Y + connect \Y $xor$ls180.v:5090$973_Y end - attribute \src "ls180.v:4993.899-4993.983" - cell $xor $xor$ls180.v:4993$859 + attribute \src "ls180.v:5091.899-5091.983" + cell $xor $xor$ls180.v:5091$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261586,10 +263931,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4993$859_Y + connect \Y $xor$ls180.v:5091$974_Y end - attribute \src "ls180.v:4993.634-4993.718" - cell $xor $xor$ls180.v:4993$860 + attribute \src "ls180.v:5091.634-5091.718" + cell $xor $xor$ls180.v:5091$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261597,21 +263942,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4993$860_Y + connect \Y $xor$ls180.v:5091$975_Y end - attribute \src "ls180.v:4993.588-4993.719" - cell $xor $xor$ls180.v:4993$861 + attribute \src "ls180.v:5091.588-5091.719" + cell $xor $xor$ls180.v:5091$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:4993$860_Y - connect \Y $xor$ls180.v:4993$861_Y + connect \B $xor$ls180.v:5091$975_Y + connect \Y $xor$ls180.v:5091$976_Y end - attribute \src "ls180.v:4993.234-4993.318" - cell $xor $xor$ls180.v:4993$862 + attribute \src "ls180.v:5091.234-5091.318" + cell $xor $xor$ls180.v:5091$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261619,21 +263964,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4993$862_Y + connect \Y $xor$ls180.v:5091$977_Y end - attribute \src "ls180.v:4993.187-4993.319" - cell $xor $xor$ls180.v:4993$863 + attribute \src "ls180.v:5091.187-5091.319" + cell $xor $xor$ls180.v:5091$978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:4993$862_Y - connect \Y $xor$ls180.v:4993$863_Y + connect \B $xor$ls180.v:5091$977_Y + connect \Y $xor$ls180.v:5091$978_Y end - attribute \src "ls180.v:5002.899-5002.983" - cell $xor $xor$ls180.v:5002$865 + attribute \src "ls180.v:5100.899-5100.983" + cell $xor $xor$ls180.v:5100$980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261641,10 +263986,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5002$865_Y + connect \Y $xor$ls180.v:5100$980_Y end - attribute \src "ls180.v:5002.634-5002.718" - cell $xor $xor$ls180.v:5002$866 + attribute \src "ls180.v:5100.634-5100.718" + cell $xor $xor$ls180.v:5100$981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261652,21 +263997,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5002$866_Y + connect \Y $xor$ls180.v:5100$981_Y end - attribute \src "ls180.v:5002.588-5002.719" - cell $xor $xor$ls180.v:5002$867 + attribute \src "ls180.v:5100.588-5100.719" + cell $xor $xor$ls180.v:5100$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5002$866_Y - connect \Y $xor$ls180.v:5002$867_Y + connect \B $xor$ls180.v:5100$981_Y + connect \Y $xor$ls180.v:5100$982_Y end - attribute \src "ls180.v:5002.234-5002.318" - cell $xor $xor$ls180.v:5002$868 + attribute \src "ls180.v:5100.234-5100.318" + cell $xor $xor$ls180.v:5100$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261674,21 +264019,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5002$868_Y + connect \Y $xor$ls180.v:5100$983_Y end - attribute \src "ls180.v:5002.187-5002.319" - cell $xor $xor$ls180.v:5002$869 + attribute \src "ls180.v:5100.187-5100.319" + cell $xor $xor$ls180.v:5100$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5002$868_Y - connect \Y $xor$ls180.v:5002$869_Y + connect \B $xor$ls180.v:5100$983_Y + connect \Y $xor$ls180.v:5100$984_Y end - attribute \src "ls180.v:5003.899-5003.983" - cell $xor $xor$ls180.v:5003$870 + attribute \src "ls180.v:5101.899-5101.983" + cell $xor $xor$ls180.v:5101$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261696,10 +264041,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5003$870_Y + connect \Y $xor$ls180.v:5101$985_Y end - attribute \src "ls180.v:5003.634-5003.718" - cell $xor $xor$ls180.v:5003$871 + attribute \src "ls180.v:5101.634-5101.718" + cell $xor $xor$ls180.v:5101$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261707,21 +264052,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5003$871_Y + connect \Y $xor$ls180.v:5101$986_Y end - attribute \src "ls180.v:5003.588-5003.719" - cell $xor $xor$ls180.v:5003$872 + attribute \src "ls180.v:5101.588-5101.719" + cell $xor $xor$ls180.v:5101$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5003$871_Y - connect \Y $xor$ls180.v:5003$872_Y + connect \B $xor$ls180.v:5101$986_Y + connect \Y $xor$ls180.v:5101$987_Y end - attribute \src "ls180.v:5003.234-5003.318" - cell $xor $xor$ls180.v:5003$873 + attribute \src "ls180.v:5101.234-5101.318" + cell $xor $xor$ls180.v:5101$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261729,21 +264074,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5003$873_Y + connect \Y $xor$ls180.v:5101$988_Y end - attribute \src "ls180.v:5003.187-5003.319" - cell $xor $xor$ls180.v:5003$874 + attribute \src "ls180.v:5101.187-5101.319" + cell $xor $xor$ls180.v:5101$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5003$873_Y - connect \Y $xor$ls180.v:5003$874_Y + connect \B $xor$ls180.v:5101$988_Y + connect \Y $xor$ls180.v:5101$989_Y end - attribute \src "ls180.v:5012.899-5012.983" - cell $xor $xor$ls180.v:5012$876 + attribute \src "ls180.v:5110.899-5110.983" + cell $xor $xor$ls180.v:5110$991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261751,10 +264096,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5012$876_Y + connect \Y $xor$ls180.v:5110$991_Y end - attribute \src "ls180.v:5012.634-5012.718" - cell $xor $xor$ls180.v:5012$877 + attribute \src "ls180.v:5110.634-5110.718" + cell $xor $xor$ls180.v:5110$992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261762,21 +264107,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5012$877_Y + connect \Y $xor$ls180.v:5110$992_Y end - attribute \src "ls180.v:5012.588-5012.719" - cell $xor $xor$ls180.v:5012$878 + attribute \src "ls180.v:5110.588-5110.719" + cell $xor $xor$ls180.v:5110$993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5012$877_Y - connect \Y $xor$ls180.v:5012$878_Y + connect \B $xor$ls180.v:5110$992_Y + connect \Y $xor$ls180.v:5110$993_Y end - attribute \src "ls180.v:5012.234-5012.318" - cell $xor $xor$ls180.v:5012$879 + attribute \src "ls180.v:5110.234-5110.318" + cell $xor $xor$ls180.v:5110$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261784,21 +264129,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5012$879_Y + connect \Y $xor$ls180.v:5110$994_Y end - attribute \src "ls180.v:5012.187-5012.319" - cell $xor $xor$ls180.v:5012$880 + attribute \src "ls180.v:5110.187-5110.319" + cell $xor $xor$ls180.v:5110$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5012$879_Y - connect \Y $xor$ls180.v:5012$880_Y + connect \B $xor$ls180.v:5110$994_Y + connect \Y $xor$ls180.v:5110$995_Y + end + attribute \src "ls180.v:5111.187-5111.319" + cell $xor $xor$ls180.v:5111$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5111$999_Y + connect \Y $xor$ls180.v:5111$1000_Y end - attribute \src "ls180.v:5013.899-5013.983" - cell $xor $xor$ls180.v:5013$881 + attribute \src "ls180.v:5111.899-5111.983" + cell $xor $xor$ls180.v:5111$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261806,10 +264162,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5013$881_Y + connect \Y $xor$ls180.v:5111$996_Y end - attribute \src "ls180.v:5013.634-5013.718" - cell $xor $xor$ls180.v:5013$882 + attribute \src "ls180.v:5111.634-5111.718" + cell $xor $xor$ls180.v:5111$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261817,21 +264173,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5013$882_Y + connect \Y $xor$ls180.v:5111$997_Y end - attribute \src "ls180.v:5013.588-5013.719" - cell $xor $xor$ls180.v:5013$883 + attribute \src "ls180.v:5111.588-5111.719" + cell $xor $xor$ls180.v:5111$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5013$882_Y - connect \Y $xor$ls180.v:5013$883_Y + connect \B $xor$ls180.v:5111$997_Y + connect \Y $xor$ls180.v:5111$998_Y end - attribute \src "ls180.v:5013.234-5013.318" - cell $xor $xor$ls180.v:5013$884 + attribute \src "ls180.v:5111.234-5111.318" + cell $xor $xor$ls180.v:5111$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261839,21 +264195,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5013$884_Y + connect \Y $xor$ls180.v:5111$999_Y end - attribute \src "ls180.v:5013.187-5013.319" - cell $xor $xor$ls180.v:5013$885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5013$884_Y - connect \Y $xor$ls180.v:5013$885_Y - end - attribute \src "ls180.v:5164.879-5164.961" - cell $xor $xor$ls180.v:5164$918 + attribute \src "ls180.v:5262.879-5262.961" + cell $xor $xor$ls180.v:5262$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261861,10 +264206,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5164$918_Y + connect \Y $xor$ls180.v:5262$1033_Y end - attribute \src "ls180.v:5164.620-5164.702" - cell $xor $xor$ls180.v:5164$919 + attribute \src "ls180.v:5262.620-5262.702" + cell $xor $xor$ls180.v:5262$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261872,21 +264217,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5164$919_Y + connect \Y $xor$ls180.v:5262$1034_Y end - attribute \src "ls180.v:5164.575-5164.703" - cell $xor $xor$ls180.v:5164$920 + attribute \src "ls180.v:5262.575-5262.703" + cell $xor $xor$ls180.v:5262$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5164$919_Y - connect \Y $xor$ls180.v:5164$920_Y + connect \B $xor$ls180.v:5262$1034_Y + connect \Y $xor$ls180.v:5262$1035_Y end - attribute \src "ls180.v:5164.229-5164.311" - cell $xor $xor$ls180.v:5164$921 + attribute \src "ls180.v:5262.229-5262.311" + cell $xor $xor$ls180.v:5262$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261894,21 +264239,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5164$921_Y + connect \Y $xor$ls180.v:5262$1036_Y end - attribute \src "ls180.v:5164.183-5164.312" - cell $xor $xor$ls180.v:5164$922 + attribute \src "ls180.v:5262.183-5262.312" + cell $xor $xor$ls180.v:5262$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5164$921_Y - connect \Y $xor$ls180.v:5164$922_Y + connect \B $xor$ls180.v:5262$1036_Y + connect \Y $xor$ls180.v:5262$1037_Y end - attribute \src "ls180.v:5165.879-5165.961" - cell $xor $xor$ls180.v:5165$923 + attribute \src "ls180.v:5263.879-5263.961" + cell $xor $xor$ls180.v:5263$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261916,10 +264261,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5165$923_Y + connect \Y $xor$ls180.v:5263$1038_Y end - attribute \src "ls180.v:5165.620-5165.702" - cell $xor $xor$ls180.v:5165$924 + attribute \src "ls180.v:5263.620-5263.702" + cell $xor $xor$ls180.v:5263$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261927,21 +264272,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5165$924_Y + connect \Y $xor$ls180.v:5263$1039_Y end - attribute \src "ls180.v:5165.575-5165.703" - cell $xor $xor$ls180.v:5165$925 + attribute \src "ls180.v:5263.575-5263.703" + cell $xor $xor$ls180.v:5263$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5165$924_Y - connect \Y $xor$ls180.v:5165$925_Y + connect \B $xor$ls180.v:5263$1039_Y + connect \Y $xor$ls180.v:5263$1040_Y end - attribute \src "ls180.v:5165.229-5165.311" - cell $xor $xor$ls180.v:5165$926 + attribute \src "ls180.v:5263.229-5263.311" + cell $xor $xor$ls180.v:5263$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261949,21 +264294,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5165$926_Y + connect \Y $xor$ls180.v:5263$1041_Y end - attribute \src "ls180.v:5165.183-5165.312" - cell $xor $xor$ls180.v:5165$927 + attribute \src "ls180.v:5263.183-5263.312" + cell $xor $xor$ls180.v:5263$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5165$926_Y - connect \Y $xor$ls180.v:5165$927_Y + connect \B $xor$ls180.v:5263$1041_Y + connect \Y $xor$ls180.v:5263$1042_Y end - attribute \src "ls180.v:5174.879-5174.961" - cell $xor $xor$ls180.v:5174$929 + attribute \src "ls180.v:5272.879-5272.961" + cell $xor $xor$ls180.v:5272$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261971,10 +264316,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5174$929_Y + connect \Y $xor$ls180.v:5272$1044_Y end - attribute \src "ls180.v:5174.620-5174.702" - cell $xor $xor$ls180.v:5174$930 + attribute \src "ls180.v:5272.620-5272.702" + cell $xor $xor$ls180.v:5272$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261982,21 +264327,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5174$930_Y + connect \Y $xor$ls180.v:5272$1045_Y end - attribute \src "ls180.v:5174.575-5174.703" - cell $xor $xor$ls180.v:5174$931 + attribute \src "ls180.v:5272.575-5272.703" + cell $xor $xor$ls180.v:5272$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5174$930_Y - connect \Y $xor$ls180.v:5174$931_Y + connect \B $xor$ls180.v:5272$1045_Y + connect \Y $xor$ls180.v:5272$1046_Y end - attribute \src "ls180.v:5174.229-5174.311" - cell $xor $xor$ls180.v:5174$932 + attribute \src "ls180.v:5272.229-5272.311" + cell $xor $xor$ls180.v:5272$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262004,21 +264349,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5174$932_Y + connect \Y $xor$ls180.v:5272$1047_Y end - attribute \src "ls180.v:5174.183-5174.312" - cell $xor $xor$ls180.v:5174$933 + attribute \src "ls180.v:5272.183-5272.312" + cell $xor $xor$ls180.v:5272$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5174$932_Y - connect \Y $xor$ls180.v:5174$933_Y + connect \B $xor$ls180.v:5272$1047_Y + connect \Y $xor$ls180.v:5272$1048_Y end - attribute \src "ls180.v:5175.879-5175.961" - cell $xor $xor$ls180.v:5175$934 + attribute \src "ls180.v:5273.879-5273.961" + cell $xor $xor$ls180.v:5273$1049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262026,10 +264371,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5175$934_Y + connect \Y $xor$ls180.v:5273$1049_Y end - attribute \src "ls180.v:5175.620-5175.702" - cell $xor $xor$ls180.v:5175$935 + attribute \src "ls180.v:5273.620-5273.702" + cell $xor $xor$ls180.v:5273$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262037,21 +264382,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5175$935_Y + connect \Y $xor$ls180.v:5273$1050_Y end - attribute \src "ls180.v:5175.575-5175.703" - cell $xor $xor$ls180.v:5175$936 + attribute \src "ls180.v:5273.575-5273.703" + cell $xor $xor$ls180.v:5273$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5175$935_Y - connect \Y $xor$ls180.v:5175$936_Y + connect \B $xor$ls180.v:5273$1050_Y + connect \Y $xor$ls180.v:5273$1051_Y end - attribute \src "ls180.v:5175.229-5175.311" - cell $xor $xor$ls180.v:5175$937 + attribute \src "ls180.v:5273.229-5273.311" + cell $xor $xor$ls180.v:5273$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262059,21 +264404,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5175$937_Y + connect \Y $xor$ls180.v:5273$1052_Y end - attribute \src "ls180.v:5175.183-5175.312" - cell $xor $xor$ls180.v:5175$938 + attribute \src "ls180.v:5273.183-5273.312" + cell $xor $xor$ls180.v:5273$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5175$937_Y - connect \Y $xor$ls180.v:5175$938_Y + connect \B $xor$ls180.v:5273$1052_Y + connect \Y $xor$ls180.v:5273$1053_Y end - attribute \src "ls180.v:5184.879-5184.961" - cell $xor $xor$ls180.v:5184$940 + attribute \src "ls180.v:5282.879-5282.961" + cell $xor $xor$ls180.v:5282$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262081,10 +264426,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5184$940_Y + connect \Y $xor$ls180.v:5282$1055_Y end - attribute \src "ls180.v:5184.620-5184.702" - cell $xor $xor$ls180.v:5184$941 + attribute \src "ls180.v:5282.620-5282.702" + cell $xor $xor$ls180.v:5282$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262092,21 +264437,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5184$941_Y + connect \Y $xor$ls180.v:5282$1056_Y end - attribute \src "ls180.v:5184.575-5184.703" - cell $xor $xor$ls180.v:5184$942 + attribute \src "ls180.v:5282.575-5282.703" + cell $xor $xor$ls180.v:5282$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5184$941_Y - connect \Y $xor$ls180.v:5184$942_Y + connect \B $xor$ls180.v:5282$1056_Y + connect \Y $xor$ls180.v:5282$1057_Y end - attribute \src "ls180.v:5184.229-5184.311" - cell $xor $xor$ls180.v:5184$943 + attribute \src "ls180.v:5282.229-5282.311" + cell $xor $xor$ls180.v:5282$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262114,21 +264459,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5184$943_Y + connect \Y $xor$ls180.v:5282$1058_Y end - attribute \src "ls180.v:5184.183-5184.312" - cell $xor $xor$ls180.v:5184$944 + attribute \src "ls180.v:5282.183-5282.312" + cell $xor $xor$ls180.v:5282$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5184$943_Y - connect \Y $xor$ls180.v:5184$944_Y + connect \B $xor$ls180.v:5282$1058_Y + connect \Y $xor$ls180.v:5282$1059_Y end - attribute \src "ls180.v:5185.879-5185.961" - cell $xor $xor$ls180.v:5185$945 + attribute \src "ls180.v:5283.879-5283.961" + cell $xor $xor$ls180.v:5283$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262136,10 +264481,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5185$945_Y + connect \Y $xor$ls180.v:5283$1060_Y end - attribute \src "ls180.v:5185.620-5185.702" - cell $xor $xor$ls180.v:5185$946 + attribute \src "ls180.v:5283.620-5283.702" + cell $xor $xor$ls180.v:5283$1061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262147,21 +264492,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5185$946_Y + connect \Y $xor$ls180.v:5283$1061_Y end - attribute \src "ls180.v:5185.575-5185.703" - cell $xor $xor$ls180.v:5185$947 + attribute \src "ls180.v:5283.575-5283.703" + cell $xor $xor$ls180.v:5283$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5185$946_Y - connect \Y $xor$ls180.v:5185$947_Y + connect \B $xor$ls180.v:5283$1061_Y + connect \Y $xor$ls180.v:5283$1062_Y end - attribute \src "ls180.v:5185.229-5185.311" - cell $xor $xor$ls180.v:5185$948 + attribute \src "ls180.v:5283.229-5283.311" + cell $xor $xor$ls180.v:5283$1063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262169,21 +264514,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5185$948_Y + connect \Y $xor$ls180.v:5283$1063_Y end - attribute \src "ls180.v:5185.183-5185.312" - cell $xor $xor$ls180.v:5185$949 + attribute \src "ls180.v:5283.183-5283.312" + cell $xor $xor$ls180.v:5283$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5185$948_Y - connect \Y $xor$ls180.v:5185$949_Y + connect \B $xor$ls180.v:5283$1063_Y + connect \Y $xor$ls180.v:5283$1064_Y end - attribute \src "ls180.v:5194.879-5194.961" - cell $xor $xor$ls180.v:5194$951 + attribute \src "ls180.v:5292.879-5292.961" + cell $xor $xor$ls180.v:5292$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262191,10 +264536,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5194$951_Y + connect \Y $xor$ls180.v:5292$1066_Y end - attribute \src "ls180.v:5194.620-5194.702" - cell $xor $xor$ls180.v:5194$952 + attribute \src "ls180.v:5292.620-5292.702" + cell $xor $xor$ls180.v:5292$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262202,21 +264547,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5194$952_Y + connect \Y $xor$ls180.v:5292$1067_Y end - attribute \src "ls180.v:5194.575-5194.703" - cell $xor $xor$ls180.v:5194$953 + attribute \src "ls180.v:5292.575-5292.703" + cell $xor $xor$ls180.v:5292$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5194$952_Y - connect \Y $xor$ls180.v:5194$953_Y + connect \B $xor$ls180.v:5292$1067_Y + connect \Y $xor$ls180.v:5292$1068_Y end - attribute \src "ls180.v:5194.229-5194.311" - cell $xor $xor$ls180.v:5194$954 + attribute \src "ls180.v:5292.229-5292.311" + cell $xor $xor$ls180.v:5292$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262224,21 +264569,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5194$954_Y + connect \Y $xor$ls180.v:5292$1069_Y end - attribute \src "ls180.v:5194.183-5194.312" - cell $xor $xor$ls180.v:5194$955 + attribute \src "ls180.v:5292.183-5292.312" + cell $xor $xor$ls180.v:5292$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5194$954_Y - connect \Y $xor$ls180.v:5194$955_Y + connect \B $xor$ls180.v:5292$1069_Y + connect \Y $xor$ls180.v:5292$1070_Y end - attribute \src "ls180.v:5195.879-5195.961" - cell $xor $xor$ls180.v:5195$956 + attribute \src "ls180.v:5293.879-5293.961" + cell $xor $xor$ls180.v:5293$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262246,10 +264591,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5195$956_Y + connect \Y $xor$ls180.v:5293$1071_Y end - attribute \src "ls180.v:5195.620-5195.702" - cell $xor $xor$ls180.v:5195$957 + attribute \src "ls180.v:5293.620-5293.702" + cell $xor $xor$ls180.v:5293$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262257,21 +264602,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5195$957_Y + connect \Y $xor$ls180.v:5293$1072_Y end - attribute \src "ls180.v:5195.575-5195.703" - cell $xor $xor$ls180.v:5195$958 + attribute \src "ls180.v:5293.575-5293.703" + cell $xor $xor$ls180.v:5293$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5195$957_Y - connect \Y $xor$ls180.v:5195$958_Y + connect \B $xor$ls180.v:5293$1072_Y + connect \Y $xor$ls180.v:5293$1073_Y end - attribute \src "ls180.v:5195.229-5195.311" - cell $xor $xor$ls180.v:5195$959 + attribute \src "ls180.v:5293.229-5293.311" + cell $xor $xor$ls180.v:5293$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262279,21 +264624,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5195$959_Y + connect \Y $xor$ls180.v:5293$1074_Y end - attribute \src "ls180.v:5195.183-5195.312" - cell $xor $xor$ls180.v:5195$960 + attribute \src "ls180.v:5293.183-5293.312" + cell $xor $xor$ls180.v:5293$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5195$959_Y - connect \Y $xor$ls180.v:5195$960_Y + connect \B $xor$ls180.v:5293$1074_Y + connect \Y $xor$ls180.v:5293$1075_Y end attribute \module_not_derived 1 - attribute \src "ls180.v:10179.13-10553.2" + attribute \src "ls180.v:10435.13-10809.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi @@ -262489,7 +264834,7 @@ module \ls180 connect \pwm_0__pad__o \pwm_1 [0] connect \pwm_1__core__o \pwm [1] connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10279$2750_Y + connect \rst $or$ls180.v:10535$2982_Y connect \sd0_clk__core__o \sdcard_clk connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk connect \sd0_cmd__core__i \sdcard_cmd_i @@ -262670,28 +265015,100 @@ module \ls180 connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3701 + process $proc$ls180.v:0$3977 sync always sync init end - attribute \src "ls180.v:1000.5-1000.31" - process $proc$ls180.v:1000$3130 + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3978 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3979 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3980 + sync always + sync init + end + attribute \src "ls180.v:100.11-100.56" + process $proc$ls180.v:100$3041 assign { } { } - assign $1\main_spimaster12_re[0:0] 1'0 + assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 sync always sync init - update \main_spimaster12_re $1\main_spimaster12_re[0:0] + update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] end - attribute \src "ls180.v:1004.11-1004.42" - process $proc$ls180.v:1004$3131 + attribute \src "ls180.v:1003.11-1003.42" + process $proc$ls180.v:1003$3381 assign { } { } - assign $1\main_spimaster16_storage[7:0] 8'00000000 + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always sync init - update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:1004.5-1004.37" + process $proc$ls180.v:1004$3382 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1005.11-1005.43" + process $proc$ls180.v:1005$3383 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end - attribute \src "ls180.v:10043.1-10053.4" - process $proc$ls180.v:10043$2680 + attribute \src "ls180.v:1006.11-1006.43" + process $proc$ls180.v:1006$3384 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:1007.11-1007.46" + process $proc$ls180.v:1007$3385 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:101.5-101.50" + process $proc$ls180.v:101$3042 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + end + attribute \src "ls180.v:102.5-102.50" + process $proc$ls180.v:102$3043 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + end + attribute \src "ls180.v:10207.1-10225.4" + process $proc$ls180.v:10207$2822 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -262705,5370 +265122,5894 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 0 - assign $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 0 - assign $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 0 - assign $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 0 - assign $0\memadr[6:0] \main_libresocsim_adr - attribute \src "ls180.v:10044.2-10045.65" + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10223$8_ADDR[8:0]$2844 9'xxxxxxxxx + assign $0$memwr$\mem$ls180.v:10223$8_DATA[63:0]$2845 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10223$8_EN[63:0]$2846 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10221$7_ADDR[8:0]$2841 9'xxxxxxxxx + assign $0$memwr$\mem$ls180.v:10221$7_DATA[63:0]$2842 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10221$7_EN[63:0]$2843 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10219$6_ADDR[8:0]$2838 9'xxxxxxxxx + assign $0$memwr$\mem$ls180.v:10219$6_DATA[63:0]$2839 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10219$6_EN[63:0]$2840 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10217$5_ADDR[8:0]$2835 9'xxxxxxxxx + assign $0$memwr$\mem$ls180.v:10217$5_DATA[63:0]$2836 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10217$5_EN[63:0]$2837 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10215$4_ADDR[8:0]$2832 9'xxxxxxxxx + assign $0$memwr$\mem$ls180.v:10215$4_DATA[63:0]$2833 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10215$4_EN[63:0]$2834 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10213$3_ADDR[8:0]$2829 9'xxxxxxxxx + assign $0$memwr$\mem$ls180.v:10213$3_DATA[63:0]$2830 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10213$3_EN[63:0]$2831 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10211$2_ADDR[8:0]$2826 9'xxxxxxxxx + assign $0$memwr$\mem$ls180.v:10211$2_DATA[63:0]$2827 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10211$2_EN[63:0]$2828 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10209$1_ADDR[8:0]$2823 9'xxxxxxxxx + assign $0$memwr$\mem$ls180.v:10209$1_DATA[63:0]$2824 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10209$1_EN[63:0]$2825 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr[8:0] \main_libresocsim_adr + attribute \src "ls180.v:10208.2-10209.65" switch \main_libresocsim_we [0] - attribute \src "ls180.v:10044.6-10044.28" + attribute \src "ls180.v:10208.6-10208.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 255 + assign $0$memwr$\mem$ls180.v:10209$1_ADDR[8:0]$2823 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10209$1_DATA[63:0]$2824 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10209$1_EN[63:0]$2825 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10046.2-10047.67" + attribute \src "ls180.v:10210.2-10211.67" switch \main_libresocsim_we [1] - attribute \src "ls180.v:10046.6-10046.28" + attribute \src "ls180.v:10210.6-10210.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 65280 + assign $0$memwr$\mem$ls180.v:10211$2_ADDR[8:0]$2826 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10211$2_DATA[63:0]$2827 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10211$2_EN[63:0]$2828 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10048.2-10049.69" + attribute \src "ls180.v:10212.2-10213.69" switch \main_libresocsim_we [2] - attribute \src "ls180.v:10048.6-10048.28" + attribute \src "ls180.v:10212.6-10212.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 16711680 + assign $0$memwr$\mem$ls180.v:10213$3_ADDR[8:0]$2829 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10213$3_DATA[63:0]$2830 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10213$3_EN[63:0]$2831 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10050.2-10051.69" + attribute \src "ls180.v:10214.2-10215.69" switch \main_libresocsim_we [3] - attribute \src "ls180.v:10050.6-10050.28" + attribute \src "ls180.v:10214.6-10214.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10215$4_ADDR[8:0]$2832 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10215$4_DATA[63:0]$2833 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10215$4_EN[63:0]$2834 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10216.2-10217.69" + switch \main_libresocsim_we [4] + attribute \src "ls180.v:10216.6-10216.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10217$5_ADDR[8:0]$2835 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10217$5_DATA[63:0]$2836 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10217$5_EN[63:0]$2837 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10218.2-10219.69" + switch \main_libresocsim_we [5] + attribute \src "ls180.v:10218.6-10218.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 32'11111111000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10219$6_ADDR[8:0]$2838 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10219$6_DATA[63:0]$2839 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10219$6_EN[63:0]$2840 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10220.2-10221.69" + switch \main_libresocsim_we [6] + attribute \src "ls180.v:10220.6-10220.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10221$7_ADDR[8:0]$2841 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10221$7_DATA[63:0]$2842 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10221$7_EN[63:0]$2843 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10222.2-10223.69" + switch \main_libresocsim_we [7] + attribute \src "ls180.v:10222.6-10222.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10223$8_ADDR[8:0]$2844 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10223$8_DATA[63:0]$2845 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10223$8_EN[63:0]$2846 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:10045$1_ADDR $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 - update $memwr$\mem$ls180.v:10045$1_DATA $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 - update $memwr$\mem$ls180.v:10045$1_EN $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 - update $memwr$\mem$ls180.v:10047$2_ADDR $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 - update $memwr$\mem$ls180.v:10047$2_DATA $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 - update $memwr$\mem$ls180.v:10047$2_EN $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 - update $memwr$\mem$ls180.v:10049$3_ADDR $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 - update $memwr$\mem$ls180.v:10049$3_DATA $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 - update $memwr$\mem$ls180.v:10049$3_EN $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 - update $memwr$\mem$ls180.v:10051$4_ADDR $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 - update $memwr$\mem$ls180.v:10051$4_DATA $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 - update $memwr$\mem$ls180.v:10051$4_EN $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 - end - attribute \src "ls180.v:1005.5-1005.31" - process $proc$ls180.v:1005$3132 + update \memadr $0\memadr[8:0] + update $memwr$\mem$ls180.v:10209$1_ADDR $0$memwr$\mem$ls180.v:10209$1_ADDR[8:0]$2823 + update $memwr$\mem$ls180.v:10209$1_DATA $0$memwr$\mem$ls180.v:10209$1_DATA[63:0]$2824 + update $memwr$\mem$ls180.v:10209$1_EN $0$memwr$\mem$ls180.v:10209$1_EN[63:0]$2825 + update $memwr$\mem$ls180.v:10211$2_ADDR $0$memwr$\mem$ls180.v:10211$2_ADDR[8:0]$2826 + update $memwr$\mem$ls180.v:10211$2_DATA $0$memwr$\mem$ls180.v:10211$2_DATA[63:0]$2827 + update $memwr$\mem$ls180.v:10211$2_EN $0$memwr$\mem$ls180.v:10211$2_EN[63:0]$2828 + update $memwr$\mem$ls180.v:10213$3_ADDR $0$memwr$\mem$ls180.v:10213$3_ADDR[8:0]$2829 + update $memwr$\mem$ls180.v:10213$3_DATA $0$memwr$\mem$ls180.v:10213$3_DATA[63:0]$2830 + update $memwr$\mem$ls180.v:10213$3_EN $0$memwr$\mem$ls180.v:10213$3_EN[63:0]$2831 + update $memwr$\mem$ls180.v:10215$4_ADDR $0$memwr$\mem$ls180.v:10215$4_ADDR[8:0]$2832 + update $memwr$\mem$ls180.v:10215$4_DATA $0$memwr$\mem$ls180.v:10215$4_DATA[63:0]$2833 + update $memwr$\mem$ls180.v:10215$4_EN $0$memwr$\mem$ls180.v:10215$4_EN[63:0]$2834 + update $memwr$\mem$ls180.v:10217$5_ADDR $0$memwr$\mem$ls180.v:10217$5_ADDR[8:0]$2835 + update $memwr$\mem$ls180.v:10217$5_DATA $0$memwr$\mem$ls180.v:10217$5_DATA[63:0]$2836 + update $memwr$\mem$ls180.v:10217$5_EN $0$memwr$\mem$ls180.v:10217$5_EN[63:0]$2837 + update $memwr$\mem$ls180.v:10219$6_ADDR $0$memwr$\mem$ls180.v:10219$6_ADDR[8:0]$2838 + update $memwr$\mem$ls180.v:10219$6_DATA $0$memwr$\mem$ls180.v:10219$6_DATA[63:0]$2839 + update $memwr$\mem$ls180.v:10219$6_EN $0$memwr$\mem$ls180.v:10219$6_EN[63:0]$2840 + update $memwr$\mem$ls180.v:10221$7_ADDR $0$memwr$\mem$ls180.v:10221$7_ADDR[8:0]$2841 + update $memwr$\mem$ls180.v:10221$7_DATA $0$memwr$\mem$ls180.v:10221$7_DATA[63:0]$2842 + update $memwr$\mem$ls180.v:10221$7_EN $0$memwr$\mem$ls180.v:10221$7_EN[63:0]$2843 + update $memwr$\mem$ls180.v:10223$8_ADDR $0$memwr$\mem$ls180.v:10223$8_ADDR[8:0]$2844 + update $memwr$\mem$ls180.v:10223$8_DATA $0$memwr$\mem$ls180.v:10223$8_DATA[63:0]$2845 + update $memwr$\mem$ls180.v:10223$8_EN $0$memwr$\mem$ls180.v:10223$8_EN[63:0]$2846 + end + attribute \src "ls180.v:1022.5-1022.27" + process $proc$ls180.v:1022$3386 assign { } { } - assign $1\main_spimaster17_re[0:0] 1'0 + assign $0\main_uart_reset[0:0] 1'0 sync always + update \main_uart_reset $0\main_uart_reset[0:0] sync init - update \main_spimaster17_re $1\main_spimaster17_re[0:0] end - attribute \src "ls180.v:10063.1-10067.4" - process $proc$ls180.v:10063$2694 + attribute \src "ls180.v:1023.12-1023.40" + process $proc$ls180.v:1023$3387 + assign { } { } + assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] + end + attribute \src "ls180.v:10235.1-10253.4" + process $proc$ls180.v:10235$2848 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 3'xxx - assign $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10066$2698_DATA - attribute \src "ls180.v:10064.2-10065.129" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_1$ls180.v:10251$16_ADDR[8:0]$2870 9'xxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10251$16_DATA[63:0]$2871 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10251$16_EN[63:0]$2872 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10249$15_ADDR[8:0]$2867 9'xxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10249$15_DATA[63:0]$2868 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10249$15_EN[63:0]$2869 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10247$14_ADDR[8:0]$2864 9'xxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10247$14_DATA[63:0]$2865 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10247$14_EN[63:0]$2866 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10245$13_ADDR[8:0]$2861 9'xxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10245$13_DATA[63:0]$2862 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10245$13_EN[63:0]$2863 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10243$12_ADDR[8:0]$2858 9'xxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10243$12_DATA[63:0]$2859 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10243$12_EN[63:0]$2860 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10241$11_ADDR[8:0]$2855 9'xxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10241$11_DATA[63:0]$2856 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10241$11_EN[63:0]$2857 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10239$10_ADDR[8:0]$2852 9'xxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10239$10_DATA[63:0]$2853 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10239$10_EN[63:0]$2854 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10237$9_ADDR[8:0]$2849 9'xxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10237$9_DATA[63:0]$2850 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10237$9_EN[63:0]$2851 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_1[8:0] \main_sram0_adr + attribute \src "ls180.v:10236.2-10237.55" + switch \main_sram0_we [0] + attribute \src "ls180.v:10236.6-10236.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10237$9_ADDR[8:0]$2849 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10237$9_DATA[63:0]$2850 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10237$9_EN[63:0]$2851 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10238.2-10239.57" + switch \main_sram0_we [1] + attribute \src "ls180.v:10238.6-10238.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10239$10_ADDR[8:0]$2852 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10239$10_DATA[63:0]$2853 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10239$10_EN[63:0]$2854 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10240.2-10241.59" + switch \main_sram0_we [2] + attribute \src "ls180.v:10240.6-10240.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10241$11_ADDR[8:0]$2855 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10241$11_DATA[63:0]$2856 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10241$11_EN[63:0]$2857 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10242.2-10243.59" + switch \main_sram0_we [3] + attribute \src "ls180.v:10242.6-10242.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10243$12_ADDR[8:0]$2858 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10243$12_DATA[63:0]$2859 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10243$12_EN[63:0]$2860 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10244.2-10245.59" + switch \main_sram0_we [4] + attribute \src "ls180.v:10244.6-10244.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10245$13_ADDR[8:0]$2861 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10245$13_DATA[63:0]$2862 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10245$13_EN[63:0]$2863 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10246.2-10247.59" + switch \main_sram0_we [5] + attribute \src "ls180.v:10246.6-10246.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10247$14_ADDR[8:0]$2864 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10247$14_DATA[63:0]$2865 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10247$14_EN[63:0]$2866 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10248.2-10249.59" + switch \main_sram0_we [6] + attribute \src "ls180.v:10248.6-10248.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10249$15_ADDR[8:0]$2867 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10249$15_DATA[63:0]$2868 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10249$15_EN[63:0]$2869 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10250.2-10251.59" + switch \main_sram0_we [7] + attribute \src "ls180.v:10250.6-10250.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10251$16_ADDR[8:0]$2870 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10251$16_DATA[63:0]$2871 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10251$16_EN[63:0]$2872 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_1 $0\memadr_1[8:0] + update $memwr$\mem_1$ls180.v:10237$9_ADDR $0$memwr$\mem_1$ls180.v:10237$9_ADDR[8:0]$2849 + update $memwr$\mem_1$ls180.v:10237$9_DATA $0$memwr$\mem_1$ls180.v:10237$9_DATA[63:0]$2850 + update $memwr$\mem_1$ls180.v:10237$9_EN $0$memwr$\mem_1$ls180.v:10237$9_EN[63:0]$2851 + update $memwr$\mem_1$ls180.v:10239$10_ADDR $0$memwr$\mem_1$ls180.v:10239$10_ADDR[8:0]$2852 + update $memwr$\mem_1$ls180.v:10239$10_DATA $0$memwr$\mem_1$ls180.v:10239$10_DATA[63:0]$2853 + update $memwr$\mem_1$ls180.v:10239$10_EN $0$memwr$\mem_1$ls180.v:10239$10_EN[63:0]$2854 + update $memwr$\mem_1$ls180.v:10241$11_ADDR $0$memwr$\mem_1$ls180.v:10241$11_ADDR[8:0]$2855 + update $memwr$\mem_1$ls180.v:10241$11_DATA $0$memwr$\mem_1$ls180.v:10241$11_DATA[63:0]$2856 + update $memwr$\mem_1$ls180.v:10241$11_EN $0$memwr$\mem_1$ls180.v:10241$11_EN[63:0]$2857 + update $memwr$\mem_1$ls180.v:10243$12_ADDR $0$memwr$\mem_1$ls180.v:10243$12_ADDR[8:0]$2858 + update $memwr$\mem_1$ls180.v:10243$12_DATA $0$memwr$\mem_1$ls180.v:10243$12_DATA[63:0]$2859 + update $memwr$\mem_1$ls180.v:10243$12_EN $0$memwr$\mem_1$ls180.v:10243$12_EN[63:0]$2860 + update $memwr$\mem_1$ls180.v:10245$13_ADDR $0$memwr$\mem_1$ls180.v:10245$13_ADDR[8:0]$2861 + update $memwr$\mem_1$ls180.v:10245$13_DATA $0$memwr$\mem_1$ls180.v:10245$13_DATA[63:0]$2862 + update $memwr$\mem_1$ls180.v:10245$13_EN $0$memwr$\mem_1$ls180.v:10245$13_EN[63:0]$2863 + update $memwr$\mem_1$ls180.v:10247$14_ADDR $0$memwr$\mem_1$ls180.v:10247$14_ADDR[8:0]$2864 + update $memwr$\mem_1$ls180.v:10247$14_DATA $0$memwr$\mem_1$ls180.v:10247$14_DATA[63:0]$2865 + update $memwr$\mem_1$ls180.v:10247$14_EN $0$memwr$\mem_1$ls180.v:10247$14_EN[63:0]$2866 + update $memwr$\mem_1$ls180.v:10249$15_ADDR $0$memwr$\mem_1$ls180.v:10249$15_ADDR[8:0]$2867 + update $memwr$\mem_1$ls180.v:10249$15_DATA $0$memwr$\mem_1$ls180.v:10249$15_DATA[63:0]$2868 + update $memwr$\mem_1$ls180.v:10249$15_EN $0$memwr$\mem_1$ls180.v:10249$15_EN[63:0]$2869 + update $memwr$\mem_1$ls180.v:10251$16_ADDR $0$memwr$\mem_1$ls180.v:10251$16_ADDR[8:0]$2870 + update $memwr$\mem_1$ls180.v:10251$16_DATA $0$memwr$\mem_1$ls180.v:10251$16_DATA[63:0]$2871 + update $memwr$\mem_1$ls180.v:10251$16_EN $0$memwr$\mem_1$ls180.v:10251$16_EN[63:0]$2872 + end + attribute \src "ls180.v:1024.5-1024.27" + process $proc$ls180.v:1024$3388 + assign { } { } + assign $1\main_gpio_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] + end + attribute \src "ls180.v:1025.12-1025.36" + process $proc$ls180.v:1025$3389 + assign { } { } + assign $1\main_gpio_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_status $1\main_gpio_status[15:0] + end + attribute \src "ls180.v:10263.1-10281.4" + process $proc$ls180.v:10263$2874 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_2$ls180.v:10279$24_ADDR[8:0]$2896 9'xxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10279$24_DATA[63:0]$2897 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10279$24_EN[63:0]$2898 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10277$23_ADDR[8:0]$2893 9'xxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10277$23_DATA[63:0]$2894 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10277$23_EN[63:0]$2895 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10275$22_ADDR[8:0]$2890 9'xxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10275$22_DATA[63:0]$2891 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10275$22_EN[63:0]$2892 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10273$21_ADDR[8:0]$2887 9'xxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10273$21_DATA[63:0]$2888 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10273$21_EN[63:0]$2889 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10271$20_ADDR[8:0]$2884 9'xxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10271$20_DATA[63:0]$2885 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10271$20_EN[63:0]$2886 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10269$19_ADDR[8:0]$2881 9'xxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10269$19_DATA[63:0]$2882 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10269$19_EN[63:0]$2883 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10267$18_ADDR[8:0]$2878 9'xxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10267$18_DATA[63:0]$2879 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10267$18_EN[63:0]$2880 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10265$17_ADDR[8:0]$2875 9'xxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10265$17_DATA[63:0]$2876 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10265$17_EN[63:0]$2877 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_2[8:0] \main_sram1_adr + attribute \src "ls180.v:10264.2-10265.55" + switch \main_sram1_we [0] + attribute \src "ls180.v:10264.6-10264.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10265$17_ADDR[8:0]$2875 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10265$17_DATA[63:0]$2876 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } + assign $0$memwr$\mem_2$ls180.v:10265$17_EN[63:0]$2877 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10266.2-10267.57" + switch \main_sram1_we [1] + attribute \src "ls180.v:10266.6-10266.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10267$18_ADDR[8:0]$2878 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10267$18_DATA[63:0]$2879 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10267$18_EN[63:0]$2880 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10268.2-10269.59" + switch \main_sram1_we [2] + attribute \src "ls180.v:10268.6-10268.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10269$19_ADDR[8:0]$2881 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10269$19_DATA[63:0]$2882 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10269$19_EN[63:0]$2883 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10270.2-10271.59" + switch \main_sram1_we [3] + attribute \src "ls180.v:10270.6-10270.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10271$20_ADDR[8:0]$2884 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10271$20_DATA[63:0]$2885 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10271$20_EN[63:0]$2886 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10272.2-10273.59" + switch \main_sram1_we [4] + attribute \src "ls180.v:10272.6-10272.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10273$21_ADDR[8:0]$2887 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10273$21_DATA[63:0]$2888 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10273$21_EN[63:0]$2889 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10274.2-10275.59" + switch \main_sram1_we [5] + attribute \src "ls180.v:10274.6-10274.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10275$22_ADDR[8:0]$2890 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10275$22_DATA[63:0]$2891 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10275$22_EN[63:0]$2892 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10276.2-10277.59" + switch \main_sram1_we [6] + attribute \src "ls180.v:10276.6-10276.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10277$23_ADDR[8:0]$2893 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10277$23_DATA[63:0]$2894 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10277$23_EN[63:0]$2895 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10278.2-10279.59" + switch \main_sram1_we [7] + attribute \src "ls180.v:10278.6-10278.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10279$24_ADDR[8:0]$2896 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10279$24_DATA[63:0]$2897 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10279$24_EN[63:0]$2898 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_2 $0\memadr_2[8:0] + update $memwr$\mem_2$ls180.v:10265$17_ADDR $0$memwr$\mem_2$ls180.v:10265$17_ADDR[8:0]$2875 + update $memwr$\mem_2$ls180.v:10265$17_DATA $0$memwr$\mem_2$ls180.v:10265$17_DATA[63:0]$2876 + update $memwr$\mem_2$ls180.v:10265$17_EN $0$memwr$\mem_2$ls180.v:10265$17_EN[63:0]$2877 + update $memwr$\mem_2$ls180.v:10267$18_ADDR $0$memwr$\mem_2$ls180.v:10267$18_ADDR[8:0]$2878 + update $memwr$\mem_2$ls180.v:10267$18_DATA $0$memwr$\mem_2$ls180.v:10267$18_DATA[63:0]$2879 + update $memwr$\mem_2$ls180.v:10267$18_EN $0$memwr$\mem_2$ls180.v:10267$18_EN[63:0]$2880 + update $memwr$\mem_2$ls180.v:10269$19_ADDR $0$memwr$\mem_2$ls180.v:10269$19_ADDR[8:0]$2881 + update $memwr$\mem_2$ls180.v:10269$19_DATA $0$memwr$\mem_2$ls180.v:10269$19_DATA[63:0]$2882 + update $memwr$\mem_2$ls180.v:10269$19_EN $0$memwr$\mem_2$ls180.v:10269$19_EN[63:0]$2883 + update $memwr$\mem_2$ls180.v:10271$20_ADDR $0$memwr$\mem_2$ls180.v:10271$20_ADDR[8:0]$2884 + update $memwr$\mem_2$ls180.v:10271$20_DATA $0$memwr$\mem_2$ls180.v:10271$20_DATA[63:0]$2885 + update $memwr$\mem_2$ls180.v:10271$20_EN $0$memwr$\mem_2$ls180.v:10271$20_EN[63:0]$2886 + update $memwr$\mem_2$ls180.v:10273$21_ADDR $0$memwr$\mem_2$ls180.v:10273$21_ADDR[8:0]$2887 + update $memwr$\mem_2$ls180.v:10273$21_DATA $0$memwr$\mem_2$ls180.v:10273$21_DATA[63:0]$2888 + update $memwr$\mem_2$ls180.v:10273$21_EN $0$memwr$\mem_2$ls180.v:10273$21_EN[63:0]$2889 + update $memwr$\mem_2$ls180.v:10275$22_ADDR $0$memwr$\mem_2$ls180.v:10275$22_ADDR[8:0]$2890 + update $memwr$\mem_2$ls180.v:10275$22_DATA $0$memwr$\mem_2$ls180.v:10275$22_DATA[63:0]$2891 + update $memwr$\mem_2$ls180.v:10275$22_EN $0$memwr$\mem_2$ls180.v:10275$22_EN[63:0]$2892 + update $memwr$\mem_2$ls180.v:10277$23_ADDR $0$memwr$\mem_2$ls180.v:10277$23_ADDR[8:0]$2893 + update $memwr$\mem_2$ls180.v:10277$23_DATA $0$memwr$\mem_2$ls180.v:10277$23_DATA[63:0]$2894 + update $memwr$\mem_2$ls180.v:10277$23_EN $0$memwr$\mem_2$ls180.v:10277$23_EN[63:0]$2895 + update $memwr$\mem_2$ls180.v:10279$24_ADDR $0$memwr$\mem_2$ls180.v:10279$24_ADDR[8:0]$2896 + update $memwr$\mem_2$ls180.v:10279$24_DATA $0$memwr$\mem_2$ls180.v:10279$24_DATA[63:0]$2897 + update $memwr$\mem_2$ls180.v:10279$24_EN $0$memwr$\mem_2$ls180.v:10279$24_EN[63:0]$2898 + end + attribute \src "ls180.v:1027.12-1027.41" + process $proc$ls180.v:1027$3390 + assign { } { } + assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] + end + attribute \src "ls180.v:1028.5-1028.28" + process $proc$ls180.v:1028$3391 + assign { } { } + assign $1\main_gpio_out_re[0:0] 1'0 + sync always + sync init + update \main_gpio_out_re $1\main_gpio_out_re[0:0] + end + attribute \src "ls180.v:10291.1-10309.4" + process $proc$ls180.v:10291$2900 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_3$ls180.v:10307$32_ADDR[8:0]$2922 9'xxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10307$32_DATA[63:0]$2923 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10307$32_EN[63:0]$2924 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10305$31_ADDR[8:0]$2919 9'xxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10305$31_DATA[63:0]$2920 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10305$31_EN[63:0]$2921 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10303$30_ADDR[8:0]$2916 9'xxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10303$30_DATA[63:0]$2917 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10303$30_EN[63:0]$2918 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10301$29_ADDR[8:0]$2913 9'xxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10301$29_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10301$29_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10299$28_ADDR[8:0]$2910 9'xxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10299$28_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10299$28_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10297$27_ADDR[8:0]$2907 9'xxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10297$27_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10297$27_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10295$26_ADDR[8:0]$2904 9'xxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10295$26_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10295$26_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10293$25_ADDR[8:0]$2901 9'xxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10293$25_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10293$25_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_3[8:0] \main_sram2_adr + attribute \src "ls180.v:10292.2-10293.55" + switch \main_sram2_we [0] + attribute \src "ls180.v:10292.6-10292.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10293$25_ADDR[8:0]$2901 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10293$25_DATA[63:0]$2902 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } + assign $0$memwr$\mem_3$ls180.v:10293$25_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10294.2-10295.57" + switch \main_sram2_we [1] + attribute \src "ls180.v:10294.6-10294.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10295$26_ADDR[8:0]$2904 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10295$26_DATA[63:0]$2905 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10295$26_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10296.2-10297.59" + switch \main_sram2_we [2] + attribute \src "ls180.v:10296.6-10296.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10297$27_ADDR[8:0]$2907 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10297$27_DATA[63:0]$2908 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10297$27_EN[63:0]$2909 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10298.2-10299.59" + switch \main_sram2_we [3] + attribute \src "ls180.v:10298.6-10298.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10299$28_ADDR[8:0]$2910 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10299$28_DATA[63:0]$2911 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10299$28_EN[63:0]$2912 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10300.2-10301.59" + switch \main_sram2_we [4] + attribute \src "ls180.v:10300.6-10300.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10301$29_ADDR[8:0]$2913 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10301$29_DATA[63:0]$2914 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10301$29_EN[63:0]$2915 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10302.2-10303.59" + switch \main_sram2_we [5] + attribute \src "ls180.v:10302.6-10302.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10303$30_ADDR[8:0]$2916 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10303$30_DATA[63:0]$2917 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10303$30_EN[63:0]$2918 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10304.2-10305.59" + switch \main_sram2_we [6] + attribute \src "ls180.v:10304.6-10304.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10305$31_ADDR[8:0]$2919 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10305$31_DATA[63:0]$2920 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10305$31_EN[63:0]$2921 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10306.2-10307.59" + switch \main_sram2_we [7] + attribute \src "ls180.v:10306.6-10306.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10307$32_ADDR[8:0]$2922 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10307$32_DATA[63:0]$2923 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10307$32_EN[63:0]$2924 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_3 $0\memadr_3[8:0] + update $memwr$\mem_3$ls180.v:10293$25_ADDR $0$memwr$\mem_3$ls180.v:10293$25_ADDR[8:0]$2901 + update $memwr$\mem_3$ls180.v:10293$25_DATA $0$memwr$\mem_3$ls180.v:10293$25_DATA[63:0]$2902 + update $memwr$\mem_3$ls180.v:10293$25_EN $0$memwr$\mem_3$ls180.v:10293$25_EN[63:0]$2903 + update $memwr$\mem_3$ls180.v:10295$26_ADDR $0$memwr$\mem_3$ls180.v:10295$26_ADDR[8:0]$2904 + update $memwr$\mem_3$ls180.v:10295$26_DATA $0$memwr$\mem_3$ls180.v:10295$26_DATA[63:0]$2905 + update $memwr$\mem_3$ls180.v:10295$26_EN $0$memwr$\mem_3$ls180.v:10295$26_EN[63:0]$2906 + update $memwr$\mem_3$ls180.v:10297$27_ADDR $0$memwr$\mem_3$ls180.v:10297$27_ADDR[8:0]$2907 + update $memwr$\mem_3$ls180.v:10297$27_DATA $0$memwr$\mem_3$ls180.v:10297$27_DATA[63:0]$2908 + update $memwr$\mem_3$ls180.v:10297$27_EN $0$memwr$\mem_3$ls180.v:10297$27_EN[63:0]$2909 + update $memwr$\mem_3$ls180.v:10299$28_ADDR $0$memwr$\mem_3$ls180.v:10299$28_ADDR[8:0]$2910 + update $memwr$\mem_3$ls180.v:10299$28_DATA $0$memwr$\mem_3$ls180.v:10299$28_DATA[63:0]$2911 + update $memwr$\mem_3$ls180.v:10299$28_EN $0$memwr$\mem_3$ls180.v:10299$28_EN[63:0]$2912 + update $memwr$\mem_3$ls180.v:10301$29_ADDR $0$memwr$\mem_3$ls180.v:10301$29_ADDR[8:0]$2913 + update $memwr$\mem_3$ls180.v:10301$29_DATA $0$memwr$\mem_3$ls180.v:10301$29_DATA[63:0]$2914 + update $memwr$\mem_3$ls180.v:10301$29_EN $0$memwr$\mem_3$ls180.v:10301$29_EN[63:0]$2915 + update $memwr$\mem_3$ls180.v:10303$30_ADDR $0$memwr$\mem_3$ls180.v:10303$30_ADDR[8:0]$2916 + update $memwr$\mem_3$ls180.v:10303$30_DATA $0$memwr$\mem_3$ls180.v:10303$30_DATA[63:0]$2917 + update $memwr$\mem_3$ls180.v:10303$30_EN $0$memwr$\mem_3$ls180.v:10303$30_EN[63:0]$2918 + update $memwr$\mem_3$ls180.v:10305$31_ADDR $0$memwr$\mem_3$ls180.v:10305$31_ADDR[8:0]$2919 + update $memwr$\mem_3$ls180.v:10305$31_DATA $0$memwr$\mem_3$ls180.v:10305$31_DATA[63:0]$2920 + update $memwr$\mem_3$ls180.v:10305$31_EN $0$memwr$\mem_3$ls180.v:10305$31_EN[63:0]$2921 + update $memwr$\mem_3$ls180.v:10307$32_ADDR $0$memwr$\mem_3$ls180.v:10307$32_ADDR[8:0]$2922 + update $memwr$\mem_3$ls180.v:10307$32_DATA $0$memwr$\mem_3$ls180.v:10307$32_DATA[63:0]$2923 + update $memwr$\mem_3$ls180.v:10307$32_EN $0$memwr$\mem_3$ls180.v:10307$32_EN[63:0]$2924 + end + attribute \src "ls180.v:10319.1-10323.4" + process $proc$ls180.v:10319$2926 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10321$33_ADDR[2:0]$2927 3'xxx + assign $0$memwr$\storage$ls180.v:10321$33_DATA[24:0]$2928 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10321$33_EN[24:0]$2929 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10322$2930_DATA + attribute \src "ls180.v:10320.2-10321.129" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10064.6-10064.60" + attribute \src "ls180.v:10320.6-10320.60" case 1'1 - assign $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 25'1111111111111111111111111 + assign $0$memwr$\storage$ls180.v:10321$33_ADDR[2:0]$2927 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10321$33_DATA[24:0]$2928 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10321$33_EN[24:0]$2929 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10065$5_ADDR $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 - update $memwr$\storage$ls180.v:10065$5_DATA $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 - update $memwr$\storage$ls180.v:10065$5_EN $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 + update $memwr$\storage$ls180.v:10321$33_ADDR $0$memwr$\storage$ls180.v:10321$33_ADDR[2:0]$2927 + update $memwr$\storage$ls180.v:10321$33_DATA $0$memwr$\storage$ls180.v:10321$33_DATA[24:0]$2928 + update $memwr$\storage$ls180.v:10321$33_EN $0$memwr$\storage$ls180.v:10321$33_EN[24:0]$2929 end - attribute \src "ls180.v:10069.1-10070.4" - process $proc$ls180.v:10069$2699 + attribute \src "ls180.v:10325.1-10326.4" + process $proc$ls180.v:10325$2931 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10077.1-10081.4" - process $proc$ls180.v:10077$2701 + attribute \src "ls180.v:10333.1-10337.4" + process $proc$ls180.v:10333$2933 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 3'xxx - assign $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10080$2705_DATA - attribute \src "ls180.v:10078.2-10079.131" + assign $0$memwr$\storage_1$ls180.v:10335$34_ADDR[2:0]$2934 3'xxx + assign $0$memwr$\storage_1$ls180.v:10335$34_DATA[24:0]$2935 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10335$34_EN[24:0]$2936 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10336$2937_DATA + attribute \src "ls180.v:10334.2-10335.131" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10078.6-10078.60" + attribute \src "ls180.v:10334.6-10334.60" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 25'1111111111111111111111111 + assign $0$memwr$\storage_1$ls180.v:10335$34_ADDR[2:0]$2934 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10335$34_DATA[24:0]$2935 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10335$34_EN[24:0]$2936 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10079$6_ADDR $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 - update $memwr$\storage_1$ls180.v:10079$6_DATA $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 - update $memwr$\storage_1$ls180.v:10079$6_EN $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 + update $memwr$\storage_1$ls180.v:10335$34_ADDR $0$memwr$\storage_1$ls180.v:10335$34_ADDR[2:0]$2934 + update $memwr$\storage_1$ls180.v:10335$34_DATA $0$memwr$\storage_1$ls180.v:10335$34_DATA[24:0]$2935 + update $memwr$\storage_1$ls180.v:10335$34_EN $0$memwr$\storage_1$ls180.v:10335$34_EN[24:0]$2936 end - attribute \src "ls180.v:10083.1-10084.4" - process $proc$ls180.v:10083$2706 + attribute \src "ls180.v:10339.1-10340.4" + process $proc$ls180.v:10339$2938 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1009.5-1009.36" - process $proc$ls180.v:1009$3133 + attribute \src "ls180.v:1034.5-1034.32" + process $proc$ls180.v:1034$3392 assign { } { } - assign $1\main_spimaster21_storage[0:0] 1'1 + assign $1\main_spimaster2_done[0:0] 1'0 sync always sync init - update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] + update \main_spimaster2_done $1\main_spimaster2_done[0:0] end - attribute \src "ls180.v:10091.1-10095.4" - process $proc$ls180.v:10091$2708 + attribute \src "ls180.v:10347.1-10351.4" + process $proc$ls180.v:10347$2940 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 3'xxx - assign $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10094$2712_DATA - attribute \src "ls180.v:10092.2-10093.131" + assign $0$memwr$\storage_2$ls180.v:10349$35_ADDR[2:0]$2941 3'xxx + assign $0$memwr$\storage_2$ls180.v:10349$35_DATA[24:0]$2942 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10349$35_EN[24:0]$2943 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10350$2944_DATA + attribute \src "ls180.v:10348.2-10349.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10092.6-10092.60" + attribute \src "ls180.v:10348.6-10348.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10349$35_ADDR[2:0]$2941 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10349$35_DATA[24:0]$2942 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10349$35_EN[24:0]$2943 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10093$7_ADDR $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 - update $memwr$\storage_2$ls180.v:10093$7_DATA $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 - update $memwr$\storage_2$ls180.v:10093$7_EN $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 - end - attribute \src "ls180.v:10097.1-10098.4" - process $proc$ls180.v:10097$2713 - sync posedge \sys_clk_1 + update $memwr$\storage_2$ls180.v:10349$35_ADDR $0$memwr$\storage_2$ls180.v:10349$35_ADDR[2:0]$2941 + update $memwr$\storage_2$ls180.v:10349$35_DATA $0$memwr$\storage_2$ls180.v:10349$35_DATA[24:0]$2942 + update $memwr$\storage_2$ls180.v:10349$35_EN $0$memwr$\storage_2$ls180.v:10349$35_EN[24:0]$2943 end - attribute \src "ls180.v:1010.5-1010.31" - process $proc$ls180.v:1010$3134 + attribute \src "ls180.v:1035.5-1035.31" + process $proc$ls180.v:1035$3393 assign { } { } - assign $1\main_spimaster22_re[0:0] 1'0 + assign $1\main_spimaster3_irq[0:0] 1'0 sync always sync init - update \main_spimaster22_re $1\main_spimaster22_re[0:0] + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] end - attribute \src "ls180.v:10105.1-10109.4" - process $proc$ls180.v:10105$2715 + attribute \src "ls180.v:10353.1-10354.4" + process $proc$ls180.v:10353$2945 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10361.1-10365.4" + process $proc$ls180.v:10361$2947 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 3'xxx - assign $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10108$2719_DATA - attribute \src "ls180.v:10106.2-10107.131" + assign $0$memwr$\storage_3$ls180.v:10363$36_ADDR[2:0]$2948 3'xxx + assign $0$memwr$\storage_3$ls180.v:10363$36_DATA[24:0]$2949 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10363$36_EN[24:0]$2950 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10364$2951_DATA + attribute \src "ls180.v:10362.2-10363.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10106.6-10106.60" + attribute \src "ls180.v:10362.6-10362.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10363$36_ADDR[2:0]$2948 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10363$36_DATA[24:0]$2949 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10363$36_EN[24:0]$2950 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10107$8_ADDR $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 - update $memwr$\storage_3$ls180.v:10107$8_DATA $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 - update $memwr$\storage_3$ls180.v:10107$8_EN $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 + update $memwr$\storage_3$ls180.v:10363$36_ADDR $0$memwr$\storage_3$ls180.v:10363$36_ADDR[2:0]$2948 + update $memwr$\storage_3$ls180.v:10363$36_DATA $0$memwr$\storage_3$ls180.v:10363$36_DATA[24:0]$2949 + update $memwr$\storage_3$ls180.v:10363$36_EN $0$memwr$\storage_3$ls180.v:10363$36_EN[24:0]$2950 end - attribute \src "ls180.v:1011.5-1011.36" - process $proc$ls180.v:1011$3135 - assign { } { } - assign $1\main_spimaster23_storage[0:0] 1'0 - sync always - sync init - update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] - end - attribute \src "ls180.v:10111.1-10112.4" - process $proc$ls180.v:10111$2720 + attribute \src "ls180.v:10367.1-10368.4" + process $proc$ls180.v:10367$2952 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1012.5-1012.31" - process $proc$ls180.v:1012$3136 + attribute \src "ls180.v:1037.11-1037.38" + process $proc$ls180.v:1037$3394 assign { } { } - assign $1\main_spimaster24_re[0:0] 1'0 + assign $1\main_spimaster5_miso[7:0] 8'00000000 sync always sync init - update \main_spimaster24_re $1\main_spimaster24_re[0:0] + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] end - attribute \src "ls180.v:10120.1-10124.4" - process $proc$ls180.v:10120$2722 + attribute \src "ls180.v:10376.1-10380.4" + process $proc$ls180.v:10376$2954 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10123$2726_DATA - attribute \src "ls180.v:10121.2-10122.77" + assign $0$memwr$\storage_4$ls180.v:10378$37_ADDR[3:0]$2955 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10378$37_DATA[9:0]$2956 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10378$37_EN[9:0]$2957 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10379$2958_DATA + attribute \src "ls180.v:10377.2-10378.77" switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10121.6-10121.33" + attribute \src "ls180.v:10377.6-10377.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10378$37_ADDR[3:0]$2955 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10378$37_DATA[9:0]$2956 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10378$37_EN[9:0]$2957 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10122$9_ADDR $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 - update $memwr$\storage_4$ls180.v:10122$9_DATA $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 - update $memwr$\storage_4$ls180.v:10122$9_EN $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 + update $memwr$\storage_4$ls180.v:10378$37_ADDR $0$memwr$\storage_4$ls180.v:10378$37_ADDR[3:0]$2955 + update $memwr$\storage_4$ls180.v:10378$37_DATA $0$memwr$\storage_4$ls180.v:10378$37_DATA[9:0]$2956 + update $memwr$\storage_4$ls180.v:10378$37_EN $0$memwr$\storage_4$ls180.v:10378$37_EN[9:0]$2957 end - attribute \src "ls180.v:10126.1-10129.4" - process $proc$ls180.v:10126$2727 + attribute \src "ls180.v:10382.1-10385.4" + process $proc$ls180.v:10382$2959 assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10127.2-10128.55" + attribute \src "ls180.v:10383.2-10384.55" switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10127.6-10127.33" + attribute \src "ls180.v:10383.6-10383.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10128$2728_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10384$2960_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end - attribute \src "ls180.v:1013.5-1013.39" - process $proc$ls180.v:1013$3137 - assign { } { } - assign $1\main_spimaster25_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] - end - attribute \src "ls180.v:10137.1-10141.4" - process $proc$ls180.v:10137$2729 + attribute \src "ls180.v:10393.1-10397.4" + process $proc$ls180.v:10393$2961 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10140$2733_DATA - attribute \src "ls180.v:10138.2-10139.77" + assign $0$memwr$\storage_5$ls180.v:10395$38_ADDR[3:0]$2962 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10395$38_DATA[9:0]$2963 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10395$38_EN[9:0]$2964 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10396$2965_DATA + attribute \src "ls180.v:10394.2-10395.77" switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10138.6-10138.33" + attribute \src "ls180.v:10394.6-10394.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10395$38_ADDR[3:0]$2962 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10395$38_DATA[9:0]$2963 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10395$38_EN[9:0]$2964 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10139$10_ADDR $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 - update $memwr$\storage_5$ls180.v:10139$10_DATA $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 - update $memwr$\storage_5$ls180.v:10139$10_EN $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 + update $memwr$\storage_5$ls180.v:10395$38_ADDR $0$memwr$\storage_5$ls180.v:10395$38_ADDR[3:0]$2962 + update $memwr$\storage_5$ls180.v:10395$38_DATA $0$memwr$\storage_5$ls180.v:10395$38_DATA[9:0]$2963 + update $memwr$\storage_5$ls180.v:10395$38_EN $0$memwr$\storage_5$ls180.v:10395$38_EN[9:0]$2964 end - attribute \src "ls180.v:1014.5-1014.38" - process $proc$ls180.v:1014$3138 - assign { } { } - assign $1\main_spimaster26_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] - end - attribute \src "ls180.v:10143.1-10146.4" - process $proc$ls180.v:10143$2734 + attribute \src "ls180.v:10399.1-10402.4" + process $proc$ls180.v:10399$2966 assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10144.2-10145.55" + attribute \src "ls180.v:10400.2-10401.55" switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10144.6-10144.33" + attribute \src "ls180.v:10400.6-10400.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10145$2735_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10401$2967_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end - attribute \src "ls180.v:1015.11-1015.40" - process $proc$ls180.v:1015$3139 + attribute \src "ls180.v:104.5-104.49" + process $proc$ls180.v:104$3044 assign { } { } - assign $1\main_spimaster27_count[2:0] 3'000 + assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 sync always sync init - update \main_spimaster27_count $1\main_spimaster27_count[2:0] + update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] end - attribute \src "ls180.v:10153.1-10157.4" - process $proc$ls180.v:10153$2736 + attribute \src "ls180.v:1040.12-1040.47" + process $proc$ls180.v:1040$3395 + assign { } { } + assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 + sync always + update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] + sync init + end + attribute \src "ls180.v:10409.1-10413.4" + process $proc$ls180.v:10409$2968 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10156$2740_DATA - attribute \src "ls180.v:10154.2-10155.85" + assign $0$memwr$\storage_6$ls180.v:10411$39_ADDR[4:0]$2969 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10411$39_DATA[9:0]$2970 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10411$39_EN[9:0]$2971 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10412$2972_DATA + attribute \src "ls180.v:10410.2-10411.85" switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10154.6-10154.37" + attribute \src "ls180.v:10410.6-10410.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10411$39_ADDR[4:0]$2969 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10411$39_DATA[9:0]$2970 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10411$39_EN[9:0]$2971 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10155$11_ADDR $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 - update $memwr$\storage_6$ls180.v:10155$11_DATA $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 - update $memwr$\storage_6$ls180.v:10155$11_EN $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 + update $memwr$\storage_6$ls180.v:10411$39_ADDR $0$memwr$\storage_6$ls180.v:10411$39_ADDR[4:0]$2969 + update $memwr$\storage_6$ls180.v:10411$39_DATA $0$memwr$\storage_6$ls180.v:10411$39_DATA[9:0]$2970 + update $memwr$\storage_6$ls180.v:10411$39_EN $0$memwr$\storage_6$ls180.v:10411$39_EN[9:0]$2971 end - attribute \src "ls180.v:10159.1-10160.4" - process $proc$ls180.v:10159$2741 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1016.5-1016.39" - process $proc$ls180.v:1016$3140 + attribute \src "ls180.v:1041.5-1041.33" + process $proc$ls180.v:1041$3396 assign { } { } - assign $1\main_spimaster28_mosi_latch[0:0] 1'0 + assign $1\main_spimaster9_start[0:0] 1'0 sync always sync init - update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] + update \main_spimaster9_start $1\main_spimaster9_start[0:0] end - attribute \src "ls180.v:10167.1-10171.4" - process $proc$ls180.v:10167$2743 + attribute \src "ls180.v:10415.1-10416.4" + process $proc$ls180.v:10415$2973 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10423.1-10427.4" + process $proc$ls180.v:10423$2975 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10170$2747_DATA - attribute \src "ls180.v:10168.2-10169.85" + assign $0$memwr$\storage_7$ls180.v:10425$40_ADDR[4:0]$2976 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10425$40_DATA[9:0]$2977 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10425$40_EN[9:0]$2978 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10426$2979_DATA + attribute \src "ls180.v:10424.2-10425.85" switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10168.6-10168.37" + attribute \src "ls180.v:10424.6-10424.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10425$40_ADDR[4:0]$2976 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10425$40_DATA[9:0]$2977 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10425$40_EN[9:0]$2978 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10169$12_ADDR $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 - update $memwr$\storage_7$ls180.v:10169$12_DATA $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 - update $memwr$\storage_7$ls180.v:10169$12_EN $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 + update $memwr$\storage_7$ls180.v:10425$40_ADDR $0$memwr$\storage_7$ls180.v:10425$40_ADDR[4:0]$2976 + update $memwr$\storage_7$ls180.v:10425$40_DATA $0$memwr$\storage_7$ls180.v:10425$40_DATA[9:0]$2977 + update $memwr$\storage_7$ls180.v:10425$40_EN $0$memwr$\storage_7$ls180.v:10425$40_EN[9:0]$2978 + end + attribute \src "ls180.v:10429.1-10430.4" + process $proc$ls180.v:10429$2980 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1043.12-1043.44" + process $proc$ls180.v:1043$3397 + assign { } { } + assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] + end + attribute \src "ls180.v:1044.5-1044.31" + process $proc$ls180.v:1044$3398 + assign { } { } + assign $1\main_spimaster12_re[0:0] 1'0 + sync always + sync init + update \main_spimaster12_re $1\main_spimaster12_re[0:0] end - attribute \src "ls180.v:1017.5-1017.39" - process $proc$ls180.v:1017$3141 + attribute \src "ls180.v:1048.11-1048.42" + process $proc$ls180.v:1048$3399 + assign { } { } + assign $1\main_spimaster16_storage[7:0] 8'00000000 + sync always + sync init + update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] + end + attribute \src "ls180.v:1049.5-1049.31" + process $proc$ls180.v:1049$3400 + assign { } { } + assign $1\main_spimaster17_re[0:0] 1'0 + sync always + sync init + update \main_spimaster17_re $1\main_spimaster17_re[0:0] + end + attribute \src "ls180.v:1053.5-1053.36" + process $proc$ls180.v:1053$3401 + assign { } { } + assign $1\main_spimaster21_storage[0:0] 1'1 + sync always + sync init + update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] + end + attribute \src "ls180.v:1054.5-1054.31" + process $proc$ls180.v:1054$3402 + assign { } { } + assign $1\main_spimaster22_re[0:0] 1'0 + sync always + sync init + update \main_spimaster22_re $1\main_spimaster22_re[0:0] + end + attribute \src "ls180.v:1055.5-1055.36" + process $proc$ls180.v:1055$3403 + assign { } { } + assign $1\main_spimaster23_storage[0:0] 1'0 + sync always + sync init + update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] + end + attribute \src "ls180.v:1056.5-1056.31" + process $proc$ls180.v:1056$3404 + assign { } { } + assign $1\main_spimaster24_re[0:0] 1'0 + sync always + sync init + update \main_spimaster24_re $1\main_spimaster24_re[0:0] + end + attribute \src "ls180.v:1057.5-1057.39" + process $proc$ls180.v:1057$3405 + assign { } { } + assign $1\main_spimaster25_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] + end + attribute \src "ls180.v:1058.5-1058.38" + process $proc$ls180.v:1058$3406 + assign { } { } + assign $1\main_spimaster26_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] + end + attribute \src "ls180.v:1059.11-1059.40" + process $proc$ls180.v:1059$3407 + assign { } { } + assign $1\main_spimaster27_count[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count $1\main_spimaster27_count[2:0] + end + attribute \src "ls180.v:1060.5-1060.39" + process $proc$ls180.v:1060$3408 + assign { } { } + assign $1\main_spimaster28_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] + end + attribute \src "ls180.v:1061.5-1061.39" + process $proc$ls180.v:1061$3409 assign { } { } assign $1\main_spimaster29_miso_latch[0:0] 1'0 sync always sync init update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] end - attribute \src "ls180.v:10173.1-10174.4" - process $proc$ls180.v:10173$2748 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1018.12-1018.48" - process $proc$ls180.v:1018$3142 + attribute \src "ls180.v:1062.12-1062.48" + process $proc$ls180.v:1062$3410 assign { } { } assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 sync always sync init update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] end - attribute \src "ls180.v:1021.11-1021.44" - process $proc$ls180.v:1021$3143 + attribute \src "ls180.v:1065.11-1065.44" + process $proc$ls180.v:1065$3411 assign { } { } assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 sync always sync init update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] end - attribute \src "ls180.v:1022.11-1022.43" - process $proc$ls180.v:1022$3144 + attribute \src "ls180.v:1066.11-1066.43" + process $proc$ls180.v:1066$3412 assign { } { } assign $1\main_spimaster34_mosi_sel[2:0] 3'000 sync always sync init update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] end - attribute \src "ls180.v:1023.11-1023.44" - process $proc$ls180.v:1023$3145 + attribute \src "ls180.v:1067.11-1067.44" + process $proc$ls180.v:1067$3413 assign { } { } assign $1\main_spimaster35_miso_data[7:0] 8'00000000 sync always sync init update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] end - attribute \src "ls180.v:1026.5-1026.32" - process $proc$ls180.v:1026$3146 + attribute \src "ls180.v:1070.5-1070.32" + process $proc$ls180.v:1070$3414 assign { } { } assign $1\main_spisdcard_done0[0:0] 1'0 sync always sync init update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] end - attribute \src "ls180.v:1027.5-1027.30" - process $proc$ls180.v:1027$3147 + attribute \src "ls180.v:1071.5-1071.30" + process $proc$ls180.v:1071$3415 assign { } { } assign $1\main_spisdcard_irq[0:0] 1'0 sync always sync init update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] end - attribute \src "ls180.v:1029.11-1029.37" - process $proc$ls180.v:1029$3148 + attribute \src "ls180.v:1073.11-1073.37" + process $proc$ls180.v:1073$3416 assign { } { } assign $1\main_spisdcard_miso[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] end - attribute \src "ls180.v:1033.5-1033.33" - process $proc$ls180.v:1033$3149 + attribute \src "ls180.v:1077.5-1077.33" + process $proc$ls180.v:1077$3417 assign { } { } assign $1\main_spisdcard_start1[0:0] 1'0 sync always sync init update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] end - attribute \src "ls180.v:1035.12-1035.50" - process $proc$ls180.v:1035$3150 + attribute \src "ls180.v:1079.12-1079.50" + process $proc$ls180.v:1079$3418 assign { } { } assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] end - attribute \src "ls180.v:1036.5-1036.37" - process $proc$ls180.v:1036$3151 + attribute \src "ls180.v:1080.5-1080.37" + process $proc$ls180.v:1080$3419 assign { } { } assign $1\main_spisdcard_control_re[0:0] 1'0 sync always sync init update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] end - attribute \src "ls180.v:1040.11-1040.45" - process $proc$ls180.v:1040$3152 + attribute \src "ls180.v:1084.11-1084.45" + process $proc$ls180.v:1084$3420 assign { } { } assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] end - attribute \src "ls180.v:1041.5-1041.34" - process $proc$ls180.v:1041$3153 + attribute \src "ls180.v:1085.5-1085.34" + process $proc$ls180.v:1085$3421 assign { } { } assign $1\main_spisdcard_mosi_re[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] end - attribute \src "ls180.v:1045.5-1045.37" - process $proc$ls180.v:1045$3154 + attribute \src "ls180.v:1089.5-1089.37" + process $proc$ls180.v:1089$3422 assign { } { } assign $1\main_spisdcard_cs_storage[0:0] 1'1 sync always sync init update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] end - attribute \src "ls180.v:1046.5-1046.32" - process $proc$ls180.v:1046$3155 + attribute \src "ls180.v:1090.5-1090.32" + process $proc$ls180.v:1090$3423 assign { } { } assign $1\main_spisdcard_cs_re[0:0] 1'0 sync always sync init update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] end - attribute \src "ls180.v:1047.5-1047.43" - process $proc$ls180.v:1047$3156 + attribute \src "ls180.v:1091.5-1091.43" + process $proc$ls180.v:1091$3424 assign { } { } assign $1\main_spisdcard_loopback_storage[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] end - attribute \src "ls180.v:1048.5-1048.38" - process $proc$ls180.v:1048$3157 + attribute \src "ls180.v:1092.5-1092.38" + process $proc$ls180.v:1092$3425 assign { } { } assign $1\main_spisdcard_loopback_re[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] end - attribute \src "ls180.v:1049.5-1049.37" - process $proc$ls180.v:1049$3158 + attribute \src "ls180.v:1093.5-1093.37" + process $proc$ls180.v:1093$3426 assign { } { } assign $1\main_spisdcard_clk_enable[0:0] 1'0 sync always sync init update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] end - attribute \src "ls180.v:1050.5-1050.36" - process $proc$ls180.v:1050$3159 + attribute \src "ls180.v:1094.5-1094.36" + process $proc$ls180.v:1094$3427 assign { } { } assign $1\main_spisdcard_cs_enable[0:0] 1'0 sync always sync init update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] end - attribute \src "ls180.v:1051.11-1051.38" - process $proc$ls180.v:1051$3160 + attribute \src "ls180.v:1095.11-1095.38" + process $proc$ls180.v:1095$3428 assign { } { } assign $1\main_spisdcard_count[2:0] 3'000 sync always sync init update \main_spisdcard_count $1\main_spisdcard_count[2:0] end - attribute \src "ls180.v:1052.5-1052.37" - process $proc$ls180.v:1052$3161 + attribute \src "ls180.v:1096.5-1096.37" + process $proc$ls180.v:1096$3429 assign { } { } assign $1\main_spisdcard_mosi_latch[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] end - attribute \src "ls180.v:1053.5-1053.37" - process $proc$ls180.v:1053$3162 + attribute \src "ls180.v:1097.5-1097.37" + process $proc$ls180.v:1097$3430 assign { } { } assign $1\main_spisdcard_miso_latch[0:0] 1'0 sync always sync init update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] end - attribute \src "ls180.v:1054.12-1054.47" - process $proc$ls180.v:1054$3163 + attribute \src "ls180.v:1098.12-1098.47" + process $proc$ls180.v:1098$3431 assign { } { } assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] end - attribute \src "ls180.v:1057.11-1057.42" - process $proc$ls180.v:1057$3164 + attribute \src "ls180.v:1101.11-1101.42" + process $proc$ls180.v:1101$3432 assign { } { } assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] end - attribute \src "ls180.v:1058.11-1058.41" - process $proc$ls180.v:1058$3165 + attribute \src "ls180.v:1102.11-1102.41" + process $proc$ls180.v:1102$3433 assign { } { } assign $1\main_spisdcard_mosi_sel[2:0] 3'000 sync always sync init update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] end - attribute \src "ls180.v:1059.11-1059.42" - process $proc$ls180.v:1059$3166 + attribute \src "ls180.v:1103.11-1103.42" + process $proc$ls180.v:1103$3434 assign { } { } assign $1\main_spisdcard_miso_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] end - attribute \src "ls180.v:1060.12-1060.45" - process $proc$ls180.v:1060$3167 + attribute \src "ls180.v:1104.12-1104.45" + process $proc$ls180.v:1104$3435 assign { } { } assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 sync always sync init update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] end - attribute \src "ls180.v:1061.5-1061.30" - process $proc$ls180.v:1061$3168 + attribute \src "ls180.v:1105.5-1105.30" + process $proc$ls180.v:1105$3436 assign { } { } assign $1\main_spimaster1_re[0:0] 1'0 sync always sync init update \main_spimaster1_re $1\main_spimaster1_re[0:0] end - attribute \src "ls180.v:1063.12-1063.30" - process $proc$ls180.v:1063$3169 + attribute \src "ls180.v:1107.12-1107.30" + process $proc$ls180.v:1107$3437 assign { } { } assign $1\main_dummy[23:0] 24'000000000000000000000000 sync always sync init update \main_dummy $1\main_dummy[23:0] end - attribute \src "ls180.v:1067.12-1067.37" - process $proc$ls180.v:1067$3170 + attribute \src "ls180.v:1111.12-1111.37" + process $proc$ls180.v:1111$3438 assign { } { } assign $1\main_pwm0_counter[31:0] 0 sync always sync init update \main_pwm0_counter $1\main_pwm0_counter[31:0] end - attribute \src "ls180.v:1068.5-1068.36" - process $proc$ls180.v:1068$3171 + attribute \src "ls180.v:1112.5-1112.36" + process $proc$ls180.v:1112$3439 assign { } { } assign $1\main_pwm0_enable_storage[0:0] 1'0 sync always sync init update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] end - attribute \src "ls180.v:1069.5-1069.31" - process $proc$ls180.v:1069$3172 + attribute \src "ls180.v:1113.5-1113.31" + process $proc$ls180.v:1113$3440 assign { } { } assign $1\main_pwm0_enable_re[0:0] 1'0 sync always sync init update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] end - attribute \src "ls180.v:1070.12-1070.43" - process $proc$ls180.v:1070$3173 + attribute \src "ls180.v:1114.12-1114.43" + process $proc$ls180.v:1114$3441 assign { } { } assign $1\main_pwm0_width_storage[31:0] 0 sync always sync init update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] end - attribute \src "ls180.v:1071.5-1071.30" - process $proc$ls180.v:1071$3174 + attribute \src "ls180.v:1115.5-1115.30" + process $proc$ls180.v:1115$3442 assign { } { } assign $1\main_pwm0_width_re[0:0] 1'0 sync always sync init update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] end - attribute \src "ls180.v:1072.12-1072.44" - process $proc$ls180.v:1072$3175 + attribute \src "ls180.v:1116.12-1116.44" + process $proc$ls180.v:1116$3443 assign { } { } assign $1\main_pwm0_period_storage[31:0] 0 sync always sync init update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] end - attribute \src "ls180.v:1073.5-1073.31" - process $proc$ls180.v:1073$3176 + attribute \src "ls180.v:1117.5-1117.31" + process $proc$ls180.v:1117$3444 assign { } { } assign $1\main_pwm0_period_re[0:0] 1'0 sync always sync init update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] end - attribute \src "ls180.v:1077.12-1077.37" - process $proc$ls180.v:1077$3177 + attribute \src "ls180.v:1121.12-1121.37" + process $proc$ls180.v:1121$3445 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always sync init update \main_pwm1_counter $1\main_pwm1_counter[31:0] end - attribute \src "ls180.v:1078.5-1078.36" - process $proc$ls180.v:1078$3178 + attribute \src "ls180.v:1122.5-1122.36" + process $proc$ls180.v:1122$3446 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always sync init update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end - attribute \src "ls180.v:1079.5-1079.31" - process $proc$ls180.v:1079$3179 + attribute \src "ls180.v:1123.5-1123.31" + process $proc$ls180.v:1123$3447 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always sync init update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end - attribute \src "ls180.v:1080.12-1080.43" - process $proc$ls180.v:1080$3180 + attribute \src "ls180.v:1124.12-1124.43" + process $proc$ls180.v:1124$3448 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always sync init update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end - attribute \src "ls180.v:1081.5-1081.30" - process $proc$ls180.v:1081$3181 + attribute \src "ls180.v:1125.5-1125.30" + process $proc$ls180.v:1125$3449 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always sync init update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end - attribute \src "ls180.v:1082.12-1082.44" - process $proc$ls180.v:1082$3182 + attribute \src "ls180.v:1126.12-1126.44" + process $proc$ls180.v:1126$3450 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always sync init update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end - attribute \src "ls180.v:1083.5-1083.31" - process $proc$ls180.v:1083$3183 + attribute \src "ls180.v:1127.5-1127.31" + process $proc$ls180.v:1127$3451 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always sync init update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end - attribute \src "ls180.v:1087.11-1087.34" - process $proc$ls180.v:1087$3184 + attribute \src "ls180.v:1131.11-1131.34" + process $proc$ls180.v:1131$3452 assign { } { } assign $1\main_i2c_storage[2:0] 3'000 sync always sync init update \main_i2c_storage $1\main_i2c_storage[2:0] end - attribute \src "ls180.v:1088.5-1088.23" - process $proc$ls180.v:1088$3185 + attribute \src "ls180.v:1132.5-1132.23" + process $proc$ls180.v:1132$3453 assign { } { } assign $1\main_i2c_re[0:0] 1'0 sync always sync init update \main_i2c_re $1\main_i2c_re[0:0] end - attribute \src "ls180.v:1094.11-1094.46" - process $proc$ls180.v:1094$3186 + attribute \src "ls180.v:1138.11-1138.46" + process $proc$ls180.v:1138$3454 assign { } { } assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always sync init update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end - attribute \src "ls180.v:1095.5-1095.33" - process $proc$ls180.v:1095$3187 + attribute \src "ls180.v:1139.5-1139.33" + process $proc$ls180.v:1139$3455 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always sync init update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end - attribute \src "ls180.v:1097.5-1097.35" - process $proc$ls180.v:1097$3188 + attribute \src "ls180.v:114.11-114.55" + process $proc$ls180.v:114$3045 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + sync init + end + attribute \src "ls180.v:1141.5-1141.35" + process $proc$ls180.v:1141$3456 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end - attribute \src "ls180.v:1099.11-1099.41" - process $proc$ls180.v:1099$3189 + attribute \src "ls180.v:1143.11-1143.41" + process $proc$ls180.v:1143$3457 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always sync init update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end - attribute \src "ls180.v:1100.5-1100.35" - process $proc$ls180.v:1100$3190 + attribute \src "ls180.v:1144.5-1144.35" + process $proc$ls180.v:1144$3458 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:1101.5-1101.36" - process $proc$ls180.v:1101$3191 + attribute \src "ls180.v:1145.5-1145.36" + process $proc$ls180.v:1145$3459 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end - attribute \src "ls180.v:1105.5-1105.40" - process $proc$ls180.v:1105$3192 + attribute \src "ls180.v:1149.5-1149.40" + process $proc$ls180.v:1149$3460 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] sync init end - attribute \src "ls180.v:1110.5-1110.48" - process $proc$ls180.v:1110$3193 + attribute \src "ls180.v:115.11-115.55" + process $proc$ls180.v:115$3046 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + sync init + end + attribute \src "ls180.v:1154.5-1154.48" + process $proc$ls180.v:1154$3461 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1111.5-1111.50" - process $proc$ls180.v:1111$3194 + attribute \src "ls180.v:1155.5-1155.50" + process $proc$ls180.v:1155$3462 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1112.5-1112.51" - process $proc$ls180.v:1112$3195 + attribute \src "ls180.v:1156.5-1156.51" + process $proc$ls180.v:1156$3463 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1113.11-1113.57" - process $proc$ls180.v:1113$3196 + attribute \src "ls180.v:1157.11-1157.57" + process $proc$ls180.v:1157$3464 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1114.5-1114.52" - process $proc$ls180.v:1114$3197 + attribute \src "ls180.v:1158.5-1158.52" + process $proc$ls180.v:1158$3465 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1115.11-1115.39" - process $proc$ls180.v:1115$3198 + attribute \src "ls180.v:1159.11-1159.39" + process $proc$ls180.v:1159$3466 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end - attribute \src "ls180.v:112.5-112.49" - process $proc$ls180.v:112$2773 - assign { } { } - assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - end - attribute \src "ls180.v:1120.5-1120.48" - process $proc$ls180.v:1120$3199 + attribute \src "ls180.v:1164.5-1164.48" + process $proc$ls180.v:1164$3467 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1121.5-1121.50" - process $proc$ls180.v:1121$3200 + attribute \src "ls180.v:1165.5-1165.50" + process $proc$ls180.v:1165$3468 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1122.5-1122.51" - process $proc$ls180.v:1122$3201 + attribute \src "ls180.v:1166.5-1166.51" + process $proc$ls180.v:1166$3469 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1123.11-1123.57" - process $proc$ls180.v:1123$3202 + attribute \src "ls180.v:1167.11-1167.57" + process $proc$ls180.v:1167$3470 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1124.5-1124.52" - process $proc$ls180.v:1124$3203 + attribute \src "ls180.v:1168.5-1168.52" + process $proc$ls180.v:1168$3471 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1125.5-1125.38" - process $proc$ls180.v:1125$3204 + attribute \src "ls180.v:1169.5-1169.38" + process $proc$ls180.v:1169$3472 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end - attribute \src "ls180.v:1126.5-1126.38" - process $proc$ls180.v:1126$3205 + attribute \src "ls180.v:1170.5-1170.38" + process $proc$ls180.v:1170$3473 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end - attribute \src "ls180.v:1127.5-1127.37" - process $proc$ls180.v:1127$3206 + attribute \src "ls180.v:1171.5-1171.37" + process $proc$ls180.v:1171$3474 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end - attribute \src "ls180.v:1128.11-1128.51" - process $proc$ls180.v:1128$3207 + attribute \src "ls180.v:1172.11-1172.51" + process $proc$ls180.v:1172$3475 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end - attribute \src "ls180.v:1129.5-1129.32" - process $proc$ls180.v:1129$3208 + attribute \src "ls180.v:1173.5-1173.32" + process $proc$ls180.v:1173$3476 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end - attribute \src "ls180.v:1130.11-1130.39" - process $proc$ls180.v:1130$3209 + attribute \src "ls180.v:1174.11-1174.39" + process $proc$ls180.v:1174$3477 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end - attribute \src "ls180.v:1133.5-1133.49" - process $proc$ls180.v:1133$3210 + attribute \src "ls180.v:1177.5-1177.49" + process $proc$ls180.v:1177$3478 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1134.5-1134.48" - process $proc$ls180.v:1134$3211 + attribute \src "ls180.v:1178.5-1178.48" + process $proc$ls180.v:1178$3479 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1135.5-1135.55" - process $proc$ls180.v:1135$3212 + attribute \src "ls180.v:1179.5-1179.55" + process $proc$ls180.v:1179$3480 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1137.5-1137.57" - process $proc$ls180.v:1137$3213 + attribute \src "ls180.v:1181.5-1181.57" + process $proc$ls180.v:1181$3481 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1138.5-1138.58" - process $proc$ls180.v:1138$3214 + attribute \src "ls180.v:1182.5-1182.58" + process $proc$ls180.v:1182$3482 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:114.5-114.49" - process $proc$ls180.v:114$2774 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - sync init - end - attribute \src "ls180.v:1140.11-1140.64" - process $proc$ls180.v:1140$3215 + attribute \src "ls180.v:1184.11-1184.64" + process $proc$ls180.v:1184$3483 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1141.5-1141.59" - process $proc$ls180.v:1141$3216 + attribute \src "ls180.v:1185.5-1185.59" + process $proc$ls180.v:1185$3484 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1143.5-1143.48" - process $proc$ls180.v:1143$3217 + attribute \src "ls180.v:1187.5-1187.48" + process $proc$ls180.v:1187$3485 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1144.5-1144.50" - process $proc$ls180.v:1144$3218 + attribute \src "ls180.v:1188.5-1188.50" + process $proc$ls180.v:1188$3486 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1145.5-1145.51" - process $proc$ls180.v:1145$3219 + attribute \src "ls180.v:1189.5-1189.51" + process $proc$ls180.v:1189$3487 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1146.11-1146.57" - process $proc$ls180.v:1146$3220 + attribute \src "ls180.v:1190.11-1190.57" + process $proc$ls180.v:1190$3488 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1147.5-1147.52" - process $proc$ls180.v:1147$3221 + attribute \src "ls180.v:1191.5-1191.52" + process $proc$ls180.v:1191$3489 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1148.5-1148.38" - process $proc$ls180.v:1148$3222 + attribute \src "ls180.v:1192.5-1192.38" + process $proc$ls180.v:1192$3490 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end - attribute \src "ls180.v:1149.5-1149.38" - process $proc$ls180.v:1149$3223 + attribute \src "ls180.v:1193.5-1193.38" + process $proc$ls180.v:1193$3491 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end - attribute \src "ls180.v:1150.5-1150.37" - process $proc$ls180.v:1150$3224 + attribute \src "ls180.v:1194.5-1194.37" + process $proc$ls180.v:1194$3492 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end - attribute \src "ls180.v:1151.11-1151.53" - process $proc$ls180.v:1151$3225 + attribute \src "ls180.v:1195.11-1195.53" + process $proc$ls180.v:1195$3493 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end - attribute \src "ls180.v:1152.5-1152.40" - process $proc$ls180.v:1152$3226 + attribute \src "ls180.v:1196.5-1196.40" + process $proc$ls180.v:1196$3494 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end - attribute \src "ls180.v:1153.5-1153.40" - process $proc$ls180.v:1153$3227 + attribute \src "ls180.v:1197.5-1197.40" + process $proc$ls180.v:1197$3495 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end - attribute \src "ls180.v:1154.5-1154.39" - process $proc$ls180.v:1154$3228 + attribute \src "ls180.v:1198.5-1198.39" + process $proc$ls180.v:1198$3496 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end - attribute \src "ls180.v:1155.11-1155.53" - process $proc$ls180.v:1155$3229 + attribute \src "ls180.v:1199.11-1199.53" + process $proc$ls180.v:1199$3497 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end - attribute \src "ls180.v:1156.11-1156.55" - process $proc$ls180.v:1156$3230 + attribute \src "ls180.v:1200.11-1200.55" + process $proc$ls180.v:1200$3498 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end - attribute \src "ls180.v:1157.12-1157.48" - process $proc$ls180.v:1157$3231 + attribute \src "ls180.v:1201.12-1201.48" + process $proc$ls180.v:1201$3499 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always sync init update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end - attribute \src "ls180.v:1158.11-1158.39" - process $proc$ls180.v:1158$3232 + attribute \src "ls180.v:1202.11-1202.39" + process $proc$ls180.v:1202$3500 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end - attribute \src "ls180.v:1160.5-1160.46" - process $proc$ls180.v:1160$3233 + attribute \src "ls180.v:1204.5-1204.46" + process $proc$ls180.v:1204$3501 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1171.5-1171.53" - process $proc$ls180.v:1171$3234 + attribute \src "ls180.v:1215.5-1215.53" + process $proc$ls180.v:1215$3502 assign { } { } assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end - attribute \src "ls180.v:1176.5-1176.36" - process $proc$ls180.v:1176$3235 + attribute \src "ls180.v:1220.5-1220.36" + process $proc$ls180.v:1220$3503 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end - attribute \src "ls180.v:1179.5-1179.53" - process $proc$ls180.v:1179$3236 + attribute \src "ls180.v:1223.5-1223.53" + process $proc$ls180.v:1223$3504 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1180.5-1180.52" - process $proc$ls180.v:1180$3237 + attribute \src "ls180.v:1224.5-1224.52" + process $proc$ls180.v:1224$3505 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1184.5-1184.55" - process $proc$ls180.v:1184$3238 + attribute \src "ls180.v:1228.5-1228.55" + process $proc$ls180.v:1228$3506 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end - attribute \src "ls180.v:1185.5-1185.54" - process $proc$ls180.v:1185$3239 + attribute \src "ls180.v:1229.5-1229.54" + process $proc$ls180.v:1229$3507 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end - attribute \src "ls180.v:1186.11-1186.68" - process $proc$ls180.v:1186$3240 + attribute \src "ls180.v:1230.11-1230.68" + process $proc$ls180.v:1230$3508 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1187.11-1187.81" - process $proc$ls180.v:1187$3241 + attribute \src "ls180.v:1231.11-1231.81" + process $proc$ls180.v:1231$3509 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1188.11-1188.54" - process $proc$ls180.v:1188$3242 + attribute \src "ls180.v:1232.11-1232.54" + process $proc$ls180.v:1232$3510 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end - attribute \src "ls180.v:1190.5-1190.53" - process $proc$ls180.v:1190$3243 + attribute \src "ls180.v:1234.5-1234.53" + process $proc$ls180.v:1234$3511 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1201.5-1201.49" - process $proc$ls180.v:1201$3244 + attribute \src "ls180.v:1245.5-1245.49" + process $proc$ls180.v:1245$3512 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end - attribute \src "ls180.v:1203.5-1203.49" - process $proc$ls180.v:1203$3245 + attribute \src "ls180.v:1247.5-1247.49" + process $proc$ls180.v:1247$3513 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end - attribute \src "ls180.v:1204.5-1204.48" - process $proc$ls180.v:1204$3246 + attribute \src "ls180.v:1248.5-1248.48" + process $proc$ls180.v:1248$3514 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end - attribute \src "ls180.v:1205.11-1205.62" - process $proc$ls180.v:1205$3247 + attribute \src "ls180.v:1249.11-1249.62" + process $proc$ls180.v:1249$3515 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1206.5-1206.38" - process $proc$ls180.v:1206$3248 + attribute \src "ls180.v:1250.5-1250.38" + process $proc$ls180.v:1250$3516 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end - attribute \src "ls180.v:1211.5-1211.49" - process $proc$ls180.v:1211$3249 + attribute \src "ls180.v:1255.5-1255.49" + process $proc$ls180.v:1255$3517 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1212.5-1212.51" - process $proc$ls180.v:1212$3250 + attribute \src "ls180.v:1256.5-1256.51" + process $proc$ls180.v:1256$3518 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1213.5-1213.52" - process $proc$ls180.v:1213$3251 + attribute \src "ls180.v:1257.5-1257.52" + process $proc$ls180.v:1257$3519 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1214.11-1214.58" - process $proc$ls180.v:1214$3252 + attribute \src "ls180.v:1258.11-1258.58" + process $proc$ls180.v:1258$3520 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1215.5-1215.53" - process $proc$ls180.v:1215$3253 + attribute \src "ls180.v:1259.5-1259.53" + process $proc$ls180.v:1259$3521 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1216.5-1216.39" - process $proc$ls180.v:1216$3254 + attribute \src "ls180.v:1260.5-1260.39" + process $proc$ls180.v:1260$3522 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end - attribute \src "ls180.v:1217.5-1217.39" - process $proc$ls180.v:1217$3255 + attribute \src "ls180.v:1261.5-1261.39" + process $proc$ls180.v:1261$3523 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end - attribute \src "ls180.v:1218.5-1218.39" - process $proc$ls180.v:1218$3256 + attribute \src "ls180.v:1262.5-1262.39" + process $proc$ls180.v:1262$3524 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end - attribute \src "ls180.v:1219.5-1219.38" - process $proc$ls180.v:1219$3257 + attribute \src "ls180.v:1263.5-1263.38" + process $proc$ls180.v:1263$3525 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end - attribute \src "ls180.v:1220.11-1220.52" - process $proc$ls180.v:1220$3258 + attribute \src "ls180.v:1264.11-1264.52" + process $proc$ls180.v:1264$3526 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end - attribute \src "ls180.v:1221.5-1221.33" - process $proc$ls180.v:1221$3259 + attribute \src "ls180.v:1265.5-1265.33" + process $proc$ls180.v:1265$3527 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always sync init update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end - attribute \src "ls180.v:1222.11-1222.40" - process $proc$ls180.v:1222$3260 + attribute \src "ls180.v:1266.11-1266.40" + process $proc$ls180.v:1266$3528 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end - attribute \src "ls180.v:1223.5-1223.50" - process $proc$ls180.v:1223$3261 + attribute \src "ls180.v:1267.5-1267.50" + process $proc$ls180.v:1267$3529 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] sync init end - attribute \src "ls180.v:1225.5-1225.50" - process $proc$ls180.v:1225$3262 + attribute \src "ls180.v:1269.5-1269.50" + process $proc$ls180.v:1269$3530 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1226.5-1226.49" - process $proc$ls180.v:1226$3263 + attribute \src "ls180.v:1270.5-1270.49" + process $proc$ls180.v:1270$3531 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1227.5-1227.56" - process $proc$ls180.v:1227$3264 + attribute \src "ls180.v:1271.5-1271.56" + process $proc$ls180.v:1271$3532 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1228.5-1228.58" - process $proc$ls180.v:1228$3265 + attribute \src "ls180.v:1272.5-1272.58" + process $proc$ls180.v:1272$3533 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] sync init end - attribute \src "ls180.v:1229.5-1229.58" - process $proc$ls180.v:1229$3266 + attribute \src "ls180.v:1273.5-1273.58" + process $proc$ls180.v:1273$3534 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1230.5-1230.59" - process $proc$ls180.v:1230$3267 + attribute \src "ls180.v:1274.5-1274.59" + process $proc$ls180.v:1274$3535 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1231.11-1231.65" - process $proc$ls180.v:1231$3268 + attribute \src "ls180.v:1275.11-1275.65" + process $proc$ls180.v:1275$3536 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] sync init end - attribute \src "ls180.v:1232.11-1232.65" - process $proc$ls180.v:1232$3269 + attribute \src "ls180.v:1276.11-1276.65" + process $proc$ls180.v:1276$3537 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1233.5-1233.60" - process $proc$ls180.v:1233$3270 + attribute \src "ls180.v:1277.5-1277.60" + process $proc$ls180.v:1277$3538 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1234.5-1234.34" - process $proc$ls180.v:1234$3271 + attribute \src "ls180.v:1278.5-1278.34" + process $proc$ls180.v:1278$3539 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always sync init update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end - attribute \src "ls180.v:1235.5-1235.34" - process $proc$ls180.v:1235$3272 + attribute \src "ls180.v:1279.5-1279.34" + process $proc$ls180.v:1279$3540 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end - attribute \src "ls180.v:1236.5-1236.34" - process $proc$ls180.v:1236$3273 + attribute \src "ls180.v:1280.5-1280.34" + process $proc$ls180.v:1280$3541 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always sync init update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end - attribute \src "ls180.v:1238.5-1238.47" - process $proc$ls180.v:1238$3274 + attribute \src "ls180.v:1282.5-1282.47" + process $proc$ls180.v:1282$3542 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1249.5-1249.54" - process $proc$ls180.v:1249$3275 + attribute \src "ls180.v:1293.5-1293.54" + process $proc$ls180.v:1293$3543 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end - attribute \src "ls180.v:1254.5-1254.37" - process $proc$ls180.v:1254$3276 + attribute \src "ls180.v:1298.5-1298.37" + process $proc$ls180.v:1298$3544 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end - attribute \src "ls180.v:1257.5-1257.54" - process $proc$ls180.v:1257$3277 + attribute \src "ls180.v:1301.5-1301.54" + process $proc$ls180.v:1301$3545 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1258.5-1258.53" - process $proc$ls180.v:1258$3278 + attribute \src "ls180.v:1302.5-1302.53" + process $proc$ls180.v:1302$3546 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1262.5-1262.56" - process $proc$ls180.v:1262$3279 + attribute \src "ls180.v:1306.5-1306.56" + process $proc$ls180.v:1306$3547 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end - attribute \src "ls180.v:1263.5-1263.55" - process $proc$ls180.v:1263$3280 + attribute \src "ls180.v:1307.5-1307.55" + process $proc$ls180.v:1307$3548 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end - attribute \src "ls180.v:1264.11-1264.69" - process $proc$ls180.v:1264$3281 + attribute \src "ls180.v:1308.11-1308.69" + process $proc$ls180.v:1308$3549 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1265.11-1265.82" - process $proc$ls180.v:1265$3282 + attribute \src "ls180.v:1309.11-1309.82" + process $proc$ls180.v:1309$3550 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1266.11-1266.55" - process $proc$ls180.v:1266$3283 + attribute \src "ls180.v:1310.11-1310.55" + process $proc$ls180.v:1310$3551 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end - attribute \src "ls180.v:1268.5-1268.54" - process $proc$ls180.v:1268$3284 + attribute \src "ls180.v:1312.5-1312.54" + process $proc$ls180.v:1312$3552 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1279.5-1279.50" - process $proc$ls180.v:1279$3285 + attribute \src "ls180.v:1323.5-1323.50" + process $proc$ls180.v:1323$3553 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end - attribute \src "ls180.v:1281.5-1281.50" - process $proc$ls180.v:1281$3286 + attribute \src "ls180.v:1325.5-1325.50" + process $proc$ls180.v:1325$3554 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end - attribute \src "ls180.v:1282.5-1282.49" - process $proc$ls180.v:1282$3287 + attribute \src "ls180.v:1326.5-1326.49" + process $proc$ls180.v:1326$3555 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end - attribute \src "ls180.v:1283.11-1283.63" - process $proc$ls180.v:1283$3288 + attribute \src "ls180.v:1327.11-1327.63" + process $proc$ls180.v:1327$3556 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1284.5-1284.39" - process $proc$ls180.v:1284$3289 + attribute \src "ls180.v:1328.5-1328.39" + process $proc$ls180.v:1328$3557 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end - attribute \src "ls180.v:1287.5-1287.50" - process $proc$ls180.v:1287$3290 + attribute \src "ls180.v:1331.5-1331.50" + process $proc$ls180.v:1331$3558 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1288.5-1288.49" - process $proc$ls180.v:1288$3291 + attribute \src "ls180.v:1332.5-1332.49" + process $proc$ls180.v:1332$3559 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1289.5-1289.56" - process $proc$ls180.v:1289$3292 + attribute \src "ls180.v:1333.5-1333.56" + process $proc$ls180.v:1333$3560 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1291.5-1291.58" - process $proc$ls180.v:1291$3293 + attribute \src "ls180.v:1335.5-1335.58" + process $proc$ls180.v:1335$3561 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1292.5-1292.59" - process $proc$ls180.v:1292$3294 + attribute \src "ls180.v:1336.5-1336.59" + process $proc$ls180.v:1336$3562 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1294.11-1294.65" - process $proc$ls180.v:1294$3295 + attribute \src "ls180.v:1338.11-1338.65" + process $proc$ls180.v:1338$3563 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1295.5-1295.60" - process $proc$ls180.v:1295$3296 + attribute \src "ls180.v:1339.5-1339.60" + process $proc$ls180.v:1339$3564 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1297.5-1297.49" - process $proc$ls180.v:1297$3297 + attribute \src "ls180.v:1341.5-1341.49" + process $proc$ls180.v:1341$3565 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1298.5-1298.51" - process $proc$ls180.v:1298$3298 + attribute \src "ls180.v:1342.5-1342.51" + process $proc$ls180.v:1342$3566 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1299.5-1299.52" - process $proc$ls180.v:1299$3299 + attribute \src "ls180.v:1343.5-1343.52" + process $proc$ls180.v:1343$3567 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1300.11-1300.58" - process $proc$ls180.v:1300$3300 + attribute \src "ls180.v:1344.11-1344.58" + process $proc$ls180.v:1344$3568 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1301.5-1301.53" - process $proc$ls180.v:1301$3301 + attribute \src "ls180.v:1345.5-1345.53" + process $proc$ls180.v:1345$3569 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1302.5-1302.39" - process $proc$ls180.v:1302$3302 + attribute \src "ls180.v:1346.5-1346.39" + process $proc$ls180.v:1346$3570 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end - attribute \src "ls180.v:1303.5-1303.39" - process $proc$ls180.v:1303$3303 + attribute \src "ls180.v:1347.5-1347.39" + process $proc$ls180.v:1347$3571 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end - attribute \src "ls180.v:1304.5-1304.38" - process $proc$ls180.v:1304$3304 + attribute \src "ls180.v:1348.5-1348.38" + process $proc$ls180.v:1348$3572 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end - attribute \src "ls180.v:1305.11-1305.61" - process $proc$ls180.v:1305$3305 + attribute \src "ls180.v:1349.11-1349.61" + process $proc$ls180.v:1349$3573 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end - attribute \src "ls180.v:1306.5-1306.41" - process $proc$ls180.v:1306$3306 + attribute \src "ls180.v:1350.5-1350.41" + process $proc$ls180.v:1350$3574 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end - attribute \src "ls180.v:1307.5-1307.41" - process $proc$ls180.v:1307$3307 + attribute \src "ls180.v:1351.5-1351.41" + process $proc$ls180.v:1351$3575 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end - attribute \src "ls180.v:1308.5-1308.41" - process $proc$ls180.v:1308$3308 + attribute \src "ls180.v:1352.5-1352.41" + process $proc$ls180.v:1352$3576 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] sync init end - attribute \src "ls180.v:1309.5-1309.40" - process $proc$ls180.v:1309$3309 + attribute \src "ls180.v:1353.5-1353.40" + process $proc$ls180.v:1353$3577 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end - attribute \src "ls180.v:1310.11-1310.54" - process $proc$ls180.v:1310$3310 + attribute \src "ls180.v:1354.11-1354.54" + process $proc$ls180.v:1354$3578 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end - attribute \src "ls180.v:1311.11-1311.56" - process $proc$ls180.v:1311$3311 + attribute \src "ls180.v:1355.11-1355.56" + process $proc$ls180.v:1355$3579 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end - attribute \src "ls180.v:1312.5-1312.33" - process $proc$ls180.v:1312$3312 + attribute \src "ls180.v:1356.5-1356.33" + process $proc$ls180.v:1356$3580 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always sync init update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end - attribute \src "ls180.v:1313.12-1313.49" - process $proc$ls180.v:1313$3313 + attribute \src "ls180.v:1357.12-1357.49" + process $proc$ls180.v:1357$3581 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always sync init update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end - attribute \src "ls180.v:1314.11-1314.41" - process $proc$ls180.v:1314$3314 + attribute \src "ls180.v:1358.11-1358.41" + process $proc$ls180.v:1358$3582 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end - attribute \src "ls180.v:1316.5-1316.48" - process $proc$ls180.v:1316$3315 + attribute \src "ls180.v:1360.5-1360.48" + process $proc$ls180.v:1360$3583 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1327.5-1327.55" - process $proc$ls180.v:1327$3316 + attribute \src "ls180.v:1371.5-1371.55" + process $proc$ls180.v:1371$3584 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end - attribute \src "ls180.v:1332.5-1332.38" - process $proc$ls180.v:1332$3317 + attribute \src "ls180.v:1376.5-1376.38" + process $proc$ls180.v:1376$3585 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end - attribute \src "ls180.v:1335.5-1335.55" - process $proc$ls180.v:1335$3318 + attribute \src "ls180.v:1379.5-1379.55" + process $proc$ls180.v:1379$3586 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1336.5-1336.54" - process $proc$ls180.v:1336$3319 + attribute \src "ls180.v:1380.5-1380.54" + process $proc$ls180.v:1380$3587 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1340.5-1340.57" - process $proc$ls180.v:1340$3320 + attribute \src "ls180.v:1384.5-1384.57" + process $proc$ls180.v:1384$3588 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end - attribute \src "ls180.v:1341.5-1341.56" - process $proc$ls180.v:1341$3321 + attribute \src "ls180.v:1385.5-1385.56" + process $proc$ls180.v:1385$3589 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end - attribute \src "ls180.v:1342.11-1342.70" - process $proc$ls180.v:1342$3322 + attribute \src "ls180.v:1386.11-1386.70" + process $proc$ls180.v:1386$3590 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1343.11-1343.83" - process $proc$ls180.v:1343$3323 + attribute \src "ls180.v:1387.11-1387.83" + process $proc$ls180.v:1387$3591 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end - attribute \src "ls180.v:1344.5-1344.50" - process $proc$ls180.v:1344$3324 + attribute \src "ls180.v:1388.5-1388.50" + process $proc$ls180.v:1388$3592 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end - attribute \src "ls180.v:1346.5-1346.55" - process $proc$ls180.v:1346$3325 + attribute \src "ls180.v:1390.5-1390.55" + process $proc$ls180.v:1390$3593 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end - attribute \src "ls180.v:1357.5-1357.51" - process $proc$ls180.v:1357$3326 + attribute \src "ls180.v:1401.5-1401.51" + process $proc$ls180.v:1401$3594 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end - attribute \src "ls180.v:1359.5-1359.51" - process $proc$ls180.v:1359$3327 + attribute \src "ls180.v:1403.5-1403.51" + process $proc$ls180.v:1403$3595 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end - attribute \src "ls180.v:1360.5-1360.50" - process $proc$ls180.v:1360$3328 + attribute \src "ls180.v:1404.5-1404.50" + process $proc$ls180.v:1404$3596 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end - attribute \src "ls180.v:1361.11-1361.64" - process $proc$ls180.v:1361$3329 + attribute \src "ls180.v:1405.11-1405.64" + process $proc$ls180.v:1405$3597 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1362.5-1362.40" - process $proc$ls180.v:1362$3330 + attribute \src "ls180.v:1406.5-1406.40" + process $proc$ls180.v:1406$3598 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end - attribute \src "ls180.v:1364.5-1364.35" - process $proc$ls180.v:1364$3331 + attribute \src "ls180.v:1408.5-1408.35" + process $proc$ls180.v:1408$3599 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always sync init update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end - attribute \src "ls180.v:1367.11-1367.42" - process $proc$ls180.v:1367$3332 + attribute \src "ls180.v:1411.11-1411.42" + process $proc$ls180.v:1411$3600 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always sync init update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:1380.12-1380.52" - process $proc$ls180.v:1380$3333 + attribute \src "ls180.v:1424.12-1424.52" + process $proc$ls180.v:1424$3601 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end - attribute \src "ls180.v:1381.5-1381.39" - process $proc$ls180.v:1381$3334 + attribute \src "ls180.v:1425.5-1425.39" + process $proc$ls180.v:1425$3602 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end - attribute \src "ls180.v:1382.12-1382.51" - process $proc$ls180.v:1382$3335 + attribute \src "ls180.v:1426.12-1426.51" + process $proc$ls180.v:1426$3603 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end - attribute \src "ls180.v:1383.5-1383.38" - process $proc$ls180.v:1383$3336 + attribute \src "ls180.v:1427.5-1427.38" + process $proc$ls180.v:1427$3604 assign { } { } assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end - attribute \src "ls180.v:1387.5-1387.34" - process $proc$ls180.v:1387$3337 + attribute \src "ls180.v:1431.5-1431.34" + process $proc$ls180.v:1431$3605 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] sync init end - attribute \src "ls180.v:1388.13-1388.53" - process $proc$ls180.v:1388$3338 + attribute \src "ls180.v:1432.13-1432.53" + process $proc$ls180.v:1432$3606 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end - attribute \src "ls180.v:1394.11-1394.51" - process $proc$ls180.v:1394$3339 + attribute \src "ls180.v:1438.11-1438.51" + process $proc$ls180.v:1438$3607 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always sync init update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end - attribute \src "ls180.v:1395.5-1395.39" - process $proc$ls180.v:1395$3340 + attribute \src "ls180.v:1439.5-1439.39" + process $proc$ls180.v:1439$3608 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always sync init update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end - attribute \src "ls180.v:1396.12-1396.51" - process $proc$ls180.v:1396$3341 + attribute \src "ls180.v:1440.12-1440.51" + process $proc$ls180.v:1440$3609 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always sync init update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end - attribute \src "ls180.v:1397.5-1397.38" - process $proc$ls180.v:1397$3342 + attribute \src "ls180.v:1441.5-1441.38" + process $proc$ls180.v:1441$3610 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always sync init update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end - attribute \src "ls180.v:1398.11-1398.51" - process $proc$ls180.v:1398$3343 + attribute \src "ls180.v:1442.11-1442.51" + process $proc$ls180.v:1442$3611 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end - attribute \src "ls180.v:1440.11-1440.47" - process $proc$ls180.v:1440$3344 + attribute \src "ls180.v:1484.11-1484.47" + process $proc$ls180.v:1484$3612 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:1444.5-1444.49" - process $proc$ls180.v:1444$3345 + attribute \src "ls180.v:1488.5-1488.49" + process $proc$ls180.v:1488$3613 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end - attribute \src "ls180.v:1448.5-1448.51" - process $proc$ls180.v:1448$3346 + attribute \src "ls180.v:1492.5-1492.51" + process $proc$ls180.v:1492$3614 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end - attribute \src "ls180.v:1449.5-1449.51" - process $proc$ls180.v:1449$3347 + attribute \src "ls180.v:1493.5-1493.51" + process $proc$ls180.v:1493$3615 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end - attribute \src "ls180.v:1450.5-1450.51" - process $proc$ls180.v:1450$3348 + attribute \src "ls180.v:1494.5-1494.51" + process $proc$ls180.v:1494$3616 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] sync init end - attribute \src "ls180.v:1451.5-1451.50" - process $proc$ls180.v:1451$3349 + attribute \src "ls180.v:1495.5-1495.50" + process $proc$ls180.v:1495$3617 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end - attribute \src "ls180.v:1452.11-1452.64" - process $proc$ls180.v:1452$3350 + attribute \src "ls180.v:1496.11-1496.64" + process $proc$ls180.v:1496$3618 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end - attribute \src "ls180.v:1453.11-1453.48" - process $proc$ls180.v:1453$3351 + attribute \src "ls180.v:1497.11-1497.48" + process $proc$ls180.v:1497$3619 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end - attribute \src "ls180.v:1454.12-1454.59" - process $proc$ls180.v:1454$3352 + attribute \src "ls180.v:1498.12-1498.59" + process $proc$ls180.v:1498$3620 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1458.12-1458.55" - process $proc$ls180.v:1458$3353 + attribute \src "ls180.v:1502.12-1502.55" + process $proc$ls180.v:1502$3621 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:1461.12-1461.59" - process $proc$ls180.v:1461$3354 + attribute \src "ls180.v:1505.12-1505.59" + process $proc$ls180.v:1505$3622 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1465.12-1465.55" - process $proc$ls180.v:1465$3355 + attribute \src "ls180.v:1509.12-1509.55" + process $proc$ls180.v:1509$3623 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:1468.12-1468.59" - process $proc$ls180.v:1468$3356 + attribute \src "ls180.v:1512.12-1512.59" + process $proc$ls180.v:1512$3624 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1472.12-1472.55" - process $proc$ls180.v:1472$3357 + attribute \src "ls180.v:1516.12-1516.55" + process $proc$ls180.v:1516$3625 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:1475.12-1475.59" - process $proc$ls180.v:1475$3358 + attribute \src "ls180.v:1519.12-1519.59" + process $proc$ls180.v:1519$3626 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1479.12-1479.55" - process $proc$ls180.v:1479$3359 + attribute \src "ls180.v:1523.12-1523.55" + process $proc$ls180.v:1523$3627 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:1482.12-1482.54" - process $proc$ls180.v:1482$3360 + attribute \src "ls180.v:1526.12-1526.54" + process $proc$ls180.v:1526$3628 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end - attribute \src "ls180.v:1483.12-1483.54" - process $proc$ls180.v:1483$3361 + attribute \src "ls180.v:1527.12-1527.54" + process $proc$ls180.v:1527$3629 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end - attribute \src "ls180.v:1484.12-1484.54" - process $proc$ls180.v:1484$3362 + attribute \src "ls180.v:1528.12-1528.54" + process $proc$ls180.v:1528$3630 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end - attribute \src "ls180.v:1485.12-1485.54" - process $proc$ls180.v:1485$3363 + attribute \src "ls180.v:1529.12-1529.54" + process $proc$ls180.v:1529$3631 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end - attribute \src "ls180.v:1486.5-1486.48" - process $proc$ls180.v:1486$3364 + attribute \src "ls180.v:1530.5-1530.48" + process $proc$ls180.v:1530$3632 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end - attribute \src "ls180.v:1487.5-1487.48" - process $proc$ls180.v:1487$3365 + attribute \src "ls180.v:1531.5-1531.48" + process $proc$ls180.v:1531$3633 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:1488.5-1488.48" - process $proc$ls180.v:1488$3366 + attribute \src "ls180.v:1532.5-1532.48" + process $proc$ls180.v:1532$3634 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end - attribute \src "ls180.v:1489.5-1489.47" - process $proc$ls180.v:1489$3367 + attribute \src "ls180.v:1533.5-1533.47" + process $proc$ls180.v:1533$3635 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end - attribute \src "ls180.v:1490.11-1490.61" - process $proc$ls180.v:1490$3368 + attribute \src "ls180.v:1534.11-1534.61" + process $proc$ls180.v:1534$3636 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end - attribute \src "ls180.v:1491.5-1491.50" - process $proc$ls180.v:1491$3369 + attribute \src "ls180.v:1535.5-1535.50" + process $proc$ls180.v:1535$3637 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:1493.5-1493.50" - process $proc$ls180.v:1493$3370 + attribute \src "ls180.v:1537.5-1537.50" + process $proc$ls180.v:1537$3638 assign { } { } assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] sync init end - attribute \src "ls180.v:1496.11-1496.47" - process $proc$ls180.v:1496$3371 + attribute \src "ls180.v:1540.11-1540.47" + process $proc$ls180.v:1540$3639 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end - attribute \src "ls180.v:1497.11-1497.47" - process $proc$ls180.v:1497$3372 + attribute \src "ls180.v:1541.11-1541.47" + process $proc$ls180.v:1541$3640 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always sync init update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end - attribute \src "ls180.v:1498.12-1498.58" - process $proc$ls180.v:1498$3373 + attribute \src "ls180.v:1542.12-1542.58" + process $proc$ls180.v:1542$3641 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1502.12-1502.54" - process $proc$ls180.v:1502$3374 + attribute \src "ls180.v:1546.12-1546.54" + process $proc$ls180.v:1546$3642 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:1503.5-1503.46" - process $proc$ls180.v:1503$3375 + attribute \src "ls180.v:1547.5-1547.46" + process $proc$ls180.v:1547$3643 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:1505.12-1505.58" - process $proc$ls180.v:1505$3376 + attribute \src "ls180.v:1549.12-1549.58" + process $proc$ls180.v:1549$3644 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1509.12-1509.54" - process $proc$ls180.v:1509$3377 + attribute \src "ls180.v:1553.12-1553.54" + process $proc$ls180.v:1553$3645 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:1510.5-1510.46" - process $proc$ls180.v:1510$3378 + attribute \src "ls180.v:1554.5-1554.46" + process $proc$ls180.v:1554$3646 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:1512.12-1512.58" - process $proc$ls180.v:1512$3379 + attribute \src "ls180.v:1556.12-1556.58" + process $proc$ls180.v:1556$3647 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1516.12-1516.54" - process $proc$ls180.v:1516$3380 + attribute \src "ls180.v:1560.12-1560.54" + process $proc$ls180.v:1560$3648 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:1517.5-1517.46" - process $proc$ls180.v:1517$3381 + attribute \src "ls180.v:1561.5-1561.46" + process $proc$ls180.v:1561$3649 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:1519.12-1519.58" - process $proc$ls180.v:1519$3382 + attribute \src "ls180.v:1563.12-1563.58" + process $proc$ls180.v:1563$3650 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1523.12-1523.54" - process $proc$ls180.v:1523$3383 + attribute \src "ls180.v:1567.12-1567.54" + process $proc$ls180.v:1567$3651 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:1524.5-1524.46" - process $proc$ls180.v:1524$3384 + attribute \src "ls180.v:1568.5-1568.46" + process $proc$ls180.v:1568$3652 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:1526.12-1526.53" - process $proc$ls180.v:1526$3385 + attribute \src "ls180.v:1570.12-1570.53" + process $proc$ls180.v:1570$3653 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end - attribute \src "ls180.v:1527.12-1527.53" - process $proc$ls180.v:1527$3386 + attribute \src "ls180.v:1571.12-1571.53" + process $proc$ls180.v:1571$3654 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end - attribute \src "ls180.v:1528.12-1528.53" - process $proc$ls180.v:1528$3387 + attribute \src "ls180.v:1572.12-1572.53" + process $proc$ls180.v:1572$3655 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end - attribute \src "ls180.v:1529.12-1529.53" - process $proc$ls180.v:1529$3388 + attribute \src "ls180.v:1573.12-1573.53" + process $proc$ls180.v:1573$3656 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end - attribute \src "ls180.v:1530.5-1530.43" - process $proc$ls180.v:1530$3389 + attribute \src "ls180.v:1574.5-1574.43" + process $proc$ls180.v:1574$3657 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:1531.12-1531.51" - process $proc$ls180.v:1531$3390 + attribute \src "ls180.v:1575.12-1575.51" + process $proc$ls180.v:1575$3658 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end - attribute \src "ls180.v:1532.12-1532.51" - process $proc$ls180.v:1532$3391 + attribute \src "ls180.v:1576.12-1576.51" + process $proc$ls180.v:1576$3659 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end - attribute \src "ls180.v:1533.12-1533.51" - process $proc$ls180.v:1533$3392 + attribute \src "ls180.v:1577.12-1577.51" + process $proc$ls180.v:1577$3660 assign { } { } assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end - attribute \src "ls180.v:1534.12-1534.51" - process $proc$ls180.v:1534$3393 + attribute \src "ls180.v:1578.12-1578.51" + process $proc$ls180.v:1578$3661 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end - attribute \src "ls180.v:1536.11-1536.39" - process $proc$ls180.v:1536$3394 + attribute \src "ls180.v:1580.11-1580.39" + process $proc$ls180.v:1580$3662 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end - attribute \src "ls180.v:1537.5-1537.32" - process $proc$ls180.v:1537$3395 + attribute \src "ls180.v:1581.5-1581.32" + process $proc$ls180.v:1581$3663 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end - attribute \src "ls180.v:1538.5-1538.33" - process $proc$ls180.v:1538$3396 + attribute \src "ls180.v:1582.5-1582.33" + process $proc$ls180.v:1582$3664 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end - attribute \src "ls180.v:1539.5-1539.35" - process $proc$ls180.v:1539$3397 + attribute \src "ls180.v:1583.5-1583.35" + process $proc$ls180.v:1583$3665 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end - attribute \src "ls180.v:1541.12-1541.42" - process $proc$ls180.v:1541$3398 + attribute \src "ls180.v:1585.12-1585.42" + process $proc$ls180.v:1585$3666 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always sync init update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end - attribute \src "ls180.v:1542.5-1542.33" - process $proc$ls180.v:1542$3399 + attribute \src "ls180.v:1586.5-1586.33" + process $proc$ls180.v:1586$3667 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always sync init update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end - attribute \src "ls180.v:1543.5-1543.34" - process $proc$ls180.v:1543$3400 + attribute \src "ls180.v:1587.5-1587.34" + process $proc$ls180.v:1587$3668 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always sync init update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end - attribute \src "ls180.v:1544.5-1544.36" - process $proc$ls180.v:1544$3401 + attribute \src "ls180.v:1588.5-1588.36" + process $proc$ls180.v:1588$3669 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end - attribute \src "ls180.v:1553.11-1553.41" - process $proc$ls180.v:1553$3402 + attribute \src "ls180.v:1597.11-1597.41" + process $proc$ls180.v:1597$3670 assign { } { } assign $0\main_interface0_bus_cti[2:0] 3'000 sync always update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] sync init end - attribute \src "ls180.v:1554.11-1554.41" - process $proc$ls180.v:1554$3403 + attribute \src "ls180.v:1598.11-1598.41" + process $proc$ls180.v:1598$3671 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] sync init end - attribute \src "ls180.v:1577.11-1577.45" - process $proc$ls180.v:1577$3404 + attribute \src "ls180.v:1621.11-1621.45" + process $proc$ls180.v:1621$3672 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always sync init update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end - attribute \src "ls180.v:1578.5-1578.41" - process $proc$ls180.v:1578$3405 + attribute \src "ls180.v:1622.5-1622.41" + process $proc$ls180.v:1622$3673 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1579.11-1579.47" - process $proc$ls180.v:1579$3406 + attribute \src "ls180.v:1623.11-1623.47" + process $proc$ls180.v:1623$3674 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end - attribute \src "ls180.v:158.12-158.71" - process $proc$ls180.v:158$2775 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1580.11-1580.47" - process $proc$ls180.v:1580$3407 + attribute \src "ls180.v:1624.11-1624.47" + process $proc$ls180.v:1624$3675 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end - attribute \src "ls180.v:1581.11-1581.50" - process $proc$ls180.v:1581$3408 + attribute \src "ls180.v:1625.11-1625.50" + process $proc$ls180.v:1625$3676 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:159.12-159.73" - process $proc$ls180.v:159$2776 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1601.5-1601.51" - process $proc$ls180.v:1601$3409 + attribute \src "ls180.v:1645.5-1645.51" + process $proc$ls180.v:1645$3677 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end - attribute \src "ls180.v:1602.5-1602.50" - process $proc$ls180.v:1602$3410 + attribute \src "ls180.v:1646.5-1646.50" + process $proc$ls180.v:1646$3678 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end - attribute \src "ls180.v:1603.12-1603.66" - process $proc$ls180.v:1603$3411 + attribute \src "ls180.v:1647.12-1647.66" + process $proc$ls180.v:1647$3679 assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 + assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] end - attribute \src "ls180.v:1604.11-1604.77" - process $proc$ls180.v:1604$3412 + attribute \src "ls180.v:1648.11-1648.77" + process $proc$ls180.v:1648$3680 assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init - update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1605.11-1605.50" - process $proc$ls180.v:1605$3413 + attribute \src "ls180.v:1649.11-1649.50" + process $proc$ls180.v:1649$3681 assign { } { } - assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 sync always sync init - update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] end - attribute \src "ls180.v:1607.5-1607.49" - process $proc$ls180.v:1607$3414 + attribute \src "ls180.v:1651.5-1651.49" + process $proc$ls180.v:1651$3682 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:161.11-161.69" - process $proc$ls180.v:161$2777 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1613.5-1613.45" - process $proc$ls180.v:1613$3415 + attribute \src "ls180.v:1657.5-1657.45" + process $proc$ls180.v:1657$3683 assign { } { } assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always sync init update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:1615.12-1615.62" - process $proc$ls180.v:1615$3416 + attribute \src "ls180.v:1659.12-1659.62" + process $proc$ls180.v:1659$3684 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end - attribute \src "ls180.v:1616.12-1616.60" - process $proc$ls180.v:1616$3417 + attribute \src "ls180.v:166.5-166.40" + process $proc$ls180.v:166$3047 assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:1618.5-1618.57" - process $proc$ls180.v:1618$3418 + attribute \src "ls180.v:1660.12-1660.60" + process $proc$ls180.v:1660$3685 assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] end - attribute \src "ls180.v:162.5-162.63" - process $proc$ls180.v:162$2778 + attribute \src "ls180.v:1662.5-1662.57" + process $proc$ls180.v:1662$3686 assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always sync init - update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end - attribute \src "ls180.v:1622.12-1622.67" - process $proc$ls180.v:1622$3419 + attribute \src "ls180.v:1666.12-1666.67" + process $proc$ls180.v:1666$3687 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end - attribute \src "ls180.v:1623.5-1623.54" - process $proc$ls180.v:1623$3420 + attribute \src "ls180.v:1667.5-1667.54" + process $proc$ls180.v:1667$3688 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end - attribute \src "ls180.v:1624.12-1624.69" - process $proc$ls180.v:1624$3421 + attribute \src "ls180.v:1668.12-1668.69" + process $proc$ls180.v:1668$3689 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end - attribute \src "ls180.v:1625.5-1625.56" - process $proc$ls180.v:1625$3422 + attribute \src "ls180.v:1669.5-1669.56" + process $proc$ls180.v:1669$3690 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end - attribute \src "ls180.v:1626.5-1626.61" - process $proc$ls180.v:1626$3423 + attribute \src "ls180.v:1670.5-1670.61" + process $proc$ls180.v:1670$3691 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end - attribute \src "ls180.v:1627.5-1627.56" - process $proc$ls180.v:1627$3424 + attribute \src "ls180.v:1671.5-1671.56" + process $proc$ls180.v:1671$3692 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end - attribute \src "ls180.v:1628.5-1628.53" - process $proc$ls180.v:1628$3425 + attribute \src "ls180.v:1672.5-1672.53" + process $proc$ls180.v:1672$3693 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end - attribute \src "ls180.v:163.5-163.63" - process $proc$ls180.v:163$2779 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1630.5-1630.59" - process $proc$ls180.v:1630$3426 + attribute \src "ls180.v:1674.5-1674.59" + process $proc$ls180.v:1674$3694 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end - attribute \src "ls180.v:1631.5-1631.54" - process $proc$ls180.v:1631$3427 + attribute \src "ls180.v:1675.5-1675.54" + process $proc$ls180.v:1675$3695 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end - attribute \src "ls180.v:1633.12-1633.61" - process $proc$ls180.v:1633$3428 + attribute \src "ls180.v:1677.12-1677.61" + process $proc$ls180.v:1677$3696 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end - attribute \src "ls180.v:1636.12-1636.43" - process $proc$ls180.v:1636$3429 + attribute \src "ls180.v:1680.12-1680.43" + process $proc$ls180.v:1680$3697 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always sync init update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end - attribute \src "ls180.v:1637.12-1637.45" - process $proc$ls180.v:1637$3430 + attribute \src "ls180.v:1681.12-1681.45" + process $proc$ls180.v:1681$3698 assign { } { } - assign $0\main_interface1_bus_dat_w[31:0] 0 + assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] sync init end - attribute \src "ls180.v:1639.11-1639.41" - process $proc$ls180.v:1639$3431 + attribute \src "ls180.v:1683.11-1683.41" + process $proc$ls180.v:1683$3699 assign { } { } - assign $1\main_interface1_bus_sel[3:0] 4'0000 + assign $1\main_interface1_bus_sel[7:0] 8'00000000 sync always sync init - update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] + update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] end - attribute \src "ls180.v:1640.5-1640.35" - process $proc$ls180.v:1640$3432 + attribute \src "ls180.v:1684.5-1684.35" + process $proc$ls180.v:1684$3700 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always sync init update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end - attribute \src "ls180.v:1641.5-1641.35" - process $proc$ls180.v:1641$3433 + attribute \src "ls180.v:1685.5-1685.35" + process $proc$ls180.v:1685$3701 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always sync init update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end - attribute \src "ls180.v:1643.5-1643.34" - process $proc$ls180.v:1643$3434 + attribute \src "ls180.v:1687.5-1687.34" + process $proc$ls180.v:1687$3702 assign { } { } assign $1\main_interface1_bus_we[0:0] 1'0 sync always sync init update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end - attribute \src "ls180.v:1644.11-1644.41" - process $proc$ls180.v:1644$3435 + attribute \src "ls180.v:1688.11-1688.41" + process $proc$ls180.v:1688$3703 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] sync init end - attribute \src "ls180.v:1645.11-1645.41" - process $proc$ls180.v:1645$3436 + attribute \src "ls180.v:1689.11-1689.41" + process $proc$ls180.v:1689$3704 assign { } { } assign $0\main_interface1_bus_bte[1:0] 2'00 sync always update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end - attribute \src "ls180.v:165.5-165.62" - process $proc$ls180.v:165$2780 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] - end - attribute \src "ls180.v:1652.5-1652.43" - process $proc$ls180.v:1652$3437 + attribute \src "ls180.v:1696.5-1696.43" + process $proc$ls180.v:1696$3705 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end - attribute \src "ls180.v:1653.5-1653.43" - process $proc$ls180.v:1653$3438 + attribute \src "ls180.v:1697.5-1697.43" + process $proc$ls180.v:1697$3706 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end - attribute \src "ls180.v:1654.5-1654.42" - process $proc$ls180.v:1654$3439 + attribute \src "ls180.v:1698.5-1698.42" + process $proc$ls180.v:1698$3707 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end - attribute \src "ls180.v:1655.12-1655.61" - process $proc$ls180.v:1655$3440 + attribute \src "ls180.v:1699.12-1699.61" + process $proc$ls180.v:1699$3708 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always sync init update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end - attribute \src "ls180.v:1656.5-1656.45" - process $proc$ls180.v:1656$3441 + attribute \src "ls180.v:170.5-170.40" + process $proc$ls180.v:170$3048 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:1700.5-1700.45" + process $proc$ls180.v:1700$3709 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end - attribute \src "ls180.v:1658.5-1658.45" - process $proc$ls180.v:1658$3442 + attribute \src "ls180.v:1702.5-1702.45" + process $proc$ls180.v:1702$3710 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] sync init end - attribute \src "ls180.v:1659.5-1659.44" - process $proc$ls180.v:1659$3443 + attribute \src "ls180.v:1703.5-1703.44" + process $proc$ls180.v:1703$3711 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end - attribute \src "ls180.v:166.11-166.69" - process $proc$ls180.v:166$2781 + attribute \src "ls180.v:1704.12-1704.60" + process $proc$ls180.v:1704$3712 assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] end - attribute \src "ls180.v:1660.12-1660.60" - process $proc$ls180.v:1660$3444 + attribute \src "ls180.v:1705.12-1705.45" + process $proc$ls180.v:1705$3713 assign { } { } - assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] end - attribute \src "ls180.v:1661.12-1661.45" - process $proc$ls180.v:1661$3445 - assign { } { } - assign $1\main_sdmem2block_dma_data[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] - end - attribute \src "ls180.v:1662.12-1662.53" - process $proc$ls180.v:1662$3446 + attribute \src "ls180.v:1706.12-1706.53" + process $proc$ls180.v:1706$3714 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end - attribute \src "ls180.v:1663.5-1663.40" - process $proc$ls180.v:1663$3447 + attribute \src "ls180.v:1707.5-1707.40" + process $proc$ls180.v:1707$3715 assign { } { } assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end - attribute \src "ls180.v:1664.12-1664.55" - process $proc$ls180.v:1664$3448 + attribute \src "ls180.v:1708.12-1708.55" + process $proc$ls180.v:1708$3716 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always sync init update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end - attribute \src "ls180.v:1665.5-1665.42" - process $proc$ls180.v:1665$3449 + attribute \src "ls180.v:1709.5-1709.42" + process $proc$ls180.v:1709$3717 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end - attribute \src "ls180.v:1666.5-1666.47" - process $proc$ls180.v:1666$3450 + attribute \src "ls180.v:1710.5-1710.47" + process $proc$ls180.v:1710$3718 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end - attribute \src "ls180.v:1667.5-1667.42" - process $proc$ls180.v:1667$3451 + attribute \src "ls180.v:1711.5-1711.42" + process $proc$ls180.v:1711$3719 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end - attribute \src "ls180.v:1668.5-1668.44" - process $proc$ls180.v:1668$3452 + attribute \src "ls180.v:1712.5-1712.44" + process $proc$ls180.v:1712$3720 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end - attribute \src "ls180.v:167.11-167.69" - process $proc$ls180.v:167$2782 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1670.5-1670.45" - process $proc$ls180.v:1670$3453 + attribute \src "ls180.v:1714.5-1714.45" + process $proc$ls180.v:1714$3721 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end - attribute \src "ls180.v:1671.5-1671.40" - process $proc$ls180.v:1671$3454 + attribute \src "ls180.v:1715.5-1715.40" + process $proc$ls180.v:1715$3722 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end - attribute \src "ls180.v:1675.12-1675.47" - process $proc$ls180.v:1675$3455 + attribute \src "ls180.v:1719.12-1719.47" + process $proc$ls180.v:1719$3723 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end - attribute \src "ls180.v:1687.11-1687.64" - process $proc$ls180.v:1687$3456 + attribute \src "ls180.v:173.11-173.37" + process $proc$ls180.v:173$3049 assign { } { } - assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + assign $1\main_libresocsim_we[7:0] 8'00000000 sync always sync init - update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + update \main_libresocsim_we $1\main_libresocsim_we[7:0] end - attribute \src "ls180.v:1689.11-1689.48" - process $proc$ls180.v:1689$3457 + attribute \src "ls180.v:1731.11-1731.64" + process $proc$ls180.v:1731$3724 assign { } { } - assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:169.5-169.44" - process $proc$ls180.v:169$2783 + attribute \src "ls180.v:1733.11-1733.48" + process $proc$ls180.v:1733$3725 assign { } { } - assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + assign $1\main_sdmem2block_converter_mux[2:0] 3'000 sync always sync init - update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:170.5-170.47" - process $proc$ls180.v:170$2784 + attribute \src "ls180.v:175.12-175.49" + process $proc$ls180.v:175$3050 assign { } { } - assign $1\main_libresocsim_converter0_counter[0:0] 1'0 + assign $1\main_libresocsim_load_storage[31:0] 0 sync always sync init - update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] end - attribute \src "ls180.v:1713.11-1713.45" - process $proc$ls180.v:1713$3458 + attribute \src "ls180.v:1757.11-1757.45" + process $proc$ls180.v:1757$3726 assign { } { } assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always sync init update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end - attribute \src "ls180.v:1714.5-1714.41" - process $proc$ls180.v:1714$3459 + attribute \src "ls180.v:1758.5-1758.41" + process $proc$ls180.v:1758$3727 assign { } { } assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1715.11-1715.47" - process $proc$ls180.v:1715$3460 + attribute \src "ls180.v:1759.11-1759.47" + process $proc$ls180.v:1759$3728 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end - attribute \src "ls180.v:1716.11-1716.47" - process $proc$ls180.v:1716$3461 + attribute \src "ls180.v:176.5-176.36" + process $proc$ls180.v:176$3051 assign { } { } - assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $1\main_libresocsim_load_re[0:0] 1'0 sync always sync init - update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end - attribute \src "ls180.v:1717.11-1717.50" - process $proc$ls180.v:1717$3462 + attribute \src "ls180.v:1760.11-1760.47" + process $proc$ls180.v:1760$3729 assign { } { } - assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always sync init - update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end - attribute \src "ls180.v:172.12-172.53" - process $proc$ls180.v:172$2785 + attribute \src "ls180.v:1761.11-1761.50" + process $proc$ls180.v:1761$3730 assign { } { } - assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always sync init - update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:173.12-173.71" - process $proc$ls180.v:173$2786 + attribute \src "ls180.v:177.12-177.51" + process $proc$ls180.v:177$3052 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $1\main_libresocsim_reload_storage[31:0] 0 sync always sync init - update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:1730.5-1730.36" - process $proc$ls180.v:1730$3463 + attribute \src "ls180.v:1774.5-1774.36" + process $proc$ls180.v:1774$3731 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always sync init update \builder_converter0_state $1\builder_converter0_state[0:0] end - attribute \src "ls180.v:1731.5-1731.41" - process $proc$ls180.v:1731$3464 + attribute \src "ls180.v:1775.5-1775.41" + process $proc$ls180.v:1775$3732 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always sync init update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end - attribute \src "ls180.v:1732.5-1732.69" - process $proc$ls180.v:1732$3465 + attribute \src "ls180.v:1776.5-1776.57" + process $proc$ls180.v:1776$3733 assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] end - attribute \src "ls180.v:1733.5-1733.72" - process $proc$ls180.v:1733$3466 + attribute \src "ls180.v:1777.5-1777.60" + process $proc$ls180.v:1777$3734 assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always sync init - update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:1734.5-1734.36" - process $proc$ls180.v:1734$3467 + attribute \src "ls180.v:1778.5-1778.36" + process $proc$ls180.v:1778$3735 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always sync init update \builder_converter1_state $1\builder_converter1_state[0:0] end - attribute \src "ls180.v:1735.5-1735.41" - process $proc$ls180.v:1735$3468 + attribute \src "ls180.v:1779.5-1779.41" + process $proc$ls180.v:1779$3736 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always sync init update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end - attribute \src "ls180.v:1736.5-1736.69" - process $proc$ls180.v:1736$3469 + attribute \src "ls180.v:178.5-178.38" + process $proc$ls180.v:178$3053 assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $1\main_libresocsim_reload_re[0:0] 1'0 sync always sync init - update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] end - attribute \src "ls180.v:1737.5-1737.72" - process $proc$ls180.v:1737$3470 + attribute \src "ls180.v:1780.5-1780.57" + process $proc$ls180.v:1780$3737 assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] end - attribute \src "ls180.v:1738.5-1738.36" - process $proc$ls180.v:1738$3471 + attribute \src "ls180.v:1781.5-1781.60" + process $proc$ls180.v:1781$3738 assign { } { } - assign $1\builder_converter2_state[0:0] 1'0 + assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always sync init - update \builder_converter2_state $1\builder_converter2_state[0:0] + update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:1739.5-1739.41" - process $proc$ls180.v:1739$3472 + attribute \src "ls180.v:1782.5-1782.36" + process $proc$ls180.v:1782$3739 assign { } { } - assign $1\builder_converter2_next_state[0:0] 1'0 + assign $1\builder_converter2_state[0:0] 1'0 sync always sync init - update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + update \builder_converter2_state $1\builder_converter2_state[0:0] end - attribute \src "ls180.v:174.12-174.73" - process $proc$ls180.v:174$2787 + attribute \src "ls180.v:1783.5-1783.41" + process $proc$ls180.v:1783$3740 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + assign $1\builder_converter2_next_state[0:0] 1'0 sync always sync init - update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end - attribute \src "ls180.v:1740.5-1740.69" - process $proc$ls180.v:1740$3473 + attribute \src "ls180.v:1784.5-1784.60" + process $proc$ls180.v:1784$3741 assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] end - attribute \src "ls180.v:1741.5-1741.72" - process $proc$ls180.v:1741$3474 + attribute \src "ls180.v:1785.5-1785.63" + process $proc$ls180.v:1785$3742 assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 sync always sync init - update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:1742.11-1742.41" - process $proc$ls180.v:1742$3475 + attribute \src "ls180.v:1786.11-1786.41" + process $proc$ls180.v:1786$3743 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always sync init update \builder_refresher_state $1\builder_refresher_state[1:0] end - attribute \src "ls180.v:1743.11-1743.46" - process $proc$ls180.v:1743$3476 + attribute \src "ls180.v:1787.11-1787.46" + process $proc$ls180.v:1787$3744 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always sync init update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:1744.11-1744.44" - process $proc$ls180.v:1744$3477 + attribute \src "ls180.v:1788.11-1788.44" + process $proc$ls180.v:1788$3745 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end - attribute \src "ls180.v:1745.11-1745.49" - process $proc$ls180.v:1745$3478 + attribute \src "ls180.v:1789.11-1789.49" + process $proc$ls180.v:1789$3746 assign { } { } assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:1746.11-1746.44" - process $proc$ls180.v:1746$3479 + attribute \src "ls180.v:179.5-179.39" + process $proc$ls180.v:179$3054 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:1790.11-1790.44" + process $proc$ls180.v:1790$3747 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end - attribute \src "ls180.v:1747.11-1747.49" - process $proc$ls180.v:1747$3480 + attribute \src "ls180.v:1791.11-1791.49" + process $proc$ls180.v:1791$3748 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:1748.11-1748.44" - process $proc$ls180.v:1748$3481 + attribute \src "ls180.v:1792.11-1792.44" + process $proc$ls180.v:1792$3749 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end - attribute \src "ls180.v:1749.11-1749.49" - process $proc$ls180.v:1749$3482 + attribute \src "ls180.v:1793.11-1793.49" + process $proc$ls180.v:1793$3750 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:1750.11-1750.44" - process $proc$ls180.v:1750$3483 + attribute \src "ls180.v:1794.11-1794.44" + process $proc$ls180.v:1794$3751 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end - attribute \src "ls180.v:1751.11-1751.49" - process $proc$ls180.v:1751$3484 + attribute \src "ls180.v:1795.11-1795.49" + process $proc$ls180.v:1795$3752 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:1752.11-1752.43" - process $proc$ls180.v:1752$3485 + attribute \src "ls180.v:1796.11-1796.43" + process $proc$ls180.v:1796$3753 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always sync init update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end - attribute \src "ls180.v:1753.11-1753.48" - process $proc$ls180.v:1753$3486 + attribute \src "ls180.v:1797.11-1797.48" + process $proc$ls180.v:1797$3754 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always sync init update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:176.11-176.69" - process $proc$ls180.v:176$2788 + attribute \src "ls180.v:180.5-180.34" + process $proc$ls180.v:180$3055 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $1\main_libresocsim_en_re[0:0] 1'0 sync always sync init - update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:181.5-181.49" + process $proc$ls180.v:181$3056 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end - attribute \src "ls180.v:1766.5-1766.27" - process $proc$ls180.v:1766$3487 + attribute \src "ls180.v:1810.5-1810.27" + process $proc$ls180.v:1810$3755 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always update \builder_locked0 $0\builder_locked0[0:0] sync init end - attribute \src "ls180.v:1767.5-1767.27" - process $proc$ls180.v:1767$3488 + attribute \src "ls180.v:1811.5-1811.27" + process $proc$ls180.v:1811$3756 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:1768.5-1768.27" - process $proc$ls180.v:1768$3489 + attribute \src "ls180.v:1812.5-1812.27" + process $proc$ls180.v:1812$3757 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always update \builder_locked2 $0\builder_locked2[0:0] sync init end - attribute \src "ls180.v:1769.5-1769.27" - process $proc$ls180.v:1769$3490 + attribute \src "ls180.v:1813.5-1813.27" + process $proc$ls180.v:1813$3758 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always update \builder_locked3 $0\builder_locked3[0:0] sync init end - attribute \src "ls180.v:177.5-177.63" - process $proc$ls180.v:177$2789 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1770.5-1770.42" - process $proc$ls180.v:1770$3491 + attribute \src "ls180.v:1814.5-1814.42" + process $proc$ls180.v:1814$3759 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always sync init update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:1771.5-1771.43" - process $proc$ls180.v:1771$3492 + attribute \src "ls180.v:1815.5-1815.43" + process $proc$ls180.v:1815$3760 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:1772.5-1772.43" - process $proc$ls180.v:1772$3493 + attribute \src "ls180.v:1816.5-1816.43" + process $proc$ls180.v:1816$3761 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:1773.5-1773.43" - process $proc$ls180.v:1773$3494 + attribute \src "ls180.v:1817.5-1817.43" + process $proc$ls180.v:1817$3762 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:1774.5-1774.43" - process $proc$ls180.v:1774$3495 + attribute \src "ls180.v:1818.5-1818.43" + process $proc$ls180.v:1818$3763 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:1775.5-1775.35" - process $proc$ls180.v:1775$3496 + attribute \src "ls180.v:1819.5-1819.35" + process $proc$ls180.v:1819$3764 assign { } { } assign $1\builder_converter_state[0:0] 1'0 sync always sync init update \builder_converter_state $1\builder_converter_state[0:0] end - attribute \src "ls180.v:1776.5-1776.40" - process $proc$ls180.v:1776$3497 + attribute \src "ls180.v:182.5-182.44" + process $proc$ls180.v:182$3057 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:1820.5-1820.40" + process $proc$ls180.v:1820$3765 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always sync init update \builder_converter_next_state $1\builder_converter_next_state[0:0] end - attribute \src "ls180.v:1777.5-1777.55" - process $proc$ls180.v:1777$3498 + attribute \src "ls180.v:1821.5-1821.55" + process $proc$ls180.v:1821$3766 assign { } { } assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end - attribute \src "ls180.v:1778.5-1778.58" - process $proc$ls180.v:1778$3499 + attribute \src "ls180.v:1822.5-1822.58" + process $proc$ls180.v:1822$3767 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:1779.11-1779.42" - process $proc$ls180.v:1779$3500 + attribute \src "ls180.v:1823.11-1823.42" + process $proc$ls180.v:1823$3768 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always sync init update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end - attribute \src "ls180.v:178.5-178.63" - process $proc$ls180.v:178$2790 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1780.11-1780.47" - process $proc$ls180.v:1780$3501 + attribute \src "ls180.v:1824.11-1824.47" + process $proc$ls180.v:1824$3769 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always sync init update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end - attribute \src "ls180.v:1781.11-1781.62" - process $proc$ls180.v:1781$3502 + attribute \src "ls180.v:1825.11-1825.62" + process $proc$ls180.v:1825$3770 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 sync always sync init update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] end - attribute \src "ls180.v:1782.5-1782.59" - process $proc$ls180.v:1782$3503 + attribute \src "ls180.v:1826.5-1826.59" + process $proc$ls180.v:1826$3771 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 sync always sync init update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:1783.11-1783.42" - process $proc$ls180.v:1783$3504 + attribute \src "ls180.v:1827.11-1827.42" + process $proc$ls180.v:1827$3772 assign { } { } assign $1\builder_spimaster1_state[1:0] 2'00 sync always sync init update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] end - attribute \src "ls180.v:1784.11-1784.47" - process $proc$ls180.v:1784$3505 + attribute \src "ls180.v:1828.11-1828.47" + process $proc$ls180.v:1828$3773 assign { } { } assign $1\builder_spimaster1_next_state[1:0] 2'00 sync always sync init update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] end - attribute \src "ls180.v:1785.11-1785.60" - process $proc$ls180.v:1785$3506 + attribute \src "ls180.v:1829.11-1829.60" + process $proc$ls180.v:1829$3774 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 sync always sync init update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] end - attribute \src "ls180.v:1786.5-1786.57" - process $proc$ls180.v:1786$3507 + attribute \src "ls180.v:183.12-183.49" + process $proc$ls180.v:183$3058 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:1830.5-1830.57" + process $proc$ls180.v:1830$3775 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 sync always sync init update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:1787.5-1787.41" - process $proc$ls180.v:1787$3508 + attribute \src "ls180.v:1831.5-1831.41" + process $proc$ls180.v:1831$3776 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end - attribute \src "ls180.v:1788.5-1788.46" - process $proc$ls180.v:1788$3509 + attribute \src "ls180.v:1832.5-1832.46" + process $proc$ls180.v:1832$3777 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end - attribute \src "ls180.v:1789.11-1789.66" - process $proc$ls180.v:1789$3510 + attribute \src "ls180.v:1833.11-1833.66" + process $proc$ls180.v:1833$3778 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end - attribute \src "ls180.v:1790.5-1790.63" - process $proc$ls180.v:1790$3511 + attribute \src "ls180.v:1834.5-1834.63" + process $proc$ls180.v:1834$3779 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:1791.11-1791.47" - process $proc$ls180.v:1791$3512 + attribute \src "ls180.v:1835.11-1835.47" + process $proc$ls180.v:1835$3780 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end - attribute \src "ls180.v:1792.11-1792.52" - process $proc$ls180.v:1792$3513 + attribute \src "ls180.v:1836.11-1836.52" + process $proc$ls180.v:1836$3781 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end - attribute \src "ls180.v:1793.11-1793.66" - process $proc$ls180.v:1793$3514 + attribute \src "ls180.v:1837.11-1837.66" + process $proc$ls180.v:1837$3782 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end - attribute \src "ls180.v:1794.5-1794.63" - process $proc$ls180.v:1794$3515 + attribute \src "ls180.v:1838.5-1838.63" + process $proc$ls180.v:1838$3783 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:1795.11-1795.47" - process $proc$ls180.v:1795$3516 + attribute \src "ls180.v:1839.11-1839.47" + process $proc$ls180.v:1839$3784 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end - attribute \src "ls180.v:1796.11-1796.52" - process $proc$ls180.v:1796$3517 + attribute \src "ls180.v:1840.11-1840.52" + process $proc$ls180.v:1840$3785 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end - attribute \src "ls180.v:1797.11-1797.67" - process $proc$ls180.v:1797$3518 + attribute \src "ls180.v:1841.11-1841.67" + process $proc$ls180.v:1841$3786 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end - attribute \src "ls180.v:1798.5-1798.64" - process $proc$ls180.v:1798$3519 + attribute \src "ls180.v:1842.5-1842.64" + process $proc$ls180.v:1842$3787 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end - attribute \src "ls180.v:1799.12-1799.71" - process $proc$ls180.v:1799$3520 + attribute \src "ls180.v:1843.12-1843.71" + process $proc$ls180.v:1843$3788 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end - attribute \src "ls180.v:180.5-180.62" - process $proc$ls180.v:180$2791 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] - end - attribute \src "ls180.v:1800.5-1800.66" - process $proc$ls180.v:1800$3521 + attribute \src "ls180.v:1844.5-1844.66" + process $proc$ls180.v:1844$3789 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end - attribute \src "ls180.v:1801.5-1801.66" - process $proc$ls180.v:1801$3522 + attribute \src "ls180.v:1845.5-1845.66" + process $proc$ls180.v:1845$3790 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end - attribute \src "ls180.v:1802.5-1802.69" - process $proc$ls180.v:1802$3523 + attribute \src "ls180.v:1846.5-1846.69" + process $proc$ls180.v:1846$3791 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:1803.5-1803.41" - process $proc$ls180.v:1803$3524 + attribute \src "ls180.v:1847.5-1847.41" + process $proc$ls180.v:1847$3792 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end - attribute \src "ls180.v:1804.5-1804.46" - process $proc$ls180.v:1804$3525 + attribute \src "ls180.v:1848.5-1848.46" + process $proc$ls180.v:1848$3793 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end - attribute \src "ls180.v:1805.5-1805.66" - process $proc$ls180.v:1805$3526 + attribute \src "ls180.v:1849.5-1849.66" + process $proc$ls180.v:1849$3794 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end - attribute \src "ls180.v:1806.5-1806.69" - process $proc$ls180.v:1806$3527 + attribute \src "ls180.v:1850.5-1850.69" + process $proc$ls180.v:1850$3795 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:1807.11-1807.41" - process $proc$ls180.v:1807$3528 + attribute \src "ls180.v:1851.11-1851.41" + process $proc$ls180.v:1851$3796 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end - attribute \src "ls180.v:1808.11-1808.46" - process $proc$ls180.v:1808$3529 + attribute \src "ls180.v:1852.11-1852.46" + process $proc$ls180.v:1852$3797 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end - attribute \src "ls180.v:1809.11-1809.61" - process $proc$ls180.v:1809$3530 + attribute \src "ls180.v:1853.11-1853.61" + process $proc$ls180.v:1853$3798 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end - attribute \src "ls180.v:181.11-181.69" - process $proc$ls180.v:181$2792 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1810.5-1810.58" - process $proc$ls180.v:1810$3531 + attribute \src "ls180.v:1854.5-1854.58" + process $proc$ls180.v:1854$3799 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1811.11-1811.48" - process $proc$ls180.v:1811$3532 + attribute \src "ls180.v:1855.11-1855.48" + process $proc$ls180.v:1855$3800 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end - attribute \src "ls180.v:1812.11-1812.53" - process $proc$ls180.v:1812$3533 + attribute \src "ls180.v:1856.11-1856.53" + process $proc$ls180.v:1856$3801 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end - attribute \src "ls180.v:1813.11-1813.70" - process $proc$ls180.v:1813$3534 + attribute \src "ls180.v:1857.11-1857.70" + process $proc$ls180.v:1857$3802 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end - attribute \src "ls180.v:1814.5-1814.66" - process $proc$ls180.v:1814$3535 + attribute \src "ls180.v:1858.5-1858.66" + process $proc$ls180.v:1858$3803 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end - attribute \src "ls180.v:1815.12-1815.73" - process $proc$ls180.v:1815$3536 + attribute \src "ls180.v:1859.12-1859.73" + process $proc$ls180.v:1859$3804 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end - attribute \src "ls180.v:1816.5-1816.68" - process $proc$ls180.v:1816$3537 + attribute \src "ls180.v:1860.5-1860.68" + process $proc$ls180.v:1860$3805 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end - attribute \src "ls180.v:1817.5-1817.69" - process $proc$ls180.v:1817$3538 + attribute \src "ls180.v:1861.5-1861.69" + process $proc$ls180.v:1861$3806 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end - attribute \src "ls180.v:1818.5-1818.72" - process $proc$ls180.v:1818$3539 + attribute \src "ls180.v:1862.5-1862.72" + process $proc$ls180.v:1862$3807 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:1819.5-1819.52" - process $proc$ls180.v:1819$3540 + attribute \src "ls180.v:1863.5-1863.52" + process $proc$ls180.v:1863$3808 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end - attribute \src "ls180.v:182.11-182.69" - process $proc$ls180.v:182$2793 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1820.5-1820.57" - process $proc$ls180.v:1820$3541 + attribute \src "ls180.v:1864.5-1864.57" + process $proc$ls180.v:1864$3809 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end - attribute \src "ls180.v:1821.12-1821.93" - process $proc$ls180.v:1821$3542 + attribute \src "ls180.v:1865.12-1865.93" + process $proc$ls180.v:1865$3810 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end - attribute \src "ls180.v:1822.5-1822.88" - process $proc$ls180.v:1822$3543 + attribute \src "ls180.v:1866.5-1866.88" + process $proc$ls180.v:1866$3811 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end - attribute \src "ls180.v:1823.12-1823.93" - process $proc$ls180.v:1823$3544 + attribute \src "ls180.v:1867.12-1867.93" + process $proc$ls180.v:1867$3812 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end - attribute \src "ls180.v:1824.5-1824.88" - process $proc$ls180.v:1824$3545 + attribute \src "ls180.v:1868.5-1868.88" + process $proc$ls180.v:1868$3813 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end - attribute \src "ls180.v:1825.12-1825.93" - process $proc$ls180.v:1825$3546 + attribute \src "ls180.v:1869.12-1869.93" + process $proc$ls180.v:1869$3814 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end - attribute \src "ls180.v:1826.5-1826.88" - process $proc$ls180.v:1826$3547 + attribute \src "ls180.v:187.5-187.41" + process $proc$ls180.v:187$3059 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:1870.5-1870.88" + process $proc$ls180.v:1870$3815 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end - attribute \src "ls180.v:1827.12-1827.93" - process $proc$ls180.v:1827$3548 + attribute \src "ls180.v:1871.12-1871.93" + process $proc$ls180.v:1871$3816 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end - attribute \src "ls180.v:1828.5-1828.88" - process $proc$ls180.v:1828$3549 + attribute \src "ls180.v:1872.5-1872.88" + process $proc$ls180.v:1872$3817 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end - attribute \src "ls180.v:1829.11-1829.87" - process $proc$ls180.v:1829$3550 + attribute \src "ls180.v:1873.11-1873.87" + process $proc$ls180.v:1873$3818 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end - attribute \src "ls180.v:1830.5-1830.84" - process $proc$ls180.v:1830$3551 + attribute \src "ls180.v:1874.5-1874.84" + process $proc$ls180.v:1874$3819 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:1831.11-1831.42" - process $proc$ls180.v:1831$3552 + attribute \src "ls180.v:1875.11-1875.42" + process $proc$ls180.v:1875$3820 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end - attribute \src "ls180.v:1832.11-1832.47" - process $proc$ls180.v:1832$3553 + attribute \src "ls180.v:1876.11-1876.47" + process $proc$ls180.v:1876$3821 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end - attribute \src "ls180.v:1833.5-1833.55" - process $proc$ls180.v:1833$3554 + attribute \src "ls180.v:1877.5-1877.55" + process $proc$ls180.v:1877$3822 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end - attribute \src "ls180.v:1834.5-1834.58" - process $proc$ls180.v:1834$3555 + attribute \src "ls180.v:1878.5-1878.58" + process $proc$ls180.v:1878$3823 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end - attribute \src "ls180.v:1835.5-1835.56" - process $proc$ls180.v:1835$3556 + attribute \src "ls180.v:1879.5-1879.56" + process $proc$ls180.v:1879$3824 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end - attribute \src "ls180.v:1836.5-1836.59" - process $proc$ls180.v:1836$3557 + attribute \src "ls180.v:1880.5-1880.59" + process $proc$ls180.v:1880$3825 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end - attribute \src "ls180.v:1837.11-1837.62" - process $proc$ls180.v:1837$3558 + attribute \src "ls180.v:1881.11-1881.62" + process $proc$ls180.v:1881$3826 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:1838.5-1838.59" - process $proc$ls180.v:1838$3559 + attribute \src "ls180.v:1882.5-1882.59" + process $proc$ls180.v:1882$3827 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end - attribute \src "ls180.v:1839.12-1839.65" - process $proc$ls180.v:1839$3560 + attribute \src "ls180.v:1883.12-1883.65" + process $proc$ls180.v:1883$3828 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end - attribute \src "ls180.v:184.5-184.44" - process $proc$ls180.v:184$2794 - assign { } { } - assign $1\main_libresocsim_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] - end - attribute \src "ls180.v:1840.5-1840.60" - process $proc$ls180.v:1840$3561 + attribute \src "ls180.v:1884.5-1884.60" + process $proc$ls180.v:1884$3829 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end - attribute \src "ls180.v:1841.5-1841.56" - process $proc$ls180.v:1841$3562 + attribute \src "ls180.v:1885.5-1885.56" + process $proc$ls180.v:1885$3830 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end - attribute \src "ls180.v:1842.5-1842.59" - process $proc$ls180.v:1842$3563 + attribute \src "ls180.v:1886.5-1886.59" + process $proc$ls180.v:1886$3831 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end - attribute \src "ls180.v:1843.5-1843.58" - process $proc$ls180.v:1843$3564 + attribute \src "ls180.v:1887.5-1887.58" + process $proc$ls180.v:1887$3832 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end - attribute \src "ls180.v:1844.5-1844.61" - process $proc$ls180.v:1844$3565 + attribute \src "ls180.v:1888.5-1888.61" + process $proc$ls180.v:1888$3833 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end - attribute \src "ls180.v:1845.5-1845.57" - process $proc$ls180.v:1845$3566 + attribute \src "ls180.v:1889.5-1889.57" + process $proc$ls180.v:1889$3834 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end - attribute \src "ls180.v:1846.5-1846.60" - process $proc$ls180.v:1846$3567 + attribute \src "ls180.v:189.5-189.39" + process $proc$ls180.v:189$3060 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:1890.5-1890.60" + process $proc$ls180.v:1890$3835 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end - attribute \src "ls180.v:1847.5-1847.59" - process $proc$ls180.v:1847$3568 + attribute \src "ls180.v:1891.5-1891.59" + process $proc$ls180.v:1891$3836 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end - attribute \src "ls180.v:1848.5-1848.62" - process $proc$ls180.v:1848$3569 + attribute \src "ls180.v:1892.5-1892.62" + process $proc$ls180.v:1892$3837 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end - attribute \src "ls180.v:1849.13-1849.76" - process $proc$ls180.v:1849$3570 + attribute \src "ls180.v:1893.13-1893.76" + process $proc$ls180.v:1893$3838 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end - attribute \src "ls180.v:185.5-185.47" - process $proc$ls180.v:185$2795 - assign { } { } - assign $1\main_libresocsim_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] - end - attribute \src "ls180.v:1850.5-1850.69" - process $proc$ls180.v:1850$3571 + attribute \src "ls180.v:1894.5-1894.69" + process $proc$ls180.v:1894$3839 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:1851.11-1851.46" - process $proc$ls180.v:1851$3572 + attribute \src "ls180.v:1895.11-1895.46" + process $proc$ls180.v:1895$3840 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end - attribute \src "ls180.v:1852.11-1852.51" - process $proc$ls180.v:1852$3573 + attribute \src "ls180.v:1896.11-1896.51" + process $proc$ls180.v:1896$3841 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end - attribute \src "ls180.v:1853.12-1853.87" - process $proc$ls180.v:1853$3574 + attribute \src "ls180.v:1897.12-1897.87" + process $proc$ls180.v:1897$3842 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end - attribute \src "ls180.v:1854.5-1854.82" - process $proc$ls180.v:1854$3575 + attribute \src "ls180.v:1898.5-1898.82" + process $proc$ls180.v:1898$3843 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:1855.5-1855.44" - process $proc$ls180.v:1855$3576 + attribute \src "ls180.v:1899.5-1899.44" + process $proc$ls180.v:1899$3844 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end - attribute \src "ls180.v:1856.5-1856.49" - process $proc$ls180.v:1856$3577 + attribute \src "ls180.v:190.5-190.45" + process $proc$ls180.v:190$3061 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:1900.5-1900.49" + process $proc$ls180.v:1900$3845 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end - attribute \src "ls180.v:1857.12-1857.75" - process $proc$ls180.v:1857$3578 + attribute \src "ls180.v:1901.12-1901.75" + process $proc$ls180.v:1901$3846 assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] end - attribute \src "ls180.v:1858.5-1858.70" - process $proc$ls180.v:1858$3579 + attribute \src "ls180.v:1902.5-1902.70" + process $proc$ls180.v:1902$3847 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1859.11-1859.60" - process $proc$ls180.v:1859$3580 + attribute \src "ls180.v:1903.11-1903.60" + process $proc$ls180.v:1903$3848 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end - attribute \src "ls180.v:1860.11-1860.65" - process $proc$ls180.v:1860$3581 + attribute \src "ls180.v:1904.11-1904.65" + process $proc$ls180.v:1904$3849 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end - attribute \src "ls180.v:1861.12-1861.87" - process $proc$ls180.v:1861$3582 + attribute \src "ls180.v:1905.12-1905.87" + process $proc$ls180.v:1905$3850 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end - attribute \src "ls180.v:1862.5-1862.82" - process $proc$ls180.v:1862$3583 + attribute \src "ls180.v:1906.5-1906.82" + process $proc$ls180.v:1906$3851 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:1863.12-1863.43" - process $proc$ls180.v:1863$3584 + attribute \src "ls180.v:1907.12-1907.43" + process $proc$ls180.v:1907$3852 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end - attribute \src "ls180.v:1864.5-1864.34" - process $proc$ls180.v:1864$3585 + attribute \src "ls180.v:1908.5-1908.34" + process $proc$ls180.v:1908$3853 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always sync init update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end - attribute \src "ls180.v:1865.11-1865.43" - process $proc$ls180.v:1865$3586 + attribute \src "ls180.v:1909.11-1909.43" + process $proc$ls180.v:1909$3854 assign { } { } assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1869.12-1869.54" - process $proc$ls180.v:1869$3587 + attribute \src "ls180.v:1911.12-1911.52" + process $proc$ls180.v:1911$3855 assign { } { } - assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 sync always + update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] sync init - update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:187.12-187.53" - process $proc$ls180.v:187$2796 + attribute \src "ls180.v:1912.12-1912.54" + process $proc$ls180.v:1912$3856 assign { } { } - assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 sync always + update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] sync init - update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] end - attribute \src "ls180.v:1873.5-1873.44" - process $proc$ls180.v:1873$3588 + attribute \src "ls180.v:1913.12-1913.54" + process $proc$ls180.v:1913$3857 assign { } { } - assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init - update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1877.5-1877.44" - process $proc$ls180.v:1877$3589 + attribute \src "ls180.v:1914.11-1914.50" + process $proc$ls180.v:1914$3858 assign { } { } - assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 sync always - update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] sync init end - attribute \src "ls180.v:188.12-188.71" - process $proc$ls180.v:188$2797 + attribute \src "ls180.v:1915.5-1915.44" + process $proc$ls180.v:1915$3859 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 sync always + update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] sync init - update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] end - attribute \src "ls180.v:1880.12-1880.40" - process $proc$ls180.v:1880$3590 + attribute \src "ls180.v:1916.5-1916.44" + process $proc$ls180.v:1916$3860 assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 sync always + update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:1884.5-1884.30" - process $proc$ls180.v:1884$3591 + attribute \src "ls180.v:1917.5-1917.44" + process $proc$ls180.v:1917$3861 assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:189.12-189.73" - process $proc$ls180.v:189$2798 + attribute \src "ls180.v:1918.5-1918.43" + process $proc$ls180.v:1918$3862 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 sync always + update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] sync init - update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1890.11-1890.31" - process $proc$ls180.v:1890$3592 + attribute \src "ls180.v:1921.12-1921.65" + process $proc$ls180.v:1921$3863 assign { } { } - assign $1\builder_grant[2:0] 3'000 + assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always + update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] sync init - update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:1891.11-1891.35" - process $proc$ls180.v:1891$3593 + attribute \src "ls180.v:1925.5-1925.55" + process $proc$ls180.v:1925$3864 assign { } { } - assign $1\builder_slave_sel[4:0] 5'00000 + assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 sync always + update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] sync init - update \builder_slave_sel $1\builder_slave_sel[4:0] end - attribute \src "ls180.v:1892.11-1892.37" - process $proc$ls180.v:1892$3594 + attribute \src "ls180.v:1929.5-1929.55" + process $proc$ls180.v:1929$3865 assign { } { } - assign $1\builder_slave_sel_r[4:0] 5'00000 + assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 sync always + update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] end - attribute \src "ls180.v:1893.5-1893.25" - process $proc$ls180.v:1893$3595 + attribute \src "ls180.v:1932.12-1932.40" + process $proc$ls180.v:1932$3866 assign { } { } - assign $1\builder_error[0:0] 1'0 + assign $1\builder_shared_dat_r[31:0] 0 sync always sync init - update \builder_error $1\builder_error[0:0] + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:1896.12-1896.39" - process $proc$ls180.v:1896$3596 + attribute \src "ls180.v:1936.5-1936.30" + process $proc$ls180.v:1936$3867 assign { } { } - assign $1\builder_count[19:0] 20'11110100001001000000 + assign $1\builder_shared_ack[0:0] 1'0 sync always sync init - update \builder_count $1\builder_count[19:0] + update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "ls180.v:1900.11-1900.51" - process $proc$ls180.v:1900$3597 + attribute \src "ls180.v:1942.11-1942.31" + process $proc$ls180.v:1942$3868 assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_grant[2:0] 3'000 sync always sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:191.11-191.69" - process $proc$ls180.v:191$2799 + attribute \src "ls180.v:1943.11-1943.35" + process $proc$ls180.v:1943$3869 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $1\builder_slave_sel[7:0] 8'00000000 sync always sync init - update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] + update \builder_slave_sel $1\builder_slave_sel[7:0] end - attribute \src "ls180.v:192.5-192.63" - process $proc$ls180.v:192$2800 + attribute \src "ls180.v:1944.11-1944.37" + process $proc$ls180.v:1944$3870 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $1\builder_slave_sel_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \builder_slave_sel_r $1\builder_slave_sel_r[7:0] end - attribute \src "ls180.v:193.5-193.63" - process $proc$ls180.v:193$2801 + attribute \src "ls180.v:1945.5-1945.25" + process $proc$ls180.v:1945$3871 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $1\builder_error[0:0] 1'0 sync always sync init - update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] + update \builder_error $1\builder_error[0:0] end - attribute \src "ls180.v:1941.11-1941.51" - process $proc$ls180.v:1941$3598 + attribute \src "ls180.v:1948.12-1948.39" + process $proc$ls180.v:1948$3872 assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_count[19:0] 20'11110100001001000000 sync always sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + update \builder_count $1\builder_count[19:0] end - attribute \src "ls180.v:195.5-195.62" - process $proc$ls180.v:195$2802 + attribute \src "ls180.v:1952.11-1952.51" + process $proc$ls180.v:1952$3873 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:196.11-196.69" - process $proc$ls180.v:196$2803 + attribute \src "ls180.v:199.5-199.49" + process $proc$ls180.v:199$3062 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always - update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:197.11-197.69" - process $proc$ls180.v:197$2804 + attribute \src "ls180.v:1993.11-1993.51" + process $proc$ls180.v:1993$3874 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always - update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:1970.11-1970.51" - process $proc$ls180.v:1970$3599 + attribute \src "ls180.v:200.5-200.44" + process $proc$ls180.v:200$3063 assign { } { } - assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 sync always sync init - update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end - attribute \src "ls180.v:1983.11-1983.51" - process $proc$ls180.v:1983$3600 + attribute \src "ls180.v:201.12-201.42" + process $proc$ls180.v:201$3064 assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_value[31:0] 0 sync always sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + update \main_libresocsim_value $1\main_libresocsim_value[31:0] end - attribute \src "ls180.v:199.5-199.44" - process $proc$ls180.v:199$2805 + attribute \src "ls180.v:2022.11-2022.51" + process $proc$ls180.v:2022$3875 assign { } { } - assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:200.5-200.47" - process $proc$ls180.v:200$2806 + attribute \src "ls180.v:2035.11-2035.51" + process $proc$ls180.v:2035$3876 assign { } { } - assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:202.12-202.53" - process $proc$ls180.v:202$2807 + attribute \src "ls180.v:2076.11-2076.51" + process $proc$ls180.v:2076$3877 assign { } { } - assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2024.11-2024.51" - process $proc$ls180.v:2024$3601 + attribute \src "ls180.v:208.5-208.39" + process $proc$ls180.v:208$3065 assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_interface0_ram_bus_ack[0:0] 1'0 sync always sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] end - attribute \src "ls180.v:2065.11-2065.51" - process $proc$ls180.v:2065$3602 + attribute \src "ls180.v:2117.11-2117.51" + process $proc$ls180.v:2117$3878 assign { } { } assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:209.5-209.40" - process $proc$ls180.v:209$2808 + attribute \src "ls180.v:212.5-212.39" + process $proc$ls180.v:212$3066 assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_interface0_ram_bus_err[0:0] 1'0 sync always + update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:213.5-213.40" - process $proc$ls180.v:213$2809 + attribute \src "ls180.v:215.11-215.31" + process $proc$ls180.v:215$3067 assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + assign $1\main_sram0_we[7:0] 8'00000000 sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init + update \main_sram0_we $1\main_sram0_we[7:0] end - attribute \src "ls180.v:2130.11-2130.51" - process $proc$ls180.v:2130$3603 + attribute \src "ls180.v:2182.11-2182.51" + process $proc$ls180.v:2182$3879 assign { } { } assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:216.11-216.37" - process $proc$ls180.v:216$2810 - assign { } { } - assign $1\main_libresocsim_we[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_we $1\main_libresocsim_we[3:0] - end - attribute \src "ls180.v:218.12-218.49" - process $proc$ls180.v:218$2811 + attribute \src "ls180.v:223.5-223.39" + process $proc$ls180.v:223$3068 assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 + assign $1\main_interface1_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] end - attribute \src "ls180.v:219.5-219.36" - process $proc$ls180.v:219$2812 + attribute \src "ls180.v:227.5-227.39" + process $proc$ls180.v:227$3069 assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_interface1_ram_bus_err[0:0] 1'0 sync always + update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end - attribute \src "ls180.v:220.12-220.51" - process $proc$ls180.v:220$2813 + attribute \src "ls180.v:230.11-230.31" + process $proc$ls180.v:230$3070 assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 + assign $1\main_sram1_we[7:0] 8'00000000 sync always sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] - end - attribute \src "ls180.v:221.5-221.38" - process $proc$ls180.v:221$2814 - assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] - end - attribute \src "ls180.v:222.5-222.39" - process $proc$ls180.v:222$2815 - assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] - end - attribute \src "ls180.v:223.5-223.34" - process $proc$ls180.v:223$2816 - assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] - end - attribute \src "ls180.v:224.5-224.49" - process $proc$ls180.v:224$2817 - assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + update \main_sram1_we $1\main_sram1_we[7:0] end - attribute \src "ls180.v:225.5-225.44" - process $proc$ls180.v:225$2818 - assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] - end - attribute \src "ls180.v:226.12-226.49" - process $proc$ls180.v:226$2819 - assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 - sync always - sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] - end - attribute \src "ls180.v:2263.11-2263.51" - process $proc$ls180.v:2263$3604 + attribute \src "ls180.v:2315.11-2315.51" + process $proc$ls180.v:2315$3880 assign { } { } assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:230.5-230.41" - process $proc$ls180.v:230$2820 + attribute \src "ls180.v:238.5-238.39" + process $proc$ls180.v:238$3071 assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 + assign $1\main_interface2_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] end - attribute \src "ls180.v:232.5-232.39" - process $proc$ls180.v:232$2821 + attribute \src "ls180.v:2396.11-2396.51" + process $proc$ls180.v:2396$3881 assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:233.5-233.45" - process $proc$ls180.v:233$2822 + attribute \src "ls180.v:2413.11-2413.51" + process $proc$ls180.v:2413$3882 assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2344.11-2344.51" - process $proc$ls180.v:2344$3605 + attribute \src "ls180.v:242.5-242.39" + process $proc$ls180.v:242$3072 assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_interface2_ram_bus_err[0:0] 1'0 sync always + update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2361.11-2361.51" - process $proc$ls180.v:2361$3606 + attribute \src "ls180.v:245.11-245.31" + process $proc$ls180.v:245$3073 assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_sram2_we[7:0] 8'00000000 sync always sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + update \main_sram2_we $1\main_sram2_we[7:0] end - attribute \src "ls180.v:2402.11-2402.52" - process $proc$ls180.v:2402$3607 + attribute \src "ls180.v:2454.11-2454.52" + process $proc$ls180.v:2454$3883 assign { } { } assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:242.5-242.49" - process $proc$ls180.v:242$2823 + attribute \src "ls180.v:2487.11-2487.52" + process $proc$ls180.v:2487$3884 assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:243.5-243.44" - process $proc$ls180.v:243$2824 + attribute \src "ls180.v:2528.11-2528.52" + process $proc$ls180.v:2528$3885 assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2435.11-2435.52" - process $proc$ls180.v:2435$3608 + attribute \src "ls180.v:253.5-253.51" + process $proc$ls180.v:253$3074 assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_interface0_converted_interface_ack[0:0] 1'0 sync always sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] end - attribute \src "ls180.v:244.12-244.42" - process $proc$ls180.v:244$2825 + attribute \src "ls180.v:257.5-257.51" + process $proc$ls180.v:257$3075 assign { } { } - assign $1\main_libresocsim_value[31:0] 0 + assign $0\main_interface0_converted_interface_err[0:0] 1'0 sync always + update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] end - attribute \src "ls180.v:2476.11-2476.52" - process $proc$ls180.v:2476$3609 + attribute \src "ls180.v:258.5-258.32" + process $proc$ls180.v:258$3076 assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_converter0_skip[0:0] 1'0 sync always sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + update \main_converter0_skip $1\main_converter0_skip[0:0] end - attribute \src "ls180.v:248.5-248.24" - process $proc$ls180.v:248$2826 + attribute \src "ls180.v:259.5-259.35" + process $proc$ls180.v:259$3077 assign { } { } - assign $1\main_int_rst[0:0] 1'1 + assign $1\main_converter0_counter[0:0] 1'0 sync always sync init - update \main_int_rst $1\main_int_rst[0:0] + update \main_converter0_counter $1\main_converter0_counter[0:0] end - attribute \src "ls180.v:2541.11-2541.52" - process $proc$ls180.v:2541$3610 + attribute \src "ls180.v:2593.11-2593.52" + process $proc$ls180.v:2593$3886 assign { } { } assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2566.11-2566.52" - process $proc$ls180.v:2566$3611 + attribute \src "ls180.v:261.12-261.41" + process $proc$ls180.v:261$3078 + assign { } { } + assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] + end + attribute \src "ls180.v:2618.11-2618.52" + process $proc$ls180.v:2618$3887 assign { } { } assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2588.11-2588.31" - process $proc$ls180.v:2588$3612 + attribute \src "ls180.v:2640.11-2640.31" + process $proc$ls180.v:2640$3888 assign { } { } assign $1\builder_state[1:0] 2'00 sync always sync init update \builder_state $1\builder_state[1:0] end - attribute \src "ls180.v:2589.11-2589.36" - process $proc$ls180.v:2589$3613 + attribute \src "ls180.v:2641.11-2641.36" + process $proc$ls180.v:2641$3889 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always sync init update \builder_next_state $1\builder_next_state[1:0] end - attribute \src "ls180.v:2590.11-2590.55" - process $proc$ls180.v:2590$3614 + attribute \src "ls180.v:2642.11-2642.55" + process $proc$ls180.v:2642$3890 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end - attribute \src "ls180.v:2591.5-2591.52" - process $proc$ls180.v:2591$3615 + attribute \src "ls180.v:2643.5-2643.52" + process $proc$ls180.v:2643$3891 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always sync init update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end - attribute \src "ls180.v:2592.12-2592.55" - process $proc$ls180.v:2592$3616 + attribute \src "ls180.v:2644.12-2644.55" + process $proc$ls180.v:2644$3892 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end - attribute \src "ls180.v:2593.5-2593.50" - process $proc$ls180.v:2593$3617 + attribute \src "ls180.v:2645.5-2645.50" + process $proc$ls180.v:2645$3893 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always sync init update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end - attribute \src "ls180.v:2594.5-2594.46" - process $proc$ls180.v:2594$3618 + attribute \src "ls180.v:2646.5-2646.46" + process $proc$ls180.v:2646$3894 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end - attribute \src "ls180.v:2595.5-2595.49" - process $proc$ls180.v:2595$3619 + attribute \src "ls180.v:2647.5-2647.49" + process $proc$ls180.v:2647$3895 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:2596.5-2596.41" - process $proc$ls180.v:2596$3620 + attribute \src "ls180.v:2648.5-2648.41" + process $proc$ls180.v:2648$3896 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2597.12-2597.49" - process $proc$ls180.v:2597$3621 + attribute \src "ls180.v:2649.12-2649.49" + process $proc$ls180.v:2649$3897 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2598.11-2598.47" - process $proc$ls180.v:2598$3622 + attribute \src "ls180.v:2650.11-2650.47" + process $proc$ls180.v:2650$3898 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2599.5-2599.41" - process $proc$ls180.v:2599$3623 + attribute \src "ls180.v:2651.5-2651.41" + process $proc$ls180.v:2651$3899 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2600.5-2600.41" - process $proc$ls180.v:2600$3624 + attribute \src "ls180.v:2652.5-2652.41" + process $proc$ls180.v:2652$3900 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2601.5-2601.41" - process $proc$ls180.v:2601$3625 + attribute \src "ls180.v:2653.5-2653.41" + process $proc$ls180.v:2653$3901 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2602.5-2602.39" - process $proc$ls180.v:2602$3626 + attribute \src "ls180.v:2654.5-2654.39" + process $proc$ls180.v:2654$3902 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:2603.5-2603.39" - process $proc$ls180.v:2603$3627 + attribute \src "ls180.v:2655.5-2655.39" + process $proc$ls180.v:2655$3903 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:2604.5-2604.39" - process $proc$ls180.v:2604$3628 + attribute \src "ls180.v:2656.5-2656.39" + process $proc$ls180.v:2656$3904 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:2605.5-2605.41" - process $proc$ls180.v:2605$3629 + attribute \src "ls180.v:2657.5-2657.41" + process $proc$ls180.v:2657$3905 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2606.12-2606.49" - process $proc$ls180.v:2606$3630 + attribute \src "ls180.v:2658.12-2658.49" + process $proc$ls180.v:2658$3906 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2607.11-2607.47" - process $proc$ls180.v:2607$3631 + attribute \src "ls180.v:2659.11-2659.47" + process $proc$ls180.v:2659$3907 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2608.5-2608.41" - process $proc$ls180.v:2608$3632 + attribute \src "ls180.v:2660.5-2660.41" + process $proc$ls180.v:2660$3908 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2609.5-2609.42" - process $proc$ls180.v:2609$3633 + attribute \src "ls180.v:2661.5-2661.42" + process $proc$ls180.v:2661$3909 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2610.5-2610.42" - process $proc$ls180.v:2610$3634 + attribute \src "ls180.v:2662.5-2662.42" + process $proc$ls180.v:2662$3910 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2611.5-2611.39" - process $proc$ls180.v:2611$3635 + attribute \src "ls180.v:2663.5-2663.39" + process $proc$ls180.v:2663$3911 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:2612.5-2612.39" - process $proc$ls180.v:2612$3636 + attribute \src "ls180.v:2664.5-2664.39" + process $proc$ls180.v:2664$3912 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:2613.5-2613.39" - process $proc$ls180.v:2613$3637 + attribute \src "ls180.v:2665.5-2665.39" + process $proc$ls180.v:2665$3913 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:2614.12-2614.50" - process $proc$ls180.v:2614$3638 + attribute \src "ls180.v:2666.12-2666.50" + process $proc$ls180.v:2666$3914 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:2615.5-2615.42" - process $proc$ls180.v:2615$3639 + attribute \src "ls180.v:2667.5-2667.42" + process $proc$ls180.v:2667$3915 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:2616.5-2616.42" - process $proc$ls180.v:2616$3640 + attribute \src "ls180.v:2668.5-2668.42" + process $proc$ls180.v:2668$3916 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2617.12-2617.50" - process $proc$ls180.v:2617$3641 + attribute \src "ls180.v:2669.12-2669.50" + process $proc$ls180.v:2669$3917 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2618.5-2618.42" - process $proc$ls180.v:2618$3642 + attribute \src "ls180.v:2670.5-2670.42" + process $proc$ls180.v:2670$3918 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2619.5-2619.42" - process $proc$ls180.v:2619$3643 + attribute \src "ls180.v:2671.5-2671.42" + process $proc$ls180.v:2671$3919 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:2620.12-2620.50" - process $proc$ls180.v:2620$3644 + attribute \src "ls180.v:2672.12-2672.50" + process $proc$ls180.v:2672$3920 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2621.5-2621.42" - process $proc$ls180.v:2621$3645 + attribute \src "ls180.v:2673.5-2673.42" + process $proc$ls180.v:2673$3921 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2622.5-2622.42" - process $proc$ls180.v:2622$3646 + attribute \src "ls180.v:2674.5-2674.42" + process $proc$ls180.v:2674$3922 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:2623.12-2623.50" - process $proc$ls180.v:2623$3647 + attribute \src "ls180.v:2675.12-2675.50" + process $proc$ls180.v:2675$3923 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2624.5-2624.42" - process $proc$ls180.v:2624$3648 + attribute \src "ls180.v:2676.5-2676.42" + process $proc$ls180.v:2676$3924 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:2625.5-2625.42" - process $proc$ls180.v:2625$3649 + attribute \src "ls180.v:2677.5-2677.42" + process $proc$ls180.v:2677$3925 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2626.12-2626.50" - process $proc$ls180.v:2626$3650 + attribute \src "ls180.v:2678.12-2678.50" + process $proc$ls180.v:2678$3926 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:2627.12-2627.50" - process $proc$ls180.v:2627$3651 + attribute \src "ls180.v:2679.12-2679.50" + process $proc$ls180.v:2679$3927 assign { } { } - assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:2628.11-2628.48" - process $proc$ls180.v:2628$3652 + attribute \src "ls180.v:268.5-268.51" + process $proc$ls180.v:268$3079 assign { } { } - assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + assign $1\main_interface1_converted_interface_ack[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] end - attribute \src "ls180.v:2629.5-2629.42" - process $proc$ls180.v:2629$3653 + attribute \src "ls180.v:2680.11-2680.48" + process $proc$ls180.v:2680$3928 assign { } { } - assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:263.12-263.38" - process $proc$ls180.v:263$2827 + attribute \src "ls180.v:2681.5-2681.42" + process $proc$ls180.v:2681$3929 assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2630.5-2630.42" - process $proc$ls180.v:2630$3654 + attribute \src "ls180.v:2682.5-2682.42" + process $proc$ls180.v:2682$3930 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2631.5-2631.42" - process $proc$ls180.v:2631$3655 + attribute \src "ls180.v:2683.5-2683.42" + process $proc$ls180.v:2683$3931 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2632.11-2632.48" - process $proc$ls180.v:2632$3656 + attribute \src "ls180.v:2684.11-2684.48" + process $proc$ls180.v:2684$3932 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always sync init update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2633.11-2633.48" - process $proc$ls180.v:2633$3657 + attribute \src "ls180.v:2685.11-2685.48" + process $proc$ls180.v:2685$3933 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2634.11-2634.47" - process $proc$ls180.v:2634$3658 + attribute \src "ls180.v:2686.11-2686.47" + process $proc$ls180.v:2686$3934 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always sync init update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:2635.12-2635.49" - process $proc$ls180.v:2635$3659 + attribute \src "ls180.v:2687.12-2687.49" + process $proc$ls180.v:2687$3935 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2636.5-2636.41" - process $proc$ls180.v:2636$3660 + attribute \src "ls180.v:2688.5-2688.41" + process $proc$ls180.v:2688$3936 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:2637.5-2637.41" - process $proc$ls180.v:2637$3661 + attribute \src "ls180.v:2689.5-2689.41" + process $proc$ls180.v:2689$3937 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2638.5-2638.41" - process $proc$ls180.v:2638$3662 + attribute \src "ls180.v:2690.5-2690.41" + process $proc$ls180.v:2690$3938 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2639.5-2639.41" - process $proc$ls180.v:2639$3663 + attribute \src "ls180.v:2691.5-2691.41" + process $proc$ls180.v:2691$3939 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:264.5-264.36" - process $proc$ls180.v:264$2828 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:2640.5-2640.41" - process $proc$ls180.v:2640$3664 + attribute \src "ls180.v:2692.5-2692.41" + process $proc$ls180.v:2692$3940 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2641.5-2641.39" - process $proc$ls180.v:2641$3665 + attribute \src "ls180.v:2693.5-2693.39" + process $proc$ls180.v:2693$3941 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:2642.5-2642.39" - process $proc$ls180.v:2642$3666 + attribute \src "ls180.v:2694.5-2694.39" + process $proc$ls180.v:2694$3942 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:265.11-265.32" - process $proc$ls180.v:265$2829 + attribute \src "ls180.v:272.5-272.51" + process $proc$ls180.v:272$3080 assign { } { } - assign $1\main_rddata_en[2:0] 3'000 + assign $0\main_interface1_converted_interface_err[0:0] 1'0 sync always + update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] sync init - update \main_rddata_en $1\main_rddata_en[2:0] end - attribute \src "ls180.v:268.5-268.36" - process $proc$ls180.v:268$2830 + attribute \src "ls180.v:273.5-273.32" + process $proc$ls180.v:273$3081 assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $1\main_converter1_skip[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + update \main_converter1_skip $1\main_converter1_skip[0:0] end - attribute \src "ls180.v:269.5-269.35" - process $proc$ls180.v:269$2831 + attribute \src "ls180.v:274.5-274.35" + process $proc$ls180.v:274$3082 assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $1\main_converter1_counter[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + update \main_converter1_counter $1\main_converter1_counter[0:0] end - attribute \src "ls180.v:2699.32-2699.66" - process $proc$ls180.v:2699$3667 + attribute \src "ls180.v:2751.32-2751.66" + process $proc$ls180.v:2751$3943 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end - attribute \src "ls180.v:270.5-270.36" - process $proc$ls180.v:270$2832 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:2700.32-2700.66" - process $proc$ls180.v:2700$3668 + attribute \src "ls180.v:2752.32-2752.66" + process $proc$ls180.v:2752$3944 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end - attribute \src "ls180.v:2701.32-2701.66" - process $proc$ls180.v:2701$3669 + attribute \src "ls180.v:2753.32-2753.66" + process $proc$ls180.v:2753$3945 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end - attribute \src "ls180.v:2702.32-2702.66" - process $proc$ls180.v:2702$3670 + attribute \src "ls180.v:2754.32-2754.66" + process $proc$ls180.v:2754$3946 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end - attribute \src "ls180.v:2703.32-2703.66" - process $proc$ls180.v:2703$3671 + attribute \src "ls180.v:2755.32-2755.66" + process $proc$ls180.v:2755$3947 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end - attribute \src "ls180.v:2704.32-2704.66" - process $proc$ls180.v:2704$3672 + attribute \src "ls180.v:2756.32-2756.66" + process $proc$ls180.v:2756$3948 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end - attribute \src "ls180.v:2705.32-2705.66" - process $proc$ls180.v:2705$3673 + attribute \src "ls180.v:2757.32-2757.66" + process $proc$ls180.v:2757$3949 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end - attribute \src "ls180.v:2706.32-2706.66" - process $proc$ls180.v:2706$3674 + attribute \src "ls180.v:2758.32-2758.66" + process $proc$ls180.v:2758$3950 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end - attribute \src "ls180.v:2707.32-2707.66" - process $proc$ls180.v:2707$3675 + attribute \src "ls180.v:2759.32-2759.66" + process $proc$ls180.v:2759$3951 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end - attribute \src "ls180.v:2708.32-2708.66" - process $proc$ls180.v:2708$3676 + attribute \src "ls180.v:276.12-276.41" + process $proc$ls180.v:276$3083 assign { } { } - assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] end - attribute \src "ls180.v:2709.32-2709.66" - process $proc$ls180.v:2709$3677 + attribute \src "ls180.v:2760.32-2760.66" + process $proc$ls180.v:2760$3952 assign { } { } - assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always sync init - update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end - attribute \src "ls180.v:271.5-271.35" - process $proc$ls180.v:271$2833 + attribute \src "ls180.v:2761.32-2761.66" + process $proc$ls180.v:2761$3953 assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end - attribute \src "ls180.v:2710.32-2710.66" - process $proc$ls180.v:2710$3678 + attribute \src "ls180.v:2762.32-2762.66" + process $proc$ls180.v:2762$3954 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end - attribute \src "ls180.v:2711.32-2711.66" - process $proc$ls180.v:2711$3679 + attribute \src "ls180.v:2763.32-2763.66" + process $proc$ls180.v:2763$3955 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end - attribute \src "ls180.v:2712.32-2712.66" - process $proc$ls180.v:2712$3680 + attribute \src "ls180.v:2764.32-2764.66" + process $proc$ls180.v:2764$3956 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end - attribute \src "ls180.v:2713.32-2713.66" - process $proc$ls180.v:2713$3681 + attribute \src "ls180.v:2765.32-2765.66" + process $proc$ls180.v:2765$3957 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end - attribute \src "ls180.v:2714.32-2714.66" - process $proc$ls180.v:2714$3682 + attribute \src "ls180.v:2766.32-2766.66" + process $proc$ls180.v:2766$3958 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end - attribute \src "ls180.v:2715.32-2715.66" - process $proc$ls180.v:2715$3683 + attribute \src "ls180.v:2767.32-2767.66" + process $proc$ls180.v:2767$3959 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end - attribute \src "ls180.v:2716.32-2716.66" - process $proc$ls180.v:2716$3684 + attribute \src "ls180.v:2768.32-2768.66" + process $proc$ls180.v:2768$3960 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end - attribute \src "ls180.v:2717.32-2717.66" - process $proc$ls180.v:2717$3685 + attribute \src "ls180.v:2769.32-2769.66" + process $proc$ls180.v:2769$3961 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end - attribute \src "ls180.v:2718.32-2718.66" - process $proc$ls180.v:2718$3686 + attribute \src "ls180.v:2770.32-2770.66" + process $proc$ls180.v:2770$3962 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end - attribute \src "ls180.v:2719.32-2719.67" - process $proc$ls180.v:2719$3687 + attribute \src "ls180.v:2771.32-2771.67" + process $proc$ls180.v:2771$3963 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end - attribute \src "ls180.v:2720.32-2720.67" - process $proc$ls180.v:2720$3688 + attribute \src "ls180.v:2772.32-2772.67" + process $proc$ls180.v:2772$3964 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end - attribute \src "ls180.v:2721.32-2721.67" - process $proc$ls180.v:2721$3689 + attribute \src "ls180.v:2773.32-2773.67" + process $proc$ls180.v:2773$3965 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end - attribute \src "ls180.v:2722.32-2722.67" - process $proc$ls180.v:2722$3690 + attribute \src "ls180.v:2774.32-2774.67" + process $proc$ls180.v:2774$3966 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end - attribute \src "ls180.v:2723.32-2723.67" - process $proc$ls180.v:2723$3691 + attribute \src "ls180.v:2775.32-2775.67" + process $proc$ls180.v:2775$3967 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end - attribute \src "ls180.v:2724.32-2724.67" - process $proc$ls180.v:2724$3692 + attribute \src "ls180.v:2776.32-2776.67" + process $proc$ls180.v:2776$3968 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end - attribute \src "ls180.v:2725.32-2725.67" - process $proc$ls180.v:2725$3693 + attribute \src "ls180.v:2777.32-2777.67" + process $proc$ls180.v:2777$3969 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end - attribute \src "ls180.v:2726.32-2726.67" - process $proc$ls180.v:2726$3694 + attribute \src "ls180.v:2778.32-2778.67" + process $proc$ls180.v:2778$3970 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end - attribute \src "ls180.v:2727.32-2727.67" - process $proc$ls180.v:2727$3695 + attribute \src "ls180.v:2779.32-2779.67" + process $proc$ls180.v:2779$3971 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end - attribute \src "ls180.v:2728.32-2728.67" - process $proc$ls180.v:2728$3696 + attribute \src "ls180.v:2780.32-2780.67" + process $proc$ls180.v:2780$3972 assign { } { } assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end - attribute \src "ls180.v:2729.32-2729.67" - process $proc$ls180.v:2729$3697 + attribute \src "ls180.v:2781.32-2781.67" + process $proc$ls180.v:2781$3973 assign { } { } assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end - attribute \src "ls180.v:2730.32-2730.67" - process $proc$ls180.v:2730$3698 + attribute \src "ls180.v:2782.32-2782.67" + process $proc$ls180.v:2782$3974 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end - attribute \src "ls180.v:2731.32-2731.67" - process $proc$ls180.v:2731$3699 + attribute \src "ls180.v:2783.32-2783.67" + process $proc$ls180.v:2783$3975 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end - attribute \src "ls180.v:2732.32-2732.67" - process $proc$ls180.v:2732$3700 + attribute \src "ls180.v:2784.32-2784.67" + process $proc$ls180.v:2784$3976 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:275.5-275.36" - process $proc$ls180.v:275$2834 + attribute \src "ls180.v:280.5-280.24" + process $proc$ls180.v:280$3084 assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + assign $1\main_int_rst[0:0] 1'1 sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init + update \main_int_rst $1\main_int_rst[0:0] end - attribute \src "ls180.v:2767.1-2772.4" - process $proc$ls180.v:2767$13 + attribute \src "ls180.v:2819.1-2824.4" + process $proc$ls180.v:2819$41 assign { } { } assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } @@ -268077,25 +271018,25 @@ module \ls180 sync always update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:2774.1-2784.4" - process $proc$ls180.v:2774$15 + attribute \src "ls180.v:2826.1-2836.4" + process $proc$ls180.v:2826$43 assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2776.2-2783.9" - switch \main_libresocsim_converter0_counter + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + attribute \src "ls180.v:2828.2-2835.9" + switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:2786.1-2832.4" - process $proc$ls180.v:2786$16 + attribute \src "ls180.v:2838.1-2884.4" + process $proc$ls180.v:2838$44 assign { } { } assign { } { } assign { } { } @@ -268106,51 +271047,51 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - assign $0\main_libresocsim_converter0_skip[0:0] 1'0 assign { } { } - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_interface0_converted_interface_ack[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\main_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2798.2-2831.9" + attribute \src "ls180.v:2850.2-2883.9" switch \builder_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } - attribute \src "ls180.v:2801.4-2808.11" - switch \main_libresocsim_converter0_counter + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } + attribute \src "ls180.v:2853.4-2860.11" + switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2809.4-2822.7" - switch $and$ls180.v:2809$17_Y - attribute \src "ls180.v:2809.8-2809.81" + attribute \src "ls180.v:2861.4-2874.7" + switch $and$ls180.v:2861$45_Y + attribute \src "ls180.v:2861.8-2861.91" case 1'1 - assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2810$18_Y - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2812$19_Y - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2813$20_Y - attribute \src "ls180.v:2814.5-2821.8" - switch $or$ls180.v:2814$21_Y - attribute \src "ls180.v:2814.9-2814.97" + assign $0\main_converter0_skip[0:0] $eq$ls180.v:2862$46_Y + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2864$47_Y + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2865$48_Y + attribute \src "ls180.v:2866.5-2873.8" + switch $or$ls180.v:2866$49_Y + attribute \src "ls180.v:2866.9-2866.72" case 1'1 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2815$22_Y - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2817.6-2820.9" - switch $eq$ls180.v:2817$23_Y - attribute \src "ls180.v:2817.10-2817.55" + assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2867$50_Y + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2869.6-2872.9" + switch $eq$ls180.v:2869$51_Y + attribute \src "ls180.v:2869.10-2869.43" case 1'1 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\main_interface0_converted_interface_ack[0:0] 1'1 assign $0\builder_converter0_next_state[0:0] 1'0 case end @@ -268160,63 +271101,47 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2827.4-2829.7" - switch $and$ls180.v:2827$24_Y - attribute \src "ls180.v:2827.8-2827.81" + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2879.4-2881.7" + switch $and$ls180.v:2879$52_Y + attribute \src "ls180.v:2879.8-2879.91" case 1'1 assign $0\builder_converter0_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] - update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] - update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] - update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] - update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] - update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] + update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] + update \main_converter0_skip $0\main_converter0_skip[0:0] update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:280.12-280.45" - process $proc$ls180.v:280$2835 - assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] - end - attribute \src "ls180.v:281.5-281.43" - process $proc$ls180.v:281$2836 - assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:2834.1-2844.4" - process $proc$ls180.v:2834$26 + attribute \src "ls180.v:2886.1-2896.4" + process $proc$ls180.v:2886$54 assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2836.2-2843.9" - switch \main_libresocsim_converter1_counter + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + attribute \src "ls180.v:2888.2-2895.9" + switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:2846.1-2892.4" - process $proc$ls180.v:2846$27 + attribute \src "ls180.v:2898.1-2944.4" + process $proc$ls180.v:2898$55 assign { } { } assign { } { } assign { } { } @@ -268227,51 +271152,51 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_converter1_skip[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 assign { } { } - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + assign $0\main_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2858.2-2891.9" + attribute \src "ls180.v:2910.2-2943.9" switch \builder_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } - attribute \src "ls180.v:2861.4-2868.11" - switch \main_libresocsim_converter1_counter + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } + attribute \src "ls180.v:2913.4-2920.11" + switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2869.4-2882.7" - switch $and$ls180.v:2869$28_Y - attribute \src "ls180.v:2869.8-2869.81" + attribute \src "ls180.v:2921.4-2934.7" + switch $and$ls180.v:2921$56_Y + attribute \src "ls180.v:2921.8-2921.91" case 1'1 - assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2870$29_Y - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2872$30_Y - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2873$31_Y - attribute \src "ls180.v:2874.5-2881.8" - switch $or$ls180.v:2874$32_Y - attribute \src "ls180.v:2874.9-2874.97" + assign $0\main_converter1_skip[0:0] $eq$ls180.v:2922$57_Y + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2924$58_Y + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2925$59_Y + attribute \src "ls180.v:2926.5-2933.8" + switch $or$ls180.v:2926$60_Y + attribute \src "ls180.v:2926.9-2926.72" case 1'1 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2875$33_Y - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2877.6-2880.9" - switch $eq$ls180.v:2877$34_Y - attribute \src "ls180.v:2877.10-2877.55" + assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2927$61_Y + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2929.6-2932.9" + switch $eq$ls180.v:2929$62_Y + attribute \src "ls180.v:2929.10-2929.43" case 1'1 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\main_interface1_converted_interface_ack[0:0] 1'1 assign $0\builder_converter1_next_state[0:0] 1'0 case end @@ -268281,47 +271206,55 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2887.4-2889.7" - switch $and$ls180.v:2887$35_Y - attribute \src "ls180.v:2887.8-2887.81" + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2939.4-2941.7" + switch $and$ls180.v:2939$63_Y + attribute \src "ls180.v:2939.8-2939.91" case 1'1 assign $0\builder_converter1_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] - update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] - update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] - update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] - update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] - update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] + update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] + update \main_converter1_skip $0\main_converter1_skip[0:0] update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] + update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:2894.1-2904.4" - process $proc$ls180.v:2894$37 + attribute \src "ls180.v:2946.1-2956.4" + process $proc$ls180.v:2946$65 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2896.2-2903.9" - switch \main_libresocsim_converter2_counter + assign $0\main_wb_sdram_dat_w[31:0] 0 + attribute \src "ls180.v:2948.2-2955.9" + switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:295.12-295.38" + process $proc$ls180.v:295$3085 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] end - attribute \src "ls180.v:2906.1-2952.4" - process $proc$ls180.v:2906$38 + attribute \src "ls180.v:2958.1-3004.4" + process $proc$ls180.v:2958$66 assign { } { } assign { } { } assign { } { } @@ -268332,51 +271265,51 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 + assign $0\main_wb_sdram_sel[3:0] 4'0000 + assign $0\main_wb_sdram_cyc[0:0] 1'0 + assign $0\main_wb_sdram_stb[0:0] 1'0 + assign $0\main_socbushandler_skip[0:0] 1'0 + assign $0\main_wb_sdram_we[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:2918.2-2951.9" + attribute \src "ls180.v:2970.2-3003.9" switch \builder_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } - attribute \src "ls180.v:2921.4-2928.11" - switch \main_libresocsim_converter2_counter + assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } + attribute \src "ls180.v:2973.4-2980.11" + switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2929.4-2942.7" - switch $and$ls180.v:2929$39_Y - attribute \src "ls180.v:2929.8-2929.87" + attribute \src "ls180.v:2981.4-2994.7" + switch $and$ls180.v:2981$67_Y + attribute \src "ls180.v:2981.8-2981.97" case 1'1 - assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2930$40_Y - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2932$41_Y - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2933$42_Y - attribute \src "ls180.v:2934.5-2941.8" - switch $or$ls180.v:2934$43_Y - attribute \src "ls180.v:2934.9-2934.97" + assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:2982$68_Y + assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we + assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:2984$69_Y + assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:2985$70_Y + attribute \src "ls180.v:2986.5-2993.8" + switch $or$ls180.v:2986$71_Y + attribute \src "ls180.v:2986.9-2986.54" case 1'1 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2935$44_Y - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2937.6-2940.9" - switch $eq$ls180.v:2937$45_Y - attribute \src "ls180.v:2937.10-2937.55" + assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:2987$72_Y + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2989.6-2992.9" + switch $eq$ls180.v:2989$73_Y + attribute \src "ls180.v:2989.10-2989.46" case 1'1 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 assign $0\builder_converter2_next_state[0:0] 1'0 case end @@ -268386,54 +271319,90 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2947.4-2949.7" - switch $and$ls180.v:2947$46_Y - attribute \src "ls180.v:2947.8-2947.87" + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2999.4-3001.7" + switch $and$ls180.v:2999$74_Y + attribute \src "ls180.v:2999.8-2999.97" case 1'1 assign $0\builder_converter2_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] - update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] - update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] - update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] - update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] + update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] + update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] + update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] + update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] + update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] + update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] + update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:2955.1-2961.4" - process $proc$ls180.v:2955$47 + attribute \src "ls180.v:296.5-296.36" + process $proc$ls180.v:296$3086 assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:297.11-297.32" + process $proc$ls180.v:297$3087 assign { } { } - assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2957$50_Y - assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2958$53_Y - assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2959$56_Y - assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2960$59_Y + assign $1\main_rddata_en[2:0] 3'000 sync always - update \main_libresocsim_we $0\main_libresocsim_we[3:0] + sync init + update \main_rddata_en $1\main_rddata_en[2:0] end - attribute \src "ls180.v:296.12-296.46" - process $proc$ls180.v:296$2837 + attribute \src "ls180.v:300.5-300.36" + process $proc$ls180.v:300$3088 assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:3007.1-3017.4" + process $proc$ls180.v:3007$75 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3009$78_Y + assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3010$81_Y + assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3011$84_Y + assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3012$87_Y + assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3013$90_Y + assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3014$93_Y + assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3015$96_Y + assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3016$99_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:301.5-301.35" + process $proc$ls180.v:301$3089 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:302.5-302.36" + process $proc$ls180.v:302$3090 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:2967.1-2972.4" - process $proc$ls180.v:2967$61 + attribute \src "ls180.v:3023.1-3028.4" + process $proc$ls180.v:3023$101 assign { } { } assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:2969.2-2971.5" - switch $and$ls180.v:2969$62_Y - attribute \src "ls180.v:2969.6-2969.90" + attribute \src "ls180.v:3025.2-3027.5" + switch $and$ls180.v:3025$102_Y + attribute \src "ls180.v:3025.6-3025.90" case 1'1 assign $0\main_libresocsim_zero_clear[0:0] 1'1 case @@ -268441,48 +271410,69 @@ module \ls180 sync always update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:297.5-297.44" - process $proc$ls180.v:297$2838 + attribute \src "ls180.v:303.5-303.35" + process $proc$ls180.v:303$3091 assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:298.12-298.48" - process $proc$ls180.v:298$2839 + attribute \src "ls180.v:3032.1-3042.4" + process $proc$ls180.v:3032$104 assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign { } { } + assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3034$107_Y + assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3035$110_Y + assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3036$113_Y + assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3037$116_Y + assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3038$119_Y + assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3039$122_Y + assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3040$125_Y + assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3041$128_Y sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + update \main_sram0_we $0\main_sram0_we[7:0] end - attribute \src "ls180.v:299.11-299.43" - process $proc$ls180.v:299$2840 + attribute \src "ls180.v:3046.1-3056.4" + process $proc$ls180.v:3046$129 assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 + assign { } { } + assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3048$132_Y + assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3049$135_Y + assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3050$138_Y + assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3051$141_Y + assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3052$144_Y + assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3053$147_Y + assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3054$150_Y + assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3055$153_Y sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + update \main_sram1_we $0\main_sram1_we[7:0] end - attribute \src "ls180.v:300.5-300.38" - process $proc$ls180.v:300$2841 + attribute \src "ls180.v:3060.1-3070.4" + process $proc$ls180.v:3060$154 assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + assign { } { } + assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3062$157_Y + assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3063$160_Y + assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3064$163_Y + assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3065$166_Y + assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3066$169_Y + assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3067$172_Y + assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3068$175_Y + assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3069$178_Y sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + update \main_sram2_we $0\main_sram2_we[7:0] end - attribute \src "ls180.v:301.5-301.37" - process $proc$ls180.v:301$2842 + attribute \src "ls180.v:307.5-307.36" + process $proc$ls180.v:307$3092 assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:3011.1-3065.4" - process $proc$ls180.v:3011$64 + attribute \src "ls180.v:3109.1-3163.4" + process $proc$ls180.v:3109$179 assign { } { } assign { } { } assign { } { } @@ -268501,12 +271491,17 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_master_p0_act_n[0:0] 1'1 assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 @@ -268514,14 +271509,9 @@ module \ls180 assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_master_p0_we_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cke[0:0] 1'0 - assign $0\main_sdram_master_p0_odt[0:0] 1'0 - assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - attribute \src "ls180.v:3030.2-3064.5" + attribute \src "ls180.v:3128.2-3162.5" switch \main_sdram_sel - attribute \src "ls180.v:3030.6-3030.20" + attribute \src "ls180.v:3128.6-3128.20" case 1'1 assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank @@ -268539,7 +271529,7 @@ module \ls180 assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3047.6-3047.10" + attribute \src "ls180.v:3145.6-3145.10" case assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank @@ -268578,65 +271568,41 @@ module \ls180 update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:302.5-302.38" - process $proc$ls180.v:302$2843 + attribute \src "ls180.v:312.12-312.45" + process $proc$ls180.v:312$3093 assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:303.5-303.37" - process $proc$ls180.v:303$2844 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:304.5-304.36" - process $proc$ls180.v:304$2845 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:305.5-305.36" - process $proc$ls180.v:305$2846 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] end - attribute \src "ls180.v:306.5-306.40" - process $proc$ls180.v:306$2847 + attribute \src "ls180.v:313.5-313.43" + process $proc$ls180.v:313$3094 assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:3069.1-3085.4" - process $proc$ls180.v:3069$65 + attribute \src "ls180.v:3167.1-3183.4" + process $proc$ls180.v:3167$180 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - attribute \src "ls180.v:3074.2-3084.5" + attribute \src "ls180.v:3172.2-3182.5" switch \main_sdram_command_issue_re - attribute \src "ls180.v:3074.6-3074.33" + attribute \src "ls180.v:3172.6-3172.33" case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3075$66_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3076$67_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3077$68_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3078$69_Y - attribute \src "ls180.v:3079.6-3079.10" + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3173$181_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3174$182_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3175$183_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3176$184_Y + attribute \src "ls180.v:3177.6-3177.10" case assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 @@ -268649,65 +271615,25 @@ module \ls180 update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:307.5-307.38" - process $proc$ls180.v:307$2848 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:308.12-308.47" - process $proc$ls180.v:308$2849 + attribute \src "ls180.v:3226.1-3256.4" + process $proc$ls180.v:3226$193 assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] - end - attribute \src "ls180.v:309.5-309.42" - process $proc$ls180.v:309$2850 assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:310.11-310.50" - process $proc$ls180.v:310$2851 assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] - end - attribute \src "ls180.v:311.5-311.42" - process $proc$ls180.v:311$2852 assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:3128.1-3158.4" - process $proc$ls180.v:3128$78 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 assign { } { } assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3134.2-3157.9" + attribute \src "ls180.v:3232.2-3255.9" switch \builder_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3137.4-3140.7" + attribute \src "ls180.v:3235.4-3238.7" switch \main_sdram_cmd_ready - attribute \src "ls180.v:3137.8-3137.28" + attribute \src "ls180.v:3235.8-3235.28" case 1'1 assign $0\main_sdram_sequencer_start0[0:0] 1'1 assign $0\builder_refresher_next_state[1:0] 2'10 @@ -268716,9 +271642,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3144.4-3148.7" + attribute \src "ls180.v:3242.4-3246.7" switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3144.8-3144.34" + attribute \src "ls180.v:3242.8-3242.34" case 1'1 assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\main_sdram_cmd_last[0:0] 1'1 @@ -268727,13 +271653,13 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3151.4-3155.7" + attribute \src "ls180.v:3249.4-3253.7" switch 1'1 - attribute \src "ls180.v:3151.8-3151.12" + attribute \src "ls180.v:3249.8-3249.12" case 1'1 - attribute \src "ls180.v:3152.5-3154.8" + attribute \src "ls180.v:3250.5-3252.8" switch \main_sdram_wants_refresh - attribute \src "ls180.v:3152.9-3152.33" + attribute \src "ls180.v:3250.9-3250.33" case 1'1 assign $0\builder_refresher_next_state[1:0] 2'01 case @@ -268747,43 +271673,43 @@ module \ls180 update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:3173.1-3180.4" - process $proc$ls180.v:3173$82 + attribute \src "ls180.v:3271.1-3278.4" + process $proc$ls180.v:3271$197 assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3175.2-3179.5" + attribute \src "ls180.v:3273.2-3277.5" switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3175.6-3175.48" + attribute \src "ls180.v:3273.6-3273.48" case 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3177.6-3177.10" + attribute \src "ls180.v:3275.6-3275.10" case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3178$84_Y + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3276$199_Y end sync always update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:318.11-318.36" - process $proc$ls180.v:318$2853 + attribute \src "ls180.v:328.12-328.46" + process $proc$ls180.v:328$3095 assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] end - attribute \src "ls180.v:3184.1-3191.4" - process $proc$ls180.v:3184$91 + attribute \src "ls180.v:3282.1-3289.4" + process $proc$ls180.v:3282$206 assign { } { } assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3186.2-3190.5" - switch $and$ls180.v:3186$92_Y - attribute \src "ls180.v:3186.6-3186.115" + attribute \src "ls180.v:3284.2-3288.5" + switch $and$ls180.v:3284$207_Y + attribute \src "ls180.v:3284.6-3284.115" case 1'1 - attribute \src "ls180.v:3187.3-3189.6" - switch $ne$ls180.v:3187$93_Y - attribute \src "ls180.v:3187.7-3187.143" + attribute \src "ls180.v:3285.3-3287.6" + switch $ne$ls180.v:3285$208_Y + attribute \src "ls180.v:3285.7-3285.143" case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3188$94_Y + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3286$209_Y case end case @@ -268791,48 +271717,56 @@ module \ls180 sync always update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:319.5-319.25" - process $proc$ls180.v:319$2854 + attribute \src "ls180.v:329.5-329.44" + process $proc$ls180.v:329$3096 assign { } { } - assign $1\main_sdram_re[0:0] 1'0 + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_re $1\main_sdram_re[0:0] + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] end - attribute \src "ls180.v:320.11-320.44" - process $proc$ls180.v:320$2855 + attribute \src "ls180.v:330.12-330.48" + process $proc$ls180.v:330$3097 assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 sync always sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] end - attribute \src "ls180.v:3206.1-3213.4" - process $proc$ls180.v:3206$95 + attribute \src "ls180.v:3304.1-3311.4" + process $proc$ls180.v:3304$210 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3208.2-3212.5" + attribute \src "ls180.v:3306.2-3310.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3208.6-3208.58" + attribute \src "ls180.v:3306.6-3306.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3209$96_Y - attribute \src "ls180.v:3210.6-3210.10" + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3307$211_Y + attribute \src "ls180.v:3308.6-3308.10" case assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:321.5-321.33" - process $proc$ls180.v:321$2856 + attribute \src "ls180.v:331.11-331.43" + process $proc$ls180.v:331$3098 assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 + assign $1\main_sdram_master_p0_bank[1:0] 2'00 sync always sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:332.5-332.38" + process $proc$ls180.v:332$3099 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] end - attribute \src "ls180.v:3222.1-3315.4" - process $proc$ls180.v:3222$104 + attribute \src "ls180.v:3320.1-3413.4" + process $proc$ls180.v:3320$219 assign { } { } assign { } { } assign { } { } @@ -268847,37 +271781,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3238.2-3314.9" + attribute \src "ls180.v:3336.2-3412.9" switch \builder_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3240.4-3248.7" - switch $and$ls180.v:3240$105_Y - attribute \src "ls180.v:3240.8-3240.87" + attribute \src "ls180.v:3338.4-3346.7" + switch $and$ls180.v:3338$220_Y + attribute \src "ls180.v:3338.8-3338.87" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3242.5-3244.8" + attribute \src "ls180.v:3340.5-3342.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3242.9-3242.42" + attribute \src "ls180.v:3340.9-3340.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case @@ -268887,27 +271821,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3252.4-3254.7" - switch $and$ls180.v:3252$106_Y - attribute \src "ls180.v:3252.8-3252.87" + attribute \src "ls180.v:3350.4-3352.7" + switch $and$ls180.v:3350$221_Y + attribute \src "ls180.v:3350.8-3350.87" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3258.4-3267.7" + attribute \src "ls180.v:3356.4-3365.7" switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3258.8-3258.44" + attribute \src "ls180.v:3356.8-3356.44" case 1'1 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3263.5-3265.8" + attribute \src "ls180.v:3361.5-3363.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3263.9-3263.42" + attribute \src "ls180.v:3361.9-3361.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'110 case @@ -268918,16 +271852,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3270.4-3272.7" + attribute \src "ls180.v:3368.4-3370.7" switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3270.8-3270.45" + attribute \src "ls180.v:3368.8-3368.45" case 1'1 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3275.4-3277.7" - switch $not$ls180.v:3275$107_Y - attribute \src "ls180.v:3275.8-3275.46" + attribute \src "ls180.v:3373.4-3375.7" + switch $not$ls180.v:3373$222_Y + attribute \src "ls180.v:3373.8-3373.46" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'000 case @@ -268940,51 +271874,51 @@ module \ls180 assign $0\builder_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3286.4-3312.7" + attribute \src "ls180.v:3384.4-3410.7" switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3286.8-3286.43" + attribute \src "ls180.v:3384.8-3384.43" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3288.8-3288.12" + attribute \src "ls180.v:3386.8-3386.12" case - attribute \src "ls180.v:3289.5-3311.8" + attribute \src "ls180.v:3387.5-3409.8" switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3289.9-3289.56" + attribute \src "ls180.v:3387.9-3387.56" case 1'1 - attribute \src "ls180.v:3290.6-3310.9" + attribute \src "ls180.v:3388.6-3408.9" switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3290.10-3290.44" + attribute \src "ls180.v:3388.10-3388.44" case 1'1 - attribute \src "ls180.v:3291.7-3307.10" + attribute \src "ls180.v:3389.7-3405.10" switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3291.11-3291.42" + attribute \src "ls180.v:3389.11-3389.42" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3293.8-3300.11" + attribute \src "ls180.v:3391.8-3398.11" switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3293.12-3293.64" + attribute \src "ls180.v:3391.12-3391.64" case 1'1 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3297.12-3297.16" + attribute \src "ls180.v:3395.12-3395.16" case assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3302.8-3304.11" - switch $and$ls180.v:3302$108_Y - attribute \src "ls180.v:3302.12-3302.88" + attribute \src "ls180.v:3400.8-3402.11" + switch $and$ls180.v:3400$223_Y + attribute \src "ls180.v:3400.12-3400.88" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3305.11-3305.15" + attribute \src "ls180.v:3403.11-3403.15" case assign $0\builder_bankmachine0_next_state[2:0] 3'001 end - attribute \src "ls180.v:3308.10-3308.14" + attribute \src "ls180.v:3406.10-3406.14" case assign $0\builder_bankmachine0_next_state[2:0] 3'011 end @@ -269008,99 +271942,123 @@ module \ls180 update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:325.5-325.38" - process $proc$ls180.v:325$2857 + attribute \src "ls180.v:333.5-333.37" + process $proc$ls180.v:333$3100 assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:326.12-326.46" - process $proc$ls180.v:326$2858 + attribute \src "ls180.v:334.5-334.38" + process $proc$ls180.v:334$3101 assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:327.5-327.33" - process $proc$ls180.v:327$2859 + attribute \src "ls180.v:335.5-335.37" + process $proc$ls180.v:335$3102 assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] end - attribute \src "ls180.v:328.11-328.45" - process $proc$ls180.v:328$2860 + attribute \src "ls180.v:336.5-336.36" + process $proc$ls180.v:336$3103 assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 + assign $1\main_sdram_master_p0_cke[0:0] 1'0 sync always sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] end - attribute \src "ls180.v:329.5-329.34" - process $proc$ls180.v:329$2861 + attribute \src "ls180.v:337.5-337.36" + process $proc$ls180.v:337$3104 assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 + assign $1\main_sdram_master_p0_odt[0:0] 1'0 sync always sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] end - attribute \src "ls180.v:330.12-330.45" - process $proc$ls180.v:330$2862 + attribute \src "ls180.v:338.5-338.40" + process $proc$ls180.v:338$3105 assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 sync always sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] end - attribute \src "ls180.v:331.5-331.32" - process $proc$ls180.v:331$2863 + attribute \src "ls180.v:339.5-339.38" + process $proc$ls180.v:339$3106 assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 sync always sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] end - attribute \src "ls180.v:332.12-332.37" - process $proc$ls180.v:332$2864 + attribute \src "ls180.v:340.12-340.47" + process $proc$ls180.v:340$3107 assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_status $1\main_sdram_status[15:0] + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:341.5-341.42" + process $proc$ls180.v:341$3108 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:342.11-342.50" + process $proc$ls180.v:342$3109 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] end - attribute \src "ls180.v:3330.1-3337.4" - process $proc$ls180.v:3330$112 + attribute \src "ls180.v:3428.1-3435.4" + process $proc$ls180.v:3428$227 assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3332.2-3336.5" + attribute \src "ls180.v:3430.2-3434.5" switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3332.6-3332.48" + attribute \src "ls180.v:3430.6-3430.48" case 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3334.6-3334.10" + attribute \src "ls180.v:3432.6-3432.10" case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3335$114_Y + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3433$229_Y end sync always update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:3341.1-3348.4" - process $proc$ls180.v:3341$121 + attribute \src "ls180.v:343.5-343.42" + process $proc$ls180.v:343$3110 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3439.1-3446.4" + process $proc$ls180.v:3439$236 assign { } { } assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3343.2-3347.5" - switch $and$ls180.v:3343$122_Y - attribute \src "ls180.v:3343.6-3343.115" + attribute \src "ls180.v:3441.2-3445.5" + switch $and$ls180.v:3441$237_Y + attribute \src "ls180.v:3441.6-3441.115" case 1'1 - attribute \src "ls180.v:3344.3-3346.6" - switch $ne$ls180.v:3344$123_Y - attribute \src "ls180.v:3344.7-3344.143" + attribute \src "ls180.v:3442.3-3444.6" + switch $ne$ls180.v:3442$238_Y + attribute \src "ls180.v:3442.7-3442.143" case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3345$124_Y + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3443$239_Y case end case @@ -269108,24 +272066,24 @@ module \ls180 sync always update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:3363.1-3370.4" - process $proc$ls180.v:3363$125 + attribute \src "ls180.v:3461.1-3468.4" + process $proc$ls180.v:3461$240 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3365.2-3369.5" + attribute \src "ls180.v:3463.2-3467.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3365.6-3365.58" + attribute \src "ls180.v:3463.6-3463.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3366$126_Y - attribute \src "ls180.v:3367.6-3367.10" + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3464$241_Y + attribute \src "ls180.v:3465.6-3465.10" case assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3379.1-3472.4" - process $proc$ls180.v:3379$134 + attribute \src "ls180.v:3477.1-3570.4" + process $proc$ls180.v:3477$249 assign { } { } assign { } { } assign { } { } @@ -269140,37 +272098,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3395.2-3471.9" + attribute \src "ls180.v:3493.2-3569.9" switch \builder_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3397.4-3405.7" - switch $and$ls180.v:3397$135_Y - attribute \src "ls180.v:3397.8-3397.87" + attribute \src "ls180.v:3495.4-3503.7" + switch $and$ls180.v:3495$250_Y + attribute \src "ls180.v:3495.8-3495.87" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3399.5-3401.8" + attribute \src "ls180.v:3497.5-3499.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3399.9-3399.42" + attribute \src "ls180.v:3497.9-3497.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case @@ -269180,27 +272138,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3409.4-3411.7" - switch $and$ls180.v:3409$136_Y - attribute \src "ls180.v:3409.8-3409.87" + attribute \src "ls180.v:3507.4-3509.7" + switch $and$ls180.v:3507$251_Y + attribute \src "ls180.v:3507.8-3507.87" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3415.4-3424.7" + attribute \src "ls180.v:3513.4-3522.7" switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3415.8-3415.44" + attribute \src "ls180.v:3513.8-3513.44" case 1'1 assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3420.5-3422.8" + attribute \src "ls180.v:3518.5-3520.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3420.9-3420.42" + attribute \src "ls180.v:3518.9-3518.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'110 case @@ -269211,16 +272169,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3427.4-3429.7" + attribute \src "ls180.v:3525.4-3527.7" switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3427.8-3427.45" + attribute \src "ls180.v:3525.8-3525.45" case 1'1 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3432.4-3434.7" - switch $not$ls180.v:3432$137_Y - attribute \src "ls180.v:3432.8-3432.46" + attribute \src "ls180.v:3530.4-3532.7" + switch $not$ls180.v:3530$252_Y + attribute \src "ls180.v:3530.8-3530.46" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'000 case @@ -269233,51 +272191,51 @@ module \ls180 assign $0\builder_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3443.4-3469.7" + attribute \src "ls180.v:3541.4-3567.7" switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3443.8-3443.43" + attribute \src "ls180.v:3541.8-3541.43" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3445.8-3445.12" + attribute \src "ls180.v:3543.8-3543.12" case - attribute \src "ls180.v:3446.5-3468.8" + attribute \src "ls180.v:3544.5-3566.8" switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3446.9-3446.56" + attribute \src "ls180.v:3544.9-3544.56" case 1'1 - attribute \src "ls180.v:3447.6-3467.9" + attribute \src "ls180.v:3545.6-3565.9" switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3447.10-3447.44" + attribute \src "ls180.v:3545.10-3545.44" case 1'1 - attribute \src "ls180.v:3448.7-3464.10" + attribute \src "ls180.v:3546.7-3562.10" switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3448.11-3448.42" + attribute \src "ls180.v:3546.11-3546.42" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3450.8-3457.11" + attribute \src "ls180.v:3548.8-3555.11" switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3450.12-3450.64" + attribute \src "ls180.v:3548.12-3548.64" case 1'1 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3454.12-3454.16" + attribute \src "ls180.v:3552.12-3552.16" case assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3459.8-3461.11" - switch $and$ls180.v:3459$138_Y - attribute \src "ls180.v:3459.12-3459.88" + attribute \src "ls180.v:3557.8-3559.11" + switch $and$ls180.v:3557$253_Y + attribute \src "ls180.v:3557.12-3557.88" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3462.11-3462.15" + attribute \src "ls180.v:3560.11-3560.15" case assign $0\builder_bankmachine1_next_state[2:0] 3'001 end - attribute \src "ls180.v:3465.10-3465.14" + attribute \src "ls180.v:3563.10-3563.14" case assign $0\builder_bankmachine1_next_state[2:0] 3'011 end @@ -269301,35 +272259,91 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:3487.1-3494.4" - process $proc$ls180.v:3487$142 + attribute \src "ls180.v:350.11-350.36" + process $proc$ls180.v:350$3111 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:351.5-351.25" + process $proc$ls180.v:351$3112 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:352.11-352.44" + process $proc$ls180.v:352$3113 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:353.5-353.33" + process $proc$ls180.v:353$3114 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:357.5-357.38" + process $proc$ls180.v:357$3115 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:358.12-358.46" + process $proc$ls180.v:358$3116 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:3585.1-3592.4" + process $proc$ls180.v:3585$257 assign { } { } assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3489.2-3493.5" + attribute \src "ls180.v:3587.2-3591.5" switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3489.6-3489.48" + attribute \src "ls180.v:3587.6-3587.48" case 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3491.6-3491.10" + attribute \src "ls180.v:3589.6-3589.10" case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3492$144_Y + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3590$259_Y end sync always update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:3498.1-3505.4" - process $proc$ls180.v:3498$151 + attribute \src "ls180.v:359.5-359.33" + process $proc$ls180.v:359$3117 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:3596.1-3603.4" + process $proc$ls180.v:3596$266 assign { } { } assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3500.2-3504.5" - switch $and$ls180.v:3500$152_Y - attribute \src "ls180.v:3500.6-3500.115" + attribute \src "ls180.v:3598.2-3602.5" + switch $and$ls180.v:3598$267_Y + attribute \src "ls180.v:3598.6-3598.115" case 1'1 - attribute \src "ls180.v:3501.3-3503.6" - switch $ne$ls180.v:3501$153_Y - attribute \src "ls180.v:3501.7-3501.143" + attribute \src "ls180.v:3599.3-3601.6" + switch $ne$ls180.v:3599$268_Y + attribute \src "ls180.v:3599.7-3599.143" case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3502$154_Y + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3600$269_Y case end case @@ -269337,25 +272351,56 @@ module \ls180 sync always update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:3520.1-3527.4" - process $proc$ls180.v:3520$155 + attribute \src "ls180.v:360.11-360.45" + process $proc$ls180.v:360$3118 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:361.5-361.34" + process $proc$ls180.v:361$3119 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:3618.1-3625.4" + process $proc$ls180.v:3618$270 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3522.2-3526.5" + attribute \src "ls180.v:3620.2-3624.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3522.6-3522.58" + attribute \src "ls180.v:3620.6-3620.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3523$156_Y - attribute \src "ls180.v:3524.6-3524.10" + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3621$271_Y + attribute \src "ls180.v:3622.6-3622.10" case assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3536.1-3629.4" - process $proc$ls180.v:3536$164 + attribute \src "ls180.v:362.12-362.45" + process $proc$ls180.v:362$3120 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:363.5-363.32" + process $proc$ls180.v:363$3121 assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:3634.1-3727.4" + process $proc$ls180.v:3634$279 assign { } { } assign { } { } assign { } { } @@ -269369,6 +272414,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 @@ -269378,28 +272427,25 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign { } { } assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3552.2-3628.9" + attribute \src "ls180.v:3650.2-3726.9" switch \builder_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3554.4-3562.7" - switch $and$ls180.v:3554$165_Y - attribute \src "ls180.v:3554.8-3554.87" + attribute \src "ls180.v:3652.4-3660.7" + switch $and$ls180.v:3652$280_Y + attribute \src "ls180.v:3652.8-3652.87" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3556.5-3558.8" + attribute \src "ls180.v:3654.5-3656.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3556.9-3556.42" + attribute \src "ls180.v:3654.9-3654.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case @@ -269409,27 +272455,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3566.4-3568.7" - switch $and$ls180.v:3566$166_Y - attribute \src "ls180.v:3566.8-3566.87" + attribute \src "ls180.v:3664.4-3666.7" + switch $and$ls180.v:3664$281_Y + attribute \src "ls180.v:3664.8-3664.87" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3572.4-3581.7" + attribute \src "ls180.v:3670.4-3679.7" switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3572.8-3572.44" + attribute \src "ls180.v:3670.8-3670.44" case 1'1 assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3577.5-3579.8" + attribute \src "ls180.v:3675.5-3677.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3577.9-3577.42" + attribute \src "ls180.v:3675.9-3675.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'110 case @@ -269440,16 +272486,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3584.4-3586.7" + attribute \src "ls180.v:3682.4-3684.7" switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3584.8-3584.45" + attribute \src "ls180.v:3682.8-3682.45" case 1'1 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3589.4-3591.7" - switch $not$ls180.v:3589$167_Y - attribute \src "ls180.v:3589.8-3589.46" + attribute \src "ls180.v:3687.4-3689.7" + switch $not$ls180.v:3687$282_Y + attribute \src "ls180.v:3687.8-3687.46" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'000 case @@ -269462,51 +272508,51 @@ module \ls180 assign $0\builder_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3600.4-3626.7" + attribute \src "ls180.v:3698.4-3724.7" switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3600.8-3600.43" + attribute \src "ls180.v:3698.8-3698.43" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3602.8-3602.12" + attribute \src "ls180.v:3700.8-3700.12" case - attribute \src "ls180.v:3603.5-3625.8" + attribute \src "ls180.v:3701.5-3723.8" switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3603.9-3603.56" + attribute \src "ls180.v:3701.9-3701.56" case 1'1 - attribute \src "ls180.v:3604.6-3624.9" + attribute \src "ls180.v:3702.6-3722.9" switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3604.10-3604.44" + attribute \src "ls180.v:3702.10-3702.44" case 1'1 - attribute \src "ls180.v:3605.7-3621.10" + attribute \src "ls180.v:3703.7-3719.10" switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3605.11-3605.42" + attribute \src "ls180.v:3703.11-3703.42" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3607.8-3614.11" + attribute \src "ls180.v:3705.8-3712.11" switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3607.12-3607.64" + attribute \src "ls180.v:3705.12-3705.64" case 1'1 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3611.12-3611.16" + attribute \src "ls180.v:3709.12-3709.16" case assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3616.8-3618.11" - switch $and$ls180.v:3616$168_Y - attribute \src "ls180.v:3616.12-3616.88" + attribute \src "ls180.v:3714.8-3716.11" + switch $and$ls180.v:3714$283_Y + attribute \src "ls180.v:3714.12-3714.88" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3619.11-3619.15" + attribute \src "ls180.v:3717.11-3717.15" case assign $0\builder_bankmachine2_next_state[2:0] 3'001 end - attribute \src "ls180.v:3622.10-3622.14" + attribute \src "ls180.v:3720.10-3720.14" case assign $0\builder_bankmachine2_next_state[2:0] 3'011 end @@ -269530,59 +272576,43 @@ module \ls180 update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:362.12-362.46" - process $proc$ls180.v:362$2865 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:363.11-363.47" - process $proc$ls180.v:363$2866 + attribute \src "ls180.v:364.12-364.37" + process $proc$ls180.v:364$3122 assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + assign $1\main_sdram_status[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + update \main_sdram_status $1\main_sdram_status[15:0] end - attribute \src "ls180.v:3644.1-3651.4" - process $proc$ls180.v:3644$172 + attribute \src "ls180.v:3742.1-3749.4" + process $proc$ls180.v:3742$287 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3646.2-3650.5" + attribute \src "ls180.v:3744.2-3748.5" switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3646.6-3646.48" + attribute \src "ls180.v:3744.6-3744.48" case 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3648.6-3648.10" + attribute \src "ls180.v:3746.6-3746.10" case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3649$174_Y + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3747$289_Y end sync always update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:365.12-365.45" - process $proc$ls180.v:365$2867 - assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:3655.1-3662.4" - process $proc$ls180.v:3655$181 + attribute \src "ls180.v:3753.1-3760.4" + process $proc$ls180.v:3753$296 assign { } { } assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3657.2-3661.5" - switch $and$ls180.v:3657$182_Y - attribute \src "ls180.v:3657.6-3657.115" + attribute \src "ls180.v:3755.2-3759.5" + switch $and$ls180.v:3755$297_Y + attribute \src "ls180.v:3755.6-3755.115" case 1'1 - attribute \src "ls180.v:3658.3-3660.6" - switch $ne$ls180.v:3658$183_Y - attribute \src "ls180.v:3658.7-3658.143" + attribute \src "ls180.v:3756.3-3758.6" + switch $ne$ls180.v:3756$298_Y + attribute \src "ls180.v:3756.7-3756.143" case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3659$184_Y + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3757$299_Y case end case @@ -269590,56 +272620,25 @@ module \ls180 sync always update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:366.11-366.40" - process $proc$ls180.v:366$2868 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:367.5-367.35" - process $proc$ls180.v:367$2869 - assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:3677.1-3684.4" - process $proc$ls180.v:3677$185 + attribute \src "ls180.v:3775.1-3782.4" + process $proc$ls180.v:3775$300 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3679.2-3683.5" + attribute \src "ls180.v:3777.2-3781.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3679.6-3679.58" + attribute \src "ls180.v:3777.6-3777.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3680$186_Y - attribute \src "ls180.v:3681.6-3681.10" + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3778$301_Y + attribute \src "ls180.v:3779.6-3779.10" case assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:368.5-368.34" - process $proc$ls180.v:368$2870 - assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] - end - attribute \src "ls180.v:369.5-369.35" - process $proc$ls180.v:369$2871 + attribute \src "ls180.v:3791.1-3884.4" + process $proc$ls180.v:3791$309 assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] - end - attribute \src "ls180.v:3693.1-3786.4" - process $proc$ls180.v:3693$194 assign { } { } assign { } { } assign { } { } @@ -269653,38 +272652,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign { } { } + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3709.2-3785.9" + attribute \src "ls180.v:3807.2-3883.9" switch \builder_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3711.4-3719.7" - switch $and$ls180.v:3711$195_Y - attribute \src "ls180.v:3711.8-3711.87" + attribute \src "ls180.v:3809.4-3817.7" + switch $and$ls180.v:3809$310_Y + attribute \src "ls180.v:3809.8-3809.87" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3713.5-3715.8" + attribute \src "ls180.v:3811.5-3813.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3713.9-3713.42" + attribute \src "ls180.v:3811.9-3811.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case @@ -269694,27 +272692,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3723.4-3725.7" - switch $and$ls180.v:3723$196_Y - attribute \src "ls180.v:3723.8-3723.87" + attribute \src "ls180.v:3821.4-3823.7" + switch $and$ls180.v:3821$311_Y + attribute \src "ls180.v:3821.8-3821.87" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3729.4-3738.7" + attribute \src "ls180.v:3827.4-3836.7" switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3729.8-3729.44" + attribute \src "ls180.v:3827.8-3827.44" case 1'1 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3734.5-3736.8" + attribute \src "ls180.v:3832.5-3834.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3734.9-3734.42" + attribute \src "ls180.v:3832.9-3832.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'110 case @@ -269725,16 +272723,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3741.4-3743.7" + attribute \src "ls180.v:3839.4-3841.7" switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3741.8-3741.45" + attribute \src "ls180.v:3839.8-3839.45" case 1'1 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3746.4-3748.7" - switch $not$ls180.v:3746$197_Y - attribute \src "ls180.v:3746.8-3746.46" + attribute \src "ls180.v:3844.4-3846.7" + switch $not$ls180.v:3844$312_Y + attribute \src "ls180.v:3844.8-3844.46" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'000 case @@ -269747,51 +272745,51 @@ module \ls180 assign $0\builder_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3757.4-3783.7" + attribute \src "ls180.v:3855.4-3881.7" switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3757.8-3757.43" + attribute \src "ls180.v:3855.8-3855.43" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3759.8-3759.12" + attribute \src "ls180.v:3857.8-3857.12" case - attribute \src "ls180.v:3760.5-3782.8" + attribute \src "ls180.v:3858.5-3880.8" switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3760.9-3760.56" + attribute \src "ls180.v:3858.9-3858.56" case 1'1 - attribute \src "ls180.v:3761.6-3781.9" + attribute \src "ls180.v:3859.6-3879.9" switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3761.10-3761.44" + attribute \src "ls180.v:3859.10-3859.44" case 1'1 - attribute \src "ls180.v:3762.7-3778.10" + attribute \src "ls180.v:3860.7-3876.10" switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3762.11-3762.42" + attribute \src "ls180.v:3860.11-3860.42" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3764.8-3771.11" + attribute \src "ls180.v:3862.8-3869.11" switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3764.12-3764.64" + attribute \src "ls180.v:3862.12-3862.64" case 1'1 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3768.12-3768.16" + attribute \src "ls180.v:3866.12-3866.16" case assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3773.8-3775.11" - switch $and$ls180.v:3773$198_Y - attribute \src "ls180.v:3773.12-3773.88" + attribute \src "ls180.v:3871.8-3873.11" + switch $and$ls180.v:3871$313_Y + attribute \src "ls180.v:3871.12-3871.88" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3776.11-3776.15" + attribute \src "ls180.v:3874.11-3874.15" case assign $0\builder_bankmachine3_next_state[2:0] 3'001 end - attribute \src "ls180.v:3779.10-3779.14" + attribute \src "ls180.v:3877.10-3877.14" case assign $0\builder_bankmachine3_next_state[2:0] 3'011 end @@ -269815,72 +272813,24 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:370.5-370.34" - process $proc$ls180.v:370$2872 + attribute \src "ls180.v:3904.1-3910.4" + process $proc$ls180.v:3904$352 assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] - end - attribute \src "ls180.v:374.5-374.35" - process $proc$ls180.v:374$2873 - assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:376.5-376.39" - process $proc$ls180.v:376$2874 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:378.5-378.39" - process $proc$ls180.v:378$2875 assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:3806.1-3812.4" - process $proc$ls180.v:3806$237 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3808$250_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3809$263_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3810$276_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3811$289_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3906$365_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3907$378_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3908$391_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3909$404_Y sync always update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:381.5-381.32" - process $proc$ls180.v:381$2876 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:382.5-382.32" - process $proc$ls180.v:382$2877 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:3820.1-3825.4" - process $proc$ls180.v:3820$290 + attribute \src "ls180.v:3918.1-3923.4" + process $proc$ls180.v:3918$405 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3822.2-3824.5" + attribute \src "ls180.v:3920.2-3922.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3822.6-3822.37" + attribute \src "ls180.v:3920.6-3920.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 case @@ -269888,13 +272838,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3826.1-3831.4" - process $proc$ls180.v:3826$291 + attribute \src "ls180.v:3924.1-3929.4" + process $proc$ls180.v:3924$406 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3828.2-3830.5" + attribute \src "ls180.v:3926.2-3928.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3828.6-3828.37" + attribute \src "ls180.v:3926.6-3926.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 case @@ -269902,21 +272852,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:383.5-383.31" - process $proc$ls180.v:383$2878 - assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:3832.1-3837.4" - process $proc$ls180.v:3832$292 + attribute \src "ls180.v:3930.1-3935.4" + process $proc$ls180.v:3930$407 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3834.2-3836.5" + attribute \src "ls180.v:3932.2-3934.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3834.6-3834.37" + attribute \src "ls180.v:3932.6-3932.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 case @@ -269924,40 +272866,40 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:3839.1-3845.4" - process $proc$ls180.v:3839$295 + attribute \src "ls180.v:3937.1-3943.4" + process $proc$ls180.v:3937$410 assign { } { } assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3841$308_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3842$321_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3843$334_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3844$347_Y + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3939$423_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3940$436_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3941$449_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3942$462_Y sync always update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:384.12-384.44" - process $proc$ls180.v:384$2879 + attribute \src "ls180.v:394.12-394.46" + process $proc$ls180.v:394$3123 assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] end - attribute \src "ls180.v:385.11-385.43" - process $proc$ls180.v:385$2880 + attribute \src "ls180.v:395.11-395.47" + process $proc$ls180.v:395$3124 assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 sync always sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:3853.1-3858.4" - process $proc$ls180.v:3853$348 + attribute \src "ls180.v:3951.1-3956.4" + process $proc$ls180.v:3951$463 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3855.2-3857.5" + attribute \src "ls180.v:3953.2-3955.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3855.6-3855.37" + attribute \src "ls180.v:3953.6-3953.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 case @@ -269965,13 +272907,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3859.1-3864.4" - process $proc$ls180.v:3859$349 + attribute \src "ls180.v:3957.1-3962.4" + process $proc$ls180.v:3957$464 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3861.2-3863.5" + attribute \src "ls180.v:3959.2-3961.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3861.6-3861.37" + attribute \src "ls180.v:3959.6-3959.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 case @@ -269979,21 +272921,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:386.5-386.38" - process $proc$ls180.v:386$2881 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3865.1-3870.4" - process $proc$ls180.v:3865$350 + attribute \src "ls180.v:3963.1-3968.4" + process $proc$ls180.v:3963$465 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3867.2-3869.5" + attribute \src "ls180.v:3965.2-3967.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3867.6-3867.37" + attribute \src "ls180.v:3965.6-3965.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 case @@ -270001,28 +272935,20 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:387.5-387.38" - process $proc$ls180.v:387$2882 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3871.1-3879.4" - process $proc$ls180.v:3871$351 + attribute \src "ls180.v:3969.1-3977.4" + process $proc$ls180.v:3969$466 assign { } { } assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3873.2-3875.5" - switch $and$ls180.v:3873$354_Y - attribute \src "ls180.v:3873.6-3873.115" + attribute \src "ls180.v:3971.2-3973.5" + switch $and$ls180.v:3971$469_Y + attribute \src "ls180.v:3971.6-3971.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3876.2-3878.5" - switch $and$ls180.v:3876$357_Y - attribute \src "ls180.v:3876.6-3876.115" + attribute \src "ls180.v:3974.2-3976.5" + switch $and$ls180.v:3974$472_Y + attribute \src "ls180.v:3974.6-3974.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case @@ -270030,28 +272956,28 @@ module \ls180 sync always update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:388.5-388.37" - process $proc$ls180.v:388$2883 + attribute \src "ls180.v:397.12-397.45" + process $proc$ls180.v:397$3125 assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 sync always sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end - attribute \src "ls180.v:3880.1-3888.4" - process $proc$ls180.v:3880$358 + attribute \src "ls180.v:3978.1-3986.4" + process $proc$ls180.v:3978$473 assign { } { } assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3882.2-3884.5" - switch $and$ls180.v:3882$361_Y - attribute \src "ls180.v:3882.6-3882.115" + attribute \src "ls180.v:3980.2-3982.5" + switch $and$ls180.v:3980$476_Y + attribute \src "ls180.v:3980.6-3980.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3885.2-3887.5" - switch $and$ls180.v:3885$364_Y - attribute \src "ls180.v:3885.6-3885.115" + attribute \src "ls180.v:3983.2-3985.5" + switch $and$ls180.v:3983$479_Y + attribute \src "ls180.v:3983.6-3983.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case @@ -270059,20 +272985,28 @@ module \ls180 sync always update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:3889.1-3897.4" - process $proc$ls180.v:3889$365 + attribute \src "ls180.v:398.11-398.40" + process $proc$ls180.v:398$3126 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:3987.1-3995.4" + process $proc$ls180.v:3987$480 assign { } { } assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3891.2-3893.5" - switch $and$ls180.v:3891$368_Y - attribute \src "ls180.v:3891.6-3891.115" + attribute \src "ls180.v:3989.2-3991.5" + switch $and$ls180.v:3989$483_Y + attribute \src "ls180.v:3989.6-3989.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3894.2-3896.5" - switch $and$ls180.v:3894$371_Y - attribute \src "ls180.v:3894.6-3894.115" + attribute \src "ls180.v:3992.2-3994.5" + switch $and$ls180.v:3992$486_Y + attribute \src "ls180.v:3992.6-3992.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case @@ -270080,28 +273014,28 @@ module \ls180 sync always update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:389.5-389.42" - process $proc$ls180.v:389$2884 + attribute \src "ls180.v:399.5-399.35" + process $proc$ls180.v:399$3127 assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] end - attribute \src "ls180.v:3898.1-3906.4" - process $proc$ls180.v:3898$372 + attribute \src "ls180.v:3996.1-4004.4" + process $proc$ls180.v:3996$487 assign { } { } assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3900.2-3902.5" - switch $and$ls180.v:3900$375_Y - attribute \src "ls180.v:3900.6-3900.115" + attribute \src "ls180.v:3998.2-4000.5" + switch $and$ls180.v:3998$490_Y + attribute \src "ls180.v:3998.6-3998.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3903.2-3905.5" - switch $and$ls180.v:3903$378_Y - attribute \src "ls180.v:3903.6-3903.115" + attribute \src "ls180.v:4001.2-4003.5" + switch $and$ls180.v:4001$493_Y + attribute \src "ls180.v:4001.6-4001.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case @@ -270109,17 +273043,16 @@ module \ls180 sync always update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:390.5-390.43" - process $proc$ls180.v:390$2885 + attribute \src "ls180.v:400.5-400.34" + process $proc$ls180.v:400$3128 assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] end - attribute \src "ls180.v:3911.1-3983.4" - process $proc$ls180.v:3911$381 - assign { } { } + attribute \src "ls180.v:4009.1-4081.4" + process $proc$ls180.v:4009$496 assign { } { } assign { } { } assign { } { } @@ -270129,46 +273062,47 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_steerer_sel[1:0] 2'00 - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 assign { } { } - assign $0\main_sdram_en0[0:0] 1'0 assign $0\main_sdram_en1[0:0] 1'0 assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_en0[0:0] 1'0 assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3923.2-3982.9" + attribute \src "ls180.v:4021.2-4080.9" switch \builder_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_en1[0:0] 1'1 assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3927.4-3933.7" + attribute \src "ls180.v:4025.4-4031.7" switch 1'1 - attribute \src "ls180.v:3927.8-3927.12" + attribute \src "ls180.v:4025.8-4025.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3928$388_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4026$503_Y case end - attribute \src "ls180.v:3935.4-3939.7" + attribute \src "ls180.v:4033.4-4037.7" switch \main_sdram_read_available - attribute \src "ls180.v:3935.8-3935.33" + attribute \src "ls180.v:4033.8-4033.33" case 1'1 - attribute \src "ls180.v:3936.5-3938.8" - switch $or$ls180.v:3936$390_Y - attribute \src "ls180.v:3936.9-3936.63" + attribute \src "ls180.v:4034.5-4036.8" + switch $or$ls180.v:4034$505_Y + attribute \src "ls180.v:4034.9-4034.63" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:3940.4-3942.7" + attribute \src "ls180.v:4038.4-4040.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3940.8-3940.32" + attribute \src "ls180.v:4038.8-4038.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -270177,18 +273111,18 @@ module \ls180 case 3'010 assign $0\main_sdram_steerer_sel[1:0] 2'11 assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:3947.4-3949.7" + attribute \src "ls180.v:4045.4-4047.7" switch \main_sdram_cmd_last - attribute \src "ls180.v:3947.8-3947.27" + attribute \src "ls180.v:4045.8-4045.27" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3952.4-3954.7" + attribute \src "ls180.v:4050.4-4052.7" switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:3952.8-3952.32" + attribute \src "ls180.v:4050.8-4050.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case @@ -270204,29 +273138,29 @@ module \ls180 assign $0\main_sdram_en0[0:0] 1'1 assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3965.4-3971.7" + attribute \src "ls180.v:4063.4-4069.7" switch 1'1 - attribute \src "ls180.v:3965.8-3965.12" + attribute \src "ls180.v:4063.8-4063.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3966$397_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4064$512_Y case end - attribute \src "ls180.v:3973.4-3977.7" + attribute \src "ls180.v:4071.4-4075.7" switch \main_sdram_write_available - attribute \src "ls180.v:3973.8-3973.34" + attribute \src "ls180.v:4071.8-4071.34" case 1'1 - attribute \src "ls180.v:3974.5-3976.8" - switch $or$ls180.v:3974$399_Y - attribute \src "ls180.v:3974.9-3974.62" + attribute \src "ls180.v:4072.5-4074.8" + switch $or$ls180.v:4072$514_Y + attribute \src "ls180.v:4072.9-4072.62" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'100 case end case end - attribute \src "ls180.v:3978.4-3980.7" + attribute \src "ls180.v:4076.4-4078.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3978.8-3978.32" + attribute \src "ls180.v:4076.8-4076.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -270243,45 +273177,53 @@ module \ls180 update \main_sdram_en1 $0\main_sdram_en1[0:0] update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:396.11-396.44" - process $proc$ls180.v:396$2886 + attribute \src "ls180.v:401.5-401.35" + process $proc$ls180.v:401$3129 assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] end - attribute \src "ls180.v:398.5-398.38" - process $proc$ls180.v:398$2887 + attribute \src "ls180.v:402.5-402.34" + process $proc$ls180.v:402$3130 assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:399.5-399.38" - process $proc$ls180.v:399$2888 + attribute \src "ls180.v:406.5-406.35" + process $proc$ls180.v:406$3131 assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] end - attribute \src "ls180.v:400.5-400.39" - process $proc$ls180.v:400$2889 + attribute \src "ls180.v:408.5-408.39" + process $proc$ls180.v:408$3132 assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "ls180.v:4007.1-4020.4" - process $proc$ls180.v:4007$528 + attribute \src "ls180.v:410.5-410.39" + process $proc$ls180.v:410$3133 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:4105.1-4118.4" + process $proc$ls180.v:4105$643 assign { } { } assign { } { } assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:4010.2-4019.9" + attribute \src "ls180.v:4108.2-4117.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -270296,11 +273238,11 @@ module \ls180 update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:4027.1-4037.4" - process $proc$ls180.v:4027$530 + attribute \src "ls180.v:4125.1-4135.4" + process $proc$ls180.v:4125$645 assign { } { } assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4029.2-4036.9" + attribute \src "ls180.v:4127.2-4134.9" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -270313,16 +273255,16 @@ module \ls180 sync always update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:403.5-403.38" - process $proc$ls180.v:403$2890 + attribute \src "ls180.v:413.5-413.32" + process $proc$ls180.v:413$3134 assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 + assign $1\main_sdram_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end - attribute \src "ls180.v:4039.1-4085.4" - process $proc$ls180.v:4039$531 + attribute \src "ls180.v:4137.1-4183.4" + process $proc$ls180.v:4137$646 assign { } { } assign { } { } assign { } { } @@ -270334,22 +273276,22 @@ module \ls180 assign { } { } assign { } { } assign $0\main_litedram_wb_we[0:0] 1'0 - assign $0\main_converter_skip[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 assign { } { } + assign $0\main_converter_skip[0:0] 1'0 assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\main_litedram_wb_cyc[0:0] 1'0 assign $0\main_litedram_wb_stb[0:0] 1'0 assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4051.2-4084.9" + attribute \src "ls180.v:4149.2-4182.9" switch \builder_converter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4054.4-4061.11" + attribute \src "ls180.v:4152.4-4159.11" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -270359,23 +273301,23 @@ module \ls180 assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] case end - attribute \src "ls180.v:4062.4-4075.7" - switch $and$ls180.v:4062$532_Y - attribute \src "ls180.v:4062.8-4062.47" + attribute \src "ls180.v:4160.4-4173.7" + switch $and$ls180.v:4160$647_Y + attribute \src "ls180.v:4160.8-4160.47" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4063$533_Y + assign $0\main_converter_skip[0:0] $eq$ls180.v:4161$648_Y assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4065$534_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4066$535_Y - attribute \src "ls180.v:4067.5-4074.8" - switch $or$ls180.v:4067$536_Y - attribute \src "ls180.v:4067.9-4067.53" + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4163$649_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4164$650_Y + attribute \src "ls180.v:4165.5-4172.8" + switch $or$ls180.v:4165$651_Y + attribute \src "ls180.v:4165.9-4165.53" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4068$537_Y + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4166$652_Y assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4070.6-4073.9" - switch $eq$ls180.v:4070$538_Y - attribute \src "ls180.v:4070.10-4070.42" + attribute \src "ls180.v:4168.6-4171.9" + switch $eq$ls180.v:4168$653_Y + attribute \src "ls180.v:4168.10-4168.42" case 1'1 assign $0\main_wb_sdram_ack[0:0] 1'1 assign $0\builder_converter_next_state[0:0] 1'0 @@ -270389,9 +273331,9 @@ module \ls180 case assign $0\main_converter_counter_converter_next_value[0:0] 1'0 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4080.4-4082.7" - switch $and$ls180.v:4080$539_Y - attribute \src "ls180.v:4080.8-4080.47" + attribute \src "ls180.v:4178.4-4180.7" + switch $and$ls180.v:4178$654_Y + attribute \src "ls180.v:4178.8-4178.47" case 1'1 assign $0\builder_converter_next_state[0:0] 1'1 case @@ -270409,45 +273351,85 @@ module \ls180 update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:404.11-404.46" - process $proc$ls180.v:404$2891 + attribute \src "ls180.v:414.5-414.32" + process $proc$ls180.v:414$3135 assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + assign $1\main_sdram_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] end - attribute \src "ls180.v:405.5-405.38" - process $proc$ls180.v:405$2892 + attribute \src "ls180.v:415.5-415.31" + process $proc$ls180.v:415$3136 assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 + assign $1\main_sdram_cmd_last[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end - attribute \src "ls180.v:411.5-411.51" - process $proc$ls180.v:411$2893 + attribute \src "ls180.v:416.12-416.44" + process $proc$ls180.v:416$3137 assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:412.5-412.51" - process $proc$ls180.v:412$2894 + attribute \src "ls180.v:417.11-417.43" + process $proc$ls180.v:417$3138 assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end - attribute \src "ls180.v:4130.1-4135.4" - process $proc$ls180.v:4130$571 + attribute \src "ls180.v:418.5-418.38" + process $proc$ls180.v:418$3139 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:419.5-419.38" + process $proc$ls180.v:419$3140 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:420.5-420.37" + process $proc$ls180.v:420$3141 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:421.5-421.42" + process $proc$ls180.v:421$3142 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:422.5-422.43" + process $proc$ls180.v:422$3143 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:4228.1-4233.4" + process $proc$ls180.v:4228$686 assign { } { } assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4132.2-4134.5" - switch $and$ls180.v:4132$572_Y - attribute \src "ls180.v:4132.6-4132.79" + attribute \src "ls180.v:4230.2-4232.5" + switch $and$ls180.v:4230$687_Y + attribute \src "ls180.v:4230.6-4230.79" case 1'1 assign $0\main_uart_tx_clear[0:0] 1'1 case @@ -270455,8 +273437,8 @@ module \ls180 sync always update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:4136.1-4140.4" - process $proc$ls180.v:4136$573 + attribute \src "ls180.v:4234.1-4238.4" + process $proc$ls180.v:4234$688 assign { } { } assign { } { } assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status @@ -270464,21 +273446,13 @@ module \ls180 sync always update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:414.5-414.47" - process $proc$ls180.v:414$2895 - assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] - end - attribute \src "ls180.v:4141.1-4146.4" - process $proc$ls180.v:4141$574 + attribute \src "ls180.v:4239.1-4244.4" + process $proc$ls180.v:4239$689 assign { } { } assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4143.2-4145.5" - switch $and$ls180.v:4143$575_Y - attribute \src "ls180.v:4143.6-4143.79" + attribute \src "ls180.v:4241.2-4243.5" + switch $and$ls180.v:4241$690_Y + attribute \src "ls180.v:4241.6-4241.79" case 1'1 assign $0\main_uart_rx_clear[0:0] 1'1 case @@ -270486,8 +273460,8 @@ module \ls180 sync always update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:4147.1-4151.4" - process $proc$ls180.v:4147$576 + attribute \src "ls180.v:4245.1-4249.4" + process $proc$ls180.v:4245$691 assign { } { } assign { } { } assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending @@ -270495,96 +273469,73 @@ module \ls180 sync always update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:415.5-415.45" - process $proc$ls180.v:415$2896 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] - end - attribute \src "ls180.v:416.5-416.45" - process $proc$ls180.v:416$2897 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:4169.1-4176.4" - process $proc$ls180.v:4169$584 + attribute \src "ls180.v:4267.1-4274.4" + process $proc$ls180.v:4267$699 assign { } { } assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4171.2-4175.5" + attribute \src "ls180.v:4269.2-4273.5" switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4171.6-4171.31" + attribute \src "ls180.v:4269.6-4269.31" case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4172$585_Y - attribute \src "ls180.v:4173.6-4173.10" + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4270$700_Y + attribute \src "ls180.v:4271.6-4271.10" case assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce end sync always update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:417.12-417.57" - process $proc$ls180.v:417$2898 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:419.5-419.51" - process $proc$ls180.v:419$2899 + attribute \src "ls180.v:428.11-428.44" + process $proc$ls180.v:428$3144 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] end - attribute \src "ls180.v:4199.1-4206.4" - process $proc$ls180.v:4199$595 + attribute \src "ls180.v:4297.1-4304.4" + process $proc$ls180.v:4297$710 assign { } { } assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4201.2-4205.5" + attribute \src "ls180.v:4299.2-4303.5" switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4201.6-4201.31" + attribute \src "ls180.v:4299.6-4299.31" case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4202$596_Y - attribute \src "ls180.v:4203.6-4203.10" + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4300$711_Y + attribute \src "ls180.v:4301.6-4301.10" case assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce end sync always update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:420.5-420.51" - process $proc$ls180.v:420$2900 + attribute \src "ls180.v:430.5-430.38" + process $proc$ls180.v:430$3145 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end - attribute \src "ls180.v:421.5-421.50" - process $proc$ls180.v:421$2901 + attribute \src "ls180.v:431.5-431.38" + process $proc$ls180.v:431$3146 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_postponer_count[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] end - attribute \src "ls180.v:422.5-422.54" - process $proc$ls180.v:422$2902 + attribute \src "ls180.v:432.5-432.39" + process $proc$ls180.v:432$3147 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_sdram_sequencer_start0[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:4229.1-4277.4" - process $proc$ls180.v:4229$606 + attribute \src "ls180.v:4327.1-4375.4" + process $proc$ls180.v:4327$721 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -270594,25 +273545,24 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 assign $0\main_spimaster25_clk_enable[0:0] 1'0 assign $0\main_spimaster26_cs_enable[0:0] 1'0 - assign { } { } assign $0\main_spimaster28_mosi_latch[0:0] 1'0 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 assign $0\main_spimaster29_miso_latch[0:0] 1'0 assign $0\main_spimaster3_irq[0:0] 1'0 assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4240.2-4276.9" + attribute \src "ls180.v:4338.2-4374.9" switch \builder_spimaster0_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4244.4-4247.7" + attribute \src "ls180.v:4342.4-4345.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4244.8-4244.33" + attribute \src "ls180.v:4342.8-4342.33" case 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'10 @@ -270622,15 +273572,15 @@ module \ls180 case 2'10 assign $0\main_spimaster25_clk_enable[0:0] 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4252.4-4258.7" + attribute \src "ls180.v:4350.4-4356.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4252.8-4252.33" + attribute \src "ls180.v:4350.8-4350.33" case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4253$607_Y + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4351$722_Y assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4255.5-4257.8" - switch $eq$ls180.v:4255$609_Y - attribute \src "ls180.v:4255.9-4255.68" + attribute \src "ls180.v:4353.5-4355.8" + switch $eq$ls180.v:4353$724_Y + attribute \src "ls180.v:4353.9-4353.68" case 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'11 case @@ -270640,9 +273590,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4262.4-4266.7" + attribute \src "ls180.v:4360.4-4364.7" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4262.8-4262.33" + attribute \src "ls180.v:4360.8-4360.33" case 1'1 assign $0\main_spimaster29_miso_latch[0:0] 1'1 assign $0\main_spimaster3_irq[0:0] 1'1 @@ -270652,9 +273602,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4270.4-4274.7" + attribute \src "ls180.v:4368.4-4372.7" switch \main_spimaster0_start - attribute \src "ls180.v:4270.8-4270.29" + attribute \src "ls180.v:4368.8-4368.29" case 1'1 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster28_mosi_latch[0:0] 1'1 @@ -270673,41 +273623,32 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:423.5-423.55" - process $proc$ls180.v:423$2903 + attribute \src "ls180.v:435.5-435.38" + process $proc$ls180.v:435$3148 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:424.5-424.56" - process $proc$ls180.v:424$2904 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:425.5-425.50" - process $proc$ls180.v:425$2905 + attribute \src "ls180.v:436.11-436.46" + process $proc$ls180.v:436$3149 assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:428.5-428.67" - process $proc$ls180.v:428$2906 + attribute \src "ls180.v:437.5-437.38" + process $proc$ls180.v:437$3150 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_sequencer_count[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] end - attribute \src "ls180.v:4288.1-4336.4" - process $proc$ls180.v:4288$614 - assign { } { } + attribute \src "ls180.v:4386.1-4434.4" + process $proc$ls180.v:4386$729 assign { } { } assign { } { } assign { } { } @@ -270725,16 +273666,17 @@ module \ls180 assign $0\main_spisdcard_done0[0:0] 1'0 assign $0\main_spisdcard_miso_latch[0:0] 1'0 assign $0\main_spisdcard_irq[0:0] 1'0 + assign { } { } assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4299.2-4335.9" + attribute \src "ls180.v:4397.2-4433.9" switch \builder_spimaster1_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4303.4-4306.7" + attribute \src "ls180.v:4401.4-4404.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4303.8-4303.31" + attribute \src "ls180.v:4401.8-4401.31" case 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'10 @@ -270744,15 +273686,15 @@ module \ls180 case 2'10 assign $0\main_spisdcard_clk_enable[0:0] 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4311.4-4317.7" + attribute \src "ls180.v:4409.4-4415.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4311.8-4311.31" + attribute \src "ls180.v:4409.8-4409.31" case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4312$615_Y + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4410$730_Y assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4314.5-4316.8" - switch $eq$ls180.v:4314$617_Y - attribute \src "ls180.v:4314.9-4314.66" + attribute \src "ls180.v:4412.5-4414.8" + switch $eq$ls180.v:4412$732_Y + attribute \src "ls180.v:4412.9-4412.66" case 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'11 case @@ -270762,9 +273704,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4321.4-4325.7" + attribute \src "ls180.v:4419.4-4423.7" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4321.8-4321.31" + attribute \src "ls180.v:4419.8-4419.31" case 1'1 assign $0\main_spisdcard_miso_latch[0:0] 1'1 assign $0\main_spisdcard_irq[0:0] 1'1 @@ -270774,9 +273716,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4329.4-4333.7" + attribute \src "ls180.v:4427.4-4431.7" switch \main_spisdcard_start0 - attribute \src "ls180.v:4329.8-4329.29" + attribute \src "ls180.v:4427.8-4427.29" case 1'1 assign $0\main_spisdcard_done0[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'1 @@ -270795,19 +273737,35 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:429.5-429.66" - process $proc$ls180.v:429$2907 + attribute \src "ls180.v:443.5-443.51" + process $proc$ls180.v:443$3151 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:444.5-444.51" + process $proc$ls180.v:444$3152 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "ls180.v:4368.1-4396.4" - process $proc$ls180.v:4368$639 + attribute \src "ls180.v:446.5-446.47" + process $proc$ls180.v:446$3153 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:4466.1-4494.4" + process $proc$ls180.v:4466$754 assign { } { } assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4370.2-4395.9" + attribute \src "ls180.v:4468.2-4493.9" switch \main_sdphy_clocker_storage attribute \src "ls180.v:0.0-0.0" case 9'000000100 @@ -270837,8 +273795,32 @@ module \ls180 sync always update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:4398.1-4431.4" - process $proc$ls180.v:4398$642 + attribute \src "ls180.v:447.5-447.45" + process $proc$ls180.v:447$3154 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:448.5-448.45" + process $proc$ls180.v:448$3155 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:449.12-449.57" + process $proc$ls180.v:449$3156 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:4496.1-4529.4" + process $proc$ls180.v:4496$757 assign { } { } assign { } { } assign { } { } @@ -270847,16 +273829,16 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign { } { } assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4408.2-4430.9" + attribute \src "ls180.v:4506.2-4528.9" switch \builder_sdphy_sdphyinit_state attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -270865,15 +273847,15 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4415.4-4421.7" + attribute \src "ls180.v:4513.4-4519.7" switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4415.8-4415.38" + attribute \src "ls180.v:4513.8-4513.38" case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4416$643_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4514$758_Y assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4418.5-4420.8" - switch $eq$ls180.v:4418$644_Y - attribute \src "ls180.v:4418.9-4418.41" + attribute \src "ls180.v:4516.5-4518.8" + switch $eq$ls180.v:4516$759_Y + attribute \src "ls180.v:4516.9-4516.41" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 case @@ -270884,9 +273866,9 @@ module \ls180 case assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4426.4-4428.7" + attribute \src "ls180.v:4524.4-4526.7" switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4426.8-4426.37" + attribute \src "ls180.v:4524.8-4524.37" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 case @@ -270902,8 +273884,32 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:4432.1-4508.4" - process $proc$ls180.v:4432$645 + attribute \src "ls180.v:451.5-451.51" + process $proc$ls180.v:451$3157 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:452.5-452.51" + process $proc$ls180.v:452$3158 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:453.5-453.50" + process $proc$ls180.v:453$3159 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:4530.1-4606.4" + process $proc$ls180.v:4530$760 assign { } { } assign { } { } assign { } { } @@ -270913,21 +273919,21 @@ module \ls180 assign { } { } assign { } { } assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign { } { } assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4442.2-4507.9" + attribute \src "ls180.v:4540.2-4605.9" switch \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4446.4-4471.11" + attribute \src "ls180.v:4544.4-4569.11" switch \main_sdphy_cmdw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -270955,22 +273961,22 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] case end - attribute \src "ls180.v:4472.4-4483.7" + attribute \src "ls180.v:4570.4-4581.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4472.8-4472.38" + attribute \src "ls180.v:4570.8-4570.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4473$646_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4571$761_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4475.5-4482.8" - switch $eq$ls180.v:4475$647_Y - attribute \src "ls180.v:4475.9-4475.40" + attribute \src "ls180.v:4573.5-4580.8" + switch $eq$ls180.v:4573$762_Y + attribute \src "ls180.v:4573.9-4573.40" case 1'1 - attribute \src "ls180.v:4476.6-4481.9" + attribute \src "ls180.v:4574.6-4579.9" switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4476.10-4476.35" + attribute \src "ls180.v:4574.10-4574.35" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4478.10-4478.14" + attribute \src "ls180.v:4576.10-4576.14" case assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -270984,15 +273990,15 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4489.4-4496.7" + attribute \src "ls180.v:4587.4-4594.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4489.8-4489.38" + attribute \src "ls180.v:4587.8-4587.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4490$648_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4588$763_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4492.5-4495.8" - switch $eq$ls180.v:4492$649_Y - attribute \src "ls180.v:4492.9-4492.40" + attribute \src "ls180.v:4590.5-4593.8" + switch $eq$ls180.v:4590$764_Y + attribute \src "ls180.v:4590.9-4590.40" case 1'1 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -271004,12 +274010,12 @@ module \ls180 case assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4501.4-4505.7" - switch $and$ls180.v:4501$650_Y - attribute \src "ls180.v:4501.8-4501.69" + attribute \src "ls180.v:4599.4-4603.7" + switch $and$ls180.v:4599$765_Y + attribute \src "ls180.v:4599.8-4599.69" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4503.8-4503.12" + attribute \src "ls180.v:4601.8-4601.12" case assign $0\main_sdphy_cmdw_done[0:0] 1'1 end @@ -271024,48 +274030,56 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:444.11-444.68" - process $proc$ls180.v:444$2908 + attribute \src "ls180.v:454.5-454.54" + process $proc$ls180.v:454$3160 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:445.5-445.64" - process $proc$ls180.v:445$2909 + attribute \src "ls180.v:455.5-455.55" + process $proc$ls180.v:455$3161 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:446.11-446.70" - process $proc$ls180.v:446$2910 + attribute \src "ls180.v:456.5-456.56" + process $proc$ls180.v:456$3162 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:447.11-447.70" - process $proc$ls180.v:447$2911 + attribute \src "ls180.v:457.5-457.50" + process $proc$ls180.v:457$3163 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:448.11-448.73" - process $proc$ls180.v:448$2912 + attribute \src "ls180.v:460.5-460.67" + process $proc$ls180.v:460$3164 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:4542.1-4635.4" - process $proc$ls180.v:4542$659 + attribute \src "ls180.v:461.5-461.66" + process $proc$ls180.v:461$3165 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4640.1-4733.4" + process $proc$ls180.v:4640$774 assign { } { } assign { } { } assign { } { } @@ -271089,35 +274103,35 @@ module \ls180 assign { } { } assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4560.2-4634.9" + attribute \src "ls180.v:4658.2-4732.9" switch \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4568$660_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4666$775_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4565.4-4567.7" + attribute \src "ls180.v:4663.4-4665.7" switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4565.8-4565.49" + attribute \src "ls180.v:4663.8-4663.49" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4570.4-4573.7" - switch $eq$ls180.v:4570$661_Y - attribute \src "ls180.v:4570.8-4570.41" + attribute \src "ls180.v:4668.4-4671.7" + switch $eq$ls180.v:4668$776_Y + attribute \src "ls180.v:4668.8-4668.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -271128,30 +274142,30 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4579$663_Y + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4677$778_Y assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4596$666_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4694$781_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4581.4-4595.7" - switch $and$ls180.v:4581$664_Y - attribute \src "ls180.v:4581.8-4581.69" + attribute \src "ls180.v:4679.4-4693.7" + switch $and$ls180.v:4679$779_Y + attribute \src "ls180.v:4679.8-4679.69" case 1'1 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4583$665_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4681$780_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4585.5-4594.8" + attribute \src "ls180.v:4683.5-4692.8" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4585.9-4585.36" + attribute \src "ls180.v:4683.9-4683.36" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4587.6-4593.9" + attribute \src "ls180.v:4685.6-4691.9" switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4587.10-4587.35" + attribute \src "ls180.v:4685.10-4685.35" case 1'1 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4591.10-4591.14" + attribute \src "ls180.v:4689.10-4689.14" case assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 end @@ -271159,9 +274173,9 @@ module \ls180 end case end - attribute \src "ls180.v:4598.4-4601.7" - switch $eq$ls180.v:4598$667_Y - attribute \src "ls180.v:4598.8-4598.41" + attribute \src "ls180.v:4696.4-4699.7" + switch $eq$ls180.v:4696$782_Y + attribute \src "ls180.v:4696.8-4696.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -271172,15 +274186,15 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4607.4-4613.7" + attribute \src "ls180.v:4705.4-4711.7" switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4607.8-4607.38" + attribute \src "ls180.v:4705.8-4705.38" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4608$668_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4706$783_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4610.5-4612.8" - switch $eq$ls180.v:4610$669_Y - attribute \src "ls180.v:4610.9-4610.40" + attribute \src "ls180.v:4708.5-4710.8" + switch $eq$ls180.v:4708$784_Y + attribute \src "ls180.v:4708.9-4708.40" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -271192,9 +274206,9 @@ module \ls180 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4619.4-4621.7" - switch $and$ls180.v:4619$670_Y - attribute \src "ls180.v:4619.8-4619.69" + attribute \src "ls180.v:4717.4-4719.7" + switch $and$ls180.v:4717$785_Y + attribute \src "ls180.v:4717.8-4717.69" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -271205,9 +274219,9 @@ module \ls180 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4628.4-4632.7" - switch $and$ls180.v:4628$672_Y - attribute \src "ls180.v:4628.8-4628.94" + attribute \src "ls180.v:4726.4-4730.7" + switch $and$ls180.v:4726$787_Y + attribute \src "ls180.v:4726.8-4726.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 @@ -271233,42 +274247,50 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:4669.1-4696.4" - process $proc$ls180.v:4669$680 + attribute \src "ls180.v:476.11-476.68" + process $proc$ls180.v:476$3166 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:4767.1-4794.4" + process $proc$ls180.v:4767$795 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_dataw_error[0:0] 1'0 assign { } { } assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4677.2-4695.9" + attribute \src "ls180.v:4775.2-4793.9" switch \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4682.4-4686.7" + attribute \src "ls180.v:4780.4-4784.7" switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4682.8-4682.50" + attribute \src "ls180.v:4780.8-4780.50" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4683$681_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4684$682_Y + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4781$796_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4782$797_Y assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 case end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4689.4-4693.7" + attribute \src "ls180.v:4787.4-4791.7" switch \main_sdphy_dataw_start - attribute \src "ls180.v:4689.8-4689.30" + attribute \src "ls180.v:4787.8-4787.30" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 @@ -271284,16 +274306,32 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:469.5-469.59" - process $proc$ls180.v:469$2913 + attribute \src "ls180.v:477.5-477.64" + process $proc$ls180.v:477$3167 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:4697.1-4769.4" - process $proc$ls180.v:4697$683 + attribute \src "ls180.v:478.11-478.70" + process $proc$ls180.v:478$3168 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:479.11-479.70" + process $proc$ls180.v:479$3169 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:4795.1-4867.4" + process $proc$ls180.v:4795$798 assign { } { } assign { } { } assign { } { } @@ -271303,36 +274341,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign { } { } + assign $0\main_sdphy_dataw_start[0:0] 1'0 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4708.2-4768.9" + attribute \src "ls180.v:4806.2-4866.9" switch \builder_sdphy_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4713.4-4715.7" + attribute \src "ls180.v:4811.4-4813.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4713.8-4713.39" + attribute \src "ls180.v:4811.8-4811.39" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4718$684_Y + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4816$799_Y assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4721.4-4728.11" + attribute \src "ls180.v:4819.4-4826.11" switch \main_sdphy_dataw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -271342,24 +274380,24 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] case end - attribute \src "ls180.v:4729.4-4741.7" + attribute \src "ls180.v:4827.4-4839.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4729.8-4729.39" + attribute \src "ls180.v:4827.8-4827.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4730$685_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4828$800_Y assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4732.5-4740.8" - switch $eq$ls180.v:4732$686_Y - attribute \src "ls180.v:4732.9-4732.41" + attribute \src "ls180.v:4830.5-4838.8" + switch $eq$ls180.v:4830$801_Y + attribute \src "ls180.v:4830.9-4830.41" case 1'1 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4735.6-4739.9" + attribute \src "ls180.v:4833.6-4837.9" switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4735.10-4735.36" + attribute \src "ls180.v:4833.10-4833.36" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4737.10-4737.14" + attribute \src "ls180.v:4835.10-4835.14" case assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 end @@ -271372,9 +274410,9 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4747.4-4750.7" + attribute \src "ls180.v:4845.4-4848.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4747.8-4747.39" + attribute \src "ls180.v:4845.8-4845.39" case 1'1 assign $0\main_sdphy_dataw_start[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 @@ -271383,13 +274421,13 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4754.4-4759.7" + attribute \src "ls180.v:4852.4-4857.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4754.8-4754.39" + attribute \src "ls180.v:4852.8-4852.39" case 1'1 - attribute \src "ls180.v:4755.5-4758.8" + attribute \src "ls180.v:4853.5-4856.8" switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4755.9-4755.51" + attribute \src "ls180.v:4853.9-4853.51" case 1'1 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 @@ -271401,9 +274439,9 @@ module \ls180 case assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4764.4-4766.7" - switch $and$ls180.v:4764$687_Y - attribute \src "ls180.v:4764.8-4764.71" + attribute \src "ls180.v:4862.4-4864.7" + switch $and$ls180.v:4862$802_Y + attribute \src "ls180.v:4862.8-4862.71" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 case @@ -271420,80 +274458,16 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:471.5-471.59" - process $proc$ls180.v:471$2914 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:472.5-472.58" - process $proc$ls180.v:472$2915 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:473.5-473.64" - process $proc$ls180.v:473$2916 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:474.12-474.74" - process $proc$ls180.v:474$2917 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:475.12-475.47" - process $proc$ls180.v:475$2918 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:476.5-476.46" - process $proc$ls180.v:476$2919 - assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] - end - attribute \src "ls180.v:478.5-478.44" - process $proc$ls180.v:478$2920 - assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:479.5-479.45" - process $proc$ls180.v:479$2921 + attribute \src "ls180.v:480.11-480.73" + process $proc$ls180.v:480$3170 assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] - end - attribute \src "ls180.v:480.5-480.54" - process $proc$ls180.v:480$2922 - assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:4803.1-4904.4" - process $proc$ls180.v:4803$695 + attribute \src "ls180.v:4901.1-5002.4" + process $proc$ls180.v:4901$810 assign { } { } assign { } { } assign { } { } @@ -271509,23 +274483,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_source_last[0:0] 1'0 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 assign { } { } assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4820.2-4903.9" + attribute \src "ls180.v:4918.2-5001.9" switch \builder_sdphy_sdphydatar_state attribute \src "ls180.v:0.0-0.0" case 3'001 @@ -271534,18 +274508,18 @@ module \ls180 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 assign { } { } assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4830$697_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4928$812_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4827.4-4829.7" + attribute \src "ls180.v:4925.4-4927.7" switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:4827.8-4827.51" + attribute \src "ls180.v:4925.8-4925.51" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4832.4-4835.7" - switch $eq$ls180.v:4832$698_Y - attribute \src "ls180.v:4832.8-4832.42" + attribute \src "ls180.v:4930.4-4933.7" + switch $eq$ls180.v:4930$813_Y + attribute \src "ls180.v:4930.8-4930.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -271556,48 +274530,48 @@ module \ls180 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4841$701_Y + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4939$816_Y assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4862$703_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4960$818_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4843.4-4861.7" + attribute \src "ls180.v:4941.4-4959.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:4843.8-4843.37" + attribute \src "ls180.v:4941.8-4941.37" case 1'1 - attribute \src "ls180.v:4844.5-4860.8" + attribute \src "ls180.v:4942.5-4958.8" switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:4844.9-4844.38" + attribute \src "ls180.v:4942.9-4942.38" case 1'1 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4846$702_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4944$817_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4848.6-4857.9" + attribute \src "ls180.v:4946.6-4955.9" switch \main_sdphy_datar_source_last - attribute \src "ls180.v:4848.10-4848.38" + attribute \src "ls180.v:4946.10-4946.38" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4850.7-4856.10" + attribute \src "ls180.v:4948.7-4954.10" switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:4850.11-4850.37" + attribute \src "ls180.v:4948.11-4948.37" case 1'1 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4854.11-4854.15" + attribute \src "ls180.v:4952.11-4952.15" case assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 end case end - attribute \src "ls180.v:4858.9-4858.13" + attribute \src "ls180.v:4956.9-4956.13" case assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:4864.4-4867.7" - switch $eq$ls180.v:4864$704_Y - attribute \src "ls180.v:4864.8-4864.42" + attribute \src "ls180.v:4962.4-4965.7" + switch $eq$ls180.v:4962$819_Y + attribute \src "ls180.v:4962.8-4962.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -271606,15 +274580,15 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4871.4-4877.7" + attribute \src "ls180.v:4969.4-4975.7" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4871.8-4871.39" + attribute \src "ls180.v:4969.8-4969.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4872$705_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4970$820_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4874.5-4876.8" - switch $eq$ls180.v:4874$706_Y - attribute \src "ls180.v:4874.9-4874.42" + attribute \src "ls180.v:4972.5-4974.8" + switch $eq$ls180.v:4972$821_Y + attribute \src "ls180.v:4972.9-4972.42" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -271626,9 +274600,9 @@ module \ls180 assign $0\main_sdphy_datar_source_valid[0:0] 1'1 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4883.4-4885.7" - switch $and$ls180.v:4883$707_Y - attribute \src "ls180.v:4883.8-4883.71" + attribute \src "ls180.v:4981.4-4983.7" + switch $and$ls180.v:4981$822_Y + attribute \src "ls180.v:4981.8-4981.71" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -271637,14 +274611,14 @@ module \ls180 case assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4890.4-4901.7" - switch $and$ls180.v:4890$708_Y - attribute \src "ls180.v:4890.8-4890.71" + attribute \src "ls180.v:4988.4-4999.7" + switch $and$ls180.v:4988$823_Y + attribute \src "ls180.v:4988.8-4988.71" case 1'1 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4892.5-4900.8" + attribute \src "ls180.v:4990.5-4998.8" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4892.9-4892.40" + attribute \src "ls180.v:4990.9-4990.40" case 1'1 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 @@ -271675,184 +274649,168 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:482.32-482.76" - process $proc$ls180.v:482$2923 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - end - attribute \src "ls180.v:483.11-483.55" - process $proc$ls180.v:483$2924 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:485.32-485.75" - process $proc$ls180.v:485$2925 + attribute \src "ls180.v:501.5-501.59" + process $proc$ls180.v:501$3171 assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:487.32-487.76" - process $proc$ls180.v:487$2926 + attribute \src "ls180.v:503.5-503.59" + process $proc$ls180.v:503$3172 assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:493.5-493.51" - process $proc$ls180.v:493$2927 + attribute \src "ls180.v:504.5-504.58" + process $proc$ls180.v:504$3173 assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:494.5-494.51" - process $proc$ls180.v:494$2928 + attribute \src "ls180.v:505.5-505.64" + process $proc$ls180.v:505$3174 assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:496.5-496.47" - process $proc$ls180.v:496$2929 + attribute \src "ls180.v:506.12-506.74" + process $proc$ls180.v:506$3175 assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:4962.1-4969.4" - process $proc$ls180.v:4962$830 + attribute \src "ls180.v:5060.1-5067.4" + process $proc$ls180.v:5060$945 assign { } { } assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:4964.2-4968.5" + attribute \src "ls180.v:5062.2-5066.5" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:4964.6-4964.38" + attribute \src "ls180.v:5062.6-5062.38" case 1'1 assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:4966.6-4966.10" + attribute \src "ls180.v:5064.6-5064.10" case assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 end sync always update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:497.5-497.45" - process $proc$ls180.v:497$2930 + attribute \src "ls180.v:507.12-507.47" + process $proc$ls180.v:507$3176 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end - attribute \src "ls180.v:498.5-498.45" - process $proc$ls180.v:498$2931 + attribute \src "ls180.v:508.5-508.46" + process $proc$ls180.v:508$3177 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] end - attribute \src "ls180.v:4984.1-4991.4" - process $proc$ls180.v:4984$853 + attribute \src "ls180.v:5082.1-5089.4" + process $proc$ls180.v:5082$968 assign { } { } assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4986.2-4990.5" + attribute \src "ls180.v:5084.2-5088.5" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:4986.6-4986.44" + attribute \src "ls180.v:5084.6-5084.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:4988.6-4988.10" + attribute \src "ls180.v:5086.6-5086.10" case assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:499.12-499.57" - process $proc$ls180.v:499$2932 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:4994.1-5001.4" - process $proc$ls180.v:4994$864 + attribute \src "ls180.v:5092.1-5099.4" + process $proc$ls180.v:5092$979 assign { } { } assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4996.2-5000.5" + attribute \src "ls180.v:5094.2-5098.5" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:4996.6-4996.44" + attribute \src "ls180.v:5094.6-5094.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:4998.6-4998.10" + attribute \src "ls180.v:5096.6-5096.10" case assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:5004.1-5011.4" - process $proc$ls180.v:5004$875 + attribute \src "ls180.v:510.5-510.44" + process $proc$ls180.v:510$3178 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:5102.1-5109.4" + process $proc$ls180.v:5102$990 assign { } { } assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5006.2-5010.5" + attribute \src "ls180.v:5104.2-5108.5" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5006.6-5006.44" + attribute \src "ls180.v:5104.6-5104.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5008.6-5008.10" + attribute \src "ls180.v:5106.6-5106.10" case assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:501.5-501.51" - process $proc$ls180.v:501$2933 + attribute \src "ls180.v:511.5-511.45" + process $proc$ls180.v:511$3179 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] end - attribute \src "ls180.v:5014.1-5021.4" - process $proc$ls180.v:5014$886 + attribute \src "ls180.v:5112.1-5119.4" + process $proc$ls180.v:5112$1001 assign { } { } assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5016.2-5020.5" + attribute \src "ls180.v:5114.2-5118.5" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5016.6-5016.44" + attribute \src "ls180.v:5114.6-5114.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5018.6-5018.10" + attribute \src "ls180.v:5116.6-5116.10" case assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:502.5-502.51" - process $proc$ls180.v:502$2934 + attribute \src "ls180.v:512.5-512.54" + process $proc$ls180.v:512$3180 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:5022.1-5101.4" - process $proc$ls180.v:5022$887 + attribute \src "ls180.v:5120.1-5199.4" + process $proc$ls180.v:5120$1002 assign { } { } assign { } { } assign { } { } @@ -271868,36 +274826,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 assign { } { } assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5039.2-5100.9" + attribute \src "ls180.v:5137.2-5198.9" switch \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5043.4-5045.7" - switch $eq$ls180.v:5043$888_Y - attribute \src "ls180.v:5043.8-5043.48" + attribute \src "ls180.v:5141.4-5143.7" + switch $eq$ls180.v:5141$1003_Y + attribute \src "ls180.v:5141.8-5141.48" case 1'1 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 case end - attribute \src "ls180.v:5046.4-5071.11" + attribute \src "ls180.v:5144.4-5169.11" switch \main_sdcore_crc16_inserter_cnt attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -271925,18 +274883,18 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } case end - attribute \src "ls180.v:5072.4-5079.7" + attribute \src "ls180.v:5170.4-5177.7" switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5072.8-5072.47" + attribute \src "ls180.v:5170.8-5170.47" case 1'1 - attribute \src "ls180.v:5073.5-5078.8" - switch $eq$ls180.v:5073$889_Y - attribute \src "ls180.v:5073.9-5073.49" + attribute \src "ls180.v:5171.5-5176.8" + switch $eq$ls180.v:5171$1004_Y + attribute \src "ls180.v:5171.9-5171.49" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5075.9-5075.13" + attribute \src "ls180.v:5173.9-5173.13" case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5076$890_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5174$1005_Y assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case @@ -271955,9 +274913,9 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5094.4-5098.7" - switch $and$ls180.v:5094$892_Y - attribute \src "ls180.v:5094.8-5094.128" + attribute \src "ls180.v:5192.4-5196.7" + switch $and$ls180.v:5192$1007_Y + attribute \src "ls180.v:5192.8-5192.128" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 @@ -271982,61 +274940,45 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:503.5-503.50" - process $proc$ls180.v:503$2935 + attribute \src "ls180.v:514.32-514.76" + process $proc$ls180.v:514$3181 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - end - attribute \src "ls180.v:504.5-504.54" - process $proc$ls180.v:504$2936 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:505.5-505.55" - process $proc$ls180.v:505$2937 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "ls180.v:506.5-506.56" - process $proc$ls180.v:506$2938 + attribute \src "ls180.v:515.11-515.55" + process $proc$ls180.v:515$3182 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] end - attribute \src "ls180.v:507.5-507.50" - process $proc$ls180.v:507$2939 + attribute \src "ls180.v:517.32-517.75" + process $proc$ls180.v:517$3183 assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:510.5-510.67" - process $proc$ls180.v:510$2940 + attribute \src "ls180.v:519.32-519.76" + process $proc$ls180.v:519$3184 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] sync init end - attribute \src "ls180.v:5102.1-5107.4" - process $proc$ls180.v:5102$893 + attribute \src "ls180.v:5200.1-5205.4" + process $proc$ls180.v:5200$1008 assign { } { } assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5104.2-5106.5" - switch $and$ls180.v:5104$900_Y - attribute \src "ls180.v:5104.6-5104.301" + attribute \src "ls180.v:5202.2-5204.5" + switch $and$ls180.v:5202$1015_Y + attribute \src "ls180.v:5202.6-5202.301" case 1'1 assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 case @@ -272044,85 +274986,77 @@ module \ls180 sync always update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:511.5-511.66" - process $proc$ls180.v:511$2941 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:5110.1-5117.4" - process $proc$ls180.v:5110$902 + attribute \src "ls180.v:5208.1-5215.4" + process $proc$ls180.v:5208$1017 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5112.2-5116.5" - switch $eq$ls180.v:5112$903_Y - attribute \src "ls180.v:5112.6-5112.45" + attribute \src "ls180.v:5210.2-5214.5" + switch $eq$ls180.v:5210$1018_Y + attribute \src "ls180.v:5210.6-5210.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5114.6-5114.10" + attribute \src "ls180.v:5212.6-5212.10" case assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:5120.1-5127.4" - process $proc$ls180.v:5120$905 + attribute \src "ls180.v:5218.1-5225.4" + process $proc$ls180.v:5218$1020 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5122.2-5126.5" - switch $eq$ls180.v:5122$906_Y - attribute \src "ls180.v:5122.6-5122.45" + attribute \src "ls180.v:5220.2-5224.5" + switch $eq$ls180.v:5220$1021_Y + attribute \src "ls180.v:5220.6-5220.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5124.6-5124.10" + attribute \src "ls180.v:5222.6-5222.10" case assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:5130.1-5137.4" - process $proc$ls180.v:5130$908 + attribute \src "ls180.v:5228.1-5235.4" + process $proc$ls180.v:5228$1023 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5132.2-5136.5" - switch $eq$ls180.v:5132$909_Y - attribute \src "ls180.v:5132.6-5132.45" + attribute \src "ls180.v:5230.2-5234.5" + switch $eq$ls180.v:5230$1024_Y + attribute \src "ls180.v:5230.6-5230.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5134.6-5134.10" + attribute \src "ls180.v:5232.6-5232.10" case assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:5140.1-5147.4" - process $proc$ls180.v:5140$911 + attribute \src "ls180.v:5238.1-5245.4" + process $proc$ls180.v:5238$1026 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5142.2-5146.5" - switch $eq$ls180.v:5142$912_Y - attribute \src "ls180.v:5142.6-5142.45" + attribute \src "ls180.v:5240.2-5244.5" + switch $eq$ls180.v:5240$1027_Y + attribute \src "ls180.v:5240.6-5240.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5144.6-5144.10" + attribute \src "ls180.v:5242.6-5242.10" case assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:5149.1-5154.4" - process $proc$ls180.v:5149$913 + attribute \src "ls180.v:5247.1-5252.4" + process $proc$ls180.v:5247$1028 assign { } { } assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5151.2-5153.5" - switch $and$ls180.v:5151$915_Y - attribute \src "ls180.v:5151.6-5151.85" + attribute \src "ls180.v:5249.2-5251.5" + switch $and$ls180.v:5249$1030_Y + attribute \src "ls180.v:5249.6-5249.85" case 1'1 assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 case @@ -272130,88 +275064,128 @@ module \ls180 sync always update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:5155.1-5162.4" - process $proc$ls180.v:5155$916 + attribute \src "ls180.v:525.5-525.51" + process $proc$ls180.v:525$3185 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:5253.1-5260.4" + process $proc$ls180.v:5253$1031 assign { } { } assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5157.2-5161.5" - switch $lt$ls180.v:5157$917_Y - attribute \src "ls180.v:5157.6-5157.44" + attribute \src "ls180.v:5255.2-5259.5" + switch $lt$ls180.v:5255$1032_Y + attribute \src "ls180.v:5255.6-5255.44" case 1'1 assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5159.6-5159.10" + attribute \src "ls180.v:5257.6-5257.10" case assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:5166.1-5173.4" - process $proc$ls180.v:5166$928 + attribute \src "ls180.v:526.5-526.51" + process $proc$ls180.v:526$3186 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:5264.1-5271.4" + process $proc$ls180.v:5264$1043 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5168.2-5172.5" + attribute \src "ls180.v:5266.2-5270.5" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5168.6-5168.43" + attribute \src "ls180.v:5266.6-5266.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5170.6-5170.10" + attribute \src "ls180.v:5268.6-5268.10" case assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end sync always update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:5176.1-5183.4" - process $proc$ls180.v:5176$939 + attribute \src "ls180.v:5274.1-5281.4" + process $proc$ls180.v:5274$1054 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5178.2-5182.5" + attribute \src "ls180.v:5276.2-5280.5" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5178.6-5178.43" + attribute \src "ls180.v:5276.6-5276.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5180.6-5180.10" + attribute \src "ls180.v:5278.6-5278.10" case assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:5186.1-5193.4" - process $proc$ls180.v:5186$950 + attribute \src "ls180.v:528.5-528.47" + process $proc$ls180.v:528$3187 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:5284.1-5291.4" + process $proc$ls180.v:5284$1065 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5188.2-5192.5" + attribute \src "ls180.v:5286.2-5290.5" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5188.6-5188.43" + attribute \src "ls180.v:5286.6-5286.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5190.6-5190.10" + attribute \src "ls180.v:5288.6-5288.10" case assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:5196.1-5203.4" - process $proc$ls180.v:5196$961 + attribute \src "ls180.v:529.5-529.45" + process $proc$ls180.v:529$3188 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:5294.1-5301.4" + process $proc$ls180.v:5294$1076 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5198.2-5202.5" + attribute \src "ls180.v:5296.2-5300.5" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5198.6-5198.43" + attribute \src "ls180.v:5296.6-5296.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5200.6-5200.10" + attribute \src "ls180.v:5298.6-5298.10" case assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:5204.1-5394.4" - process $proc$ls180.v:5204$962 + attribute \src "ls180.v:530.5-530.45" + process $proc$ls180.v:530$3189 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:5302.1-5492.4" + process $proc$ls180.v:5302$1077 assign { } { } assign { } { } assign { } { } @@ -272251,52 +275225,52 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 assign $0\main_sdphy_datar_sink_last[0:0] 1'0 assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 - assign { } { } assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign { } { } assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5245.2-5393.9" + attribute \src "ls180.v:5343.2-5491.9" switch \builder_sdcore_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5248.4-5268.11" + attribute \src "ls180.v:5346.4-5366.11" switch \main_sdcore_cmd_count attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -272316,27 +275290,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5266$963_Y + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5364$1078_Y case end - attribute \src "ls180.v:5269.4-5281.7" - switch $and$ls180.v:5269$964_Y - attribute \src "ls180.v:5269.8-5269.65" + attribute \src "ls180.v:5367.4-5379.7" + switch $and$ls180.v:5367$1079_Y + attribute \src "ls180.v:5367.8-5367.65" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5270$965_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5368$1080_Y assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5272.5-5280.8" - switch $eq$ls180.v:5272$966_Y - attribute \src "ls180.v:5272.9-5272.40" + attribute \src "ls180.v:5370.5-5378.8" + switch $eq$ls180.v:5370$1081_Y + attribute \src "ls180.v:5370.9-5370.40" case 1'1 - attribute \src "ls180.v:5273.6-5279.9" - switch $eq$ls180.v:5273$967_Y - attribute \src "ls180.v:5273.10-5273.40" + attribute \src "ls180.v:5371.6-5377.9" + switch $eq$ls180.v:5371$1082_Y + attribute \src "ls180.v:5371.10-5371.40" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5277.10-5277.14" + attribute \src "ls180.v:5375.10-5375.14" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 end @@ -272347,52 +275321,52 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5285$968_Y + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5383$1083_Y assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5286.4-5290.7" - switch $eq$ls180.v:5286$969_Y - attribute \src "ls180.v:5286.8-5286.38" + attribute \src "ls180.v:5384.4-5388.7" + switch $eq$ls180.v:5384$1084_Y + attribute \src "ls180.v:5384.8-5384.38" case 1'1 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5288.8-5288.12" + attribute \src "ls180.v:5386.8-5386.12" case assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5292.4-5313.7" + attribute \src "ls180.v:5390.4-5411.7" switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5292.8-5292.36" + attribute \src "ls180.v:5390.8-5390.36" case 1'1 - attribute \src "ls180.v:5293.5-5312.8" - switch $eq$ls180.v:5293$970_Y - attribute \src "ls180.v:5293.9-5293.56" + attribute \src "ls180.v:5391.5-5410.8" + switch $eq$ls180.v:5391$1085_Y + attribute \src "ls180.v:5391.9-5391.56" case 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5297.9-5297.13" + attribute \src "ls180.v:5395.9-5395.13" case - attribute \src "ls180.v:5298.6-5311.9" + attribute \src "ls180.v:5396.6-5409.9" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5298.10-5298.37" + attribute \src "ls180.v:5396.10-5396.37" case 1'1 - attribute \src "ls180.v:5299.7-5307.10" - switch $eq$ls180.v:5299$971_Y - attribute \src "ls180.v:5299.11-5299.42" + attribute \src "ls180.v:5397.7-5405.10" + switch $eq$ls180.v:5397$1086_Y + attribute \src "ls180.v:5397.11-5397.42" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5301.11-5301.15" + attribute \src "ls180.v:5399.11-5399.15" case - attribute \src "ls180.v:5302.8-5306.11" - switch $eq$ls180.v:5302$972_Y - attribute \src "ls180.v:5302.12-5302.43" + attribute \src "ls180.v:5400.8-5404.11" + switch $eq$ls180.v:5400$1087_Y + attribute \src "ls180.v:5400.12-5400.43" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5304.12-5304.16" + attribute \src "ls180.v:5402.12-5402.16" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 end end - attribute \src "ls180.v:5308.10-5308.14" + attribute \src "ls180.v:5406.10-5406.14" case assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 @@ -272408,28 +275382,28 @@ module \ls180 assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5321.4-5327.7" - switch $and$ls180.v:5321$974_Y - attribute \src "ls180.v:5321.8-5321.98" + attribute \src "ls180.v:5419.4-5425.7" + switch $and$ls180.v:5419$1089_Y + attribute \src "ls180.v:5419.8-5419.98" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5322$975_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5420$1090_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5324.5-5326.8" - switch $eq$ls180.v:5324$977_Y - attribute \src "ls180.v:5324.9-5324.77" + attribute \src "ls180.v:5422.5-5424.8" + switch $eq$ls180.v:5422$1092_Y + attribute \src "ls180.v:5422.9-5422.77" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 case end case end - attribute \src "ls180.v:5329.4-5334.7" + attribute \src "ls180.v:5427.4-5432.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5329.8-5329.37" + attribute \src "ls180.v:5427.8-5427.37" case 1'1 - attribute \src "ls180.v:5330.5-5333.8" - switch $ne$ls180.v:5330$978_Y - attribute \src "ls180.v:5330.9-5330.57" + attribute \src "ls180.v:5428.5-5431.8" + switch $ne$ls180.v:5428$1093_Y + attribute \src "ls180.v:5428.9-5428.57" case 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 @@ -272441,42 +275415,42 @@ module \ls180 case 3'100 assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5339$980_Y - attribute \src "ls180.v:5340.4-5366.7" + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5437$1095_Y + attribute \src "ls180.v:5438.4-5464.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5340.8-5340.37" + attribute \src "ls180.v:5438.8-5438.37" case 1'1 - attribute \src "ls180.v:5341.5-5365.8" - switch $eq$ls180.v:5341$981_Y - attribute \src "ls180.v:5341.9-5341.57" + attribute \src "ls180.v:5439.5-5463.8" + switch $eq$ls180.v:5439$1096_Y + attribute \src "ls180.v:5439.9-5439.57" case 1'1 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5347.6-5355.9" - switch $and$ls180.v:5347$982_Y - attribute \src "ls180.v:5347.10-5347.72" + attribute \src "ls180.v:5445.6-5453.9" + switch $and$ls180.v:5445$1097_Y + attribute \src "ls180.v:5445.10-5445.72" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5348$983_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5446$1098_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5350.7-5354.10" - switch $eq$ls180.v:5350$985_Y - attribute \src "ls180.v:5350.11-5350.79" + attribute \src "ls180.v:5448.7-5452.10" + switch $eq$ls180.v:5448$1100_Y + attribute \src "ls180.v:5448.11-5448.79" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5352.11-5352.15" + attribute \src "ls180.v:5450.11-5450.15" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 end case end - attribute \src "ls180.v:5356.9-5356.13" + attribute \src "ls180.v:5454.9-5454.13" case - attribute \src "ls180.v:5357.6-5364.9" - switch $eq$ls180.v:5357$986_Y - attribute \src "ls180.v:5357.10-5357.58" + attribute \src "ls180.v:5455.6-5462.9" + switch $eq$ls180.v:5455$1101_Y + attribute \src "ls180.v:5455.10-5455.58" case 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 @@ -272499,9 +275473,9 @@ module \ls180 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5377.4-5391.7" + attribute \src "ls180.v:5475.4-5489.7" switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5377.8-5377.31" + attribute \src "ls180.v:5475.8-5475.31" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 @@ -272560,64 +275534,112 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:526.11-526.68" - process $proc$ls180.v:526$2942 + attribute \src "ls180.v:531.12-531.57" + process $proc$ls180.v:531$3190 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:527.5-527.64" - process $proc$ls180.v:527$2943 + attribute \src "ls180.v:533.5-533.51" + process $proc$ls180.v:533$3191 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:528.11-528.70" - process $proc$ls180.v:528$2944 + attribute \src "ls180.v:534.5-534.51" + process $proc$ls180.v:534$3192 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] end - attribute \src "ls180.v:529.11-529.70" - process $proc$ls180.v:529$2945 + attribute \src "ls180.v:535.5-535.50" + process $proc$ls180.v:535$3193 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] end - attribute \src "ls180.v:530.11-530.73" - process $proc$ls180.v:530$2946 + attribute \src "ls180.v:536.5-536.54" + process $proc$ls180.v:536$3194 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:537.5-537.55" + process $proc$ls180.v:537$3195 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:538.5-538.56" + process $proc$ls180.v:538$3196 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:5422.1-5429.4" - process $proc$ls180.v:5422$987 + attribute \src "ls180.v:539.5-539.50" + process $proc$ls180.v:539$3197 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:542.5-542.67" + process $proc$ls180.v:542$3198 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:543.5-543.66" + process $proc$ls180.v:543$3199 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$3023 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:5520.1-5527.4" + process $proc$ls180.v:5520$1102 assign { } { } assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5424.2-5428.5" + attribute \src "ls180.v:5522.2-5526.5" switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5424.6-5424.35" + attribute \src "ls180.v:5522.6-5522.35" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5425$988_Y - attribute \src "ls180.v:5426.6-5426.10" + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5523$1103_Y + attribute \src "ls180.v:5524.6-5524.10" case assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce end sync always update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:5455.1-5494.4" - process $proc$ls180.v:5455$998 + attribute \src "ls180.v:5553.1-5592.4" + process $proc$ls180.v:5553$1113 assign { } { } assign { } { } assign { } { } @@ -272626,40 +275648,40 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5465.2-5493.9" + attribute \src "ls180.v:5563.2-5591.9" switch \builder_sdblock2memdma_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5469$999_Y + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5567$1114_Y assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5471.4-5482.7" - switch $and$ls180.v:5471$1000_Y - attribute \src "ls180.v:5471.8-5471.103" + attribute \src "ls180.v:5569.4-5580.7" + switch $and$ls180.v:5569$1115_Y + attribute \src "ls180.v:5569.8-5569.103" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5472$1001_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5570$1116_Y assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5474.5-5481.8" - switch $eq$ls180.v:5474$1003_Y - attribute \src "ls180.v:5474.9-5474.106" + attribute \src "ls180.v:5572.5-5579.8" + switch $eq$ls180.v:5572$1118_Y + attribute \src "ls180.v:5572.9-5572.106" case 1'1 - attribute \src "ls180.v:5475.6-5480.9" + attribute \src "ls180.v:5573.6-5578.9" switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5475.10-5475.57" + attribute \src "ls180.v:5573.10-5573.57" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5478.10-5478.14" + attribute \src "ls180.v:5576.10-5576.14" case assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 end @@ -272680,32 +275702,55 @@ module \ls180 sync always update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] - update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$2763 + attribute \src "ls180.v:558.11-558.68" + process $proc$ls180.v:558$3200 assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:551.5-551.59" - process $proc$ls180.v:551$2947 + attribute \src "ls180.v:559.5-559.64" + process $proc$ls180.v:559$3201 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:5514.1-5551.4" - process $proc$ls180.v:5514$1005 + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$3024 assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:560.11-560.70" + process $proc$ls180.v:560$3202 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:561.11-561.70" + process $proc$ls180.v:561$3203 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:5612.1-5649.4" + process $proc$ls180.v:5612$1120 assign { } { } assign { } { } assign { } { } @@ -272717,29 +275762,30 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_adr[31:0] 0 + assign { } { } assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'0000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_interface1_bus_sel[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_cyc[0:0] 1'0 assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 - assign { } { } - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5528.2-5550.9" + attribute \src "ls180.v:5626.2-5648.9" switch \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last - assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5533.4-5536.7" + assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5631.4-5634.7" switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5533.8-5533.41" + attribute \src "ls180.v:5631.8-5631.41" case 1'1 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 @@ -272750,13 +275796,13 @@ module \ls180 assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'1111 + assign $0\main_interface1_bus_sel[7:0] 8'11111111 assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5544.4-5548.7" - switch $and$ls180.v:5544$1006_Y - attribute \src "ls180.v:5544.8-5544.59" + attribute \src "ls180.v:5642.4-5646.7" + switch $and$ls180.v:5642$1121_Y + attribute \src "ls180.v:5642.8-5642.59" case 1'1 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 case @@ -272764,44 +275810,28 @@ module \ls180 end sync always update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] - update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] - update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:553.5-553.59" - process $proc$ls180.v:553$2948 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:554.5-554.58" - process $proc$ls180.v:554$2949 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:555.5-555.64" - process $proc$ls180.v:555$2950 + attribute \src "ls180.v:562.11-562.73" + process $proc$ls180.v:562$3204 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:5552.1-5588.4" - process $proc$ls180.v:5552$1007 + attribute \src "ls180.v:5650.1-5686.4" + process $proc$ls180.v:5650$1122 assign { } { } assign { } { } assign { } { } @@ -272810,37 +275840,37 @@ module \ls180 assign { } { } assign { } { } assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 assign { } { } - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5561.2-5587.9" + attribute \src "ls180.v:5659.2-5685.9" switch \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5564$1009_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5565$1010_Y - attribute \src "ls180.v:5566.4-5577.7" + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5662$1124_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5663$1125_Y + attribute \src "ls180.v:5664.4-5675.7" switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5566.8-5566.39" + attribute \src "ls180.v:5664.8-5664.39" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5567$1011_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5665$1126_Y assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5569.5-5576.8" + attribute \src "ls180.v:5667.5-5674.8" switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5569.9-5569.39" + attribute \src "ls180.v:5667.9-5667.39" case 1'1 - attribute \src "ls180.v:5570.6-5575.9" + attribute \src "ls180.v:5668.6-5673.9" switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5570.10-5570.43" + attribute \src "ls180.v:5668.10-5668.43" case 1'1 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5573.10-5573.14" + attribute \src "ls180.v:5671.10-5671.14" case assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end @@ -272866,60 +275896,32 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:556.12-556.74" - process $proc$ls180.v:556$2951 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:557.12-557.47" - process $proc$ls180.v:557$2952 - assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] - end - attribute \src "ls180.v:558.5-558.46" - process $proc$ls180.v:558$2953 - assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] - end - attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$2764 - assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] - end - attribute \src "ls180.v:560.5-560.44" - process $proc$ls180.v:560$2954 - assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] - end - attribute \src "ls180.v:5600.1-5616.4" - process $proc$ls180.v:5600$1017 + attribute \src "ls180.v:5698.1-5726.4" + process $proc$ls180.v:5698$1132 assign { } { } assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5602.2-5615.9" + attribute \src "ls180.v:5700.2-5725.9" switch \main_sdmem2block_converter_mux attribute \src "ls180.v:0.0-0.0" - case 2'00 + case 3'000 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] + attribute \src "ls180.v:0.0-0.0" + case 3'100 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] attribute \src "ls180.v:0.0-0.0" - case 2'01 + case 3'101 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] attribute \src "ls180.v:0.0-0.0" - case 2'10 + case 3'110 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] attribute \src "ls180.v:0.0-0.0" case @@ -272928,48 +275930,32 @@ module \ls180 sync always update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:561.5-561.45" - process $proc$ls180.v:561$2955 - assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] - end - attribute \src "ls180.v:562.5-562.54" - process $proc$ls180.v:562$2956 + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$3025 assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 sync always sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] end - attribute \src "ls180.v:5630.1-5637.4" - process $proc$ls180.v:5630$1018 + attribute \src "ls180.v:5740.1-5747.4" + process $proc$ls180.v:5740$1133 assign { } { } assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5632.2-5636.5" + attribute \src "ls180.v:5742.2-5746.5" switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5632.6-5632.35" + attribute \src "ls180.v:5742.6-5742.35" case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5633$1019_Y - attribute \src "ls180.v:5634.6-5634.10" + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5743$1134_Y + attribute \src "ls180.v:5744.6-5744.10" case assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce end sync always update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:564.32-564.76" - process $proc$ls180.v:564$2957 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - end - attribute \src "ls180.v:5645.1-5681.4" - process $proc$ls180.v:5645$1025 + attribute \src "ls180.v:5755.1-5791.4" + process $proc$ls180.v:5755$1140 assign { } { } assign { } { } assign { } { } @@ -272979,17 +275965,17 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 assign { } { } + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5656.2-5680.9" + attribute \src "ls180.v:5766.2-5790.9" switch \builder_state attribute \src "ls180.v:0.0-0.0" case 2'01 @@ -273007,13 +275993,13 @@ module \ls180 case assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5672.4-5678.7" - switch $and$ls180.v:5672$1026_Y - attribute \src "ls180.v:5672.8-5672.77" + attribute \src "ls180.v:5782.4-5788.7" + switch $and$ls180.v:5782$1141_Y + attribute \src "ls180.v:5782.8-5782.77" case 1'1 assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5675$1028_Y + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5785$1143_Y assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 assign $0\builder_next_state[1:0] 2'01 case @@ -273030,71 +276016,90 @@ module \ls180 update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:565.11-565.55" - process $proc$ls180.v:565$2958 + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$3026 assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $1\main_libresocsim_scratch_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] end - attribute \src "ls180.v:567.32-567.75" - process $proc$ls180.v:567$2959 + attribute \src "ls180.v:5816.1-5826.4" + process $proc$ls180.v:5816$1164 assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + assign { } { } + assign $0\builder_slave_sel[7:0] [0] $eq$ls180.v:5818$1165_Y + assign $0\builder_slave_sel[7:0] [1] $eq$ls180.v:5819$1166_Y + assign $0\builder_slave_sel[7:0] [2] $eq$ls180.v:5820$1167_Y + assign $0\builder_slave_sel[7:0] [3] $eq$ls180.v:5821$1168_Y + assign $0\builder_slave_sel[7:0] [4] $eq$ls180.v:5822$1169_Y + assign $0\builder_slave_sel[7:0] [5] $eq$ls180.v:5823$1170_Y + assign $0\builder_slave_sel[7:0] [6] $eq$ls180.v:5824$1171_Y + assign $0\builder_slave_sel[7:0] [7] $eq$ls180.v:5825$1172_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[7:0] + end + attribute \src "ls180.v:583.5-583.59" + process $proc$ls180.v:583$3205 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:569.32-569.76" - process $proc$ls180.v:569$2960 + attribute \src "ls180.v:585.5-585.59" + process $proc$ls180.v:585$3206 assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$2765 + attribute \src "ls180.v:586.5-586.58" + process $proc$ls180.v:586$3207 assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:5706.1-5713.4" - process $proc$ls180.v:5706$1049 + attribute \src "ls180.v:587.5-587.64" + process $proc$ls180.v:587$3208 assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:588.12-588.74" + process $proc$ls180.v:588$3209 assign { } { } - assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5708$1050_Y - assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5709$1051_Y - assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5710$1052_Y - assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5711$1053_Y - assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5712$1054_Y + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always - update \builder_slave_sel $0\builder_slave_sel[4:0] + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:575.5-575.51" - process $proc$ls180.v:575$2961 + attribute \src "ls180.v:589.12-589.47" + process $proc$ls180.v:589$3210 assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end - attribute \src "ls180.v:5756.1-5767.4" - process $proc$ls180.v:5756$1067 + attribute \src "ls180.v:5893.1-5904.4" + process $proc$ls180.v:5893$1191 assign { } { } assign { } { } assign { } { } + assign $0\builder_error[0:0] 1'0 assign { } { } assign { } { } - assign $0\builder_error[0:0] 1'0 - assign $0\builder_shared_ack[0:0] $or$ls180.v:5760$1071_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5761$1080_Y - attribute \src "ls180.v:5762.2-5766.5" + assign $0\builder_shared_ack[0:0] $or$ls180.v:5897$1198_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5898$1213_Y [31:0] + attribute \src "ls180.v:5899.2-5903.5" switch \builder_done - attribute \src "ls180.v:5762.6-5762.18" + attribute \src "ls180.v:5899.6-5899.18" case 1'1 assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 assign $0\builder_shared_ack[0:0] 1'1 @@ -273106,195 +276111,259 @@ module \ls180 update \builder_shared_ack $0\builder_shared_ack[0:0] update \builder_error $0\builder_error[0:0] end - attribute \src "ls180.v:576.5-576.51" - process $proc$ls180.v:576$2962 + attribute \src "ls180.v:590.5-590.46" + process $proc$ls180.v:590$3211 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:592.5-592.44" + process $proc$ls180.v:592$3212 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:593.5-593.45" + process $proc$ls180.v:593$3213 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:594.5-594.54" + process $proc$ls180.v:594$3214 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:596.32-596.76" + process $proc$ls180.v:596$3215 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:597.11-597.55" + process $proc$ls180.v:597$3216 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:599.32-599.75" + process $proc$ls180.v:599$3217 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:601.32-601.76" + process $proc$ls180.v:601$3218 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:607.5-607.51" + process $proc$ls180.v:607$3219 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:608.5-608.51" + process $proc$ls180.v:608$3220 assign { } { } assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:578.5-578.47" - process $proc$ls180.v:578$2963 + attribute \src "ls180.v:610.5-610.47" + process $proc$ls180.v:610$3221 assign { } { } assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:579.5-579.45" - process $proc$ls180.v:579$2964 + attribute \src "ls180.v:611.5-611.45" + process $proc$ls180.v:611$3222 assign { } { } assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$2766 - assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] - end - attribute \src "ls180.v:580.5-580.45" - process $proc$ls180.v:580$2965 + attribute \src "ls180.v:612.5-612.45" + process $proc$ls180.v:612$3223 assign { } { } assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:581.12-581.57" - process $proc$ls180.v:581$2966 + attribute \src "ls180.v:613.12-613.57" + process $proc$ls180.v:613$3224 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:583.5-583.51" - process $proc$ls180.v:583$2967 + attribute \src "ls180.v:615.5-615.51" + process $proc$ls180.v:615$3225 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:584.5-584.51" - process $proc$ls180.v:584$2968 + attribute \src "ls180.v:616.5-616.51" + process $proc$ls180.v:616$3226 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:585.5-585.50" - process $proc$ls180.v:585$2969 + attribute \src "ls180.v:617.5-617.50" + process $proc$ls180.v:617$3227 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:586.5-586.54" - process $proc$ls180.v:586$2970 + attribute \src "ls180.v:618.5-618.54" + process $proc$ls180.v:618$3228 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:587.5-587.55" - process $proc$ls180.v:587$2971 + attribute \src "ls180.v:619.5-619.55" + process $proc$ls180.v:619$3229 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:588.5-588.56" - process $proc$ls180.v:588$2972 + attribute \src "ls180.v:620.5-620.56" + process $proc$ls180.v:620$3230 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:589.5-589.50" - process $proc$ls180.v:589$2973 + attribute \src "ls180.v:621.5-621.50" + process $proc$ls180.v:621$3231 assign { } { } assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:592.5-592.67" - process $proc$ls180.v:592$2974 + attribute \src "ls180.v:624.5-624.67" + process $proc$ls180.v:624$3232 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:593.5-593.66" - process $proc$ls180.v:593$2975 + attribute \src "ls180.v:625.5-625.66" + process $proc$ls180.v:625$3233 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:608.11-608.68" - process $proc$ls180.v:608$2976 + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$3027 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:640.11-640.68" + process $proc$ls180.v:640$3234 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:609.5-609.64" - process $proc$ls180.v:609$2977 + attribute \src "ls180.v:641.5-641.64" + process $proc$ls180.v:641$3235 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:610.11-610.70" - process $proc$ls180.v:610$2978 + attribute \src "ls180.v:6418.1-6423.4" + process $proc$ls180.v:6418$2087 + assign { } { } + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6420.2-6422.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6420.6-6420.25" + case 1'1 + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + case + end + sync always + update \main_spimaster9_start $0\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:642.11-642.70" + process $proc$ls180.v:642$3236 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:611.11-611.70" - process $proc$ls180.v:611$2979 + attribute \src "ls180.v:643.11-643.70" + process $proc$ls180.v:643$3237 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:612.11-612.73" - process $proc$ls180.v:612$2980 + attribute \src "ls180.v:644.11-644.73" + process $proc$ls180.v:644$3238 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:6281.1-6286.4" - process $proc$ls180.v:6281$1954 - assign { } { } - assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6283.2-6285.5" - switch \main_spimaster12_re - attribute \src "ls180.v:6283.6-6283.25" - case 1'1 - assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] - case - end - sync always - update \main_spimaster9_start $0\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$2767 - assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 - sync always - sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] - end - attribute \src "ls180.v:6327.1-6332.4" - process $proc$ls180.v:6327$2019 + attribute \src "ls180.v:6464.1-6469.4" + process $proc$ls180.v:6464$2152 assign { } { } assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6329.2-6331.5" + attribute \src "ls180.v:6466.2-6468.5" switch \main_spisdcard_control_re - attribute \src "ls180.v:6329.6-6329.31" + attribute \src "ls180.v:6466.6-6466.31" case 1'1 assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] case @@ -273302,131 +276371,27 @@ module \ls180 sync always update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] end - attribute \src "ls180.v:633.5-633.59" - process $proc$ls180.v:633$2981 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:635.5-635.59" - process $proc$ls180.v:635$2982 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:636.5-636.58" - process $proc$ls180.v:636$2983 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:637.5-637.64" - process $proc$ls180.v:637$2984 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:638.12-638.74" - process $proc$ls180.v:638$2985 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:639.12-639.47" - process $proc$ls180.v:639$2986 - assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:640.5-640.46" - process $proc$ls180.v:640$2987 - assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] - end - attribute \src "ls180.v:642.5-642.44" - process $proc$ls180.v:642$2988 - assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] - end - attribute \src "ls180.v:643.5-643.45" - process $proc$ls180.v:643$2989 - assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] - end - attribute \src "ls180.v:644.5-644.54" - process $proc$ls180.v:644$2990 - assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:646.32-646.76" - process $proc$ls180.v:646$2991 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - end - attribute \src "ls180.v:647.11-647.55" - process $proc$ls180.v:647$2992 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] - end - attribute \src "ls180.v:649.32-649.75" - process $proc$ls180.v:649$2993 - assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] - sync init - end attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$2768 + process $proc$ls180.v:65$3028 assign { } { } assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 sync always sync init update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:651.32-651.76" - process $proc$ls180.v:651$2994 + attribute \src "ls180.v:665.5-665.59" + process $proc$ls180.v:665$3239 assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:6516.1-6532.4" - process $proc$ls180.v:6516$2240 + attribute \src "ls180.v:6653.1-6669.4" + process $proc$ls180.v:6653$2373 assign { } { } assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6518.2-6531.9" + attribute \src "ls180.v:6655.2-6668.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273444,11 +276409,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:6533.1-6549.4" - process $proc$ls180.v:6533$2241 + attribute \src "ls180.v:667.5-667.59" + process $proc$ls180.v:667$3240 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:6670.1-6686.4" + process $proc$ls180.v:6670$2374 assign { } { } assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6535.2-6548.9" + attribute \src "ls180.v:6672.2-6685.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273466,11 +276439,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:6550.1-6566.4" - process $proc$ls180.v:6550$2242 + attribute \src "ls180.v:668.5-668.58" + process $proc$ls180.v:668$3241 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:6687.1-6703.4" + process $proc$ls180.v:6687$2375 assign { } { } assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6552.2-6565.9" + attribute \src "ls180.v:6689.2-6702.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273488,11 +276469,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:6567.1-6583.4" - process $proc$ls180.v:6567$2243 + attribute \src "ls180.v:669.5-669.64" + process $proc$ls180.v:669$3242 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:670.12-670.74" + process $proc$ls180.v:670$3243 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:6704.1-6720.4" + process $proc$ls180.v:6704$2376 assign { } { } assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6569.2-6582.9" + attribute \src "ls180.v:6706.2-6719.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273510,27 +276507,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:657.5-657.51" - process $proc$ls180.v:657$2995 + attribute \src "ls180.v:671.12-671.47" + process $proc$ls180.v:671$3244 assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] end - attribute \src "ls180.v:658.5-658.51" - process $proc$ls180.v:658$2996 + attribute \src "ls180.v:672.5-672.46" + process $proc$ls180.v:672$3245 assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] end - attribute \src "ls180.v:6584.1-6600.4" - process $proc$ls180.v:6584$2244 + attribute \src "ls180.v:6721.1-6737.4" + process $proc$ls180.v:6721$2377 assign { } { } assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6586.2-6599.9" + attribute \src "ls180.v:6723.2-6736.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273548,19 +276545,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:660.5-660.47" - process $proc$ls180.v:660$2997 - assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] - end - attribute \src "ls180.v:6601.1-6617.4" - process $proc$ls180.v:6601$2245 + attribute \src "ls180.v:6738.1-6754.4" + process $proc$ls180.v:6738$2378 assign { } { } assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6603.2-6616.9" + attribute \src "ls180.v:6740.2-6753.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273578,19 +276567,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:661.5-661.45" - process $proc$ls180.v:661$2998 + attribute \src "ls180.v:674.5-674.44" + process $proc$ls180.v:674$3246 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end - attribute \src "ls180.v:6618.1-6634.4" - process $proc$ls180.v:6618$2246 + attribute \src "ls180.v:675.5-675.45" + process $proc$ls180.v:675$3247 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:6755.1-6771.4" + process $proc$ls180.v:6755$2379 assign { } { } assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6620.2-6633.9" + attribute \src "ls180.v:6757.2-6770.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273608,27 +276605,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:662.5-662.45" - process $proc$ls180.v:662$2999 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:663.12-663.57" - process $proc$ls180.v:663$3000 + attribute \src "ls180.v:676.5-676.54" + process $proc$ls180.v:676$3248 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:6635.1-6651.4" - process $proc$ls180.v:6635$2247 + attribute \src "ls180.v:6772.1-6788.4" + process $proc$ls180.v:6772$2380 assign { } { } assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6637.2-6650.9" + attribute \src "ls180.v:6774.2-6787.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273646,19 +276635,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:665.5-665.51" - process $proc$ls180.v:665$3001 + attribute \src "ls180.v:678.32-678.76" + process $proc$ls180.v:678$3249 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] end - attribute \src "ls180.v:6652.1-6668.4" - process $proc$ls180.v:6652$2248 + attribute \src "ls180.v:6789.1-6805.4" + process $proc$ls180.v:6789$2381 assign { } { } assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6654.2-6667.9" + attribute \src "ls180.v:6791.2-6804.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273676,19 +276665,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:666.5-666.51" - process $proc$ls180.v:666$3002 + attribute \src "ls180.v:679.11-679.55" + process $proc$ls180.v:679$3250 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] end - attribute \src "ls180.v:6669.1-6685.4" - process $proc$ls180.v:6669$2249 + attribute \src "ls180.v:6806.1-6822.4" + process $proc$ls180.v:6806$2382 assign { } { } assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6671.2-6684.9" + attribute \src "ls180.v:6808.2-6821.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273706,27 +276695,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:667.5-667.50" - process $proc$ls180.v:667$3003 + attribute \src "ls180.v:681.32-681.75" + process $proc$ls180.v:681$3251 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - end - attribute \src "ls180.v:668.5-668.54" - process $proc$ls180.v:668$3004 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:6686.1-6702.4" - process $proc$ls180.v:6686$2250 + attribute \src "ls180.v:6823.1-6839.4" + process $proc$ls180.v:6823$2383 assign { } { } assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6688.2-6701.9" + attribute \src "ls180.v:6825.2-6838.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273744,27 +276725,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:669.5-669.55" - process $proc$ls180.v:669$3005 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:670.5-670.56" - process $proc$ls180.v:670$3006 + attribute \src "ls180.v:683.32-683.76" + process $proc$ls180.v:683$3252 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:6703.1-6719.4" - process $proc$ls180.v:6703$2251 + attribute \src "ls180.v:6840.1-6856.4" + process $proc$ls180.v:6840$2384 assign { } { } assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6705.2-6718.9" + attribute \src "ls180.v:6842.2-6855.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273782,19 +276755,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:671.5-671.50" - process $proc$ls180.v:671$3007 - assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:6720.1-6736.4" - process $proc$ls180.v:6720$2252 + attribute \src "ls180.v:6857.1-6873.4" + process $proc$ls180.v:6857$2385 assign { } { } assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6722.2-6735.9" + attribute \src "ls180.v:6859.2-6872.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273812,11 +276777,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:6737.1-6753.4" - process $proc$ls180.v:6737$2253 + attribute \src "ls180.v:6874.1-6890.4" + process $proc$ls180.v:6874$2386 assign { } { } assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6739.2-6752.9" + attribute \src "ls180.v:6876.2-6889.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273834,27 +276799,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:674.5-674.67" - process $proc$ls180.v:674$3008 + attribute \src "ls180.v:689.5-689.51" + process $proc$ls180.v:689$3253 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:675.5-675.66" - process $proc$ls180.v:675$3009 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "ls180.v:6754.1-6770.4" - process $proc$ls180.v:6754$2254 + attribute \src "ls180.v:6891.1-6907.4" + process $proc$ls180.v:6891$2387 assign { } { } assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6756.2-6769.9" + attribute \src "ls180.v:6893.2-6906.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273872,11 +276829,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:6771.1-6787.4" - process $proc$ls180.v:6771$2255 + attribute \src "ls180.v:690.5-690.51" + process $proc$ls180.v:690$3254 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:6908.1-6924.4" + process $proc$ls180.v:6908$2388 assign { } { } assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6773.2-6786.9" + attribute \src "ls180.v:6910.2-6923.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273894,11 +276859,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:6788.1-6804.4" - process $proc$ls180.v:6788$2256 + attribute \src "ls180.v:692.5-692.47" + process $proc$ls180.v:692$3255 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:6925.1-6941.4" + process $proc$ls180.v:6925$2389 assign { } { } assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6790.2-6803.9" + attribute \src "ls180.v:6927.2-6940.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273916,11 +276889,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:6805.1-6821.4" - process $proc$ls180.v:6805$2257 + attribute \src "ls180.v:693.5-693.45" + process $proc$ls180.v:693$3256 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:694.5-694.45" + process $proc$ls180.v:694$3257 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:6942.1-6958.4" + process $proc$ls180.v:6942$2390 assign { } { } assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6807.2-6820.9" + attribute \src "ls180.v:6944.2-6957.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -273938,11 +276927,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:6822.1-6829.4" - process $proc$ls180.v:6822$2258 + attribute \src "ls180.v:695.12-695.57" + process $proc$ls180.v:695$3258 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:6959.1-6966.4" + process $proc$ls180.v:6959$2391 assign { } { } assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6824.2-6828.9" + attribute \src "ls180.v:6961.2-6965.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -273951,11 +276948,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:6830.1-6837.4" - process $proc$ls180.v:6830$2259 + attribute \src "ls180.v:6967.1-6974.4" + process $proc$ls180.v:6967$2392 assign { } { } assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6832.2-6836.9" + attribute \src "ls180.v:6969.2-6973.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -273964,24 +276961,40 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:6838.1-6845.4" - process $proc$ls180.v:6838$2260 + attribute \src "ls180.v:697.5-697.51" + process $proc$ls180.v:697$3259 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:6975.1-6982.4" + process $proc$ls180.v:6975$2393 assign { } { } assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6840.2-6844.9" + attribute \src "ls180.v:6977.2-6981.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6842$2273_Y + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6979$2406_Y end sync always update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:6846.1-6853.4" - process $proc$ls180.v:6846$2274 + attribute \src "ls180.v:698.5-698.51" + process $proc$ls180.v:698$3260 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:6983.1-6990.4" + process $proc$ls180.v:6983$2407 assign { } { } assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6848.2-6852.9" + attribute \src "ls180.v:6985.2-6989.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -273990,11 +277003,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:6854.1-6861.4" - process $proc$ls180.v:6854$2275 + attribute \src "ls180.v:699.5-699.50" + process $proc$ls180.v:699$3261 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:6991.1-6998.4" + process $proc$ls180.v:6991$2408 assign { } { } assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6856.2-6860.9" + attribute \src "ls180.v:6993.2-6997.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -274003,24 +277024,32 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:6862.1-6869.4" - process $proc$ls180.v:6862$2276 + attribute \src "ls180.v:6999.1-7006.4" + process $proc$ls180.v:6999$2409 assign { } { } assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6864.2-6868.9" + attribute \src "ls180.v:7001.2-7005.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6866$2289_Y + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7003$2422_Y end sync always update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:6870.1-6877.4" - process $proc$ls180.v:6870$2290 + attribute \src "ls180.v:700.5-700.54" + process $proc$ls180.v:700$3262 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:7007.1-7014.4" + process $proc$ls180.v:7007$2423 assign { } { } assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6872.2-6876.9" + attribute \src "ls180.v:7009.2-7013.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -274029,11 +277058,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:6878.1-6885.4" - process $proc$ls180.v:6878$2291 + attribute \src "ls180.v:701.5-701.55" + process $proc$ls180.v:701$3263 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:7015.1-7022.4" + process $proc$ls180.v:7015$2424 assign { } { } assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6880.2-6884.9" + attribute \src "ls180.v:7017.2-7021.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -274042,24 +277079,40 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:6886.1-6893.4" - process $proc$ls180.v:6886$2292 + attribute \src "ls180.v:702.5-702.56" + process $proc$ls180.v:702$3264 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:7023.1-7030.4" + process $proc$ls180.v:7023$2425 assign { } { } assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6888.2-6892.9" + attribute \src "ls180.v:7025.2-7029.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6890$2305_Y + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7027$2438_Y end sync always update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:6894.1-6901.4" - process $proc$ls180.v:6894$2306 + attribute \src "ls180.v:703.5-703.50" + process $proc$ls180.v:703$3265 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:7031.1-7038.4" + process $proc$ls180.v:7031$2439 assign { } { } assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6896.2-6900.9" + attribute \src "ls180.v:7033.2-7037.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -274068,19 +277121,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:690.11-690.68" - process $proc$ls180.v:690$3010 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:6902.1-6909.4" - process $proc$ls180.v:6902$2307 + attribute \src "ls180.v:7039.1-7046.4" + process $proc$ls180.v:7039$2440 assign { } { } assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:6904.2-6908.9" + attribute \src "ls180.v:7041.2-7045.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -274089,42 +277134,34 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:691.5-691.64" - process $proc$ls180.v:691$3011 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:6910.1-6917.4" - process $proc$ls180.v:6910$2308 + attribute \src "ls180.v:7047.1-7054.4" + process $proc$ls180.v:7047$2441 assign { } { } assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:6912.2-6916.9" + attribute \src "ls180.v:7049.2-7053.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6914$2321_Y + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7051$2454_Y end sync always update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:6918.1-6937.4" - process $proc$ls180.v:6918$2322 + attribute \src "ls180.v:7055.1-7074.4" + process $proc$ls180.v:7055$2455 assign { } { } assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:6920.2-6936.9" + attribute \src "ls180.v:7057.2-7073.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr @@ -274135,95 +277172,87 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:692.11-692.70" - process $proc$ls180.v:692$3012 + attribute \src "ls180.v:706.5-706.67" + process $proc$ls180.v:706$3266 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:693.11-693.70" - process $proc$ls180.v:693$3013 + attribute \src "ls180.v:707.5-707.66" + process $proc$ls180.v:707$3267 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:6938.1-6957.4" - process $proc$ls180.v:6938$2323 + attribute \src "ls180.v:7075.1-7094.4" + process $proc$ls180.v:7075$2456 assign { } { } - assign $0\builder_comb_rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:6940.2-6956.9" + assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "ls180.v:7077.2-7093.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w end sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:694.11-694.73" - process $proc$ls180.v:694$3014 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:6958.1-6977.4" - process $proc$ls180.v:6958$2324 + attribute \src "ls180.v:7095.1-7114.4" + process $proc$ls180.v:7095$2457 assign { } { } - assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:6960.2-6976.9" + assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + attribute \src "ls180.v:7097.2-7113.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel end sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:6978.1-6997.4" - process $proc$ls180.v:6978$2325 + attribute \src "ls180.v:7115.1-7134.4" + process $proc$ls180.v:7115$2458 assign { } { } assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:6980.2-6996.9" + attribute \src "ls180.v:7117.2-7133.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc @@ -274234,21 +277263,21 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:6998.1-7017.4" - process $proc$ls180.v:6998$2326 + attribute \src "ls180.v:7135.1-7154.4" + process $proc$ls180.v:7135$2459 assign { } { } assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7000.2-7016.9" + attribute \src "ls180.v:7137.2-7153.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb @@ -274259,21 +277288,21 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:7018.1-7037.4" - process $proc$ls180.v:7018$2327 + attribute \src "ls180.v:7155.1-7174.4" + process $proc$ls180.v:7155$2460 assign { } { } assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7020.2-7036.9" + attribute \src "ls180.v:7157.2-7173.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we @@ -274284,21 +277313,21 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:7038.1-7057.4" - process $proc$ls180.v:7038$2328 + attribute \src "ls180.v:7175.1-7194.4" + process $proc$ls180.v:7175$2461 assign { } { } assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7040.2-7056.9" + attribute \src "ls180.v:7177.2-7193.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti @@ -274309,21 +277338,21 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:7058.1-7077.4" - process $proc$ls180.v:7058$2329 + attribute \src "ls180.v:7195.1-7214.4" + process $proc$ls180.v:7195$2462 assign { } { } assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7060.2-7076.9" + attribute \src "ls180.v:7197.2-7213.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte @@ -274334,11 +277363,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:7078.1-7094.4" - process $proc$ls180.v:7078$2330 + attribute \src "ls180.v:7215.1-7231.4" + process $proc$ls180.v:7215$2463 assign { } { } assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7080.2-7093.9" + attribute \src "ls180.v:7217.2-7230.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -274356,11 +277385,27 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:7095.1-7111.4" - process $proc$ls180.v:7095$2331 + attribute \src "ls180.v:722.11-722.68" + process $proc$ls180.v:722$3268 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:723.5-723.64" + process $proc$ls180.v:723$3269 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:7232.1-7248.4" + process $proc$ls180.v:7232$2464 assign { } { } assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7097.2-7110.9" + attribute \src "ls180.v:7234.2-7247.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -274378,153 +277423,145 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:7112.1-7128.4" - process $proc$ls180.v:7112$2332 + attribute \src "ls180.v:724.11-724.70" + process $proc$ls180.v:724$3270 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:7249.1-7265.4" + process $proc$ls180.v:7249$2465 assign { } { } assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7114.2-7127.9" + attribute \src "ls180.v:7251.2-7264.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7119$2334_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7256$2467_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7122$2336_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7259$2469_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7125$2338_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7262$2471_Y end sync always update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:7129.1-7145.4" - process $proc$ls180.v:7129$2339 + attribute \src "ls180.v:725.11-725.70" + process $proc$ls180.v:725$3271 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:726.11-726.73" + process $proc$ls180.v:726$3272 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:7266.1-7282.4" + process $proc$ls180.v:7266$2472 assign { } { } assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7131.2-7144.9" + attribute \src "ls180.v:7268.2-7281.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7136$2341_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7273$2474_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7139$2343_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7276$2476_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7142$2345_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7279$2478_Y end sync always update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:7146.1-7162.4" - process $proc$ls180.v:7146$2346 + attribute \src "ls180.v:7283.1-7299.4" + process $proc$ls180.v:7283$2479 assign { } { } assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7148.2-7161.9" + attribute \src "ls180.v:7285.2-7298.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7153$2348_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7290$2481_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7156$2350_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7293$2483_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7159$2352_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7296$2485_Y end sync always update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:715.5-715.59" - process $proc$ls180.v:715$3015 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:7163.1-7179.4" - process $proc$ls180.v:7163$2353 + attribute \src "ls180.v:7300.1-7316.4" + process $proc$ls180.v:7300$2486 assign { } { } assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7165.2-7178.9" + attribute \src "ls180.v:7302.2-7315.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7170$2355_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7307$2488_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7173$2357_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7310$2490_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7176$2359_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7313$2492_Y end sync always update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:717.5-717.59" - process $proc$ls180.v:717$3016 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:718.5-718.58" - process $proc$ls180.v:718$3017 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:7180.1-7196.4" - process $proc$ls180.v:7180$2360 + attribute \src "ls180.v:7317.1-7333.4" + process $proc$ls180.v:7317$2493 assign { } { } assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7182.2-7195.9" + attribute \src "ls180.v:7319.2-7332.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7187$2362_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7324$2495_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7190$2364_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7327$2497_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7193$2366_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7330$2499_Y end sync always update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:719.5-719.64" - process $proc$ls180.v:719$3018 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:7197.1-7225.4" - process $proc$ls180.v:7197$2367 + attribute \src "ls180.v:7334.1-7362.4" + process $proc$ls180.v:7334$2500 assign { } { } assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7199.2-7224.9" + attribute \src "ls180.v:7336.2-7361.9" switch \main_spimaster34_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -274554,43 +277591,11 @@ module \ls180 sync always update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:72.5-72.46" - process $proc$ls180.v:72$2769 - assign { } { } - assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] - end - attribute \src "ls180.v:720.12-720.74" - process $proc$ls180.v:720$3019 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:721.12-721.47" - process $proc$ls180.v:721$3020 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:722.5-722.46" - process $proc$ls180.v:722$3021 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] - end - attribute \src "ls180.v:7226.1-7254.4" - process $proc$ls180.v:7226$2368 + attribute \src "ls180.v:7363.1-7391.4" + process $proc$ls180.v:7363$2501 assign { } { } assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7228.2-7253.9" + attribute \src "ls180.v:7365.2-7390.9" switch \main_spisdcard_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -274620,56 +277625,16 @@ module \ls180 sync always update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:724.5-724.44" - process $proc$ls180.v:724$3022 - assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] - end - attribute \src "ls180.v:725.5-725.45" - process $proc$ls180.v:725$3023 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:726.5-726.54" - process $proc$ls180.v:726$3024 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:728.32-728.76" - process $proc$ls180.v:728$3025 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - end - attribute \src "ls180.v:729.11-729.55" - process $proc$ls180.v:729$3026 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:731.32-731.75" - process $proc$ls180.v:731$3027 + attribute \src "ls180.v:74.11-74.52" + process $proc$ls180.v:74$3029 assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] sync init end - attribute \src "ls180.v:7312.1-7330.4" - process $proc$ls180.v:7312$2369 + attribute \src "ls180.v:7449.1-7467.4" + process $proc$ls180.v:7449$2502 assign { } { } assign { } { } assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 @@ -274691,23 +277656,31 @@ module \ls180 sync always update \main_gpio_status $0\main_gpio_status[15:0] end - attribute \src "ls180.v:733.32-733.76" - process $proc$ls180.v:733$3028 + attribute \src "ls180.v:747.5-747.59" + process $proc$ls180.v:747$3273 assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:7351.1-7353.4" - process $proc$ls180.v:7351$2370 + attribute \src "ls180.v:7488.1-7490.4" + process $proc$ls180.v:7488$2503 assign { } { } assign $0\main_int_rst[0:0] \sys_rst sync posedge \por_clk update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "ls180.v:7355.1-7425.4" - process $proc$ls180.v:7355$2371 + attribute \src "ls180.v:749.5-749.59" + process $proc$ls180.v:749$3274 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:7492.1-7562.4" + process $proc$ls180.v:7492$2504 assign { } { } assign { } { } assign { } { } @@ -274783,7 +277756,7 @@ module \ls180 assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7412$2373_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7549$2506_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -274797,6 +277770,11 @@ module \ls180 assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] sync posedge \sdrio_clk + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \sdram_a $0\sdram_a[12:0] update \sdram_dq_o $0\sdram_dq_o[15:0] update \sdram_dq_oe $0\sdram_dq_oe[0:0] @@ -274808,84 +277786,81 @@ module \ls180 update \sdram_ba $0\sdram_ba[1:0] update \sdram_dm $0\sdram_dm[1:0] update \sdram_clock $0\sdram_clock[0:0] - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:736.5-736.44" - process $proc$ls180.v:736$3029 + attribute \src "ls180.v:75.11-75.52" + process $proc$ls180.v:75$3030 assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] sync init end - attribute \src "ls180.v:737.5-737.45" - process $proc$ls180.v:737$3030 + attribute \src "ls180.v:750.5-750.58" + process $proc$ls180.v:750$3275 assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:738.5-738.43" - process $proc$ls180.v:738$3031 + attribute \src "ls180.v:751.5-751.64" + process $proc$ls180.v:751$3276 assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:739.5-739.48" - process $proc$ls180.v:739$3032 + attribute \src "ls180.v:752.12-752.74" + process $proc$ls180.v:752$3277 assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:74.5-74.46" - process $proc$ls180.v:74$2770 + attribute \src "ls180.v:753.12-753.47" + process $proc$ls180.v:753$3278 assign { } { } - assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 sync always - update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "ls180.v:741.5-741.43" - process $proc$ls180.v:741$3033 + attribute \src "ls180.v:754.5-754.46" + process $proc$ls180.v:754$3279 assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end - attribute \src "ls180.v:7427.1-10039.4" - process $proc$ls180.v:7427$2374 - assign $0\pwm[1:0] \pwm - assign $0\spimaster_clk[0:0] \spimaster_clk - assign $0\spimaster_mosi[0:0] \spimaster_mosi + attribute \src "ls180.v:756.5-756.44" + process $proc$ls180.v:756$3280 assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:7564.1-10203.4" + process $proc$ls180.v:7564$2507 assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } assign $0\uart_tx[0:0] \uart_tx + assign $0\pwm[1:0] \pwm + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi + assign { } { } assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage assign { } { } assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r assign { } { } assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage assign { } { } @@ -274903,6 +277878,13 @@ module \ls180 assign $0\main_libresocsim_value[31:0] \main_libresocsim_value assign { } { } assign { } { } + assign { } { } + assign $0\main_converter0_counter[0:0] \main_converter0_counter + assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r + assign $0\main_converter1_counter[0:0] \main_converter1_counter + assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r + assign { } { } + assign { } { } assign $0\main_sdram_storage[3:0] \main_sdram_storage assign { } { } assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage @@ -274989,6 +277971,8 @@ module \ls180 assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count assign $0\main_sdram_time0[4:0] \main_sdram_time0 assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r assign $0\main_converter_counter[0:0] \main_converter_counter assign $0\main_converter_dat_r[31:0] \main_converter_dat_r assign $0\main_cmd_consumed[0:0] \main_cmd_consumed @@ -275168,9 +278152,9 @@ module \ls180 assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count - assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage assign { } { } @@ -275181,7 +278165,7 @@ module \ls180 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage assign { } { } assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage assign { } { } assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage @@ -275191,7 +278175,7 @@ module \ls180 assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage assign { } { } assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset - assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume @@ -275279,35 +278263,38 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7428$2375_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7429$2376_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7430$2377_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7431$2378_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7432$2379_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7433$2380_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7434$2381_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7435$2382_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7436$2383_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7437$2384_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7438$2385_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7439$2386_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7440$2387_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7441$2388_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7442$2389_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7443$2390_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7444$2391_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7445$2392_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7446$2393_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7447$2394_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7448$2395_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7449$2396_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7450$2397_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7451$2398_Y + assign $0\main_dummy[23:0] [0] $or$ls180.v:7565$2508_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7566$2509_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7567$2510_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7568$2511_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7569$2512_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7570$2513_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7571$2514_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7572$2515_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7573$2516_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7574$2517_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7575$2518_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7576$2519_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7577$2520_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7578$2521_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7579$2522_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7580$2523_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7581$2524_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7582$2525_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7583$2526_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7584$2527_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7585$2528_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7586$2529_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7587$2530_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7588$2531_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\main_interface0_ram_bus_ack[0:0] 1'0 + assign $0\main_interface1_ram_bus_ack[0:0] 1'0 + assign $0\main_interface2_ram_bus_ack[0:0] 1'0 assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] assign $0\main_sdram_postponer_req_o[0:0] 1'0 @@ -275325,14 +278312,14 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7893$2495_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7894$2496_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7895$2497_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8042$2637_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8043$2638_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8044$2639_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7929$2515_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7930$2527_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8078$2657_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8079$2669_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 @@ -275342,11 +278329,11 @@ module \ls180 assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8088$2573_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8097$2576_Y + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8237$2715_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8246$2718_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8123$2578_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8132$2581_Y + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8272$2720_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8281$2723_Y assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 @@ -275362,7 +278349,7 @@ module \ls180 assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[4:0] \builder_slave_sel + assign $0\builder_slave_sel_r[7:0] \builder_slave_sel assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re @@ -275457,154 +278444,175 @@ module \ls180 assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7452.2-7454.5" - switch $or$ls180.v:7452$2399_Y - attribute \src "ls180.v:7452.6-7452.94" + attribute \src "ls180.v:7589.2-7591.5" + switch $or$ls180.v:7589$2532_Y + attribute \src "ls180.v:7589.6-7589.69" case 1'1 - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r case end - attribute \src "ls180.v:7456.2-7458.5" - switch \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7456.6-7456.66" + attribute \src "ls180.v:7593.2-7595.5" + switch \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7593.6-7593.54" case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value case end - attribute \src "ls180.v:7459.2-7462.5" - switch \main_libresocsim_converter0_reset - attribute \src "ls180.v:7459.6-7459.39" + attribute \src "ls180.v:7596.2-7599.5" + switch \main_converter0_reset + attribute \src "ls180.v:7596.6-7596.27" case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 assign $0\builder_converter0_state[0:0] 1'0 case end - attribute \src "ls180.v:7463.2-7465.5" - switch $or$ls180.v:7463$2400_Y - attribute \src "ls180.v:7463.6-7463.94" + attribute \src "ls180.v:7600.2-7602.5" + switch $or$ls180.v:7600$2533_Y + attribute \src "ls180.v:7600.6-7600.69" case 1'1 - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r case end - attribute \src "ls180.v:7467.2-7469.5" - switch \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7467.6-7467.66" + attribute \src "ls180.v:7604.2-7606.5" + switch \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7604.6-7604.54" case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value case end - attribute \src "ls180.v:7470.2-7473.5" - switch \main_libresocsim_converter1_reset - attribute \src "ls180.v:7470.6-7470.39" + attribute \src "ls180.v:7607.2-7610.5" + switch \main_converter1_reset + attribute \src "ls180.v:7607.6-7607.27" case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 assign $0\builder_converter1_state[0:0] 1'0 case end - attribute \src "ls180.v:7474.2-7476.5" - switch $or$ls180.v:7474$2401_Y - attribute \src "ls180.v:7474.6-7474.94" + attribute \src "ls180.v:7611.2-7613.5" + switch $or$ls180.v:7611$2534_Y + attribute \src "ls180.v:7611.6-7611.51" case 1'1 - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r case end - attribute \src "ls180.v:7478.2-7480.5" - switch \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:7478.6-7478.66" + attribute \src "ls180.v:7615.2-7617.5" + switch \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:7615.6-7615.57" case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value case end - attribute \src "ls180.v:7481.2-7484.5" - switch \main_libresocsim_converter2_reset - attribute \src "ls180.v:7481.6-7481.39" + attribute \src "ls180.v:7618.2-7621.5" + switch \main_socbushandler_reset + attribute \src "ls180.v:7618.6-7618.30" case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\main_socbushandler_counter[0:0] 1'0 assign $0\builder_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7485.2-7489.5" - switch $ne$ls180.v:7485$2402_Y - attribute \src "ls180.v:7485.6-7485.53" + attribute \src "ls180.v:7622.2-7626.5" + switch $ne$ls180.v:7622$2535_Y + attribute \src "ls180.v:7622.6-7622.53" case 1'1 - attribute \src "ls180.v:7486.3-7488.6" + attribute \src "ls180.v:7623.3-7625.6" switch \main_libresocsim_bus_error - attribute \src "ls180.v:7486.7-7486.33" + attribute \src "ls180.v:7623.7-7623.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7487$2403_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7624$2536_Y case end case end - attribute \src "ls180.v:7491.2-7493.5" - switch $and$ls180.v:7491$2406_Y - attribute \src "ls180.v:7491.6-7491.103" + attribute \src "ls180.v:7628.2-7630.5" + switch $and$ls180.v:7628$2539_Y + attribute \src "ls180.v:7628.6-7628.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7494.2-7502.5" + attribute \src "ls180.v:7631.2-7639.5" switch \main_libresocsim_en_storage - attribute \src "ls180.v:7494.6-7494.33" + attribute \src "ls180.v:7631.6-7631.33" case 1'1 - attribute \src "ls180.v:7495.3-7499.6" - switch $eq$ls180.v:7495$2407_Y - attribute \src "ls180.v:7495.7-7495.39" + attribute \src "ls180.v:7632.3-7636.6" + switch $eq$ls180.v:7632$2540_Y + attribute \src "ls180.v:7632.7-7632.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7497.7-7497.11" + attribute \src "ls180.v:7634.7-7634.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7498$2408_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7635$2541_Y end - attribute \src "ls180.v:7500.6-7500.10" + attribute \src "ls180.v:7637.6-7637.10" case assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage end - attribute \src "ls180.v:7503.2-7505.5" + attribute \src "ls180.v:7640.2-7642.5" switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7503.6-7503.38" + attribute \src "ls180.v:7640.6-7640.38" case 1'1 assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value case end - attribute \src "ls180.v:7506.2-7508.5" + attribute \src "ls180.v:7643.2-7645.5" switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7506.6-7506.33" + attribute \src "ls180.v:7643.6-7643.33" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7510.2-7512.5" - switch $and$ls180.v:7510$2410_Y - attribute \src "ls180.v:7510.6-7510.76" + attribute \src "ls180.v:7647.2-7649.5" + switch $and$ls180.v:7647$2543_Y + attribute \src "ls180.v:7647.6-7647.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7515.2-7517.5" + attribute \src "ls180.v:7651.2-7653.5" + switch $and$ls180.v:7651$2546_Y + attribute \src "ls180.v:7651.6-7651.100" + case 1'1 + assign $0\main_interface0_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7655.2-7657.5" + switch $and$ls180.v:7655$2549_Y + attribute \src "ls180.v:7655.6-7655.100" + case 1'1 + assign $0\main_interface1_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7659.2-7661.5" + switch $and$ls180.v:7659$2552_Y + attribute \src "ls180.v:7659.6-7659.100" + case 1'1 + assign $0\main_interface2_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7664.2-7666.5" switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7515.6-7515.37" + attribute \src "ls180.v:7664.6-7664.37" case 1'1 assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata case end - attribute \src "ls180.v:7518.2-7522.5" - switch $and$ls180.v:7518$2412_Y - attribute \src "ls180.v:7518.6-7518.57" + attribute \src "ls180.v:7667.2-7671.5" + switch $and$ls180.v:7667$2554_Y + attribute \src "ls180.v:7667.6-7667.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7519$2413_Y - attribute \src "ls180.v:7520.6-7520.10" + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7668$2555_Y + attribute \src "ls180.v:7669.6-7669.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7524.2-7530.5" + attribute \src "ls180.v:7673.2-7679.5" switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7524.6-7524.32" + attribute \src "ls180.v:7673.6-7673.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7525$2414_Y - attribute \src "ls180.v:7526.3-7529.6" - switch $eq$ls180.v:7526$2415_Y - attribute \src "ls180.v:7526.7-7526.43" + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7674$2556_Y + attribute \src "ls180.v:7675.3-7678.6" + switch $eq$ls180.v:7675$2557_Y + attribute \src "ls180.v:7675.7-7675.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 assign $0\main_sdram_postponer_req_o[0:0] 1'1 @@ -275612,30 +278620,30 @@ module \ls180 end case end - attribute \src "ls180.v:7531.2-7539.5" + attribute \src "ls180.v:7680.2-7688.5" switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7531.6-7531.33" + attribute \src "ls180.v:7680.6-7680.33" case 1'1 assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7533.6-7533.10" + attribute \src "ls180.v:7682.6-7682.10" case - attribute \src "ls180.v:7534.3-7538.6" + attribute \src "ls180.v:7683.3-7687.6" switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7534.7-7534.33" + attribute \src "ls180.v:7683.7-7683.33" case 1'1 - attribute \src "ls180.v:7535.4-7537.7" - switch $ne$ls180.v:7535$2416_Y - attribute \src "ls180.v:7535.8-7535.44" + attribute \src "ls180.v:7684.4-7686.7" + switch $ne$ls180.v:7684$2558_Y + attribute \src "ls180.v:7684.8-7684.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7536$2417_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7685$2559_Y case end case end end - attribute \src "ls180.v:7546.2-7552.5" - switch $and$ls180.v:7546$2419_Y - attribute \src "ls180.v:7546.6-7546.76" + attribute \src "ls180.v:7695.2-7701.5" + switch $and$ls180.v:7695$2561_Y + attribute \src "ls180.v:7695.6-7695.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -275644,9 +278652,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7553.2-7559.5" - switch $eq$ls180.v:7553$2420_Y - attribute \src "ls180.v:7553.6-7553.44" + attribute \src "ls180.v:7702.2-7708.5" + switch $eq$ls180.v:7702$2562_Y + attribute \src "ls180.v:7702.6-7702.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -275655,9 +278663,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7560.2-7567.5" - switch $eq$ls180.v:7560$2421_Y - attribute \src "ls180.v:7560.6-7560.44" + attribute \src "ls180.v:7709.2-7716.5" + switch $eq$ls180.v:7709$2563_Y + attribute \src "ls180.v:7709.6-7709.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -275667,83 +278675,83 @@ module \ls180 assign $0\main_sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7568.2-7578.5" - switch $eq$ls180.v:7568$2422_Y - attribute \src "ls180.v:7568.6-7568.44" + attribute \src "ls180.v:7717.2-7727.5" + switch $eq$ls180.v:7717$2564_Y + attribute \src "ls180.v:7717.6-7717.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7570.6-7570.10" + attribute \src "ls180.v:7719.6-7719.10" case - attribute \src "ls180.v:7571.3-7577.6" - switch $ne$ls180.v:7571$2423_Y - attribute \src "ls180.v:7571.7-7571.45" + attribute \src "ls180.v:7720.3-7726.6" + switch $ne$ls180.v:7720$2565_Y + attribute \src "ls180.v:7720.7-7720.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7572$2424_Y - attribute \src "ls180.v:7573.7-7573.11" + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7721$2566_Y + attribute \src "ls180.v:7722.7-7722.11" case - attribute \src "ls180.v:7574.4-7576.7" + attribute \src "ls180.v:7723.4-7725.7" switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7574.8-7574.35" + attribute \src "ls180.v:7723.8-7723.35" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7580.2-7587.5" + attribute \src "ls180.v:7729.2-7736.5" switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7580.6-7580.39" + attribute \src "ls180.v:7729.6-7729.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7582.6-7582.10" + attribute \src "ls180.v:7731.6-7731.10" case - attribute \src "ls180.v:7583.3-7586.6" + attribute \src "ls180.v:7732.3-7735.6" switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7583.7-7583.39" + attribute \src "ls180.v:7732.7-7732.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7588.2-7590.5" - switch $and$ls180.v:7588$2427_Y - attribute \src "ls180.v:7588.6-7588.191" + attribute \src "ls180.v:7737.2-7739.5" + switch $and$ls180.v:7737$2569_Y + attribute \src "ls180.v:7737.6-7737.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7589$2428_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7738$2570_Y case end - attribute \src "ls180.v:7591.2-7593.5" + attribute \src "ls180.v:7740.2-7742.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7591.6-7591.58" + attribute \src "ls180.v:7740.6-7740.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7592$2429_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7741$2571_Y case end - attribute \src "ls180.v:7594.2-7602.5" - switch $and$ls180.v:7594$2432_Y - attribute \src "ls180.v:7594.6-7594.191" + attribute \src "ls180.v:7743.2-7751.5" + switch $and$ls180.v:7743$2574_Y + attribute \src "ls180.v:7743.6-7743.191" case 1'1 - attribute \src "ls180.v:7595.3-7597.6" - switch $not$ls180.v:7595$2433_Y - attribute \src "ls180.v:7595.7-7595.62" + attribute \src "ls180.v:7744.3-7746.6" + switch $not$ls180.v:7744$2575_Y + attribute \src "ls180.v:7744.7-7744.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7596$2434_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7745$2576_Y case end - attribute \src "ls180.v:7598.6-7598.10" + attribute \src "ls180.v:7747.6-7747.10" case - attribute \src "ls180.v:7599.3-7601.6" + attribute \src "ls180.v:7748.3-7750.6" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7599.7-7599.59" + attribute \src "ls180.v:7748.7-7748.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7600$2435_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7749$2577_Y case end end - attribute \src "ls180.v:7603.2-7609.5" - switch $or$ls180.v:7603$2437_Y - attribute \src "ls180.v:7603.6-7603.108" + attribute \src "ls180.v:7752.2-7758.5" + switch $or$ls180.v:7752$2579_Y + attribute \src "ls180.v:7752.6-7752.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first @@ -275752,27 +278760,27 @@ module \ls180 assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7610.2-7624.5" + attribute \src "ls180.v:7759.2-7773.5" switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7610.6-7610.43" + attribute \src "ls180.v:7759.6-7759.43" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7612.3-7616.6" + attribute \src "ls180.v:7761.3-7765.6" switch 1'0 - attribute \src "ls180.v:7614.7-7614.11" + attribute \src "ls180.v:7763.7-7763.11" case assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7617.6-7617.10" + attribute \src "ls180.v:7766.6-7766.10" case - attribute \src "ls180.v:7618.3-7623.6" - switch $not$ls180.v:7618$2438_Y - attribute \src "ls180.v:7618.7-7618.47" + attribute \src "ls180.v:7767.3-7772.6" + switch $not$ls180.v:7767$2580_Y + attribute \src "ls180.v:7767.7-7767.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7619$2439_Y - attribute \src "ls180.v:7620.4-7622.7" - switch $eq$ls180.v:7620$2440_Y - attribute \src "ls180.v:7620.8-7620.55" + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7768$2581_Y + attribute \src "ls180.v:7769.4-7771.7" + switch $eq$ls180.v:7769$2582_Y + attribute \src "ls180.v:7769.8-7769.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case @@ -275780,60 +278788,60 @@ module \ls180 case end end - attribute \src "ls180.v:7626.2-7633.5" + attribute \src "ls180.v:7775.2-7782.5" switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7626.6-7626.39" + attribute \src "ls180.v:7775.6-7775.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7628.6-7628.10" + attribute \src "ls180.v:7777.6-7777.10" case - attribute \src "ls180.v:7629.3-7632.6" + attribute \src "ls180.v:7778.3-7781.6" switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7629.7-7629.39" + attribute \src "ls180.v:7778.7-7778.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7634.2-7636.5" - switch $and$ls180.v:7634$2443_Y - attribute \src "ls180.v:7634.6-7634.191" + attribute \src "ls180.v:7783.2-7785.5" + switch $and$ls180.v:7783$2585_Y + attribute \src "ls180.v:7783.6-7783.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7635$2444_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7784$2586_Y case end - attribute \src "ls180.v:7637.2-7639.5" + attribute \src "ls180.v:7786.2-7788.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7637.6-7637.58" + attribute \src "ls180.v:7786.6-7786.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7638$2445_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7787$2587_Y case end - attribute \src "ls180.v:7640.2-7648.5" - switch $and$ls180.v:7640$2448_Y - attribute \src "ls180.v:7640.6-7640.191" + attribute \src "ls180.v:7789.2-7797.5" + switch $and$ls180.v:7789$2590_Y + attribute \src "ls180.v:7789.6-7789.191" case 1'1 - attribute \src "ls180.v:7641.3-7643.6" - switch $not$ls180.v:7641$2449_Y - attribute \src "ls180.v:7641.7-7641.62" + attribute \src "ls180.v:7790.3-7792.6" + switch $not$ls180.v:7790$2591_Y + attribute \src "ls180.v:7790.7-7790.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7642$2450_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7791$2592_Y case end - attribute \src "ls180.v:7644.6-7644.10" + attribute \src "ls180.v:7793.6-7793.10" case - attribute \src "ls180.v:7645.3-7647.6" + attribute \src "ls180.v:7794.3-7796.6" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7645.7-7645.59" + attribute \src "ls180.v:7794.7-7794.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7646$2451_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7795$2593_Y case end end - attribute \src "ls180.v:7649.2-7655.5" - switch $or$ls180.v:7649$2453_Y - attribute \src "ls180.v:7649.6-7649.108" + attribute \src "ls180.v:7798.2-7804.5" + switch $or$ls180.v:7798$2595_Y + attribute \src "ls180.v:7798.6-7798.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first @@ -275842,27 +278850,27 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7656.2-7670.5" + attribute \src "ls180.v:7805.2-7819.5" switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7656.6-7656.43" + attribute \src "ls180.v:7805.6-7805.43" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7658.3-7662.6" + attribute \src "ls180.v:7807.3-7811.6" switch 1'0 - attribute \src "ls180.v:7660.7-7660.11" + attribute \src "ls180.v:7809.7-7809.11" case assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7663.6-7663.10" + attribute \src "ls180.v:7812.6-7812.10" case - attribute \src "ls180.v:7664.3-7669.6" - switch $not$ls180.v:7664$2454_Y - attribute \src "ls180.v:7664.7-7664.47" + attribute \src "ls180.v:7813.3-7818.6" + switch $not$ls180.v:7813$2596_Y + attribute \src "ls180.v:7813.7-7813.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7665$2455_Y - attribute \src "ls180.v:7666.4-7668.7" - switch $eq$ls180.v:7666$2456_Y - attribute \src "ls180.v:7666.8-7666.55" + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7814$2597_Y + attribute \src "ls180.v:7815.4-7817.7" + switch $eq$ls180.v:7815$2598_Y + attribute \src "ls180.v:7815.8-7815.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case @@ -275870,60 +278878,60 @@ module \ls180 case end end - attribute \src "ls180.v:7672.2-7679.5" + attribute \src "ls180.v:7821.2-7828.5" switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7672.6-7672.39" + attribute \src "ls180.v:7821.6-7821.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7674.6-7674.10" + attribute \src "ls180.v:7823.6-7823.10" case - attribute \src "ls180.v:7675.3-7678.6" + attribute \src "ls180.v:7824.3-7827.6" switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7675.7-7675.39" + attribute \src "ls180.v:7824.7-7824.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7680.2-7682.5" - switch $and$ls180.v:7680$2459_Y - attribute \src "ls180.v:7680.6-7680.191" + attribute \src "ls180.v:7829.2-7831.5" + switch $and$ls180.v:7829$2601_Y + attribute \src "ls180.v:7829.6-7829.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7681$2460_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7830$2602_Y case end - attribute \src "ls180.v:7683.2-7685.5" + attribute \src "ls180.v:7832.2-7834.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7683.6-7683.58" + attribute \src "ls180.v:7832.6-7832.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7684$2461_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7833$2603_Y case end - attribute \src "ls180.v:7686.2-7694.5" - switch $and$ls180.v:7686$2464_Y - attribute \src "ls180.v:7686.6-7686.191" + attribute \src "ls180.v:7835.2-7843.5" + switch $and$ls180.v:7835$2606_Y + attribute \src "ls180.v:7835.6-7835.191" case 1'1 - attribute \src "ls180.v:7687.3-7689.6" - switch $not$ls180.v:7687$2465_Y - attribute \src "ls180.v:7687.7-7687.62" + attribute \src "ls180.v:7836.3-7838.6" + switch $not$ls180.v:7836$2607_Y + attribute \src "ls180.v:7836.7-7836.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7688$2466_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7837$2608_Y case end - attribute \src "ls180.v:7690.6-7690.10" + attribute \src "ls180.v:7839.6-7839.10" case - attribute \src "ls180.v:7691.3-7693.6" + attribute \src "ls180.v:7840.3-7842.6" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7691.7-7691.59" + attribute \src "ls180.v:7840.7-7840.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7692$2467_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7841$2609_Y case end end - attribute \src "ls180.v:7695.2-7701.5" - switch $or$ls180.v:7695$2469_Y - attribute \src "ls180.v:7695.6-7695.108" + attribute \src "ls180.v:7844.2-7850.5" + switch $or$ls180.v:7844$2611_Y + attribute \src "ls180.v:7844.6-7844.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first @@ -275932,27 +278940,27 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7702.2-7716.5" + attribute \src "ls180.v:7851.2-7865.5" switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7702.6-7702.43" + attribute \src "ls180.v:7851.6-7851.43" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7704.3-7708.6" + attribute \src "ls180.v:7853.3-7857.6" switch 1'0 - attribute \src "ls180.v:7706.7-7706.11" + attribute \src "ls180.v:7855.7-7855.11" case assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7709.6-7709.10" + attribute \src "ls180.v:7858.6-7858.10" case - attribute \src "ls180.v:7710.3-7715.6" - switch $not$ls180.v:7710$2470_Y - attribute \src "ls180.v:7710.7-7710.47" + attribute \src "ls180.v:7859.3-7864.6" + switch $not$ls180.v:7859$2612_Y + attribute \src "ls180.v:7859.7-7859.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7711$2471_Y - attribute \src "ls180.v:7712.4-7714.7" - switch $eq$ls180.v:7712$2472_Y - attribute \src "ls180.v:7712.8-7712.55" + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7860$2613_Y + attribute \src "ls180.v:7861.4-7863.7" + switch $eq$ls180.v:7861$2614_Y + attribute \src "ls180.v:7861.8-7861.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case @@ -275960,60 +278968,60 @@ module \ls180 case end end - attribute \src "ls180.v:7718.2-7725.5" + attribute \src "ls180.v:7867.2-7874.5" switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7718.6-7718.39" + attribute \src "ls180.v:7867.6-7867.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7720.6-7720.10" + attribute \src "ls180.v:7869.6-7869.10" case - attribute \src "ls180.v:7721.3-7724.6" + attribute \src "ls180.v:7870.3-7873.6" switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7721.7-7721.39" + attribute \src "ls180.v:7870.7-7870.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7726.2-7728.5" - switch $and$ls180.v:7726$2475_Y - attribute \src "ls180.v:7726.6-7726.191" + attribute \src "ls180.v:7875.2-7877.5" + switch $and$ls180.v:7875$2617_Y + attribute \src "ls180.v:7875.6-7875.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7727$2476_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7876$2618_Y case end - attribute \src "ls180.v:7729.2-7731.5" + attribute \src "ls180.v:7878.2-7880.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7729.6-7729.58" + attribute \src "ls180.v:7878.6-7878.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7730$2477_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7879$2619_Y case end - attribute \src "ls180.v:7732.2-7740.5" - switch $and$ls180.v:7732$2480_Y - attribute \src "ls180.v:7732.6-7732.191" + attribute \src "ls180.v:7881.2-7889.5" + switch $and$ls180.v:7881$2622_Y + attribute \src "ls180.v:7881.6-7881.191" case 1'1 - attribute \src "ls180.v:7733.3-7735.6" - switch $not$ls180.v:7733$2481_Y - attribute \src "ls180.v:7733.7-7733.62" + attribute \src "ls180.v:7882.3-7884.6" + switch $not$ls180.v:7882$2623_Y + attribute \src "ls180.v:7882.7-7882.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7734$2482_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7883$2624_Y case end - attribute \src "ls180.v:7736.6-7736.10" + attribute \src "ls180.v:7885.6-7885.10" case - attribute \src "ls180.v:7737.3-7739.6" + attribute \src "ls180.v:7886.3-7888.6" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7737.7-7737.59" + attribute \src "ls180.v:7886.7-7886.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7738$2483_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7887$2625_Y case end end - attribute \src "ls180.v:7741.2-7747.5" - switch $or$ls180.v:7741$2485_Y - attribute \src "ls180.v:7741.6-7741.108" + attribute \src "ls180.v:7890.2-7896.5" + switch $or$ls180.v:7890$2627_Y + attribute \src "ls180.v:7890.6-7890.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first @@ -276022,27 +279030,27 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7748.2-7762.5" + attribute \src "ls180.v:7897.2-7911.5" switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7748.6-7748.43" + attribute \src "ls180.v:7897.6-7897.43" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7750.3-7754.6" + attribute \src "ls180.v:7899.3-7903.6" switch 1'0 - attribute \src "ls180.v:7752.7-7752.11" + attribute \src "ls180.v:7901.7-7901.11" case assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7755.6-7755.10" + attribute \src "ls180.v:7904.6-7904.10" case - attribute \src "ls180.v:7756.3-7761.6" - switch $not$ls180.v:7756$2486_Y - attribute \src "ls180.v:7756.7-7756.47" + attribute \src "ls180.v:7905.3-7910.6" + switch $not$ls180.v:7905$2628_Y + attribute \src "ls180.v:7905.7-7905.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7757$2487_Y - attribute \src "ls180.v:7758.4-7760.7" - switch $eq$ls180.v:7758$2488_Y - attribute \src "ls180.v:7758.8-7758.55" + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7906$2629_Y + attribute \src "ls180.v:7907.4-7909.7" + switch $eq$ls180.v:7907$2630_Y + attribute \src "ls180.v:7907.8-7907.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case @@ -276050,61 +279058,61 @@ module \ls180 case end end - attribute \src "ls180.v:7764.2-7770.5" - switch $not$ls180.v:7764$2489_Y - attribute \src "ls180.v:7764.6-7764.23" + attribute \src "ls180.v:7913.2-7919.5" + switch $not$ls180.v:7913$2631_Y + attribute \src "ls180.v:7913.6-7913.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7766.6-7766.10" + attribute \src "ls180.v:7915.6-7915.10" case - attribute \src "ls180.v:7767.3-7769.6" - switch $not$ls180.v:7767$2490_Y - attribute \src "ls180.v:7767.7-7767.30" + attribute \src "ls180.v:7916.3-7918.6" + switch $not$ls180.v:7916$2632_Y + attribute \src "ls180.v:7916.7-7916.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7768$2491_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7917$2633_Y case end end - attribute \src "ls180.v:7771.2-7777.5" - switch $not$ls180.v:7771$2492_Y - attribute \src "ls180.v:7771.6-7771.23" + attribute \src "ls180.v:7920.2-7926.5" + switch $not$ls180.v:7920$2634_Y + attribute \src "ls180.v:7920.6-7920.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7773.6-7773.10" + attribute \src "ls180.v:7922.6-7922.10" case - attribute \src "ls180.v:7774.3-7776.6" - switch $not$ls180.v:7774$2493_Y - attribute \src "ls180.v:7774.7-7774.30" + attribute \src "ls180.v:7923.3-7925.6" + switch $not$ls180.v:7923$2635_Y + attribute \src "ls180.v:7923.7-7923.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7775$2494_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7924$2636_Y case end end - attribute \src "ls180.v:7778.2-7833.5" + attribute \src "ls180.v:7927.2-7982.5" switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7778.6-7778.30" + attribute \src "ls180.v:7927.6-7927.30" case 1'1 - attribute \src "ls180.v:7779.3-7832.10" + attribute \src "ls180.v:7928.3-7981.10" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7781.5-7791.8" + attribute \src "ls180.v:7930.5-7940.8" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7781.9-7781.41" + attribute \src "ls180.v:7930.9-7930.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7783.9-7783.13" + attribute \src "ls180.v:7932.9-7932.13" case - attribute \src "ls180.v:7784.6-7790.9" + attribute \src "ls180.v:7933.6-7939.9" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7784.10-7784.42" + attribute \src "ls180.v:7933.10-7933.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7786.10-7786.14" + attribute \src "ls180.v:7935.10-7935.14" case - attribute \src "ls180.v:7787.7-7789.10" + attribute \src "ls180.v:7936.7-7938.10" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7787.11-7787.43" + attribute \src "ls180.v:7936.11-7936.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 case @@ -276113,23 +279121,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7794.5-7804.8" + attribute \src "ls180.v:7943.5-7953.8" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7794.9-7794.41" + attribute \src "ls180.v:7943.9-7943.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7796.9-7796.13" + attribute \src "ls180.v:7945.9-7945.13" case - attribute \src "ls180.v:7797.6-7803.9" + attribute \src "ls180.v:7946.6-7952.9" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7797.10-7797.42" + attribute \src "ls180.v:7946.10-7946.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7799.10-7799.14" + attribute \src "ls180.v:7948.10-7948.14" case - attribute \src "ls180.v:7800.7-7802.10" + attribute \src "ls180.v:7949.7-7951.10" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7800.11-7800.43" + attribute \src "ls180.v:7949.11-7949.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 case @@ -276138,23 +279146,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7807.5-7817.8" + attribute \src "ls180.v:7956.5-7966.8" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7807.9-7807.41" + attribute \src "ls180.v:7956.9-7956.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7809.9-7809.13" + attribute \src "ls180.v:7958.9-7958.13" case - attribute \src "ls180.v:7810.6-7816.9" + attribute \src "ls180.v:7959.6-7965.9" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7810.10-7810.42" + attribute \src "ls180.v:7959.10-7959.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7812.10-7812.14" + attribute \src "ls180.v:7961.10-7961.14" case - attribute \src "ls180.v:7813.7-7815.10" + attribute \src "ls180.v:7962.7-7964.10" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7813.11-7813.43" + attribute \src "ls180.v:7962.11-7962.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 case @@ -276163,23 +279171,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7820.5-7830.8" + attribute \src "ls180.v:7969.5-7979.8" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7820.9-7820.41" + attribute \src "ls180.v:7969.9-7969.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7822.9-7822.13" + attribute \src "ls180.v:7971.9-7971.13" case - attribute \src "ls180.v:7823.6-7829.9" + attribute \src "ls180.v:7972.6-7978.9" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7823.10-7823.42" + attribute \src "ls180.v:7972.10-7972.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7825.10-7825.14" + attribute \src "ls180.v:7974.10-7974.14" case - attribute \src "ls180.v:7826.7-7828.10" + attribute \src "ls180.v:7975.7-7977.10" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7826.11-7826.43" + attribute \src "ls180.v:7975.11-7975.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 case @@ -276190,31 +279198,31 @@ module \ls180 end case end - attribute \src "ls180.v:7834.2-7889.5" + attribute \src "ls180.v:7983.2-8038.5" switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7834.6-7834.30" + attribute \src "ls180.v:7983.6-7983.30" case 1'1 - attribute \src "ls180.v:7835.3-7888.10" + attribute \src "ls180.v:7984.3-8037.10" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7837.5-7847.8" + attribute \src "ls180.v:7986.5-7996.8" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7837.9-7837.41" + attribute \src "ls180.v:7986.9-7986.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7839.9-7839.13" + attribute \src "ls180.v:7988.9-7988.13" case - attribute \src "ls180.v:7840.6-7846.9" + attribute \src "ls180.v:7989.6-7995.9" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7840.10-7840.42" + attribute \src "ls180.v:7989.10-7989.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7842.10-7842.14" + attribute \src "ls180.v:7991.10-7991.14" case - attribute \src "ls180.v:7843.7-7845.10" + attribute \src "ls180.v:7992.7-7994.10" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7843.11-7843.43" + attribute \src "ls180.v:7992.11-7992.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 case @@ -276223,23 +279231,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7850.5-7860.8" + attribute \src "ls180.v:7999.5-8009.8" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7850.9-7850.41" + attribute \src "ls180.v:7999.9-7999.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7852.9-7852.13" + attribute \src "ls180.v:8001.9-8001.13" case - attribute \src "ls180.v:7853.6-7859.9" + attribute \src "ls180.v:8002.6-8008.9" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7853.10-7853.42" + attribute \src "ls180.v:8002.10-8002.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7855.10-7855.14" + attribute \src "ls180.v:8004.10-8004.14" case - attribute \src "ls180.v:7856.7-7858.10" + attribute \src "ls180.v:8005.7-8007.10" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7856.11-7856.43" + attribute \src "ls180.v:8005.11-8005.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 case @@ -276248,23 +279256,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7863.5-7873.8" + attribute \src "ls180.v:8012.5-8022.8" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7863.9-7863.41" + attribute \src "ls180.v:8012.9-8012.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7865.9-7865.13" + attribute \src "ls180.v:8014.9-8014.13" case - attribute \src "ls180.v:7866.6-7872.9" + attribute \src "ls180.v:8015.6-8021.9" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7866.10-7866.42" + attribute \src "ls180.v:8015.10-8015.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7868.10-7868.14" + attribute \src "ls180.v:8017.10-8017.14" case - attribute \src "ls180.v:7869.7-7871.10" + attribute \src "ls180.v:8018.7-8020.10" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7869.11-7869.43" + attribute \src "ls180.v:8018.11-8018.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 case @@ -276273,23 +279281,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7876.5-7886.8" + attribute \src "ls180.v:8025.5-8035.8" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7876.9-7876.41" + attribute \src "ls180.v:8025.9-8025.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7878.9-7878.13" + attribute \src "ls180.v:8027.9-8027.13" case - attribute \src "ls180.v:7879.6-7885.9" + attribute \src "ls180.v:8028.6-8034.9" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7879.10-7879.42" + attribute \src "ls180.v:8028.10-8028.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7881.10-7881.14" + attribute \src "ls180.v:8030.10-8030.14" case - attribute \src "ls180.v:7882.7-7884.10" + attribute \src "ls180.v:8031.7-8033.10" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7882.11-7882.43" + attribute \src "ls180.v:8031.11-8031.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 case @@ -276300,28 +279308,28 @@ module \ls180 end case end - attribute \src "ls180.v:7898.2-7912.5" + attribute \src "ls180.v:8047.2-8061.5" switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:7898.6-7898.30" + attribute \src "ls180.v:8047.6-8047.30" case 1'1 assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:7900.3-7904.6" + attribute \src "ls180.v:8049.3-8053.6" switch 1'1 - attribute \src "ls180.v:7900.7-7900.11" + attribute \src "ls180.v:8049.7-8049.11" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:7905.6-7905.10" + attribute \src "ls180.v:8054.6-8054.10" case - attribute \src "ls180.v:7906.3-7911.6" - switch $not$ls180.v:7906$2498_Y - attribute \src "ls180.v:7906.7-7906.34" + attribute \src "ls180.v:8055.3-8060.6" + switch $not$ls180.v:8055$2640_Y + attribute \src "ls180.v:8055.7-8055.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7907$2499_Y - attribute \src "ls180.v:7908.4-7910.7" - switch $eq$ls180.v:7908$2500_Y - attribute \src "ls180.v:7908.8-7908.42" + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8056$2641_Y + attribute \src "ls180.v:8057.4-8059.7" + switch $eq$ls180.v:8057$2642_Y + attribute \src "ls180.v:8057.8-8057.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case @@ -276329,27 +279337,27 @@ module \ls180 case end end - attribute \src "ls180.v:7913.2-7927.5" + attribute \src "ls180.v:8062.2-8076.5" switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:7913.6-7913.30" + attribute \src "ls180.v:8062.6-8062.30" case 1'1 assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:7915.3-7919.6" + attribute \src "ls180.v:8064.3-8068.6" switch 1'0 - attribute \src "ls180.v:7917.7-7917.11" + attribute \src "ls180.v:8066.7-8066.11" case assign $0\main_sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7920.6-7920.10" + attribute \src "ls180.v:8069.6-8069.10" case - attribute \src "ls180.v:7921.3-7926.6" - switch $not$ls180.v:7921$2501_Y - attribute \src "ls180.v:7921.7-7921.34" + attribute \src "ls180.v:8070.3-8075.6" + switch $not$ls180.v:8070$2643_Y + attribute \src "ls180.v:8070.7-8070.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7922$2502_Y - attribute \src "ls180.v:7923.4-7925.7" - switch $eq$ls180.v:7923$2503_Y - attribute \src "ls180.v:7923.8-7923.42" + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8071$2644_Y + attribute \src "ls180.v:8072.4-8074.7" + switch $eq$ls180.v:8072$2645_Y + attribute \src "ls180.v:8072.8-8072.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 case @@ -276357,81 +279365,81 @@ module \ls180 case end end - attribute \src "ls180.v:7934.2-7936.5" - switch $or$ls180.v:7934$2528_Y - attribute \src "ls180.v:7934.6-7934.50" + attribute \src "ls180.v:8083.2-8085.5" + switch $or$ls180.v:8083$2670_Y + attribute \src "ls180.v:8083.6-8083.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r case end - attribute \src "ls180.v:7938.2-7940.5" + attribute \src "ls180.v:8087.2-8089.5" switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:7938.6-7938.52" + attribute \src "ls180.v:8087.6-8087.52" case 1'1 assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value case end - attribute \src "ls180.v:7941.2-7944.5" + attribute \src "ls180.v:8090.2-8093.5" switch \main_converter_reset - attribute \src "ls180.v:7941.6-7941.26" + attribute \src "ls180.v:8090.6-8090.26" case 1'1 assign $0\main_converter_counter[0:0] 1'0 assign $0\builder_converter_state[0:0] 1'0 case end - attribute \src "ls180.v:7945.2-7955.5" + attribute \src "ls180.v:8094.2-8104.5" switch \main_litedram_wb_ack - attribute \src "ls180.v:7945.6-7945.26" + attribute \src "ls180.v:8094.6-8094.26" case 1'1 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:7948.6-7948.10" + attribute \src "ls180.v:8097.6-8097.10" case - attribute \src "ls180.v:7949.3-7951.6" - switch $and$ls180.v:7949$2529_Y - attribute \src "ls180.v:7949.7-7949.50" + attribute \src "ls180.v:8098.3-8100.6" + switch $and$ls180.v:8098$2671_Y + attribute \src "ls180.v:8098.7-8098.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:7952.3-7954.6" - switch $and$ls180.v:7952$2530_Y - attribute \src "ls180.v:7952.7-7952.54" + attribute \src "ls180.v:8101.3-8103.6" + switch $and$ls180.v:8101$2672_Y + attribute \src "ls180.v:8101.7-8101.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:7957.2-7978.5" - switch $and$ls180.v:7957$2534_Y - attribute \src "ls180.v:7957.6-7957.91" + attribute \src "ls180.v:8106.2-8127.5" + switch $and$ls180.v:8106$2676_Y + attribute \src "ls180.v:8106.6-8106.91" case 1'1 assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 assign $0\main_uart_phy_tx_busy[0:0] 1'1 assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:7962.6-7962.10" + attribute \src "ls180.v:8111.6-8111.10" case - attribute \src "ls180.v:7963.3-7977.6" - switch $and$ls180.v:7963$2535_Y - attribute \src "ls180.v:7963.7-7963.60" + attribute \src "ls180.v:8112.3-8126.6" + switch $and$ls180.v:8112$2677_Y + attribute \src "ls180.v:8112.7-8112.60" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7964$2536_Y - attribute \src "ls180.v:7965.4-7976.7" - switch $eq$ls180.v:7965$2537_Y - attribute \src "ls180.v:7965.8-7965.43" + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8113$2678_Y + attribute \src "ls180.v:8114.4-8125.7" + switch $eq$ls180.v:8114$2679_Y + attribute \src "ls180.v:8114.8-8114.43" case 1'1 assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:7967.8-7967.12" + attribute \src "ls180.v:8116.8-8116.12" case - attribute \src "ls180.v:7968.5-7975.8" - switch $eq$ls180.v:7968$2538_Y - attribute \src "ls180.v:7968.9-7968.44" + attribute \src "ls180.v:8117.5-8124.8" + switch $eq$ls180.v:8117$2680_Y + attribute \src "ls180.v:8117.9-8117.44" case 1'1 assign $0\uart_tx[0:0] 1'1 assign $0\main_uart_phy_tx_busy[0:0] 1'0 assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:7972.9-7972.13" + attribute \src "ls180.v:8121.9-8121.13" case assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } @@ -276440,61 +279448,61 @@ module \ls180 case end end - attribute \src "ls180.v:7979.2-7983.5" + attribute \src "ls180.v:8128.2-8132.5" switch \main_uart_phy_tx_busy - attribute \src "ls180.v:7979.6-7979.27" + attribute \src "ls180.v:8128.6-8128.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7980$2539_Y - attribute \src "ls180.v:7981.6-7981.10" + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8129$2681_Y + attribute \src "ls180.v:8130.6-8130.10" case assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } end - attribute \src "ls180.v:7986.2-8010.5" - switch $not$ls180.v:7986$2540_Y - attribute \src "ls180.v:7986.6-7986.30" + attribute \src "ls180.v:8135.2-8159.5" + switch $not$ls180.v:8135$2682_Y + attribute \src "ls180.v:8135.6-8135.30" case 1'1 - attribute \src "ls180.v:7987.3-7990.6" - switch $and$ls180.v:7987$2542_Y - attribute \src "ls180.v:7987.7-7987.49" + attribute \src "ls180.v:8136.3-8139.6" + switch $and$ls180.v:8136$2684_Y + attribute \src "ls180.v:8136.7-8136.49" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'1 assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:7991.6-7991.10" + attribute \src "ls180.v:8140.6-8140.10" case - attribute \src "ls180.v:7992.3-8009.6" + attribute \src "ls180.v:8141.3-8158.6" switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:7992.7-7992.34" + attribute \src "ls180.v:8141.7-8141.34" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7993$2543_Y - attribute \src "ls180.v:7994.4-8008.7" - switch $eq$ls180.v:7994$2544_Y - attribute \src "ls180.v:7994.8-7994.43" + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8142$2685_Y + attribute \src "ls180.v:8143.4-8157.7" + switch $eq$ls180.v:8143$2686_Y + attribute \src "ls180.v:8143.8-8143.43" case 1'1 - attribute \src "ls180.v:7995.5-7997.8" + attribute \src "ls180.v:8144.5-8146.8" switch \main_uart_phy_rx - attribute \src "ls180.v:7995.9-7995.25" + attribute \src "ls180.v:8144.9-8144.25" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:7998.8-7998.12" + attribute \src "ls180.v:8147.8-8147.12" case - attribute \src "ls180.v:7999.5-8007.8" - switch $eq$ls180.v:7999$2545_Y - attribute \src "ls180.v:7999.9-7999.44" + attribute \src "ls180.v:8148.5-8156.8" + switch $eq$ls180.v:8148$2687_Y + attribute \src "ls180.v:8148.9-8148.44" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8001.6-8004.9" + attribute \src "ls180.v:8150.6-8153.9" switch \main_uart_phy_rx - attribute \src "ls180.v:8001.10-8001.26" + attribute \src "ls180.v:8150.10-8150.26" case 1'1 assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg assign $0\main_uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:8005.9-8005.13" + attribute \src "ls180.v:8154.9-8154.13" case assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } end @@ -276502,146 +279510,146 @@ module \ls180 case end end - attribute \src "ls180.v:8011.2-8015.5" + attribute \src "ls180.v:8160.2-8164.5" switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8011.6-8011.27" + attribute \src "ls180.v:8160.6-8160.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8012$2546_Y - attribute \src "ls180.v:8013.6-8013.10" + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8161$2688_Y + attribute \src "ls180.v:8162.6-8162.10" case assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:8016.2-8018.5" + attribute \src "ls180.v:8165.2-8167.5" switch \main_uart_tx_clear - attribute \src "ls180.v:8016.6-8016.24" + attribute \src "ls180.v:8165.6-8165.24" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8020.2-8022.5" - switch $and$ls180.v:8020$2548_Y - attribute \src "ls180.v:8020.6-8020.58" + attribute \src "ls180.v:8169.2-8171.5" + switch $and$ls180.v:8169$2690_Y + attribute \src "ls180.v:8169.6-8169.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8023.2-8025.5" + attribute \src "ls180.v:8172.2-8174.5" switch \main_uart_rx_clear - attribute \src "ls180.v:8023.6-8023.24" + attribute \src "ls180.v:8172.6-8172.24" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8027.2-8029.5" - switch $and$ls180.v:8027$2550_Y - attribute \src "ls180.v:8027.6-8027.58" + attribute \src "ls180.v:8176.2-8178.5" + switch $and$ls180.v:8176$2692_Y + attribute \src "ls180.v:8176.6-8176.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8030.2-8036.5" + attribute \src "ls180.v:8179.2-8185.5" switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8030.6-8030.35" + attribute \src "ls180.v:8179.6-8179.35" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8032.6-8032.10" + attribute \src "ls180.v:8181.6-8181.10" case - attribute \src "ls180.v:8033.3-8035.6" + attribute \src "ls180.v:8182.3-8184.6" switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8033.7-8033.27" + attribute \src "ls180.v:8182.7-8182.27" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8037.2-8039.5" - switch $and$ls180.v:8037$2553_Y - attribute \src "ls180.v:8037.6-8037.108" + attribute \src "ls180.v:8186.2-8188.5" + switch $and$ls180.v:8186$2695_Y + attribute \src "ls180.v:8186.6-8186.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8038$2554_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8187$2696_Y case end - attribute \src "ls180.v:8040.2-8042.5" + attribute \src "ls180.v:8189.2-8191.5" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8040.6-8040.31" + attribute \src "ls180.v:8189.6-8189.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8041$2555_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8190$2697_Y case end - attribute \src "ls180.v:8043.2-8051.5" - switch $and$ls180.v:8043$2558_Y - attribute \src "ls180.v:8043.6-8043.108" + attribute \src "ls180.v:8192.2-8200.5" + switch $and$ls180.v:8192$2700_Y + attribute \src "ls180.v:8192.6-8192.108" case 1'1 - attribute \src "ls180.v:8044.3-8046.6" - switch $not$ls180.v:8044$2559_Y - attribute \src "ls180.v:8044.7-8044.35" + attribute \src "ls180.v:8193.3-8195.6" + switch $not$ls180.v:8193$2701_Y + attribute \src "ls180.v:8193.7-8193.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8045$2560_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8194$2702_Y case end - attribute \src "ls180.v:8047.6-8047.10" + attribute \src "ls180.v:8196.6-8196.10" case - attribute \src "ls180.v:8048.3-8050.6" + attribute \src "ls180.v:8197.3-8199.6" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8048.7-8048.32" + attribute \src "ls180.v:8197.7-8197.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8049$2561_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8198$2703_Y case end end - attribute \src "ls180.v:8052.2-8058.5" + attribute \src "ls180.v:8201.2-8207.5" switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8052.6-8052.35" + attribute \src "ls180.v:8201.6-8201.35" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8054.6-8054.10" + attribute \src "ls180.v:8203.6-8203.10" case - attribute \src "ls180.v:8055.3-8057.6" + attribute \src "ls180.v:8204.3-8206.6" switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8055.7-8055.27" + attribute \src "ls180.v:8204.7-8204.27" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8059.2-8061.5" - switch $and$ls180.v:8059$2564_Y - attribute \src "ls180.v:8059.6-8059.108" + attribute \src "ls180.v:8208.2-8210.5" + switch $and$ls180.v:8208$2706_Y + attribute \src "ls180.v:8208.6-8208.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8060$2565_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8209$2707_Y case end - attribute \src "ls180.v:8062.2-8064.5" + attribute \src "ls180.v:8211.2-8213.5" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8062.6-8062.31" + attribute \src "ls180.v:8211.6-8211.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8063$2566_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8212$2708_Y case end - attribute \src "ls180.v:8065.2-8073.5" - switch $and$ls180.v:8065$2569_Y - attribute \src "ls180.v:8065.6-8065.108" + attribute \src "ls180.v:8214.2-8222.5" + switch $and$ls180.v:8214$2711_Y + attribute \src "ls180.v:8214.6-8214.108" case 1'1 - attribute \src "ls180.v:8066.3-8068.6" - switch $not$ls180.v:8066$2570_Y - attribute \src "ls180.v:8066.7-8066.35" + attribute \src "ls180.v:8215.3-8217.6" + switch $not$ls180.v:8215$2712_Y + attribute \src "ls180.v:8215.7-8215.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8067$2571_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8216$2713_Y case end - attribute \src "ls180.v:8069.6-8069.10" + attribute \src "ls180.v:8218.6-8218.10" case - attribute \src "ls180.v:8070.3-8072.6" + attribute \src "ls180.v:8219.3-8221.6" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8070.7-8070.32" + attribute \src "ls180.v:8219.7-8219.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8071$2572_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8220$2714_Y case end end - attribute \src "ls180.v:8074.2-8087.5" + attribute \src "ls180.v:8223.2-8236.5" switch \main_uart_reset - attribute \src "ls180.v:8074.6-8074.21" + attribute \src "ls180.v:8223.6-8223.21" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 assign $0\main_uart_tx_old_trigger[0:0] 1'0 @@ -276657,38 +279665,38 @@ module \ls180 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:8089.2-8096.5" + attribute \src "ls180.v:8238.2-8245.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8089.6-8089.31" + attribute \src "ls180.v:8238.6-8238.31" case 1'1 assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8091.6-8091.10" + attribute \src "ls180.v:8240.6-8240.10" case - attribute \src "ls180.v:8092.3-8095.6" + attribute \src "ls180.v:8241.3-8244.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8092.7-8092.32" + attribute \src "ls180.v:8241.7-8241.32" case 1'1 assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 assign $0\spisdcard_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8098.2-8108.5" + attribute \src "ls180.v:8247.2-8257.5" switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8098.6-8098.33" + attribute \src "ls180.v:8247.6-8247.33" case 1'1 assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8101.6-8101.10" + attribute \src "ls180.v:8250.6-8250.10" case - attribute \src "ls180.v:8102.3-8107.6" + attribute \src "ls180.v:8251.3-8256.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8102.7-8102.32" + attribute \src "ls180.v:8251.7-8251.32" case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8106$2577_Y - attribute \src "ls180.v:8103.4-8105.7" + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8255$2719_Y + attribute \src "ls180.v:8252.4-8254.7" switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8103.8-8103.34" + attribute \src "ls180.v:8252.8-8252.34" case 1'1 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 case @@ -276696,67 +279704,67 @@ module \ls180 case end end - attribute \src "ls180.v:8109.2-8115.5" + attribute \src "ls180.v:8258.2-8264.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8109.6-8109.31" + attribute \src "ls180.v:8258.6-8258.31" case 1'1 - attribute \src "ls180.v:8110.3-8114.6" + attribute \src "ls180.v:8259.3-8263.6" switch \main_spimaster7_loopback - attribute \src "ls180.v:8110.7-8110.31" + attribute \src "ls180.v:8259.7-8259.31" case 1'1 assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8112.7-8112.11" + attribute \src "ls180.v:8261.7-8261.11" case assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } end case end - attribute \src "ls180.v:8116.2-8118.5" + attribute \src "ls180.v:8265.2-8267.5" switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8116.6-8116.33" + attribute \src "ls180.v:8265.6-8265.33" case 1'1 assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data case end - attribute \src "ls180.v:8120.2-8122.5" + attribute \src "ls180.v:8269.2-8271.5" switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8120.6-8120.53" + attribute \src "ls180.v:8269.6-8269.53" case 1'1 assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value case end - attribute \src "ls180.v:8124.2-8131.5" + attribute \src "ls180.v:8273.2-8280.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8124.6-8124.29" + attribute \src "ls180.v:8273.6-8273.29" case 1'1 assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8126.6-8126.10" + attribute \src "ls180.v:8275.6-8275.10" case - attribute \src "ls180.v:8127.3-8130.6" + attribute \src "ls180.v:8276.3-8279.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8127.7-8127.30" + attribute \src "ls180.v:8276.7-8276.30" case 1'1 assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 assign $0\spimaster_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8133.2-8143.5" + attribute \src "ls180.v:8282.2-8292.5" switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8133.6-8133.31" + attribute \src "ls180.v:8282.6-8282.31" case 1'1 assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8136.6-8136.10" + attribute \src "ls180.v:8285.6-8285.10" case - attribute \src "ls180.v:8137.3-8142.6" + attribute \src "ls180.v:8286.3-8291.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8137.7-8137.30" + attribute \src "ls180.v:8286.7-8286.30" case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8141$2582_Y - attribute \src "ls180.v:8138.4-8140.7" + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8290$2724_Y + attribute \src "ls180.v:8287.4-8289.7" switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8138.8-8138.32" + attribute \src "ls180.v:8287.8-8287.32" case 1'1 assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 case @@ -276764,169 +279772,169 @@ module \ls180 case end end - attribute \src "ls180.v:8144.2-8150.5" + attribute \src "ls180.v:8293.2-8299.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8144.6-8144.29" + attribute \src "ls180.v:8293.6-8293.29" case 1'1 - attribute \src "ls180.v:8145.3-8149.6" + attribute \src "ls180.v:8294.3-8298.6" switch \main_spisdcard_loopback - attribute \src "ls180.v:8145.7-8145.30" + attribute \src "ls180.v:8294.7-8294.30" case 1'1 assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8147.7-8147.11" + attribute \src "ls180.v:8296.7-8296.11" case assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } end case end - attribute \src "ls180.v:8151.2-8153.5" + attribute \src "ls180.v:8300.2-8302.5" switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8151.6-8151.31" + attribute \src "ls180.v:8300.6-8300.31" case 1'1 assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data case end - attribute \src "ls180.v:8155.2-8157.5" + attribute \src "ls180.v:8304.2-8306.5" switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8155.6-8155.51" + attribute \src "ls180.v:8304.6-8304.51" case 1'1 assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value case end - attribute \src "ls180.v:8158.2-8171.5" + attribute \src "ls180.v:8307.2-8320.5" switch \main_pwm0_enable - attribute \src "ls180.v:8158.6-8158.22" + attribute \src "ls180.v:8307.6-8307.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8159$2583_Y - attribute \src "ls180.v:8160.3-8164.6" - switch $lt$ls180.v:8160$2584_Y - attribute \src "ls180.v:8160.7-8160.44" + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8308$2725_Y + attribute \src "ls180.v:8309.3-8313.6" + switch $lt$ls180.v:8309$2726_Y + attribute \src "ls180.v:8309.7-8309.44" case 1'1 assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8162.7-8162.11" + attribute \src "ls180.v:8311.7-8311.11" case assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8165.3-8167.6" - switch $ge$ls180.v:8165$2586_Y - attribute \src "ls180.v:8165.7-8165.55" + attribute \src "ls180.v:8314.3-8316.6" + switch $ge$ls180.v:8314$2728_Y + attribute \src "ls180.v:8314.7-8314.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 case end - attribute \src "ls180.v:8168.6-8168.10" + attribute \src "ls180.v:8317.6-8317.10" case assign $0\main_pwm0_counter[31:0] 0 assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8172.2-8185.5" + attribute \src "ls180.v:8321.2-8334.5" switch \main_pwm1_enable - attribute \src "ls180.v:8172.6-8172.22" + attribute \src "ls180.v:8321.6-8321.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8173$2587_Y - attribute \src "ls180.v:8174.3-8178.6" - switch $lt$ls180.v:8174$2588_Y - attribute \src "ls180.v:8174.7-8174.44" + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8322$2729_Y + attribute \src "ls180.v:8323.3-8327.6" + switch $lt$ls180.v:8323$2730_Y + attribute \src "ls180.v:8323.7-8323.44" case 1'1 assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8176.7-8176.11" + attribute \src "ls180.v:8325.7-8325.11" case assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8179.3-8181.6" - switch $ge$ls180.v:8179$2590_Y - attribute \src "ls180.v:8179.7-8179.55" + attribute \src "ls180.v:8328.3-8330.6" + switch $ge$ls180.v:8328$2732_Y + attribute \src "ls180.v:8328.7-8328.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 case end - attribute \src "ls180.v:8182.6-8182.10" + attribute \src "ls180.v:8331.6-8331.10" case assign $0\main_pwm1_counter[31:0] 0 assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8186.2-8188.5" - switch $not$ls180.v:8186$2591_Y - attribute \src "ls180.v:8186.6-8186.32" + attribute \src "ls180.v:8335.2-8337.5" + switch $not$ls180.v:8335$2733_Y + attribute \src "ls180.v:8335.6-8335.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8187$2592_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8336$2734_Y case end - attribute \src "ls180.v:8192.2-8194.5" + attribute \src "ls180.v:8341.2-8343.5" switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8192.6-8192.57" + attribute \src "ls180.v:8341.6-8341.57" case 1'1 assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value case end - attribute \src "ls180.v:8196.2-8198.5" + attribute \src "ls180.v:8345.2-8347.5" switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8196.6-8196.57" + attribute \src "ls180.v:8345.6-8345.57" case 1'1 assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value case end - attribute \src "ls180.v:8199.2-8201.5" + attribute \src "ls180.v:8348.2-8350.5" switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8199.6-8199.40" + attribute \src "ls180.v:8348.6-8348.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8200$2593_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8349$2735_Y case end - attribute \src "ls180.v:8202.2-8204.5" + attribute \src "ls180.v:8351.2-8353.5" switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8202.6-8202.49" + attribute \src "ls180.v:8351.6-8351.49" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8205.2-8212.5" + attribute \src "ls180.v:8354.2-8361.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8205.6-8205.46" + attribute \src "ls180.v:8354.6-8354.46" case 1'1 - attribute \src "ls180.v:8206.3-8211.6" - switch $or$ls180.v:8206$2595_Y - attribute \src "ls180.v:8206.7-8206.98" + attribute \src "ls180.v:8355.3-8360.6" + switch $or$ls180.v:8355$2737_Y + attribute \src "ls180.v:8355.7-8355.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8209.7-8209.11" + attribute \src "ls180.v:8358.7-8358.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8210$2596_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8359$2738_Y end case end - attribute \src "ls180.v:8213.2-8226.5" - switch $and$ls180.v:8213$2597_Y - attribute \src "ls180.v:8213.6-8213.97" + attribute \src "ls180.v:8362.2-8375.5" + switch $and$ls180.v:8362$2739_Y + attribute \src "ls180.v:8362.6-8362.97" case 1'1 - attribute \src "ls180.v:8214.3-8220.6" - switch $and$ls180.v:8214$2598_Y - attribute \src "ls180.v:8214.7-8214.94" + attribute \src "ls180.v:8363.3-8369.6" + switch $and$ls180.v:8363$2740_Y + attribute \src "ls180.v:8363.7-8363.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8217.7-8217.11" + attribute \src "ls180.v:8366.7-8366.11" case assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8221.6-8221.10" + attribute \src "ls180.v:8370.6-8370.10" case - attribute \src "ls180.v:8222.3-8225.6" - switch $and$ls180.v:8222$2599_Y - attribute \src "ls180.v:8222.7-8222.94" + attribute \src "ls180.v:8371.3-8374.6" + switch $and$ls180.v:8371$2741_Y + attribute \src "ls180.v:8371.7-8371.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8223$2600_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8224$2601_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8372$2742_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8373$2743_Y case end end - attribute \src "ls180.v:8227.2-8254.5" + attribute \src "ls180.v:8376.2-8403.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8227.6-8227.46" + attribute \src "ls180.v:8376.6-8376.46" case 1'1 - attribute \src "ls180.v:8228.3-8253.10" + attribute \src "ls180.v:8377.3-8402.10" switch \main_sdphy_cmdr_cmdr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -276956,16 +279964,16 @@ module \ls180 end case end - attribute \src "ls180.v:8255.2-8257.5" + attribute \src "ls180.v:8404.2-8406.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8255.6-8255.46" + attribute \src "ls180.v:8404.6-8404.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8256$2602_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8405$2744_Y case end - attribute \src "ls180.v:8258.2-8263.5" - switch $or$ls180.v:8258$2604_Y - attribute \src "ls180.v:8258.6-8258.88" + attribute \src "ls180.v:8407.2-8412.5" + switch $or$ls180.v:8407$2746_Y + attribute \src "ls180.v:8407.6-8407.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first @@ -276973,9 +279981,9 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data case end - attribute \src "ls180.v:8264.2-8269.5" + attribute \src "ls180.v:8413.2-8418.5" switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8264.6-8264.32" + attribute \src "ls180.v:8413.6-8413.32" case 1'1 assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 @@ -276983,88 +279991,88 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8271.2-8273.5" + attribute \src "ls180.v:8420.2-8422.5" switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8271.6-8271.58" + attribute \src "ls180.v:8420.6-8420.58" case 1'1 assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 case end - attribute \src "ls180.v:8274.2-8276.5" + attribute \src "ls180.v:8423.2-8425.5" switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8274.6-8274.60" + attribute \src "ls180.v:8423.6-8423.60" case 1'1 assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 case end - attribute \src "ls180.v:8277.2-8279.5" + attribute \src "ls180.v:8426.2-8428.5" switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8277.6-8277.63" + attribute \src "ls180.v:8426.6-8426.63" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 case end - attribute \src "ls180.v:8280.2-8282.5" + attribute \src "ls180.v:8429.2-8431.5" switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8280.6-8280.41" + attribute \src "ls180.v:8429.6-8429.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8281$2605_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8430$2747_Y case end - attribute \src "ls180.v:8283.2-8285.5" + attribute \src "ls180.v:8432.2-8434.5" switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8283.6-8283.50" + attribute \src "ls180.v:8432.6-8432.50" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8286.2-8293.5" + attribute \src "ls180.v:8435.2-8442.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8286.6-8286.47" + attribute \src "ls180.v:8435.6-8435.47" case 1'1 - attribute \src "ls180.v:8287.3-8292.6" - switch $or$ls180.v:8287$2607_Y - attribute \src "ls180.v:8287.7-8287.100" + attribute \src "ls180.v:8436.3-8441.6" + switch $or$ls180.v:8436$2749_Y + attribute \src "ls180.v:8436.7-8436.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8290.7-8290.11" + attribute \src "ls180.v:8439.7-8439.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8291$2608_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8440$2750_Y end case end - attribute \src "ls180.v:8294.2-8307.5" - switch $and$ls180.v:8294$2609_Y - attribute \src "ls180.v:8294.6-8294.99" + attribute \src "ls180.v:8443.2-8456.5" + switch $and$ls180.v:8443$2751_Y + attribute \src "ls180.v:8443.6-8443.99" case 1'1 - attribute \src "ls180.v:8295.3-8301.6" - switch $and$ls180.v:8295$2610_Y - attribute \src "ls180.v:8295.7-8295.96" + attribute \src "ls180.v:8444.3-8450.6" + switch $and$ls180.v:8444$2752_Y + attribute \src "ls180.v:8444.7-8444.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8298.7-8298.11" + attribute \src "ls180.v:8447.7-8447.11" case assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8302.6-8302.10" + attribute \src "ls180.v:8451.6-8451.10" case - attribute \src "ls180.v:8303.3-8306.6" - switch $and$ls180.v:8303$2611_Y - attribute \src "ls180.v:8303.7-8303.96" + attribute \src "ls180.v:8452.3-8455.6" + switch $and$ls180.v:8452$2753_Y + attribute \src "ls180.v:8452.7-8452.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8304$2612_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8305$2613_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8453$2754_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8454$2755_Y case end end - attribute \src "ls180.v:8308.2-8335.5" + attribute \src "ls180.v:8457.2-8484.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8308.6-8308.47" + attribute \src "ls180.v:8457.6-8457.47" case 1'1 - attribute \src "ls180.v:8309.3-8334.10" + attribute \src "ls180.v:8458.3-8483.10" switch \main_sdphy_dataw_crcr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -277094,16 +280102,16 @@ module \ls180 end case end - attribute \src "ls180.v:8336.2-8338.5" + attribute \src "ls180.v:8485.2-8487.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8336.6-8336.47" + attribute \src "ls180.v:8485.6-8485.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8337$2614_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8486$2756_Y case end - attribute \src "ls180.v:8339.2-8344.5" - switch $or$ls180.v:8339$2616_Y - attribute \src "ls180.v:8339.6-8339.90" + attribute \src "ls180.v:8488.2-8493.5" + switch $or$ls180.v:8488$2758_Y + attribute \src "ls180.v:8488.6-8488.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first @@ -277111,9 +280119,9 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data case end - attribute \src "ls180.v:8345.2-8350.5" + attribute \src "ls180.v:8494.2-8499.5" switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8345.6-8345.33" + attribute \src "ls180.v:8494.6-8494.33" case 1'1 assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 @@ -277121,81 +280129,81 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8352.2-8354.5" + attribute \src "ls180.v:8501.2-8503.5" switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8352.6-8352.63" + attribute \src "ls180.v:8501.6-8501.63" case 1'1 assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value case end - attribute \src "ls180.v:8356.2-8358.5" + attribute \src "ls180.v:8505.2-8507.5" switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8356.6-8356.52" + attribute \src "ls180.v:8505.6-8505.52" case 1'1 assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value case end - attribute \src "ls180.v:8359.2-8361.5" + attribute \src "ls180.v:8508.2-8510.5" switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8359.6-8359.42" + attribute \src "ls180.v:8508.6-8508.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8360$2617_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8509$2759_Y case end - attribute \src "ls180.v:8362.2-8364.5" + attribute \src "ls180.v:8511.2-8513.5" switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8362.6-8362.51" + attribute \src "ls180.v:8511.6-8511.51" case 1'1 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8365.2-8372.5" + attribute \src "ls180.v:8514.2-8521.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8365.6-8365.48" + attribute \src "ls180.v:8514.6-8514.48" case 1'1 - attribute \src "ls180.v:8366.3-8371.6" - switch $or$ls180.v:8366$2619_Y - attribute \src "ls180.v:8366.7-8366.102" + attribute \src "ls180.v:8515.3-8520.6" + switch $or$ls180.v:8515$2761_Y + attribute \src "ls180.v:8515.7-8515.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8369.7-8369.11" + attribute \src "ls180.v:8518.7-8518.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8370$2620_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8519$2762_Y end case end - attribute \src "ls180.v:8373.2-8386.5" - switch $and$ls180.v:8373$2621_Y - attribute \src "ls180.v:8373.6-8373.101" + attribute \src "ls180.v:8522.2-8535.5" + switch $and$ls180.v:8522$2763_Y + attribute \src "ls180.v:8522.6-8522.101" case 1'1 - attribute \src "ls180.v:8374.3-8380.6" - switch $and$ls180.v:8374$2622_Y - attribute \src "ls180.v:8374.7-8374.98" + attribute \src "ls180.v:8523.3-8529.6" + switch $and$ls180.v:8523$2764_Y + attribute \src "ls180.v:8523.7-8523.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8377.7-8377.11" + attribute \src "ls180.v:8526.7-8526.11" case assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8381.6-8381.10" + attribute \src "ls180.v:8530.6-8530.10" case - attribute \src "ls180.v:8382.3-8385.6" - switch $and$ls180.v:8382$2623_Y - attribute \src "ls180.v:8382.7-8382.98" + attribute \src "ls180.v:8531.3-8534.6" + switch $and$ls180.v:8531$2765_Y + attribute \src "ls180.v:8531.7-8531.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8383$2624_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8384$2625_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8532$2766_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8533$2767_Y case end end - attribute \src "ls180.v:8387.2-8396.5" + attribute \src "ls180.v:8536.2-8545.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8387.6-8387.48" + attribute \src "ls180.v:8536.6-8536.48" case 1'1 - attribute \src "ls180.v:8388.3-8395.10" + attribute \src "ls180.v:8537.3-8544.10" switch \main_sdphy_datar_datar_converter_demux attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -277207,16 +280215,16 @@ module \ls180 end case end - attribute \src "ls180.v:8397.2-8399.5" + attribute \src "ls180.v:8546.2-8548.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8397.6-8397.48" + attribute \src "ls180.v:8546.6-8546.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8398$2626_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8547$2768_Y case end - attribute \src "ls180.v:8400.2-8405.5" - switch $or$ls180.v:8400$2628_Y - attribute \src "ls180.v:8400.6-8400.92" + attribute \src "ls180.v:8549.2-8554.5" + switch $or$ls180.v:8549$2770_Y + attribute \src "ls180.v:8549.6-8549.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first @@ -277224,9 +280232,9 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data case end - attribute \src "ls180.v:8406.2-8411.5" + attribute \src "ls180.v:8555.2-8560.5" switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8406.6-8406.34" + attribute \src "ls180.v:8555.6-8555.34" case 1'1 assign $0\main_sdphy_datar_datar_run[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 @@ -277234,598 +280242,610 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8413.2-8415.5" + attribute \src "ls180.v:8562.2-8564.5" switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8413.6-8413.60" + attribute \src "ls180.v:8562.6-8562.60" case 1'1 assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 case end - attribute \src "ls180.v:8416.2-8418.5" + attribute \src "ls180.v:8565.2-8567.5" switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8416.6-8416.62" + attribute \src "ls180.v:8565.6-8565.62" case 1'1 assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 case end - attribute \src "ls180.v:8419.2-8421.5" + attribute \src "ls180.v:8568.2-8570.5" switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8419.6-8419.66" + attribute \src "ls180.v:8568.6-8568.66" case 1'1 assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 case end - attribute \src "ls180.v:8422.2-8428.5" + attribute \src "ls180.v:8571.2-8577.5" switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8422.6-8422.35" + attribute \src "ls180.v:8571.6-8571.35" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8424.6-8424.10" + attribute \src "ls180.v:8573.6-8573.10" case - attribute \src "ls180.v:8425.3-8427.6" + attribute \src "ls180.v:8574.3-8576.6" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8425.7-8425.39" + attribute \src "ls180.v:8574.7-8574.39" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 case end end - attribute \src "ls180.v:8429.2-8435.5" + attribute \src "ls180.v:8578.2-8584.5" switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8429.6-8429.41" + attribute \src "ls180.v:8578.6-8578.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8431.6-8431.10" + attribute \src "ls180.v:8580.6-8580.10" case - attribute \src "ls180.v:8432.3-8434.6" + attribute \src "ls180.v:8581.3-8583.6" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8432.7-8432.45" + attribute \src "ls180.v:8581.7-8581.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 case end end - attribute \src "ls180.v:8436.2-8442.5" + attribute \src "ls180.v:8585.2-8591.5" switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8436.6-8436.41" + attribute \src "ls180.v:8585.6-8585.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8438.6-8438.10" + attribute \src "ls180.v:8587.6-8587.10" case - attribute \src "ls180.v:8439.3-8441.6" + attribute \src "ls180.v:8588.3-8590.6" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8439.7-8439.45" + attribute \src "ls180.v:8588.7-8588.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 case end end - attribute \src "ls180.v:8443.2-8449.5" + attribute \src "ls180.v:8592.2-8598.5" switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8443.6-8443.41" + attribute \src "ls180.v:8592.6-8592.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8445.6-8445.10" + attribute \src "ls180.v:8594.6-8594.10" case - attribute \src "ls180.v:8446.3-8448.6" + attribute \src "ls180.v:8595.3-8597.6" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8446.7-8446.45" + attribute \src "ls180.v:8595.7-8595.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 case end end - attribute \src "ls180.v:8450.2-8456.5" + attribute \src "ls180.v:8599.2-8605.5" switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8450.6-8450.41" + attribute \src "ls180.v:8599.6-8599.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8452.6-8452.10" + attribute \src "ls180.v:8601.6-8601.10" case - attribute \src "ls180.v:8453.3-8455.6" + attribute \src "ls180.v:8602.3-8604.6" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8453.7-8453.45" + attribute \src "ls180.v:8602.7-8602.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 case end end - attribute \src "ls180.v:8458.2-8460.5" + attribute \src "ls180.v:8607.2-8609.5" switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8458.6-8458.82" + attribute \src "ls180.v:8607.6-8607.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 case end - attribute \src "ls180.v:8461.2-8463.5" + attribute \src "ls180.v:8610.2-8612.5" switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8461.6-8461.82" + attribute \src "ls180.v:8610.6-8610.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 case end - attribute \src "ls180.v:8464.2-8466.5" + attribute \src "ls180.v:8613.2-8615.5" switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8464.6-8464.82" + attribute \src "ls180.v:8613.6-8613.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 case end - attribute \src "ls180.v:8467.2-8469.5" + attribute \src "ls180.v:8616.2-8618.5" switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8467.6-8467.82" + attribute \src "ls180.v:8616.6-8616.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 case end - attribute \src "ls180.v:8470.2-8472.5" + attribute \src "ls180.v:8619.2-8621.5" switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8470.6-8470.78" + attribute \src "ls180.v:8619.6-8619.78" case 1'1 assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 case end - attribute \src "ls180.v:8473.2-8475.5" - switch $and$ls180.v:8473$2629_Y - attribute \src "ls180.v:8473.6-8473.83" + attribute \src "ls180.v:8622.2-8624.5" + switch $and$ls180.v:8622$2771_Y + attribute \src "ls180.v:8622.6-8622.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end - attribute \src "ls180.v:8476.2-8478.5" - switch $and$ls180.v:8476$2630_Y - attribute \src "ls180.v:8476.6-8476.83" + attribute \src "ls180.v:8625.2-8627.5" + switch $and$ls180.v:8625$2772_Y + attribute \src "ls180.v:8625.6-8625.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end - attribute \src "ls180.v:8479.2-8481.5" - switch $and$ls180.v:8479$2631_Y - attribute \src "ls180.v:8479.6-8479.83" + attribute \src "ls180.v:8628.2-8630.5" + switch $and$ls180.v:8628$2773_Y + attribute \src "ls180.v:8628.6-8628.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end - attribute \src "ls180.v:8482.2-8484.5" - switch $and$ls180.v:8482$2632_Y - attribute \src "ls180.v:8482.6-8482.83" + attribute \src "ls180.v:8631.2-8633.5" + switch $and$ls180.v:8631$2774_Y + attribute \src "ls180.v:8631.6-8631.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc case end - attribute \src "ls180.v:8485.2-8489.5" - switch $and$ls180.v:8485$2633_Y - attribute \src "ls180.v:8485.6-8485.83" + attribute \src "ls180.v:8634.2-8638.5" + switch $and$ls180.v:8634$2775_Y + attribute \src "ls180.v:8634.6-8634.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] case end - attribute \src "ls180.v:8490.2-8494.5" - switch $and$ls180.v:8490$2634_Y - attribute \src "ls180.v:8490.6-8490.83" + attribute \src "ls180.v:8639.2-8643.5" + switch $and$ls180.v:8639$2776_Y + attribute \src "ls180.v:8639.6-8639.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] case end - attribute \src "ls180.v:8495.2-8499.5" - switch $and$ls180.v:8495$2635_Y - attribute \src "ls180.v:8495.6-8495.83" + attribute \src "ls180.v:8644.2-8648.5" + switch $and$ls180.v:8644$2777_Y + attribute \src "ls180.v:8644.6-8644.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] case end - attribute \src "ls180.v:8500.2-8504.5" - switch $and$ls180.v:8500$2636_Y - attribute \src "ls180.v:8500.6-8500.83" + attribute \src "ls180.v:8649.2-8653.5" + switch $and$ls180.v:8649$2778_Y + attribute \src "ls180.v:8649.6-8649.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] case end - attribute \src "ls180.v:8505.2-8513.5" - switch $and$ls180.v:8505$2637_Y - attribute \src "ls180.v:8505.6-8505.83" + attribute \src "ls180.v:8654.2-8662.5" + switch $and$ls180.v:8654$2779_Y + attribute \src "ls180.v:8654.6-8654.83" case 1'1 - attribute \src "ls180.v:8506.3-8512.6" + attribute \src "ls180.v:8655.3-8661.6" switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8506.7-8506.42" + attribute \src "ls180.v:8655.7-8655.42" case 1'1 assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8508.7-8508.11" + attribute \src "ls180.v:8657.7-8657.11" case - attribute \src "ls180.v:8509.4-8511.7" - switch $ne$ls180.v:8509$2638_Y - attribute \src "ls180.v:8509.8-8509.48" + attribute \src "ls180.v:8658.4-8660.7" + switch $ne$ls180.v:8658$2780_Y + attribute \src "ls180.v:8658.8-8658.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8510$2639_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8659$2781_Y case end end case end - attribute \src "ls180.v:8514.2-8520.5" + attribute \src "ls180.v:8663.2-8669.5" switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8514.6-8514.40" + attribute \src "ls180.v:8663.6-8663.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8516.6-8516.10" + attribute \src "ls180.v:8665.6-8665.10" case - attribute \src "ls180.v:8517.3-8519.6" + attribute \src "ls180.v:8666.3-8668.6" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8517.7-8517.44" + attribute \src "ls180.v:8666.7-8666.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 case end end - attribute \src "ls180.v:8521.2-8527.5" + attribute \src "ls180.v:8670.2-8676.5" switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8521.6-8521.40" + attribute \src "ls180.v:8670.6-8670.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8523.6-8523.10" + attribute \src "ls180.v:8672.6-8672.10" case - attribute \src "ls180.v:8524.3-8526.6" + attribute \src "ls180.v:8673.3-8675.6" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8524.7-8524.44" + attribute \src "ls180.v:8673.7-8673.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 case end end - attribute \src "ls180.v:8528.2-8534.5" + attribute \src "ls180.v:8677.2-8683.5" switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8528.6-8528.40" + attribute \src "ls180.v:8677.6-8677.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8530.6-8530.10" + attribute \src "ls180.v:8679.6-8679.10" case - attribute \src "ls180.v:8531.3-8533.6" + attribute \src "ls180.v:8680.3-8682.6" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8531.7-8531.44" + attribute \src "ls180.v:8680.7-8680.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 case end end - attribute \src "ls180.v:8535.2-8541.5" + attribute \src "ls180.v:8684.2-8690.5" switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8535.6-8535.40" + attribute \src "ls180.v:8684.6-8684.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8537.6-8537.10" + attribute \src "ls180.v:8686.6-8686.10" case - attribute \src "ls180.v:8538.3-8540.6" + attribute \src "ls180.v:8687.3-8689.6" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8538.7-8538.44" + attribute \src "ls180.v:8687.7-8687.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 case end end - attribute \src "ls180.v:8543.2-8545.5" + attribute \src "ls180.v:8692.2-8694.5" switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8543.6-8543.52" + attribute \src "ls180.v:8692.6-8692.52" case 1'1 assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 case end - attribute \src "ls180.v:8546.2-8548.5" + attribute \src "ls180.v:8695.2-8697.5" switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8546.6-8546.53" + attribute \src "ls180.v:8695.6-8695.53" case 1'1 assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 case end - attribute \src "ls180.v:8549.2-8551.5" + attribute \src "ls180.v:8698.2-8700.5" switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8549.6-8549.53" + attribute \src "ls180.v:8698.6-8698.53" case 1'1 assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 case end - attribute \src "ls180.v:8552.2-8554.5" + attribute \src "ls180.v:8701.2-8703.5" switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8552.6-8552.54" + attribute \src "ls180.v:8701.6-8701.54" case 1'1 assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 case end - attribute \src "ls180.v:8555.2-8557.5" + attribute \src "ls180.v:8704.2-8706.5" switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8555.6-8555.53" + attribute \src "ls180.v:8704.6-8704.53" case 1'1 assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 case end - attribute \src "ls180.v:8558.2-8560.5" + attribute \src "ls180.v:8707.2-8709.5" switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8558.6-8558.55" + attribute \src "ls180.v:8707.6-8707.55" case 1'1 assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 case end - attribute \src "ls180.v:8561.2-8563.5" + attribute \src "ls180.v:8710.2-8712.5" switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8561.6-8561.54" + attribute \src "ls180.v:8710.6-8710.54" case 1'1 assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 case end - attribute \src "ls180.v:8564.2-8566.5" + attribute \src "ls180.v:8713.2-8715.5" switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8564.6-8564.56" + attribute \src "ls180.v:8713.6-8713.56" case 1'1 assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 case end - attribute \src "ls180.v:8567.2-8569.5" + attribute \src "ls180.v:8716.2-8718.5" switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8567.6-8567.63" + attribute \src "ls180.v:8716.6-8716.63" case 1'1 assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 case end - attribute \src "ls180.v:8570.2-8572.5" - switch $and$ls180.v:8570$2642_Y - attribute \src "ls180.v:8570.6-8570.120" + attribute \src "ls180.v:8719.2-8721.5" + switch $and$ls180.v:8719$2784_Y + attribute \src "ls180.v:8719.6-8719.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8571$2643_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8720$2785_Y case end - attribute \src "ls180.v:8573.2-8575.5" + attribute \src "ls180.v:8722.2-8724.5" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8573.6-8573.35" + attribute \src "ls180.v:8722.6-8722.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8574$2644_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8723$2786_Y case end - attribute \src "ls180.v:8576.2-8584.5" - switch $and$ls180.v:8576$2647_Y - attribute \src "ls180.v:8576.6-8576.120" + attribute \src "ls180.v:8725.2-8733.5" + switch $and$ls180.v:8725$2789_Y + attribute \src "ls180.v:8725.6-8725.120" case 1'1 - attribute \src "ls180.v:8577.3-8579.6" - switch $not$ls180.v:8577$2648_Y - attribute \src "ls180.v:8577.7-8577.39" + attribute \src "ls180.v:8726.3-8728.6" + switch $not$ls180.v:8726$2790_Y + attribute \src "ls180.v:8726.7-8726.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8578$2649_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8727$2791_Y case end - attribute \src "ls180.v:8580.6-8580.10" + attribute \src "ls180.v:8729.6-8729.10" case - attribute \src "ls180.v:8581.3-8583.6" + attribute \src "ls180.v:8730.3-8732.6" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8581.7-8581.36" + attribute \src "ls180.v:8730.7-8730.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8582$2650_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8731$2792_Y case end end - attribute \src "ls180.v:8585.2-8587.5" + attribute \src "ls180.v:8734.2-8736.5" switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8585.6-8585.45" + attribute \src "ls180.v:8734.6-8734.45" case 1'1 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8588.2-8595.5" + attribute \src "ls180.v:8737.2-8744.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8588.6-8588.42" + attribute \src "ls180.v:8737.6-8737.42" case 1'1 - attribute \src "ls180.v:8589.3-8594.6" - switch $or$ls180.v:8589$2652_Y - attribute \src "ls180.v:8589.7-8589.90" + attribute \src "ls180.v:8738.3-8743.6" + switch $or$ls180.v:8738$2794_Y + attribute \src "ls180.v:8738.7-8738.90" case 1'1 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8592.7-8592.11" + attribute \src "ls180.v:8741.7-8741.11" case - assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8593$2653_Y + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8742$2795_Y end case end - attribute \src "ls180.v:8596.2-8609.5" - switch $and$ls180.v:8596$2654_Y - attribute \src "ls180.v:8596.6-8596.89" + attribute \src "ls180.v:8745.2-8758.5" + switch $and$ls180.v:8745$2796_Y + attribute \src "ls180.v:8745.6-8745.89" case 1'1 - attribute \src "ls180.v:8597.3-8603.6" - switch $and$ls180.v:8597$2655_Y - attribute \src "ls180.v:8597.7-8597.86" + attribute \src "ls180.v:8746.3-8752.6" + switch $and$ls180.v:8746$2797_Y + attribute \src "ls180.v:8746.7-8746.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8600.7-8600.11" + attribute \src "ls180.v:8749.7-8749.11" case assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8604.6-8604.10" + attribute \src "ls180.v:8753.6-8753.10" case - attribute \src "ls180.v:8605.3-8608.6" - switch $and$ls180.v:8605$2656_Y - attribute \src "ls180.v:8605.7-8605.86" + attribute \src "ls180.v:8754.3-8757.6" + switch $and$ls180.v:8754$2798_Y + attribute \src "ls180.v:8754.7-8754.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8606$2657_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8607$2658_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8755$2799_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8756$2800_Y case end end - attribute \src "ls180.v:8610.2-8625.5" + attribute \src "ls180.v:8759.2-8786.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8610.6-8610.42" + attribute \src "ls180.v:8759.6-8759.42" case 1'1 - attribute \src "ls180.v:8611.3-8624.10" + attribute \src "ls180.v:8760.3-8785.10" switch \main_sdblock2mem_converter_demux attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + case 3'000 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + case 3'001 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + case 3'010 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case 3'011 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data case end case end - attribute \src "ls180.v:8626.2-8628.5" + attribute \src "ls180.v:8787.2-8789.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8626.6-8626.42" + attribute \src "ls180.v:8787.6-8787.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8627$2659_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8788$2801_Y case end - attribute \src "ls180.v:8630.2-8632.5" + attribute \src "ls180.v:8791.2-8793.5" switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8630.6-8630.76" + attribute \src "ls180.v:8791.6-8791.76" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value case end - attribute \src "ls180.v:8633.2-8636.5" + attribute \src "ls180.v:8794.2-8797.5" switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8633.6-8633.46" + attribute \src "ls180.v:8794.6-8794.46" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 assign $0\builder_sdblock2memdma_state[1:0] 2'00 case end - attribute \src "ls180.v:8638.2-8640.5" + attribute \src "ls180.v:8799.2-8801.5" switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8638.6-8638.64" + attribute \src "ls180.v:8799.6-8799.64" case 1'1 - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value case end - attribute \src "ls180.v:8642.2-8644.5" + attribute \src "ls180.v:8803.2-8805.5" switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8642.6-8642.76" + attribute \src "ls180.v:8803.6-8803.76" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value case end - attribute \src "ls180.v:8645.2-8648.5" + attribute \src "ls180.v:8806.2-8809.5" switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8645.6-8645.32" + attribute \src "ls180.v:8806.6-8806.32" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 case end - attribute \src "ls180.v:8649.2-8655.5" - switch $and$ls180.v:8649$2660_Y - attribute \src "ls180.v:8649.6-8649.89" + attribute \src "ls180.v:8810.2-8816.5" + switch $and$ls180.v:8810$2802_Y + attribute \src "ls180.v:8810.6-8810.89" case 1'1 - attribute \src "ls180.v:8650.3-8654.6" + attribute \src "ls180.v:8811.3-8815.6" switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8650.7-8650.38" + attribute \src "ls180.v:8811.7-8811.38" case 1'1 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - attribute \src "ls180.v:8652.7-8652.11" + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + attribute \src "ls180.v:8813.7-8813.11" case - assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8653$2661_Y + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8814$2803_Y end case end - attribute \src "ls180.v:8656.2-8658.5" - switch $and$ls180.v:8656$2664_Y - attribute \src "ls180.v:8656.6-8656.120" + attribute \src "ls180.v:8817.2-8819.5" + switch $and$ls180.v:8817$2806_Y + attribute \src "ls180.v:8817.6-8817.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8657$2665_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8818$2807_Y case end - attribute \src "ls180.v:8659.2-8661.5" + attribute \src "ls180.v:8820.2-8822.5" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8659.6-8659.35" + attribute \src "ls180.v:8820.6-8820.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8660$2666_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8821$2808_Y case end - attribute \src "ls180.v:8662.2-8670.5" - switch $and$ls180.v:8662$2669_Y - attribute \src "ls180.v:8662.6-8662.120" + attribute \src "ls180.v:8823.2-8831.5" + switch $and$ls180.v:8823$2811_Y + attribute \src "ls180.v:8823.6-8823.120" case 1'1 - attribute \src "ls180.v:8663.3-8665.6" - switch $not$ls180.v:8663$2670_Y - attribute \src "ls180.v:8663.7-8663.39" + attribute \src "ls180.v:8824.3-8826.6" + switch $not$ls180.v:8824$2812_Y + attribute \src "ls180.v:8824.7-8824.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8664$2671_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8825$2813_Y case end - attribute \src "ls180.v:8666.6-8666.10" + attribute \src "ls180.v:8827.6-8827.10" case - attribute \src "ls180.v:8667.3-8669.6" + attribute \src "ls180.v:8828.3-8830.6" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8667.7-8667.36" + attribute \src "ls180.v:8828.7-8828.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8668$2672_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8829$2814_Y case end end - attribute \src "ls180.v:8672.2-8674.5" + attribute \src "ls180.v:8833.2-8835.5" switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8672.6-8672.46" + attribute \src "ls180.v:8833.6-8833.46" case 1'1 assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 case end - attribute \src "ls180.v:8675.2-8677.5" + attribute \src "ls180.v:8836.2-8838.5" switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8675.6-8675.44" + attribute \src "ls180.v:8836.6-8836.44" case 1'1 assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 case end - attribute \src "ls180.v:8678.2-8680.5" + attribute \src "ls180.v:8839.2-8841.5" switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8678.6-8678.43" + attribute \src "ls180.v:8839.6-8839.43" case 1'1 assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 case end - attribute \src "ls180.v:8681.2-8777.9" + attribute \src "ls180.v:8842.2-8938.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - attribute \src "ls180.v:8683.4-8699.7" - switch $not$ls180.v:8683$2673_Y - attribute \src "ls180.v:8683.8-8683.29" + attribute \src "ls180.v:8844.4-8860.7" + switch $not$ls180.v:8844$2815_Y + attribute \src "ls180.v:8844.8-8844.29" case 1'1 - attribute \src "ls180.v:8684.5-8698.8" + attribute \src "ls180.v:8845.5-8859.8" switch \builder_request [1] - attribute \src "ls180.v:8684.9-8684.27" + attribute \src "ls180.v:8845.9-8845.27" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8686.9-8686.13" + attribute \src "ls180.v:8847.9-8847.13" case - attribute \src "ls180.v:8687.6-8697.9" + attribute \src "ls180.v:8848.6-8858.9" switch \builder_request [2] - attribute \src "ls180.v:8687.10-8687.28" + attribute \src "ls180.v:8848.10-8848.28" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8689.10-8689.14" + attribute \src "ls180.v:8850.10-8850.14" case - attribute \src "ls180.v:8690.7-8696.10" + attribute \src "ls180.v:8851.7-8857.10" switch \builder_request [3] - attribute \src "ls180.v:8690.11-8690.29" + attribute \src "ls180.v:8851.11-8851.29" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8692.11-8692.15" + attribute \src "ls180.v:8853.11-8853.15" case - attribute \src "ls180.v:8693.8-8695.11" + attribute \src "ls180.v:8854.8-8856.11" switch \builder_request [4] - attribute \src "ls180.v:8693.12-8693.30" + attribute \src "ls180.v:8854.12-8854.30" case 1'1 assign $0\builder_grant[2:0] 3'100 case @@ -277837,34 +280857,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'001 - attribute \src "ls180.v:8702.4-8718.7" - switch $not$ls180.v:8702$2674_Y - attribute \src "ls180.v:8702.8-8702.29" + attribute \src "ls180.v:8863.4-8879.7" + switch $not$ls180.v:8863$2816_Y + attribute \src "ls180.v:8863.8-8863.29" case 1'1 - attribute \src "ls180.v:8703.5-8717.8" + attribute \src "ls180.v:8864.5-8878.8" switch \builder_request [2] - attribute \src "ls180.v:8703.9-8703.27" + attribute \src "ls180.v:8864.9-8864.27" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8705.9-8705.13" + attribute \src "ls180.v:8866.9-8866.13" case - attribute \src "ls180.v:8706.6-8716.9" + attribute \src "ls180.v:8867.6-8877.9" switch \builder_request [3] - attribute \src "ls180.v:8706.10-8706.28" + attribute \src "ls180.v:8867.10-8867.28" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8708.10-8708.14" + attribute \src "ls180.v:8869.10-8869.14" case - attribute \src "ls180.v:8709.7-8715.10" + attribute \src "ls180.v:8870.7-8876.10" switch \builder_request [4] - attribute \src "ls180.v:8709.11-8709.29" + attribute \src "ls180.v:8870.11-8870.29" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8711.11-8711.15" + attribute \src "ls180.v:8872.11-8872.15" case - attribute \src "ls180.v:8712.8-8714.11" + attribute \src "ls180.v:8873.8-8875.11" switch \builder_request [0] - attribute \src "ls180.v:8712.12-8712.30" + attribute \src "ls180.v:8873.12-8873.30" case 1'1 assign $0\builder_grant[2:0] 3'000 case @@ -277876,34 +280896,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'010 - attribute \src "ls180.v:8721.4-8737.7" - switch $not$ls180.v:8721$2675_Y - attribute \src "ls180.v:8721.8-8721.29" + attribute \src "ls180.v:8882.4-8898.7" + switch $not$ls180.v:8882$2817_Y + attribute \src "ls180.v:8882.8-8882.29" case 1'1 - attribute \src "ls180.v:8722.5-8736.8" + attribute \src "ls180.v:8883.5-8897.8" switch \builder_request [3] - attribute \src "ls180.v:8722.9-8722.27" + attribute \src "ls180.v:8883.9-8883.27" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8724.9-8724.13" + attribute \src "ls180.v:8885.9-8885.13" case - attribute \src "ls180.v:8725.6-8735.9" + attribute \src "ls180.v:8886.6-8896.9" switch \builder_request [4] - attribute \src "ls180.v:8725.10-8725.28" + attribute \src "ls180.v:8886.10-8886.28" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8727.10-8727.14" + attribute \src "ls180.v:8888.10-8888.14" case - attribute \src "ls180.v:8728.7-8734.10" + attribute \src "ls180.v:8889.7-8895.10" switch \builder_request [0] - attribute \src "ls180.v:8728.11-8728.29" + attribute \src "ls180.v:8889.11-8889.29" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8730.11-8730.15" + attribute \src "ls180.v:8891.11-8891.15" case - attribute \src "ls180.v:8731.8-8733.11" + attribute \src "ls180.v:8892.8-8894.11" switch \builder_request [1] - attribute \src "ls180.v:8731.12-8731.30" + attribute \src "ls180.v:8892.12-8892.30" case 1'1 assign $0\builder_grant[2:0] 3'001 case @@ -277915,34 +280935,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:8740.4-8756.7" - switch $not$ls180.v:8740$2676_Y - attribute \src "ls180.v:8740.8-8740.29" + attribute \src "ls180.v:8901.4-8917.7" + switch $not$ls180.v:8901$2818_Y + attribute \src "ls180.v:8901.8-8901.29" case 1'1 - attribute \src "ls180.v:8741.5-8755.8" + attribute \src "ls180.v:8902.5-8916.8" switch \builder_request [4] - attribute \src "ls180.v:8741.9-8741.27" + attribute \src "ls180.v:8902.9-8902.27" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8743.9-8743.13" + attribute \src "ls180.v:8904.9-8904.13" case - attribute \src "ls180.v:8744.6-8754.9" + attribute \src "ls180.v:8905.6-8915.9" switch \builder_request [0] - attribute \src "ls180.v:8744.10-8744.28" + attribute \src "ls180.v:8905.10-8905.28" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8746.10-8746.14" + attribute \src "ls180.v:8907.10-8907.14" case - attribute \src "ls180.v:8747.7-8753.10" + attribute \src "ls180.v:8908.7-8914.10" switch \builder_request [1] - attribute \src "ls180.v:8747.11-8747.29" + attribute \src "ls180.v:8908.11-8908.29" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8749.11-8749.15" + attribute \src "ls180.v:8910.11-8910.15" case - attribute \src "ls180.v:8750.8-8752.11" + attribute \src "ls180.v:8911.8-8913.11" switch \builder_request [2] - attribute \src "ls180.v:8750.12-8750.30" + attribute \src "ls180.v:8911.12-8911.30" case 1'1 assign $0\builder_grant[2:0] 3'010 case @@ -277954,34 +280974,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'100 - attribute \src "ls180.v:8759.4-8775.7" - switch $not$ls180.v:8759$2677_Y - attribute \src "ls180.v:8759.8-8759.29" + attribute \src "ls180.v:8920.4-8936.7" + switch $not$ls180.v:8920$2819_Y + attribute \src "ls180.v:8920.8-8920.29" case 1'1 - attribute \src "ls180.v:8760.5-8774.8" + attribute \src "ls180.v:8921.5-8935.8" switch \builder_request [0] - attribute \src "ls180.v:8760.9-8760.27" + attribute \src "ls180.v:8921.9-8921.27" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8762.9-8762.13" + attribute \src "ls180.v:8923.9-8923.13" case - attribute \src "ls180.v:8763.6-8773.9" + attribute \src "ls180.v:8924.6-8934.9" switch \builder_request [1] - attribute \src "ls180.v:8763.10-8763.28" + attribute \src "ls180.v:8924.10-8924.28" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8765.10-8765.14" + attribute \src "ls180.v:8926.10-8926.14" case - attribute \src "ls180.v:8766.7-8772.10" + attribute \src "ls180.v:8927.7-8933.10" switch \builder_request [2] - attribute \src "ls180.v:8766.11-8766.29" + attribute \src "ls180.v:8927.11-8927.29" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8768.11-8768.15" + attribute \src "ls180.v:8929.11-8929.15" case - attribute \src "ls180.v:8769.8-8771.11" + attribute \src "ls180.v:8930.8-8932.11" switch \builder_request [3] - attribute \src "ls180.v:8769.12-8769.30" + attribute \src "ls180.v:8930.12-8930.30" case 1'1 assign $0\builder_grant[2:0] 3'011 case @@ -277993,26 +281013,26 @@ module \ls180 end case end - attribute \src "ls180.v:8779.2-8785.5" + attribute \src "ls180.v:8940.2-8946.5" switch \builder_wait - attribute \src "ls180.v:8779.6-8779.18" + attribute \src "ls180.v:8940.6-8940.18" case 1'1 - attribute \src "ls180.v:8780.3-8782.6" - switch $not$ls180.v:8780$2678_Y - attribute \src "ls180.v:8780.7-8780.22" + attribute \src "ls180.v:8941.3-8943.6" + switch $not$ls180.v:8941$2820_Y + attribute \src "ls180.v:8941.7-8941.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8781$2679_Y + assign $0\builder_count[19:0] $sub$ls180.v:8942$2821_Y case end - attribute \src "ls180.v:8783.6-8783.10" + attribute \src "ls180.v:8944.6-8944.10" case assign $0\builder_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:8787.2-8817.5" + attribute \src "ls180.v:8948.2-8978.5" switch \builder_csrbank0_sel - attribute \src "ls180.v:8787.6-8787.26" + attribute \src "ls180.v:8948.6-8948.26" case 1'1 - attribute \src "ls180.v:8788.3-8816.10" + attribute \src "ls180.v:8949.3-8977.10" switch \builder_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -278045,46 +281065,46 @@ module \ls180 end case end - attribute \src "ls180.v:8818.2-8820.5" + attribute \src "ls180.v:8979.2-8981.5" switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8818.6-8818.32" + attribute \src "ls180.v:8979.6-8979.32" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r case end - attribute \src "ls180.v:8822.2-8824.5" + attribute \src "ls180.v:8983.2-8985.5" switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8822.6-8822.34" + attribute \src "ls180.v:8983.6-8983.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r case end - attribute \src "ls180.v:8825.2-8827.5" + attribute \src "ls180.v:8986.2-8988.5" switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8825.6-8825.34" + attribute \src "ls180.v:8986.6-8986.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r case end - attribute \src "ls180.v:8828.2-8830.5" + attribute \src "ls180.v:8989.2-8991.5" switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8828.6-8828.34" + attribute \src "ls180.v:8989.6-8989.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r case end - attribute \src "ls180.v:8831.2-8833.5" + attribute \src "ls180.v:8992.2-8994.5" switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8831.6-8831.34" + attribute \src "ls180.v:8992.6-8992.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r case end - attribute \src "ls180.v:8836.2-8857.5" + attribute \src "ls180.v:8997.2-9018.5" switch \builder_csrbank1_sel - attribute \src "ls180.v:8836.6-8836.26" + attribute \src "ls180.v:8997.6-8997.26" case 1'1 - attribute \src "ls180.v:8837.3-8856.10" + attribute \src "ls180.v:8998.3-9017.10" switch \builder_interface1_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -278108,39 +281128,39 @@ module \ls180 end case end - attribute \src "ls180.v:8858.2-8860.5" + attribute \src "ls180.v:9019.2-9021.5" switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:8858.6-8858.29" + attribute \src "ls180.v:9019.6-9019.29" case 1'1 assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r case end - attribute \src "ls180.v:8861.2-8863.5" + attribute \src "ls180.v:9022.2-9024.5" switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:8861.6-8861.29" + attribute \src "ls180.v:9022.6-9022.29" case 1'1 assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r case end - attribute \src "ls180.v:8865.2-8867.5" + attribute \src "ls180.v:9026.2-9028.5" switch \builder_csrbank1_out1_re - attribute \src "ls180.v:8865.6-8865.30" + attribute \src "ls180.v:9026.6-9026.30" case 1'1 assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r case end - attribute \src "ls180.v:8868.2-8870.5" + attribute \src "ls180.v:9029.2-9031.5" switch \builder_csrbank1_out0_re - attribute \src "ls180.v:8868.6-8868.30" + attribute \src "ls180.v:9029.6-9029.30" case 1'1 assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r case end - attribute \src "ls180.v:8873.2-8882.5" + attribute \src "ls180.v:9034.2-9043.5" switch \builder_csrbank2_sel - attribute \src "ls180.v:8873.6-8873.26" + attribute \src "ls180.v:9034.6-9034.26" case 1'1 - attribute \src "ls180.v:8874.3-8881.10" + attribute \src "ls180.v:9035.3-9042.10" switch \builder_interface2_bank_bus_adr [0] attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -278152,18 +281172,18 @@ module \ls180 end case end - attribute \src "ls180.v:8883.2-8885.5" + attribute \src "ls180.v:9044.2-9046.5" switch \builder_csrbank2_w0_re - attribute \src "ls180.v:8883.6-8883.28" + attribute \src "ls180.v:9044.6-9044.28" case 1'1 assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r case end - attribute \src "ls180.v:8888.2-8918.5" + attribute \src "ls180.v:9049.2-9079.5" switch \builder_csrbank3_sel - attribute \src "ls180.v:8888.6-8888.26" + attribute \src "ls180.v:9049.6-9049.26" case 1'1 - attribute \src "ls180.v:8889.3-8917.10" + attribute \src "ls180.v:9050.3-9078.10" switch \builder_interface3_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -278196,74 +281216,74 @@ module \ls180 end case end - attribute \src "ls180.v:8919.2-8921.5" + attribute \src "ls180.v:9080.2-9082.5" switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:8919.6-8919.33" + attribute \src "ls180.v:9080.6-9080.33" case 1'1 assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r case end - attribute \src "ls180.v:8923.2-8925.5" + attribute \src "ls180.v:9084.2-9086.5" switch \builder_csrbank3_width3_re - attribute \src "ls180.v:8923.6-8923.32" + attribute \src "ls180.v:9084.6-9084.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r case end - attribute \src "ls180.v:8926.2-8928.5" + attribute \src "ls180.v:9087.2-9089.5" switch \builder_csrbank3_width2_re - attribute \src "ls180.v:8926.6-8926.32" + attribute \src "ls180.v:9087.6-9087.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r case end - attribute \src "ls180.v:8929.2-8931.5" + attribute \src "ls180.v:9090.2-9092.5" switch \builder_csrbank3_width1_re - attribute \src "ls180.v:8929.6-8929.32" + attribute \src "ls180.v:9090.6-9090.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r case end - attribute \src "ls180.v:8932.2-8934.5" + attribute \src "ls180.v:9093.2-9095.5" switch \builder_csrbank3_width0_re - attribute \src "ls180.v:8932.6-8932.32" + attribute \src "ls180.v:9093.6-9093.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r case end - attribute \src "ls180.v:8936.2-8938.5" + attribute \src "ls180.v:9097.2-9099.5" switch \builder_csrbank3_period3_re - attribute \src "ls180.v:8936.6-8936.33" + attribute \src "ls180.v:9097.6-9097.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r case end - attribute \src "ls180.v:8939.2-8941.5" + attribute \src "ls180.v:9100.2-9102.5" switch \builder_csrbank3_period2_re - attribute \src "ls180.v:8939.6-8939.33" + attribute \src "ls180.v:9100.6-9100.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r case end - attribute \src "ls180.v:8942.2-8944.5" + attribute \src "ls180.v:9103.2-9105.5" switch \builder_csrbank3_period1_re - attribute \src "ls180.v:8942.6-8942.33" + attribute \src "ls180.v:9103.6-9103.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r case end - attribute \src "ls180.v:8945.2-8947.5" + attribute \src "ls180.v:9106.2-9108.5" switch \builder_csrbank3_period0_re - attribute \src "ls180.v:8945.6-8945.33" + attribute \src "ls180.v:9106.6-9106.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r case end - attribute \src "ls180.v:8950.2-8980.5" + attribute \src "ls180.v:9111.2-9141.5" switch \builder_csrbank4_sel - attribute \src "ls180.v:8950.6-8950.26" + attribute \src "ls180.v:9111.6-9111.26" case 1'1 - attribute \src "ls180.v:8951.3-8979.10" + attribute \src "ls180.v:9112.3-9140.10" switch \builder_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -278296,74 +281316,74 @@ module \ls180 end case end - attribute \src "ls180.v:8981.2-8983.5" + attribute \src "ls180.v:9142.2-9144.5" switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:8981.6-8981.33" + attribute \src "ls180.v:9142.6-9142.33" case 1'1 assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r case end - attribute \src "ls180.v:8985.2-8987.5" + attribute \src "ls180.v:9146.2-9148.5" switch \builder_csrbank4_width3_re - attribute \src "ls180.v:8985.6-8985.32" + attribute \src "ls180.v:9146.6-9146.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r case end - attribute \src "ls180.v:8988.2-8990.5" + attribute \src "ls180.v:9149.2-9151.5" switch \builder_csrbank4_width2_re - attribute \src "ls180.v:8988.6-8988.32" + attribute \src "ls180.v:9149.6-9149.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r case end - attribute \src "ls180.v:8991.2-8993.5" + attribute \src "ls180.v:9152.2-9154.5" switch \builder_csrbank4_width1_re - attribute \src "ls180.v:8991.6-8991.32" + attribute \src "ls180.v:9152.6-9152.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r case end - attribute \src "ls180.v:8994.2-8996.5" + attribute \src "ls180.v:9155.2-9157.5" switch \builder_csrbank4_width0_re - attribute \src "ls180.v:8994.6-8994.32" + attribute \src "ls180.v:9155.6-9155.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r case end - attribute \src "ls180.v:8998.2-9000.5" + attribute \src "ls180.v:9159.2-9161.5" switch \builder_csrbank4_period3_re - attribute \src "ls180.v:8998.6-8998.33" + attribute \src "ls180.v:9159.6-9159.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r case end - attribute \src "ls180.v:9001.2-9003.5" + attribute \src "ls180.v:9162.2-9164.5" switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9001.6-9001.33" + attribute \src "ls180.v:9162.6-9162.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r case end - attribute \src "ls180.v:9004.2-9006.5" + attribute \src "ls180.v:9165.2-9167.5" switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9004.6-9004.33" + attribute \src "ls180.v:9165.6-9165.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r case end - attribute \src "ls180.v:9007.2-9009.5" + attribute \src "ls180.v:9168.2-9170.5" switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9007.6-9007.33" + attribute \src "ls180.v:9168.6-9168.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r case end - attribute \src "ls180.v:9012.2-9060.5" + attribute \src "ls180.v:9173.2-9221.5" switch \builder_csrbank5_sel - attribute \src "ls180.v:9012.6-9012.26" + attribute \src "ls180.v:9173.6-9173.26" case 1'1 - attribute \src "ls180.v:9013.3-9059.10" + attribute \src "ls180.v:9174.3-9220.10" switch \builder_interface5_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -278414,109 +281434,109 @@ module \ls180 end case end - attribute \src "ls180.v:9061.2-9063.5" + attribute \src "ls180.v:9222.2-9224.5" switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9061.6-9061.35" + attribute \src "ls180.v:9222.6-9222.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r case end - attribute \src "ls180.v:9064.2-9066.5" + attribute \src "ls180.v:9225.2-9227.5" switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9064.6-9064.35" + attribute \src "ls180.v:9225.6-9225.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r case end - attribute \src "ls180.v:9067.2-9069.5" + attribute \src "ls180.v:9228.2-9230.5" switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9067.6-9067.35" + attribute \src "ls180.v:9228.6-9228.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r case end - attribute \src "ls180.v:9070.2-9072.5" + attribute \src "ls180.v:9231.2-9233.5" switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9070.6-9070.35" + attribute \src "ls180.v:9231.6-9231.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r case end - attribute \src "ls180.v:9073.2-9075.5" + attribute \src "ls180.v:9234.2-9236.5" switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9073.6-9073.35" + attribute \src "ls180.v:9234.6-9234.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r case end - attribute \src "ls180.v:9076.2-9078.5" + attribute \src "ls180.v:9237.2-9239.5" switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9076.6-9076.35" + attribute \src "ls180.v:9237.6-9237.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r case end - attribute \src "ls180.v:9079.2-9081.5" + attribute \src "ls180.v:9240.2-9242.5" switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9079.6-9079.35" + attribute \src "ls180.v:9240.6-9240.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r case end - attribute \src "ls180.v:9082.2-9084.5" + attribute \src "ls180.v:9243.2-9245.5" switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9082.6-9082.35" + attribute \src "ls180.v:9243.6-9243.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r case end - attribute \src "ls180.v:9086.2-9088.5" + attribute \src "ls180.v:9247.2-9249.5" switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9086.6-9086.37" + attribute \src "ls180.v:9247.6-9247.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r case end - attribute \src "ls180.v:9089.2-9091.5" + attribute \src "ls180.v:9250.2-9252.5" switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9089.6-9089.37" + attribute \src "ls180.v:9250.6-9250.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r case end - attribute \src "ls180.v:9092.2-9094.5" + attribute \src "ls180.v:9253.2-9255.5" switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9092.6-9092.37" + attribute \src "ls180.v:9253.6-9253.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r case end - attribute \src "ls180.v:9095.2-9097.5" + attribute \src "ls180.v:9256.2-9258.5" switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9095.6-9095.37" + attribute \src "ls180.v:9256.6-9256.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r case end - attribute \src "ls180.v:9099.2-9101.5" + attribute \src "ls180.v:9260.2-9262.5" switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9099.6-9099.37" + attribute \src "ls180.v:9260.6-9260.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r case end - attribute \src "ls180.v:9103.2-9105.5" + attribute \src "ls180.v:9264.2-9266.5" switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9103.6-9103.35" + attribute \src "ls180.v:9264.6-9264.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r case end - attribute \src "ls180.v:9108.2-9210.5" + attribute \src "ls180.v:9269.2-9371.5" switch \builder_csrbank6_sel - attribute \src "ls180.v:9108.6-9108.26" + attribute \src "ls180.v:9269.6-9269.26" case 1'1 - attribute \src "ls180.v:9109.3-9209.10" + attribute \src "ls180.v:9270.3-9370.10" switch \builder_interface6_bank_bus_adr [5:0] attribute \src "ls180.v:0.0-0.0" case 6'000000 @@ -278621,109 +281641,109 @@ module \ls180 end case end - attribute \src "ls180.v:9211.2-9213.5" + attribute \src "ls180.v:9372.2-9374.5" switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9211.6-9211.39" + attribute \src "ls180.v:9372.6-9372.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r case end - attribute \src "ls180.v:9214.2-9216.5" + attribute \src "ls180.v:9375.2-9377.5" switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9214.6-9214.39" + attribute \src "ls180.v:9375.6-9375.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r case end - attribute \src "ls180.v:9217.2-9219.5" + attribute \src "ls180.v:9378.2-9380.5" switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9217.6-9217.39" + attribute \src "ls180.v:9378.6-9378.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r case end - attribute \src "ls180.v:9220.2-9222.5" + attribute \src "ls180.v:9381.2-9383.5" switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9220.6-9220.39" + attribute \src "ls180.v:9381.6-9381.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r case end - attribute \src "ls180.v:9224.2-9226.5" + attribute \src "ls180.v:9385.2-9387.5" switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9224.6-9224.38" + attribute \src "ls180.v:9385.6-9385.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r case end - attribute \src "ls180.v:9227.2-9229.5" + attribute \src "ls180.v:9388.2-9390.5" switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9227.6-9227.38" + attribute \src "ls180.v:9388.6-9388.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r case end - attribute \src "ls180.v:9230.2-9232.5" + attribute \src "ls180.v:9391.2-9393.5" switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9230.6-9230.38" + attribute \src "ls180.v:9391.6-9391.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r case end - attribute \src "ls180.v:9233.2-9235.5" + attribute \src "ls180.v:9394.2-9396.5" switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9233.6-9233.38" + attribute \src "ls180.v:9394.6-9394.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r case end - attribute \src "ls180.v:9237.2-9239.5" + attribute \src "ls180.v:9398.2-9400.5" switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9237.6-9237.39" + attribute \src "ls180.v:9398.6-9398.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r case end - attribute \src "ls180.v:9240.2-9242.5" + attribute \src "ls180.v:9401.2-9403.5" switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9240.6-9240.39" + attribute \src "ls180.v:9401.6-9401.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r case end - attribute \src "ls180.v:9244.2-9246.5" + attribute \src "ls180.v:9405.2-9407.5" switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9244.6-9244.38" + attribute \src "ls180.v:9405.6-9405.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r case end - attribute \src "ls180.v:9247.2-9249.5" + attribute \src "ls180.v:9408.2-9410.5" switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9247.6-9247.38" + attribute \src "ls180.v:9408.6-9408.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r case end - attribute \src "ls180.v:9250.2-9252.5" + attribute \src "ls180.v:9411.2-9413.5" switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9250.6-9250.38" + attribute \src "ls180.v:9411.6-9411.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r case end - attribute \src "ls180.v:9253.2-9255.5" + attribute \src "ls180.v:9414.2-9416.5" switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9253.6-9253.38" + attribute \src "ls180.v:9414.6-9414.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r case end - attribute \src "ls180.v:9258.2-9318.5" + attribute \src "ls180.v:9419.2-9479.5" switch \builder_csrbank7_sel - attribute \src "ls180.v:9258.6-9258.26" + attribute \src "ls180.v:9419.6-9419.26" case 1'1 - attribute \src "ls180.v:9259.3-9317.10" + attribute \src "ls180.v:9420.3-9478.10" switch \builder_interface7_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -278786,109 +281806,109 @@ module \ls180 end case end - attribute \src "ls180.v:9319.2-9321.5" + attribute \src "ls180.v:9480.2-9482.5" switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9319.6-9319.35" + attribute \src "ls180.v:9480.6-9480.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r case end - attribute \src "ls180.v:9322.2-9324.5" + attribute \src "ls180.v:9483.2-9485.5" switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9322.6-9322.35" + attribute \src "ls180.v:9483.6-9483.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r case end - attribute \src "ls180.v:9325.2-9327.5" + attribute \src "ls180.v:9486.2-9488.5" switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9325.6-9325.35" + attribute \src "ls180.v:9486.6-9486.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r case end - attribute \src "ls180.v:9328.2-9330.5" + attribute \src "ls180.v:9489.2-9491.5" switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9328.6-9328.35" + attribute \src "ls180.v:9489.6-9489.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r case end - attribute \src "ls180.v:9331.2-9333.5" + attribute \src "ls180.v:9492.2-9494.5" switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9331.6-9331.35" + attribute \src "ls180.v:9492.6-9492.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r case end - attribute \src "ls180.v:9334.2-9336.5" + attribute \src "ls180.v:9495.2-9497.5" switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9334.6-9334.35" + attribute \src "ls180.v:9495.6-9495.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r case end - attribute \src "ls180.v:9337.2-9339.5" + attribute \src "ls180.v:9498.2-9500.5" switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9337.6-9337.35" + attribute \src "ls180.v:9498.6-9498.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r case end - attribute \src "ls180.v:9340.2-9342.5" + attribute \src "ls180.v:9501.2-9503.5" switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9340.6-9340.35" + attribute \src "ls180.v:9501.6-9501.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r case end - attribute \src "ls180.v:9344.2-9346.5" + attribute \src "ls180.v:9505.2-9507.5" switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9344.6-9344.37" + attribute \src "ls180.v:9505.6-9505.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r case end - attribute \src "ls180.v:9347.2-9349.5" + attribute \src "ls180.v:9508.2-9510.5" switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9347.6-9347.37" + attribute \src "ls180.v:9508.6-9508.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r case end - attribute \src "ls180.v:9350.2-9352.5" + attribute \src "ls180.v:9511.2-9513.5" switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9350.6-9350.37" + attribute \src "ls180.v:9511.6-9511.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r case end - attribute \src "ls180.v:9353.2-9355.5" + attribute \src "ls180.v:9514.2-9516.5" switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9353.6-9353.37" + attribute \src "ls180.v:9514.6-9514.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r case end - attribute \src "ls180.v:9357.2-9359.5" + attribute \src "ls180.v:9518.2-9520.5" switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9357.6-9357.37" + attribute \src "ls180.v:9518.6-9518.37" case 1'1 assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r case end - attribute \src "ls180.v:9361.2-9363.5" + attribute \src "ls180.v:9522.2-9524.5" switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9361.6-9361.35" + attribute \src "ls180.v:9522.6-9522.35" case 1'1 assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r case end - attribute \src "ls180.v:9366.2-9381.5" + attribute \src "ls180.v:9527.2-9542.5" switch \builder_csrbank8_sel - attribute \src "ls180.v:9366.6-9366.26" + attribute \src "ls180.v:9527.6-9527.26" case 1'1 - attribute \src "ls180.v:9367.3-9380.10" + attribute \src "ls180.v:9528.3-9541.10" switch \builder_interface8_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -278906,25 +281926,25 @@ module \ls180 end case end - attribute \src "ls180.v:9382.2-9384.5" + attribute \src "ls180.v:9543.2-9545.5" switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9382.6-9382.42" + attribute \src "ls180.v:9543.6-9543.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r case end - attribute \src "ls180.v:9385.2-9387.5" + attribute \src "ls180.v:9546.2-9548.5" switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9385.6-9385.42" + attribute \src "ls180.v:9546.6-9546.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r case end - attribute \src "ls180.v:9390.2-9423.5" + attribute \src "ls180.v:9551.2-9584.5" switch \builder_csrbank9_sel - attribute \src "ls180.v:9390.6-9390.26" + attribute \src "ls180.v:9551.6-9551.26" case 1'1 - attribute \src "ls180.v:9391.3-9422.10" + attribute \src "ls180.v:9552.3-9583.10" switch \builder_interface9_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -278960,60 +281980,60 @@ module \ls180 end case end - attribute \src "ls180.v:9424.2-9426.5" + attribute \src "ls180.v:9585.2-9587.5" switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9424.6-9424.39" + attribute \src "ls180.v:9585.6-9585.39" case 1'1 assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r case end - attribute \src "ls180.v:9428.2-9430.5" + attribute \src "ls180.v:9589.2-9591.5" switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9428.6-9428.43" + attribute \src "ls180.v:9589.6-9589.43" case 1'1 assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r case end - attribute \src "ls180.v:9432.2-9434.5" + attribute \src "ls180.v:9593.2-9595.5" switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9432.6-9432.43" + attribute \src "ls180.v:9593.6-9593.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r case end - attribute \src "ls180.v:9435.2-9437.5" + attribute \src "ls180.v:9596.2-9598.5" switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9435.6-9435.43" + attribute \src "ls180.v:9596.6-9596.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r case end - attribute \src "ls180.v:9439.2-9441.5" + attribute \src "ls180.v:9600.2-9602.5" switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9439.6-9439.44" + attribute \src "ls180.v:9600.6-9600.44" case 1'1 assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9443.2-9445.5" + attribute \src "ls180.v:9604.2-9606.5" switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9443.6-9443.42" + attribute \src "ls180.v:9604.6-9604.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9446.2-9448.5" + attribute \src "ls180.v:9607.2-9609.5" switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9446.6-9446.42" + attribute \src "ls180.v:9607.6-9607.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9451.2-9475.5" + attribute \src "ls180.v:9612.2-9636.5" switch \builder_csrbank10_sel - attribute \src "ls180.v:9451.6-9451.27" + attribute \src "ls180.v:9612.6-9612.27" case 1'1 - attribute \src "ls180.v:9452.3-9474.10" + attribute \src "ls180.v:9613.3-9635.10" switch \builder_interface10_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -279040,46 +282060,46 @@ module \ls180 end case end - attribute \src "ls180.v:9476.2-9478.5" + attribute \src "ls180.v:9637.2-9639.5" switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9476.6-9476.35" + attribute \src "ls180.v:9637.6-9637.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r case end - attribute \src "ls180.v:9479.2-9481.5" + attribute \src "ls180.v:9640.2-9642.5" switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9479.6-9479.35" + attribute \src "ls180.v:9640.6-9640.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r case end - attribute \src "ls180.v:9483.2-9485.5" + attribute \src "ls180.v:9644.2-9646.5" switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9483.6-9483.32" + attribute \src "ls180.v:9644.6-9644.32" case 1'1 assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r case end - attribute \src "ls180.v:9487.2-9489.5" + attribute \src "ls180.v:9648.2-9650.5" switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9487.6-9487.30" + attribute \src "ls180.v:9648.6-9648.30" case 1'1 assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r case end - attribute \src "ls180.v:9491.2-9493.5" + attribute \src "ls180.v:9652.2-9654.5" switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9491.6-9491.36" + attribute \src "ls180.v:9652.6-9652.36" case 1'1 assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r case end - attribute \src "ls180.v:9496.2-9526.5" + attribute \src "ls180.v:9657.2-9687.5" switch \builder_csrbank11_sel - attribute \src "ls180.v:9496.6-9496.27" + attribute \src "ls180.v:9657.6-9657.27" case 1'1 - attribute \src "ls180.v:9497.3-9525.10" + attribute \src "ls180.v:9658.3-9686.10" switch \builder_interface11_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -279112,60 +282132,60 @@ module \ls180 end case end - attribute \src "ls180.v:9527.2-9529.5" + attribute \src "ls180.v:9688.2-9690.5" switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9527.6-9527.35" + attribute \src "ls180.v:9688.6-9688.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r case end - attribute \src "ls180.v:9530.2-9532.5" + attribute \src "ls180.v:9691.2-9693.5" switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9530.6-9530.35" + attribute \src "ls180.v:9691.6-9691.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r case end - attribute \src "ls180.v:9534.2-9536.5" + attribute \src "ls180.v:9695.2-9697.5" switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9534.6-9534.32" + attribute \src "ls180.v:9695.6-9695.32" case 1'1 assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r case end - attribute \src "ls180.v:9538.2-9540.5" + attribute \src "ls180.v:9699.2-9701.5" switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9538.6-9538.30" + attribute \src "ls180.v:9699.6-9699.30" case 1'1 assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r case end - attribute \src "ls180.v:9542.2-9544.5" + attribute \src "ls180.v:9703.2-9705.5" switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9542.6-9542.36" + attribute \src "ls180.v:9703.6-9703.36" case 1'1 assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r case end - attribute \src "ls180.v:9546.2-9548.5" + attribute \src "ls180.v:9707.2-9709.5" switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9546.6-9546.39" + attribute \src "ls180.v:9707.6-9707.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r case end - attribute \src "ls180.v:9549.2-9551.5" + attribute \src "ls180.v:9710.2-9712.5" switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9549.6-9549.39" + attribute \src "ls180.v:9710.6-9710.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r case end - attribute \src "ls180.v:9554.2-9608.5" + attribute \src "ls180.v:9715.2-9769.5" switch \builder_csrbank12_sel - attribute \src "ls180.v:9554.6-9554.27" + attribute \src "ls180.v:9715.6-9715.27" case 1'1 - attribute \src "ls180.v:9555.3-9607.10" + attribute \src "ls180.v:9716.3-9768.10" switch \builder_interface12_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -279222,88 +282242,88 @@ module \ls180 end case end - attribute \src "ls180.v:9609.2-9611.5" + attribute \src "ls180.v:9770.2-9772.5" switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9609.6-9609.32" + attribute \src "ls180.v:9770.6-9770.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r case end - attribute \src "ls180.v:9612.2-9614.5" + attribute \src "ls180.v:9773.2-9775.5" switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9612.6-9612.32" + attribute \src "ls180.v:9773.6-9773.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r case end - attribute \src "ls180.v:9615.2-9617.5" + attribute \src "ls180.v:9776.2-9778.5" switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9615.6-9615.32" + attribute \src "ls180.v:9776.6-9776.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r case end - attribute \src "ls180.v:9618.2-9620.5" + attribute \src "ls180.v:9779.2-9781.5" switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9618.6-9618.32" + attribute \src "ls180.v:9779.6-9779.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r case end - attribute \src "ls180.v:9622.2-9624.5" + attribute \src "ls180.v:9783.2-9785.5" switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9622.6-9622.34" + attribute \src "ls180.v:9783.6-9783.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r case end - attribute \src "ls180.v:9625.2-9627.5" + attribute \src "ls180.v:9786.2-9788.5" switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9625.6-9625.34" + attribute \src "ls180.v:9786.6-9786.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r case end - attribute \src "ls180.v:9628.2-9630.5" + attribute \src "ls180.v:9789.2-9791.5" switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9628.6-9628.34" + attribute \src "ls180.v:9789.6-9789.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r case end - attribute \src "ls180.v:9631.2-9633.5" + attribute \src "ls180.v:9792.2-9794.5" switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9631.6-9631.34" + attribute \src "ls180.v:9792.6-9792.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r case end - attribute \src "ls180.v:9635.2-9637.5" + attribute \src "ls180.v:9796.2-9798.5" switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9635.6-9635.30" + attribute \src "ls180.v:9796.6-9796.30" case 1'1 assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r case end - attribute \src "ls180.v:9639.2-9641.5" + attribute \src "ls180.v:9800.2-9802.5" switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9639.6-9639.40" + attribute \src "ls180.v:9800.6-9800.40" case 1'1 assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r case end - attribute \src "ls180.v:9643.2-9645.5" + attribute \src "ls180.v:9804.2-9806.5" switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9643.6-9643.37" + attribute \src "ls180.v:9804.6-9804.37" case 1'1 assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r case end - attribute \src "ls180.v:9648.2-9675.5" + attribute \src "ls180.v:9809.2-9836.5" switch \builder_csrbank13_sel - attribute \src "ls180.v:9648.6-9648.27" + attribute \src "ls180.v:9809.6-9809.27" case 1'1 - attribute \src "ls180.v:9649.3-9674.10" + attribute \src "ls180.v:9810.3-9835.10" switch \builder_interface13_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -279333,18 +282353,18 @@ module \ls180 end case end - attribute \src "ls180.v:9676.2-9678.5" + attribute \src "ls180.v:9837.2-9839.5" switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9676.6-9676.37" + attribute \src "ls180.v:9837.6-9837.37" case 1'1 assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r case end - attribute \src "ls180.v:9681.2-9696.5" + attribute \src "ls180.v:9842.2-9857.5" switch \builder_csrbank14_sel - attribute \src "ls180.v:9681.6-9681.27" + attribute \src "ls180.v:9842.6-9842.27" case 1'1 - attribute \src "ls180.v:9682.3-9695.10" + attribute \src "ls180.v:9843.3-9856.10" switch \builder_interface14_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -279362,54 +282382,51 @@ module \ls180 end case end - attribute \src "ls180.v:9697.2-9699.5" + attribute \src "ls180.v:9858.2-9860.5" switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:9697.6-9697.39" + attribute \src "ls180.v:9858.6-9858.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r case end - attribute \src "ls180.v:9700.2-9702.5" + attribute \src "ls180.v:9861.2-9863.5" switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:9700.6-9700.39" + attribute \src "ls180.v:9861.6-9861.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r case end - attribute \src "ls180.v:9703.2-9705.5" + attribute \src "ls180.v:9864.2-9866.5" switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:9703.6-9703.39" + attribute \src "ls180.v:9864.6-9864.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r case end - attribute \src "ls180.v:9706.2-9708.5" + attribute \src "ls180.v:9867.2-9869.5" switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:9706.6-9706.39" + attribute \src "ls180.v:9867.6-9867.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r case end - attribute \src "ls180.v:9710.2-10004.5" + attribute \src "ls180.v:9871.2-10168.5" switch \sys_rst_1 - attribute \src "ls180.v:9710.6-9710.15" + attribute \src "ls180.v:9871.6-9871.15" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] 1'0 assign $0\main_libresocsim_reset_re[0:0] 1'0 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\pwm[1:0] 2'00 - assign $0\spimaster_clk[0:0] 1'0 - assign $0\spimaster_mosi[0:0] 1'0 - assign $0\spimaster_cs_n[0:0] 1'0 assign $0\spisdcard_clk[0:0] 1'0 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 assign $0\uart_tx[0:0] 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\pwm[1:0] 2'00 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 assign $0\main_libresocsim_load_re[0:0] 1'0 @@ -279425,6 +282442,11 @@ module \ls180 assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 assign $0\main_libresocsim_value[31:0] 0 + assign $0\main_interface0_ram_bus_ack[0:0] 1'0 + assign $0\main_interface1_ram_bus_ack[0:0] 1'0 + assign $0\main_interface2_ram_bus_ack[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 assign $0\main_rddata_en[2:0] 3'000 assign $0\main_sdram_storage[3:0] 4'0001 @@ -279489,6 +282511,7 @@ module \ls180 assign $0\main_sdram_twtrcon_count[2:0] 3'000 assign $0\main_sdram_time0[4:0] 5'00000 assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_socbushandler_counter[0:0] 1'0 assign $0\main_converter_counter[0:0] 1'0 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 @@ -279629,7 +282652,7 @@ module \ls180 assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 @@ -279640,7 +282663,7 @@ module \ls180 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\main_sdmem2block_dma_data[31:0] 0 + assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 assign $0\main_sdmem2block_dma_length_storage[31:0] 0 @@ -279650,7 +282673,7 @@ module \ls180 assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 @@ -279684,31 +282707,25 @@ module \ls180 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 assign $0\builder_libresocsim_we[0:0] 1'0 assign $0\builder_grant[2:0] 3'000 - assign $0\builder_slave_sel_r[4:0] 5'00000 + assign $0\builder_slave_sel_r[7:0] 8'00000000 assign $0\builder_count[19:0] 20'11110100001001000000 assign $0\builder_state[1:0] 2'00 case end sync posedge \sys_clk_1 - update \pwm $0\pwm[1:0] - update \spimaster_clk $0\spimaster_clk[0:0] - update \spimaster_mosi $0\spimaster_mosi[0:0] - update \spimaster_cs_n $0\spimaster_cs_n[0:0] update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] update \uart_tx $0\uart_tx[0:0] + update \pwm $0\pwm[1:0] + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] - update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] - update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] - update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] - update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] - update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] @@ -279724,6 +282741,13 @@ module \ls180 update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0] + update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0] + update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0] + update \main_converter0_counter $0\main_converter0_counter[0:0] + update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] + update \main_converter1_counter $0\main_converter1_counter[0:0] + update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] update \main_rddata_en $0\main_rddata_en[2:0] update \main_sdram_storage $0\main_sdram_storage[3:0] @@ -279812,6 +282836,8 @@ module \ls180 update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] update \main_sdram_time0 $0\main_sdram_time0[4:0] update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] + update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] update \main_converter_counter $0\main_converter_counter[0:0] update \main_converter_dat_r $0\main_converter_dat_r[31:0] update \main_cmd_consumed $0\main_cmd_consumed[0:0] @@ -279991,9 +283017,9 @@ module \ls180 update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] - update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] - update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] @@ -280004,7 +283030,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] @@ -280014,7 +283040,7 @@ module \ls180 update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] - update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] @@ -280050,7 +283076,7 @@ module \ls180 update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] update \builder_grant $0\builder_grant[2:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[7:0] update \builder_count $0\builder_count[19:0] update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] @@ -280103,789 +283129,885 @@ module \ls180 update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:744.5-744.49" - process $proc$ls180.v:744$3034 + attribute \src "ls180.v:757.5-757.45" + process $proc$ls180.v:757$3281 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:758.5-758.54" + process $proc$ls180.v:758$3282 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:760.32-760.76" + process $proc$ls180.v:760$3283 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "ls180.v:761.11-761.55" + process $proc$ls180.v:761$3284 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:763.32-763.75" + process $proc$ls180.v:763$3285 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:765.32-765.76" + process $proc$ls180.v:765$3286 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:768.5-768.44" + process $proc$ls180.v:768$3287 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "ls180.v:769.5-769.45" + process $proc$ls180.v:769$3288 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:770.5-770.43" + process $proc$ls180.v:770$3289 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "ls180.v:771.5-771.48" + process $proc$ls180.v:771$3290 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:773.5-773.43" + process $proc$ls180.v:773$3291 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:776.5-776.49" + process $proc$ls180.v:776$3292 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:745.5-745.49" - process $proc$ls180.v:745$3035 + attribute \src "ls180.v:777.5-777.49" + process $proc$ls180.v:777$3293 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:746.5-746.48" - process $proc$ls180.v:746$3036 + attribute \src "ls180.v:778.5-778.48" + process $proc$ls180.v:778$3294 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:750.11-750.46" - process $proc$ls180.v:750$3037 + attribute \src "ls180.v:782.11-782.46" + process $proc$ls180.v:782$3295 assign { } { } assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:752.11-752.45" - process $proc$ls180.v:752$3038 + attribute \src "ls180.v:784.11-784.45" + process $proc$ls180.v:784$3296 assign { } { } assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end - attribute \src "ls180.v:754.5-754.44" - process $proc$ls180.v:754$3039 + attribute \src "ls180.v:786.5-786.44" + process $proc$ls180.v:786$3297 assign { } { } assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \src "ls180.v:755.5-755.45" - process $proc$ls180.v:755$3040 + attribute \src "ls180.v:787.5-787.45" + process $proc$ls180.v:787$3298 assign { } { } assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \src "ls180.v:757.5-757.48" - process $proc$ls180.v:757$3041 + attribute \src "ls180.v:789.5-789.48" + process $proc$ls180.v:789$3299 assign { } { } assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \src "ls180.v:759.5-759.43" - process $proc$ls180.v:759$3042 + attribute \src "ls180.v:791.5-791.43" + process $proc$ls180.v:791$3300 assign { } { } assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \src "ls180.v:762.5-762.49" - process $proc$ls180.v:762$3043 + attribute \src "ls180.v:794.5-794.49" + process $proc$ls180.v:794$3301 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:763.5-763.49" - process $proc$ls180.v:763$3044 + attribute \src "ls180.v:795.5-795.49" + process $proc$ls180.v:795$3302 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:764.5-764.48" - process $proc$ls180.v:764$3045 + attribute \src "ls180.v:796.5-796.48" + process $proc$ls180.v:796$3303 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:768.11-768.46" - process $proc$ls180.v:768$3046 + attribute \src "ls180.v:800.11-800.46" + process $proc$ls180.v:800$3304 assign { } { } assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:770.11-770.45" - process $proc$ls180.v:770$3047 + attribute \src "ls180.v:802.11-802.45" + process $proc$ls180.v:802$3305 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "ls180.v:772.12-772.36" - process $proc$ls180.v:772$3048 + attribute \src "ls180.v:804.12-804.36" + process $proc$ls180.v:804$3306 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init end - attribute \src "ls180.v:773.11-773.35" - process $proc$ls180.v:773$3049 + attribute \src "ls180.v:805.11-805.35" + process $proc$ls180.v:805$3307 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init end - attribute \src "ls180.v:774.11-774.40" - process $proc$ls180.v:774$3050 + attribute \src "ls180.v:806.11-806.40" + process $proc$ls180.v:806$3308 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "ls180.v:775.5-775.31" - process $proc$ls180.v:775$3051 + attribute \src "ls180.v:807.5-807.31" + process $proc$ls180.v:807$3309 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init end - attribute \src "ls180.v:776.5-776.31" - process $proc$ls180.v:776$3052 + attribute \src "ls180.v:808.5-808.31" + process $proc$ls180.v:808$3310 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init end - attribute \src "ls180.v:778.32-778.63" - process $proc$ls180.v:778$3053 + attribute \src "ls180.v:810.32-810.63" + process $proc$ls180.v:810$3311 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init end - attribute \src "ls180.v:780.32-780.63" - process $proc$ls180.v:780$3054 + attribute \src "ls180.v:812.32-812.63" + process $proc$ls180.v:812$3312 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init end - attribute \src "ls180.v:782.32-782.63" - process $proc$ls180.v:782$3055 + attribute \src "ls180.v:814.32-814.63" + process $proc$ls180.v:814$3313 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "ls180.v:783.5-783.36" - process $proc$ls180.v:783$3056 + attribute \src "ls180.v:815.5-815.36" + process $proc$ls180.v:815$3314 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "ls180.v:785.32-785.63" - process $proc$ls180.v:785$3057 + attribute \src "ls180.v:817.32-817.63" + process $proc$ls180.v:817$3315 assign { } { } assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always sync init update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:786.11-786.42" - process $proc$ls180.v:786$3058 + attribute \src "ls180.v:818.11-818.42" + process $proc$ls180.v:818$3316 assign { } { } assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always sync init update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "ls180.v:789.5-789.26" - process $proc$ls180.v:789$3059 + attribute \src "ls180.v:821.5-821.26" + process $proc$ls180.v:821$3317 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always sync init update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "ls180.v:791.11-791.34" - process $proc$ls180.v:791$3060 + attribute \src "ls180.v:823.11-823.34" + process $proc$ls180.v:823$3318 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "ls180.v:792.5-792.26" - process $proc$ls180.v:792$3061 + attribute \src "ls180.v:824.5-824.26" + process $proc$ls180.v:824$3319 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always sync init update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "ls180.v:794.11-794.34" - process $proc$ls180.v:794$3062 + attribute \src "ls180.v:826.11-826.34" + process $proc$ls180.v:826$3320 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always sync init update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "ls180.v:81.5-81.46" - process $proc$ls180.v:81$2771 + attribute \src "ls180.v:841.12-841.37" + process $proc$ls180.v:841$3321 assign { } { } - assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] + update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] end - attribute \src "ls180.v:815.5-815.29" - process $proc$ls180.v:815$3063 + attribute \src "ls180.v:842.12-842.39" + process $proc$ls180.v:842$3322 + assign { } { } + assign $1\main_wb_sdram_dat_w[31:0] 0 + sync always + sync init + update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:844.11-844.35" + process $proc$ls180.v:844$3323 + assign { } { } + assign $1\main_wb_sdram_sel[3:0] 4'0000 + sync always + sync init + update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] + end + attribute \src "ls180.v:845.5-845.29" + process $proc$ls180.v:845$3324 + assign { } { } + assign $1\main_wb_sdram_cyc[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] + end + attribute \src "ls180.v:846.5-846.29" + process $proc$ls180.v:846$3325 + assign { } { } + assign $1\main_wb_sdram_stb[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] + end + attribute \src "ls180.v:847.5-847.29" + process $proc$ls180.v:847$3326 assign { } { } assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "ls180.v:819.5-819.29" - process $proc$ls180.v:819$3064 + attribute \src "ls180.v:848.5-848.28" + process $proc$ls180.v:848$3327 + assign { } { } + assign $1\main_wb_sdram_we[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] + end + attribute \src "ls180.v:85.11-85.52" + process $proc$ls180.v:85$3031 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] + sync init + end + attribute \src "ls180.v:855.5-855.54" + process $proc$ls180.v:855$3328 + assign { } { } + assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] + end + attribute \src "ls180.v:859.5-859.54" + process $proc$ls180.v:859$3329 + assign { } { } + assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + sync always + update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:86.11-86.52" + process $proc$ls180.v:86$3032 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] + sync init + end + attribute \src "ls180.v:860.5-860.35" + process $proc$ls180.v:860$3330 + assign { } { } + assign $1\main_socbushandler_skip[0:0] 1'0 + sync always + sync init + update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] + end + attribute \src "ls180.v:861.5-861.38" + process $proc$ls180.v:861$3331 + assign { } { } + assign $1\main_socbushandler_counter[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] + end + attribute \src "ls180.v:863.12-863.44" + process $proc$ls180.v:863$3332 assign { } { } - assign $0\main_wb_sdram_err[0:0] 1'0 + assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] sync init + update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] end - attribute \src "ls180.v:820.12-820.40" - process $proc$ls180.v:820$3065 + attribute \src "ls180.v:864.12-864.40" + process $proc$ls180.v:864$3333 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "ls180.v:821.12-821.42" - process $proc$ls180.v:821$3066 + attribute \src "ls180.v:865.12-865.42" + process $proc$ls180.v:865$3334 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:823.11-823.38" - process $proc$ls180.v:823$3067 + attribute \src "ls180.v:867.11-867.38" + process $proc$ls180.v:867$3335 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "ls180.v:824.5-824.32" - process $proc$ls180.v:824$3068 + attribute \src "ls180.v:868.5-868.32" + process $proc$ls180.v:868$3336 assign { } { } assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "ls180.v:825.5-825.32" - process $proc$ls180.v:825$3069 + attribute \src "ls180.v:869.5-869.32" + process $proc$ls180.v:869$3337 assign { } { } assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:827.5-827.31" - process $proc$ls180.v:827$3070 + attribute \src "ls180.v:871.5-871.31" + process $proc$ls180.v:871$3338 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "ls180.v:828.5-828.31" - process $proc$ls180.v:828$3071 + attribute \src "ls180.v:872.5-872.31" + process $proc$ls180.v:872$3339 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always sync init update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "ls180.v:829.5-829.34" - process $proc$ls180.v:829$3072 + attribute \src "ls180.v:873.5-873.34" + process $proc$ls180.v:873$3340 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always sync init update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "ls180.v:83.5-83.46" - process $proc$ls180.v:83$2772 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] - sync init - end - attribute \src "ls180.v:831.12-831.40" - process $proc$ls180.v:831$3073 + attribute \src "ls180.v:875.12-875.40" + process $proc$ls180.v:875$3341 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always sync init update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "ls180.v:832.5-832.29" - process $proc$ls180.v:832$3074 + attribute \src "ls180.v:876.5-876.29" + process $proc$ls180.v:876$3342 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "ls180.v:833.5-833.31" - process $proc$ls180.v:833$3075 + attribute \src "ls180.v:877.5-877.31" + process $proc$ls180.v:877$3343 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "ls180.v:837.12-837.47" - process $proc$ls180.v:837$3076 + attribute \src "ls180.v:88.12-88.58" + process $proc$ls180.v:88$3033 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + end + attribute \src "ls180.v:881.12-881.47" + process $proc$ls180.v:881$3344 assign { } { } assign $1\main_uart_phy_storage[31:0] 9895604 sync always sync init update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end - attribute \src "ls180.v:838.5-838.28" - process $proc$ls180.v:838$3077 + attribute \src "ls180.v:882.5-882.28" + process $proc$ls180.v:882$3345 assign { } { } assign $1\main_uart_phy_re[0:0] 1'0 sync always sync init update \main_uart_phy_re $1\main_uart_phy_re[0:0] end - attribute \src "ls180.v:840.5-840.36" - process $proc$ls180.v:840$3078 + attribute \src "ls180.v:884.5-884.36" + process $proc$ls180.v:884$3346 assign { } { } assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always sync init update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:844.5-844.39" - process $proc$ls180.v:844$3079 + attribute \src "ls180.v:888.5-888.39" + process $proc$ls180.v:888$3347 assign { } { } assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:845.12-845.54" - process $proc$ls180.v:845$3080 + attribute \src "ls180.v:889.12-889.54" + process $proc$ls180.v:889$3348 assign { } { } assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:846.11-846.38" - process $proc$ls180.v:846$3081 + attribute \src "ls180.v:89.12-89.60" + process $proc$ls180.v:89$3034 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + end + attribute \src "ls180.v:890.11-890.38" + process $proc$ls180.v:890$3349 assign { } { } assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:847.11-847.43" - process $proc$ls180.v:847$3082 + attribute \src "ls180.v:891.11-891.43" + process $proc$ls180.v:891$3350 assign { } { } assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:848.5-848.33" - process $proc$ls180.v:848$3083 + attribute \src "ls180.v:892.5-892.33" + process $proc$ls180.v:892$3351 assign { } { } assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:849.5-849.38" - process $proc$ls180.v:849$3084 + attribute \src "ls180.v:893.5-893.38" + process $proc$ls180.v:893$3352 assign { } { } assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always sync init update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end - attribute \src "ls180.v:851.5-851.38" - process $proc$ls180.v:851$3085 + attribute \src "ls180.v:895.5-895.38" + process $proc$ls180.v:895$3353 assign { } { } assign $0\main_uart_phy_source_first[0:0] 1'0 sync always update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init end - attribute \src "ls180.v:852.5-852.37" - process $proc$ls180.v:852$3086 + attribute \src "ls180.v:896.5-896.37" + process $proc$ls180.v:896$3354 assign { } { } assign $0\main_uart_phy_source_last[0:0] 1'0 sync always update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] sync init end - attribute \src "ls180.v:853.11-853.51" - process $proc$ls180.v:853$3087 + attribute \src "ls180.v:897.11-897.51" + process $proc$ls180.v:897$3355 assign { } { } assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:854.5-854.39" - process $proc$ls180.v:854$3088 + attribute \src "ls180.v:898.5-898.39" + process $proc$ls180.v:898$3356 assign { } { } assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:855.12-855.54" - process $proc$ls180.v:855$3089 + attribute \src "ls180.v:899.12-899.54" + process $proc$ls180.v:899$3357 assign { } { } assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:857.5-857.30" - process $proc$ls180.v:857$3090 + attribute \src "ls180.v:901.5-901.30" + process $proc$ls180.v:901$3358 assign { } { } assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always sync init update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end - attribute \src "ls180.v:858.11-858.38" - process $proc$ls180.v:858$3091 + attribute \src "ls180.v:902.11-902.38" + process $proc$ls180.v:902$3359 assign { } { } assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:859.11-859.43" - process $proc$ls180.v:859$3092 + attribute \src "ls180.v:903.11-903.43" + process $proc$ls180.v:903$3360 assign { } { } assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:860.5-860.33" - process $proc$ls180.v:860$3093 + attribute \src "ls180.v:904.5-904.33" + process $proc$ls180.v:904$3361 assign { } { } assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] end - attribute \src "ls180.v:871.5-871.32" - process $proc$ls180.v:871$3094 + attribute \src "ls180.v:91.11-91.56" + process $proc$ls180.v:91$3035 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + end + attribute \src "ls180.v:915.5-915.32" + process $proc$ls180.v:915$3362 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:873.5-873.30" - process $proc$ls180.v:873$3095 + attribute \src "ls180.v:917.5-917.30" + process $proc$ls180.v:917$3363 assign { } { } assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:874.5-874.36" - process $proc$ls180.v:874$3096 + attribute \src "ls180.v:918.5-918.36" + process $proc$ls180.v:918$3364 assign { } { } assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "ls180.v:876.5-876.32" - process $proc$ls180.v:876$3097 + attribute \src "ls180.v:92.5-92.50" + process $proc$ls180.v:92$3036 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + end + attribute \src "ls180.v:920.5-920.32" + process $proc$ls180.v:920$3365 assign { } { } assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "ls180.v:878.5-878.30" - process $proc$ls180.v:878$3098 + attribute \src "ls180.v:922.5-922.30" + process $proc$ls180.v:922$3366 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:879.5-879.36" - process $proc$ls180.v:879$3099 + attribute \src "ls180.v:923.5-923.36" + process $proc$ls180.v:923$3367 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "ls180.v:883.11-883.49" - process $proc$ls180.v:883$3100 + attribute \src "ls180.v:927.11-927.49" + process $proc$ls180.v:927$3368 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:887.11-887.50" - process $proc$ls180.v:887$3101 + attribute \src "ls180.v:93.5-93.50" + process $proc$ls180.v:93$3037 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + end + attribute \src "ls180.v:931.11-931.50" + process $proc$ls180.v:931$3369 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:888.11-888.48" - process $proc$ls180.v:888$3102 + attribute \src "ls180.v:932.11-932.48" + process $proc$ls180.v:932$3370 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "ls180.v:889.5-889.37" - process $proc$ls180.v:889$3103 + attribute \src "ls180.v:933.5-933.37" + process $proc$ls180.v:933$3371 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always sync init update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] end - attribute \src "ls180.v:906.5-906.40" - process $proc$ls180.v:906$3104 + attribute \src "ls180.v:95.5-95.49" + process $proc$ls180.v:95$3038 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + end + attribute \src "ls180.v:950.5-950.40" + process $proc$ls180.v:950$3372 assign { } { } assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init end - attribute \src "ls180.v:907.5-907.39" - process $proc$ls180.v:907$3105 + attribute \src "ls180.v:951.5-951.39" + process $proc$ls180.v:951$3373 assign { } { } assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init end - attribute \src "ls180.v:915.5-915.38" - process $proc$ls180.v:915$3106 + attribute \src "ls180.v:959.5-959.38" + process $proc$ls180.v:959$3374 assign { } { } assign $1\main_uart_tx_fifo_readable[0:0] 1'0 sync always sync init update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end - attribute \src "ls180.v:922.11-922.42" - process $proc$ls180.v:922$3107 + attribute \src "ls180.v:966.11-966.42" + process $proc$ls180.v:966$3375 assign { } { } assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end - attribute \src "ls180.v:923.5-923.37" - process $proc$ls180.v:923$3108 + attribute \src "ls180.v:967.5-967.37" + process $proc$ls180.v:967$3376 assign { } { } assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:924.11-924.43" - process $proc$ls180.v:924$3109 + attribute \src "ls180.v:968.11-968.43" + process $proc$ls180.v:968$3377 assign { } { } assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end - attribute \src "ls180.v:925.11-925.43" - process $proc$ls180.v:925$3110 + attribute \src "ls180.v:969.11-969.43" + process $proc$ls180.v:969$3378 assign { } { } assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end - attribute \src "ls180.v:926.11-926.46" - process $proc$ls180.v:926$3111 + attribute \src "ls180.v:97.12-97.58" + process $proc$ls180.v:97$3039 assign { } { } - assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:952.5-952.38" - process $proc$ls180.v:952$3112 - assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] - end - attribute \src "ls180.v:959.11-959.42" - process $proc$ls180.v:959$3113 - assign { } { } - assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] - end - attribute \src "ls180.v:960.5-960.37" - process $proc$ls180.v:960$3114 - assign { } { } - assign $0\main_uart_rx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:961.11-961.43" - process $proc$ls180.v:961$3115 - assign { } { } - assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] - end - attribute \src "ls180.v:962.11-962.43" - process $proc$ls180.v:962$3116 - assign { } { } - assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] - end - attribute \src "ls180.v:963.11-963.46" - process $proc$ls180.v:963$3117 - assign { } { } - assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] end - attribute \src "ls180.v:978.5-978.27" - process $proc$ls180.v:978$3118 + attribute \src "ls180.v:970.11-970.46" + process $proc$ls180.v:970$3379 assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:979.12-979.40" - process $proc$ls180.v:979$3119 - assign { } { } - assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] - end - attribute \src "ls180.v:980.5-980.27" - process $proc$ls180.v:980$3120 - assign { } { } - assign $1\main_gpio_oe_re[0:0] 1'0 - sync always - sync init - update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] - end - attribute \src "ls180.v:981.12-981.36" - process $proc$ls180.v:981$3121 - assign { } { } - assign $1\main_gpio_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_status $1\main_gpio_status[15:0] - end - attribute \src "ls180.v:983.12-983.41" - process $proc$ls180.v:983$3122 - assign { } { } - assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] - end - attribute \src "ls180.v:984.5-984.28" - process $proc$ls180.v:984$3123 - assign { } { } - assign $1\main_gpio_out_re[0:0] 1'0 - sync always - sync init - update \main_gpio_out_re $1\main_gpio_out_re[0:0] - end - attribute \src "ls180.v:990.5-990.32" - process $proc$ls180.v:990$3124 - assign { } { } - assign $1\main_spimaster2_done[0:0] 1'0 - sync always - sync init - update \main_spimaster2_done $1\main_spimaster2_done[0:0] - end - attribute \src "ls180.v:991.5-991.31" - process $proc$ls180.v:991$3125 - assign { } { } - assign $1\main_spimaster3_irq[0:0] 1'0 - sync always - sync init - update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] - end - attribute \src "ls180.v:993.11-993.38" - process $proc$ls180.v:993$3126 - assign { } { } - assign $1\main_spimaster5_miso[7:0] 8'00000000 - sync always - sync init - update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] - end - attribute \src "ls180.v:996.12-996.47" - process $proc$ls180.v:996$3127 - assign { } { } - assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always - update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:997.5-997.33" - process $proc$ls180.v:997$3128 + attribute \src "ls180.v:98.12-98.60" + process $proc$ls180.v:98$3040 assign { } { } - assign $1\main_spimaster9_start[0:0] 1'0 + assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 sync always sync init - update \main_spimaster9_start $1\main_spimaster9_start[0:0] + update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:999.12-999.44" - process $proc$ls180.v:999$3129 + attribute \src "ls180.v:996.5-996.38" + process $proc$ls180.v:996$3380 assign { } { } - assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 sync always sync init - update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] end connect \main_libresocsim_libresoc_reset \main_libresocsim_reset connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i @@ -280907,22 +284029,31 @@ module \ls180 connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 connect \main_libresocsim_bus_error \builder_error - connect \main_libresocsim_converter0_reset $not$ls180.v:2773$14_Y - connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } - connect \main_libresocsim_converter1_reset $not$ls180.v:2833$25_Y - connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } - connect \main_libresocsim_converter2_reset $not$ls180.v:2893$36_Y - connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } + connect \main_converter0_reset $not$ls180.v:2825$42_Y + connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } + connect \main_converter1_reset $not$ls180.v:2885$53_Y + connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } + connect \main_socbushandler_reset $not$ls180.v:2945$64_Y + connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } connect \main_libresocsim_reset \main_libresocsim_reset_re connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [8:0] connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:2965$60_Y + connect \main_libresocsim_zero_trigger $ne$ls180.v:3021$100_Y connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:2974$63_Y + connect \main_libresocsim_irq $and$ls180.v:3030$103_Y connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \main_sram0_adr \main_interface0_ram_bus_adr [8:0] + connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r + connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w + connect \main_sram1_adr \main_interface1_ram_bus_adr [8:0] + connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r + connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w + connect \main_sram2_adr \main_interface2_ram_bus_adr [8:0] + connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r + connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w connect \sys_clk_1 \sys_clk connect \por_clk \sys_clk connect \sys_rst_1 \main_int_rst @@ -280963,8 +284094,8 @@ module \ls180 connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n connect \main_sdram_inti_p0_address \main_sdram_address_storage connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3088$70_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3089$71_Y + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3186$185_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3187$186_Y connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage connect \main_sdram_inti_p0_wrdata_mask 2'00 connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid @@ -280995,14 +284126,14 @@ module \ls180 connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3120$72_Y + connect \main_sdram_timer_wait $not$ls180.v:3218$187_Y connect \main_sdram_postponer_req_i \main_sdram_timer_done0 connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3123$73_Y + connect \main_sdram_timer_done1 $eq$ls180.v:3221$188_Y connect \main_sdram_timer_done0 \main_sdram_timer_done1 connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3126$75_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3127$77_Y + connect \main_sdram_sequencer_start1 $or$ls180.v:3224$190_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3225$192_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we @@ -281013,13 +284144,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3169$79_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3170$80_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3171$81_Y + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3267$194_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3268$195_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3269$196_Y connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3181$86_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3182$88_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3183$90_Y + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3279$201_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3280$203_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3281$205_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable @@ -281035,13 +284166,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3215$98_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3216$99_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3313$213_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3314$214_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3219$100_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3220$101_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3221$103_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3317$215_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3318$216_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3319$218_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we @@ -281052,13 +284183,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3326$109_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3327$110_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3328$111_Y + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3424$224_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3425$225_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3426$226_Y connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3338$116_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3339$118_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3340$120_Y + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3436$231_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3437$233_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3438$235_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable @@ -281074,13 +284205,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3372$128_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3373$129_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3470$243_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3471$244_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3376$130_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3377$131_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3378$133_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3474$245_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3475$246_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3476$248_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we @@ -281091,13 +284222,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3483$139_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3484$140_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3485$141_Y + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3581$254_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3582$255_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3583$256_Y connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3495$146_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3496$148_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3497$150_Y + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3593$261_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3594$263_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3595$265_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable @@ -281113,13 +284244,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3529$158_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3530$159_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3627$273_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3628$274_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3533$160_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3534$161_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3535$163_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3631$275_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3632$276_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3633$278_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we @@ -281130,13 +284261,13 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3640$169_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3641$170_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3642$171_Y + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3738$284_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3739$285_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3740$286_Y connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3652$176_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3653$178_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3654$180_Y + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3750$291_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3751$293_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3752$295_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable @@ -281152,32 +284283,32 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3686$188_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3687$189_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3784$303_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3785$304_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3690$190_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3691$191_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3692$193_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3788$305_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3789$306_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3790$308_Y connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3788$204_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3789$210_Y - connect \main_sdram_ras_allowed $and$ls180.v:3790$211_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3791$214_Y + connect \main_sdram_trrdcon_valid $and$ls180.v:3886$319_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3887$325_Y + connect \main_sdram_ras_allowed $and$ls180.v:3888$326_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3889$329_Y connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3793$216_Y - connect \main_sdram_read_available $or$ls180.v:3794$223_Y - connect \main_sdram_write_available $or$ls180.v:3795$230_Y - connect \main_sdram_max_time0 $eq$ls180.v:3796$231_Y - connect \main_sdram_max_time1 $eq$ls180.v:3797$232_Y + connect \main_sdram_twtrcon_valid $and$ls180.v:3891$331_Y + connect \main_sdram_read_available $or$ls180.v:3892$338_Y + connect \main_sdram_write_available $or$ls180.v:3893$345_Y + connect \main_sdram_max_time0 $eq$ls180.v:3894$346_Y + connect \main_sdram_max_time1 $eq$ls180.v:3895$347_Y connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3802$235_Y + connect \main_sdram_go_to_refresh $and$ls180.v:3900$350_Y connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3805$236_Y + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3903$351_Y connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 @@ -281185,7 +284316,7 @@ module \ls180 connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3838$294_Y + connect \main_sdram_choose_cmd_ce $or$ls180.v:3936$409_Y connect \main_sdram_choose_req_request \main_sdram_choose_req_valids connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 @@ -281193,31 +284324,31 @@ module \ls180 connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3907$380_Y + connect \main_sdram_choose_req_ce $or$ls180.v:4005$495_Y connect \main_sdram_dfi_p0_reset_n 1'1 connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:3984$412_Y - connect \builder_roundrobin0_ce $and$ls180.v:3985$415_Y + connect \builder_roundrobin0_request $and$ls180.v:4082$527_Y + connect \builder_roundrobin0_ce $and$ls180.v:4083$530_Y connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:3989$428_Y - connect \builder_roundrobin1_ce $and$ls180.v:3990$431_Y + connect \builder_roundrobin1_request $and$ls180.v:4087$543_Y + connect \builder_roundrobin1_ce $and$ls180.v:4088$546_Y connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:3994$444_Y - connect \builder_roundrobin2_ce $and$ls180.v:3995$447_Y + connect \builder_roundrobin2_request $and$ls180.v:4092$559_Y + connect \builder_roundrobin2_ce $and$ls180.v:4093$562_Y connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:3999$460_Y - connect \builder_roundrobin3_ce $and$ls180.v:4000$463_Y + connect \builder_roundrobin3_request $and$ls180.v:4097$575_Y + connect \builder_roundrobin3_ce $and$ls180.v:4098$578_Y connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4004$527_Y + connect \main_port_cmd_ready $or$ls180.v:4102$642_Y connect \main_port_wdata_ready \builder_new_master_wdata_ready connect \main_port_rdata_valid \builder_new_master_rdata_valid3 connect \main_port_rdata_payload_data \main_sdram_interface_rdata @@ -281225,22 +284356,22 @@ module \ls180 connect \builder_roundrobin1_grant 1'0 connect \builder_roundrobin2_grant 1'0 connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4026$529_Y + connect \main_converter_reset $not$ls180.v:4124$644_Y connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4086$540_Y [23:0] + connect \main_port_cmd_payload_addr $sub$ls180.v:4184$655_Y [23:0] connect \main_port_cmd_payload_we \main_litedram_wb_we connect \main_port_wdata_payload_data \main_litedram_wb_dat_w connect \main_port_wdata_payload_we \main_litedram_wb_sel connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4091$541_Y - connect \main_port_cmd_last $not$ls180.v:4092$542_Y - connect \main_port_cmd_valid $and$ls180.v:4093$545_Y - connect \main_port_wdata_valid $and$ls180.v:4094$549_Y - connect \main_port_rdata_ready $and$ls180.v:4095$552_Y - connect \main_litedram_wb_ack $and$ls180.v:4096$557_Y - connect \main_ack_cmd $or$ls180.v:4097$559_Y - connect \main_ack_wdata $or$ls180.v:4098$561_Y - connect \main_ack_rdata $and$ls180.v:4099$562_Y + connect \main_port_flush $not$ls180.v:4189$656_Y + connect \main_port_cmd_last $not$ls180.v:4190$657_Y + connect \main_port_cmd_valid $and$ls180.v:4191$660_Y + connect \main_port_wdata_valid $and$ls180.v:4192$664_Y + connect \main_port_rdata_ready $and$ls180.v:4193$667_Y + connect \main_litedram_wb_ack $and$ls180.v:4194$672_Y + connect \main_ack_cmd $or$ls180.v:4195$674_Y + connect \main_ack_wdata $or$ls180.v:4196$676_Y + connect \main_ack_rdata $and$ls180.v:4197$677_Y connect \main_uart_uart_sink_valid \main_uart_phy_source_valid connect \main_uart_phy_source_ready \main_uart_uart_sink_ready connect \main_uart_uart_sink_first \main_uart_phy_source_first @@ -281253,25 +284384,25 @@ module \ls180 connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4112$563_Y - connect \main_uart_txempty_status $not$ls180.v:4113$564_Y + connect \main_uart_txfull_status $not$ls180.v:4210$678_Y + connect \main_uart_txempty_status $not$ls180.v:4211$679_Y connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4119$565_Y + connect \main_uart_tx_trigger $not$ls180.v:4217$680_Y connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4125$566_Y - connect \main_uart_rxfull_status $not$ls180.v:4126$567_Y + connect \main_uart_rxempty_status $not$ls180.v:4223$681_Y + connect \main_uart_rxfull_status $not$ls180.v:4224$682_Y connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4128$569_Y - connect \main_uart_rx_trigger $not$ls180.v:4129$570_Y - connect \main_uart_irq $or$ls180.v:4152$579_Y + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4226$684_Y + connect \main_uart_rx_trigger $not$ls180.v:4227$685_Y + connect \main_uart_irq $or$ls180.v:4250$694_Y connect \main_uart_tx_status \main_uart_tx_trigger connect \main_uart_rx_status \main_uart_rx_trigger connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } @@ -281286,16 +284417,16 @@ module \ls180 connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4167$582_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4168$583_Y + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4265$697_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4266$698_Y connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4178$587_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4179$588_Y + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4276$702_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4277$703_Y connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4183$589_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4184$590_Y + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4281$704_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4282$705_Y connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable @@ -281308,16 +284439,16 @@ module \ls180 connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4197$593_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4198$594_Y + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4295$708_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4296$709_Y connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4208$598_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4209$599_Y + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4306$713_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4307$714_Y connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4213$600_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4214$601_Y + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4311$715_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4312$716_Y connect \main_gpio_pads_i \gpio_i connect \gpio_o \main_gpio_pads_o connect \gpio_oe \main_gpio_pads_oe @@ -281330,8 +284461,8 @@ module \ls180 connect \main_spimaster18_status \main_spimaster5_miso connect \main_spimaster6_cs \main_spimaster21_storage connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4227$603_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4228$605_Y + connect \main_spimaster31_clk_rise $eq$ls180.v:4325$718_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4326$720_Y connect \main_spisdcard_start0 \main_spisdcard_start1 connect \main_spisdcard_length0 \main_spisdcard_length1 connect \main_spisdcard_mosi \main_spisdcard_mosi_storage @@ -281339,19 +284470,19 @@ module \ls180 connect \main_spisdcard_miso_status \main_spisdcard_miso connect \main_spisdcard_cs \main_spisdcard_cs_storage connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4285$611_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4286$613_Y + connect \main_spisdcard_clk_rise $eq$ls180.v:4383$726_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4384$728_Y connect \main_spisdcard_clk_divider0 \main_spimaster1_storage connect \i2c_scl \main_i2c_scl connect \i2c_sda_oe \main_i2c_oe connect \i2c_sda_o \main_i2c_sda0 connect \main_i2c_sda1 \i2c_sda_i connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4342$621_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4343$625_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4344$629_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4345$633_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4346$637_Y + connect \main_sdphy_sdpads_clk $or$ls180.v:4440$736_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4441$740_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4442$744_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4443$748_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4444$752_Y connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce @@ -281372,8 +284503,8 @@ module \ls180 connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4367$638_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4397$641_Y + connect \main_sdphy_clocker_stop $or$ls180.v:4465$753_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4495$756_Y connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first @@ -281385,8 +284516,8 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4520$651_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4521$653_Y + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4618$766_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4619$768_Y connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready @@ -281403,10 +284534,10 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4538$655_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4636$770_Y connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4540$656_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4541$658_Y + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4638$771_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4639$773_Y connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first @@ -281418,8 +284549,8 @@ module \ls180 connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4647$673_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4648$674_Y + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4745$788_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4746$789_Y connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready @@ -281436,10 +284567,10 @@ module \ls180 connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4665$676_Y + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4763$791_Y connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4667$677_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4668$679_Y + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4765$792_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4766$794_Y connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first @@ -281451,8 +284582,8 @@ module \ls180 connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4781$688_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4782$689_Y + connect \main_sdphy_datar_datar_start $eq$ls180.v:4879$803_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4880$804_Y connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready @@ -281469,10 +284600,10 @@ module \ls180 connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4799$691_Y + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4897$806_Y connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4801$692_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4802$694_Y + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4899$807_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4900$809_Y connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first @@ -281486,88 +284617,88 @@ module \ls180 connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:4918$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_data_event_status { $not$ls180.v:5016$824_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } connect \main_sdcore_crc7_inserter_clr 1'1 connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4922$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4922$710_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4923$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4923$713_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4924$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4924$716_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4925$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4925$719_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4926$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4926$722_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4927$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4927$725_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4928$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4928$728_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4929$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4929$731_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4930$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4930$734_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4931$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4931$737_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4932$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4932$740_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4933$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4933$743_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4934$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4934$746_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4935$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4935$749_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4936$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4936$752_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4937$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4937$755_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4938$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4938$758_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4939$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4939$761_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4940$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4940$764_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4941$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4941$767_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4942$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4942$770_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4943$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4943$773_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4944$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4944$776_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4945$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4945$779_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4946$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4946$782_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4947$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4947$785_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4948$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4948$788_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4949$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4949$791_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4950$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4950$794_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4951$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4951$797_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4952$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4952$800_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4953$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4953$803_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4954$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4954$806_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4955$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4955$809_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4956$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4956$812_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4957$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4957$815_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4958$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4958$818_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4959$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4959$821_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4960$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4960$824_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4961$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4961$827_Y } + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5020$827_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5020$825_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5021$830_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5021$828_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5022$833_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5022$831_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5023$836_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5023$834_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5024$839_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5024$837_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5025$842_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5025$840_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5026$845_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5026$843_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5027$848_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5027$846_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5028$851_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5028$849_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5029$854_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5029$852_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5030$857_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5030$855_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5031$860_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5031$858_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5032$863_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5032$861_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5033$866_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5033$864_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5034$869_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5034$867_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5035$872_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5035$870_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5036$875_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5036$873_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5037$878_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5037$876_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5038$881_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5038$879_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5039$884_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5039$882_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5040$887_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5040$885_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5041$890_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5041$888_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5042$893_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5042$891_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5043$896_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5043$894_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5044$899_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5044$897_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5045$902_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5045$900_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5046$905_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5046$903_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5047$908_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5047$906_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5048$911_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5048$909_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5049$914_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5049$912_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5050$917_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5050$915_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5051$920_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5051$918_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5052$923_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5052$921_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5053$926_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5053$924_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5054$929_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5054$927_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5055$932_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5055$930_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5056$935_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5056$933_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5057$938_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5057$936_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5058$941_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5058$939_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5059$944_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5059$942_Y } connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4971$832_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4972$833_Y + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5069$947_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5070$948_Y connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4974$835_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4975$836_Y + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5072$950_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5073$951_Y connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4977$838_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4978$839_Y + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5075$953_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5076$954_Y connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4980$841_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4981$842_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4982$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4982$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4982$843_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4983$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4983$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4983$848_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4992$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4992$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4992$854_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4993$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4993$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4993$859_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5002$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5002$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5002$865_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5003$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5003$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5003$870_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5012$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5012$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5012$876_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5013$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5013$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5013$881_Y } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5078$956_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5079$957_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5080$962_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5080$960_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5080$958_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5081$967_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5081$965_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5081$963_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5090$973_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5090$971_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5090$969_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5091$978_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5091$976_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5091$974_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5100$984_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5100$982_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5100$980_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5101$989_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5101$987_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5101$985_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5110$995_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5110$993_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5110$991_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5111$1000_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5111$998_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5111$996_Y } connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5109$901_Y + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5207$1016_Y connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5119$904_Y + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5217$1019_Y connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5129$907_Y + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5227$1022_Y connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5139$910_Y + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5237$1025_Y connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5164$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5164$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5164$918_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5165$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5165$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5165$923_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5174$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5174$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5174$929_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5175$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5175$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5175$934_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5184$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5184$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5184$940_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5185$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5185$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5185$945_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5194$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5194$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5194$951_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5195$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5195$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5195$956_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5262$1037_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5262$1035_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5262$1033_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5263$1042_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5263$1040_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5263$1038_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5272$1048_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5272$1046_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5272$1044_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5273$1053_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5273$1051_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5273$1049_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5282$1059_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5282$1057_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5282$1055_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5283$1064_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5283$1062_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5283$1060_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5292$1070_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5292$1068_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5292$1066_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5293$1075_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5293$1073_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5293$1071_Y } connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first @@ -281596,30 +284727,30 @@ module \ls180 connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5431$990_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5432$991_Y + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5529$1105_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5530$1106_Y connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5435$992_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5436$993_Y + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5533$1107_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5534$1108_Y connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5442$995_Y + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5540$1110_Y connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5444$996_Y + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5542$1111_Y connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_we 1'1 - connect \main_interface0_bus_sel 4'1111 + connect \main_interface0_bus_sel 8'11111111 connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address - connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack - connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] - connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5454$997_Y + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] + connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5552$1112_Y connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first @@ -281635,21 +284766,21 @@ module \ls180 connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data - connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] - connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] + connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5513$1004_Y + connect \main_sdmem2block_dma_reset $not$ls180.v:5611$1119_Y connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5594$1012_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5595$1013_Y + connect \main_sdmem2block_converter_first $eq$ls180.v:5692$1127_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5693$1128_Y connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5597$1014_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5598$1015_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5599$1016_Y + connect \main_sdmem2block_converter_source_first $and$ls180.v:5695$1129_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5696$1130_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5697$1131_Y connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout @@ -281664,107 +284795,131 @@ module \ls180 connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5639$1021_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5640$1022_Y + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5749$1136_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5750$1137_Y connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5643$1023_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5644$1024_Y + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5753$1138_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5754$1139_Y connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 connect \builder_shared_stb \builder_comb_rhs_array_muxed28 connect \builder_shared_we \builder_comb_rhs_array_muxed29 connect \builder_shared_cti \builder_comb_rhs_array_muxed30 connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r - connect \main_interface0_bus_dat_r \builder_shared_dat_r - connect \main_interface1_bus_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5695$1030_Y - connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5696$1032_Y - connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5697$1034_Y - connect \main_interface0_bus_ack $and$ls180.v:5698$1036_Y - connect \main_interface1_bus_ack $and$ls180.v:5699$1038_Y - connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5700$1040_Y - connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5701$1042_Y - connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5702$1044_Y - connect \main_interface0_bus_err $and$ls180.v:5703$1046_Y - connect \main_interface1_bus_err $and$ls180.v:5704$1048_Y - connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5805$1145_Y + connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5806$1147_Y + connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5807$1149_Y + connect \main_interface0_bus_ack $and$ls180.v:5808$1151_Y + connect \main_interface1_bus_ack $and$ls180.v:5809$1153_Y + connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5810$1155_Y + connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5811$1157_Y + connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5812$1159_Y + connect \main_interface0_bus_err $and$ls180.v:5813$1161_Y + connect \main_interface1_bus_err $and$ls180.v:5814$1163_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w - connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_libresocsim_ram_bus_stb \builder_shared_stb connect \main_libresocsim_ram_bus_we \builder_shared_we connect \main_libresocsim_ram_bus_cti \builder_shared_cti connect \main_libresocsim_ram_bus_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte - connect \main_wb_sdram_adr \builder_shared_adr - connect \main_wb_sdram_dat_w \builder_shared_dat_w - connect \main_wb_sdram_sel \builder_shared_sel - connect \main_wb_sdram_stb \builder_shared_stb - connect \main_wb_sdram_we \builder_shared_we - connect \main_wb_sdram_cti \builder_shared_cti - connect \main_wb_sdram_bte \builder_shared_bte - connect \builder_libresocsim_wishbone_adr \builder_shared_adr - connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w - connect \builder_libresocsim_wishbone_sel \builder_shared_sel - connect \builder_libresocsim_wishbone_stb \builder_shared_stb - connect \builder_libresocsim_wishbone_we \builder_shared_we - connect \builder_libresocsim_wishbone_cti \builder_shared_cti - connect \builder_libresocsim_wishbone_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5749$1055_Y - connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5750$1056_Y - connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5751$1057_Y - connect \main_wb_sdram_cyc $and$ls180.v:5752$1058_Y - connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5753$1059_Y - connect \builder_shared_err $or$ls180.v:5754$1063_Y - connect \builder_wait $and$ls180.v:5755$1066_Y - connect \builder_done $eq$ls180.v:5768$1081_Y - connect \builder_csrbank0_sel $eq$ls180.v:5769$1082_Y + connect \main_interface0_ram_bus_adr \builder_shared_adr + connect \main_interface0_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_ram_bus_stb \builder_shared_stb + connect \main_interface0_ram_bus_we \builder_shared_we + connect \main_interface0_ram_bus_cti \builder_shared_cti + connect \main_interface0_ram_bus_bte \builder_shared_bte + connect \main_interface1_ram_bus_adr \builder_shared_adr + connect \main_interface1_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_ram_bus_stb \builder_shared_stb + connect \main_interface1_ram_bus_we \builder_shared_we + connect \main_interface1_ram_bus_cti \builder_shared_cti + connect \main_interface1_ram_bus_bte \builder_shared_bte + connect \main_interface2_ram_bus_adr \builder_shared_adr + connect \main_interface2_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface2_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface2_ram_bus_stb \builder_shared_stb + connect \main_interface2_ram_bus_we \builder_shared_we + connect \main_interface2_ram_bus_cti \builder_shared_cti + connect \main_interface2_ram_bus_bte \builder_shared_bte + connect \main_interface0_converted_interface_adr \builder_shared_adr + connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_converted_interface_stb \builder_shared_stb + connect \main_interface0_converted_interface_we \builder_shared_we + connect \main_interface0_converted_interface_cti \builder_shared_cti + connect \main_interface0_converted_interface_bte \builder_shared_bte + connect \main_interface1_converted_interface_adr \builder_shared_adr + connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_converted_interface_stb \builder_shared_stb + connect \main_interface1_converted_interface_we \builder_shared_we + connect \main_interface1_converted_interface_cti \builder_shared_cti + connect \main_interface1_converted_interface_bte \builder_shared_bte + connect \main_socbushandler_converted_interface_adr \builder_shared_adr + connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_socbushandler_converted_interface_stb \builder_shared_stb + connect \main_socbushandler_converted_interface_we \builder_shared_we + connect \main_socbushandler_converted_interface_cti \builder_shared_cti + connect \main_socbushandler_converted_interface_bte \builder_shared_bte + connect \builder_libresocsim_converted_interface_adr \builder_shared_adr + connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \builder_libresocsim_converted_interface_stb \builder_shared_stb + connect \builder_libresocsim_converted_interface_we \builder_shared_we + connect \builder_libresocsim_converted_interface_cti \builder_shared_cti + connect \builder_libresocsim_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5883$1173_Y + connect \main_interface0_ram_bus_cyc $and$ls180.v:5884$1174_Y + connect \main_interface1_ram_bus_cyc $and$ls180.v:5885$1175_Y + connect \main_interface2_ram_bus_cyc $and$ls180.v:5886$1176_Y + connect \main_interface0_converted_interface_cyc $and$ls180.v:5887$1177_Y + connect \main_interface1_converted_interface_cyc $and$ls180.v:5888$1178_Y + connect \main_socbushandler_converted_interface_cyc $and$ls180.v:5889$1179_Y + connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:5890$1180_Y + connect \builder_shared_err $or$ls180.v:5891$1187_Y + connect \builder_wait $and$ls180.v:5892$1190_Y + connect \builder_done $eq$ls180.v:5905$1214_Y + connect \builder_csrbank0_sel $eq$ls180.v:5906$1215_Y connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5771$1085_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5772$1089_Y + connect \builder_csrbank0_reset0_re $and$ls180.v:5908$1218_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5909$1222_Y connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5774$1092_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5775$1096_Y + connect \builder_csrbank0_scratch3_re $and$ls180.v:5911$1225_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5912$1229_Y connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5777$1099_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5778$1103_Y + connect \builder_csrbank0_scratch2_re $and$ls180.v:5914$1232_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5915$1236_Y connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5780$1106_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5781$1110_Y + connect \builder_csrbank0_scratch1_re $and$ls180.v:5917$1239_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5918$1243_Y connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5783$1113_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5784$1117_Y + connect \builder_csrbank0_scratch0_re $and$ls180.v:5920$1246_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5921$1250_Y connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5786$1120_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5787$1124_Y + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5923$1253_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5924$1257_Y connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5789$1127_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5790$1131_Y + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5926$1260_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5927$1264_Y connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5792$1134_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5793$1138_Y + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5929$1267_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5930$1271_Y connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5795$1141_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5796$1145_Y + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5932$1274_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5933$1278_Y connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] @@ -281775,25 +284930,25 @@ module \ls180 connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5807$1146_Y + connect \builder_csrbank1_sel $eq$ls180.v:5944$1279_Y connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:5809$1149_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:5810$1153_Y + connect \builder_csrbank1_oe1_re $and$ls180.v:5946$1282_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5947$1286_Y connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:5812$1156_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:5813$1160_Y + connect \builder_csrbank1_oe0_re $and$ls180.v:5949$1289_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5950$1293_Y connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:5815$1163_Y - connect \builder_csrbank1_in1_we $and$ls180.v:5816$1167_Y + connect \builder_csrbank1_in1_re $and$ls180.v:5952$1296_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5953$1300_Y connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:5818$1170_Y - connect \builder_csrbank1_in0_we $and$ls180.v:5819$1174_Y + connect \builder_csrbank1_in0_re $and$ls180.v:5955$1303_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5956$1307_Y connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:5821$1177_Y - connect \builder_csrbank1_out1_we $and$ls180.v:5822$1181_Y + connect \builder_csrbank1_out1_re $and$ls180.v:5958$1310_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5959$1314_Y connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:5824$1184_Y - connect \builder_csrbank1_out0_we $and$ls180.v:5825$1188_Y + connect \builder_csrbank1_out0_re $and$ls180.v:5961$1317_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5962$1321_Y connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] connect \builder_csrbank1_in1_w \main_gpio_status [15:8] @@ -281801,13 +284956,13 @@ module \ls180 connect \main_gpio_we \builder_csrbank1_in0_we connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:5833$1189_Y + connect \builder_csrbank2_sel $eq$ls180.v:5970$1322_Y connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:5835$1192_Y - connect \builder_csrbank2_w0_we $and$ls180.v:5836$1196_Y + connect \builder_csrbank2_w0_re $and$ls180.v:5972$1325_Y + connect \builder_csrbank2_w0_we $and$ls180.v:5973$1329_Y connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:5838$1199_Y - connect \builder_csrbank2_r_we $and$ls180.v:5839$1203_Y + connect \builder_csrbank2_r_re $and$ls180.v:5975$1332_Y + connect \builder_csrbank2_r_we $and$ls180.v:5976$1336_Y connect \main_i2c_scl \main_i2c_storage [0] connect \main_i2c_oe \main_i2c_storage [1] connect \main_i2c_sda0 \main_i2c_storage [2] @@ -281815,34 +284970,34 @@ module \ls180 connect \main_i2c_status \main_i2c_sda1 connect \builder_csrbank2_r_w \main_i2c_status connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:5847$1204_Y + connect \builder_csrbank3_sel $eq$ls180.v:5984$1337_Y connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:5849$1207_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:5850$1211_Y + connect \builder_csrbank3_enable0_re $and$ls180.v:5986$1340_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5987$1344_Y connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:5852$1214_Y - connect \builder_csrbank3_width3_we $and$ls180.v:5853$1218_Y + connect \builder_csrbank3_width3_re $and$ls180.v:5989$1347_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5990$1351_Y connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:5855$1221_Y - connect \builder_csrbank3_width2_we $and$ls180.v:5856$1225_Y + connect \builder_csrbank3_width2_re $and$ls180.v:5992$1354_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5993$1358_Y connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:5858$1228_Y - connect \builder_csrbank3_width1_we $and$ls180.v:5859$1232_Y + connect \builder_csrbank3_width1_re $and$ls180.v:5995$1361_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5996$1365_Y connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:5861$1235_Y - connect \builder_csrbank3_width0_we $and$ls180.v:5862$1239_Y + connect \builder_csrbank3_width0_re $and$ls180.v:5998$1368_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5999$1372_Y connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:5864$1242_Y - connect \builder_csrbank3_period3_we $and$ls180.v:5865$1246_Y + connect \builder_csrbank3_period3_re $and$ls180.v:6001$1375_Y + connect \builder_csrbank3_period3_we $and$ls180.v:6002$1379_Y connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:5867$1249_Y - connect \builder_csrbank3_period2_we $and$ls180.v:5868$1253_Y + connect \builder_csrbank3_period2_re $and$ls180.v:6004$1382_Y + connect \builder_csrbank3_period2_we $and$ls180.v:6005$1386_Y connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:5870$1256_Y - connect \builder_csrbank3_period1_we $and$ls180.v:5871$1260_Y + connect \builder_csrbank3_period1_re $and$ls180.v:6007$1389_Y + connect \builder_csrbank3_period1_we $and$ls180.v:6008$1393_Y connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:5873$1263_Y - connect \builder_csrbank3_period0_we $and$ls180.v:5874$1267_Y + connect \builder_csrbank3_period0_re $and$ls180.v:6010$1396_Y + connect \builder_csrbank3_period0_we $and$ls180.v:6011$1400_Y connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] @@ -281852,34 +285007,34 @@ module \ls180 connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:5884$1268_Y + connect \builder_csrbank4_sel $eq$ls180.v:6021$1401_Y connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:5886$1271_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:5887$1275_Y + connect \builder_csrbank4_enable0_re $and$ls180.v:6023$1404_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:6024$1408_Y connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:5889$1278_Y - connect \builder_csrbank4_width3_we $and$ls180.v:5890$1282_Y + connect \builder_csrbank4_width3_re $and$ls180.v:6026$1411_Y + connect \builder_csrbank4_width3_we $and$ls180.v:6027$1415_Y connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:5892$1285_Y - connect \builder_csrbank4_width2_we $and$ls180.v:5893$1289_Y + connect \builder_csrbank4_width2_re $and$ls180.v:6029$1418_Y + connect \builder_csrbank4_width2_we $and$ls180.v:6030$1422_Y connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:5895$1292_Y - connect \builder_csrbank4_width1_we $and$ls180.v:5896$1296_Y + connect \builder_csrbank4_width1_re $and$ls180.v:6032$1425_Y + connect \builder_csrbank4_width1_we $and$ls180.v:6033$1429_Y connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:5898$1299_Y - connect \builder_csrbank4_width0_we $and$ls180.v:5899$1303_Y + connect \builder_csrbank4_width0_re $and$ls180.v:6035$1432_Y + connect \builder_csrbank4_width0_we $and$ls180.v:6036$1436_Y connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:5901$1306_Y - connect \builder_csrbank4_period3_we $and$ls180.v:5902$1310_Y + connect \builder_csrbank4_period3_re $and$ls180.v:6038$1439_Y + connect \builder_csrbank4_period3_we $and$ls180.v:6039$1443_Y connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:5904$1313_Y - connect \builder_csrbank4_period2_we $and$ls180.v:5905$1317_Y + connect \builder_csrbank4_period2_re $and$ls180.v:6041$1446_Y + connect \builder_csrbank4_period2_we $and$ls180.v:6042$1450_Y connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:5907$1320_Y - connect \builder_csrbank4_period1_we $and$ls180.v:5908$1324_Y + connect \builder_csrbank4_period1_re $and$ls180.v:6044$1453_Y + connect \builder_csrbank4_period1_we $and$ls180.v:6045$1457_Y connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:5910$1327_Y - connect \builder_csrbank4_period0_we $and$ls180.v:5911$1331_Y + connect \builder_csrbank4_period0_re $and$ls180.v:6047$1460_Y + connect \builder_csrbank4_period0_we $and$ls180.v:6048$1464_Y connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] @@ -281889,52 +285044,52 @@ module \ls180 connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:5921$1332_Y + connect \builder_csrbank5_sel $eq$ls180.v:6058$1465_Y connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:5923$1335_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:5924$1339_Y + connect \builder_csrbank5_dma_base7_re $and$ls180.v:6060$1468_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:6061$1472_Y connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:5926$1342_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:5927$1346_Y + connect \builder_csrbank5_dma_base6_re $and$ls180.v:6063$1475_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:6064$1479_Y connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:5929$1349_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:5930$1353_Y + connect \builder_csrbank5_dma_base5_re $and$ls180.v:6066$1482_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:6067$1486_Y connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:5932$1356_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:5933$1360_Y + connect \builder_csrbank5_dma_base4_re $and$ls180.v:6069$1489_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:6070$1493_Y connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:5935$1363_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:5936$1367_Y + connect \builder_csrbank5_dma_base3_re $and$ls180.v:6072$1496_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:6073$1500_Y connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:5938$1370_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:5939$1374_Y + connect \builder_csrbank5_dma_base2_re $and$ls180.v:6075$1503_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:6076$1507_Y connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:5941$1377_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:5942$1381_Y + connect \builder_csrbank5_dma_base1_re $and$ls180.v:6078$1510_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:6079$1514_Y connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:5944$1384_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:5945$1388_Y + connect \builder_csrbank5_dma_base0_re $and$ls180.v:6081$1517_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:6082$1521_Y connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:5947$1391_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:5948$1395_Y + connect \builder_csrbank5_dma_length3_re $and$ls180.v:6084$1524_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:6085$1528_Y connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:5950$1398_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:5951$1402_Y + connect \builder_csrbank5_dma_length2_re $and$ls180.v:6087$1531_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:6088$1535_Y connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:5953$1405_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:5954$1409_Y + connect \builder_csrbank5_dma_length1_re $and$ls180.v:6090$1538_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:6091$1542_Y connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:5956$1412_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:5957$1416_Y + connect \builder_csrbank5_dma_length0_re $and$ls180.v:6093$1545_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:6094$1549_Y connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5959$1419_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5960$1423_Y + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6096$1552_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6097$1556_Y connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:5962$1426_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:5963$1430_Y + connect \builder_csrbank5_dma_done_re $and$ls180.v:6099$1559_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:6100$1563_Y connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5965$1433_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5966$1437_Y + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6102$1566_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6103$1570_Y connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] @@ -281951,106 +285106,106 @@ module \ls180 connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:5983$1438_Y + connect \builder_csrbank6_sel $eq$ls180.v:6120$1571_Y connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5985$1441_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5986$1445_Y + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6122$1574_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6123$1578_Y connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5988$1448_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5989$1452_Y + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6125$1581_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6126$1585_Y connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5991$1455_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5992$1459_Y + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6128$1588_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6129$1592_Y connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5994$1462_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5995$1466_Y + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6131$1595_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6132$1599_Y connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5997$1469_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5998$1473_Y + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6134$1602_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6135$1606_Y connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6000$1476_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6001$1480_Y + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6137$1609_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6138$1613_Y connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6003$1483_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6004$1487_Y + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6140$1616_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6141$1620_Y connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6006$1490_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6007$1494_Y + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6143$1623_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6144$1627_Y connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6009$1497_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6010$1501_Y + connect \main_sdcore_cmd_send_re $and$ls180.v:6146$1630_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6147$1634_Y connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6012$1504_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6013$1508_Y + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6149$1637_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6150$1641_Y connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6015$1511_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6016$1515_Y + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6152$1644_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6153$1648_Y connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6018$1518_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6019$1522_Y + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6155$1651_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6156$1655_Y connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6021$1525_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6022$1529_Y + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6158$1658_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6159$1662_Y connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6024$1532_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6025$1536_Y + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6161$1665_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6162$1669_Y connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6027$1539_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6028$1543_Y + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6164$1672_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6165$1676_Y connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6030$1546_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6031$1550_Y + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6167$1679_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6168$1683_Y connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6033$1553_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6034$1557_Y + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6170$1686_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6171$1690_Y connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6036$1560_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6037$1564_Y + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6173$1693_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6174$1697_Y connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6039$1567_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6040$1571_Y + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6176$1700_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6177$1704_Y connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6042$1574_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6043$1578_Y + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6179$1707_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6180$1711_Y connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6045$1581_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6046$1585_Y + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6182$1714_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6183$1718_Y connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6048$1588_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6049$1592_Y + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6185$1721_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6186$1725_Y connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6051$1595_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6052$1599_Y + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6188$1728_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6189$1732_Y connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6054$1602_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6055$1606_Y + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6191$1735_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6192$1739_Y connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6057$1609_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6058$1613_Y + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6194$1742_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6195$1746_Y connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6060$1616_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6061$1620_Y + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6197$1749_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6198$1753_Y connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6063$1623_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6064$1627_Y + connect \builder_csrbank6_data_event_re $and$ls180.v:6200$1756_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6201$1760_Y connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6066$1630_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6067$1634_Y + connect \builder_csrbank6_block_length1_re $and$ls180.v:6203$1763_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6204$1767_Y connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6069$1637_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6070$1641_Y + connect \builder_csrbank6_block_length0_re $and$ls180.v:6206$1770_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6207$1774_Y connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6072$1644_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6073$1648_Y + connect \builder_csrbank6_block_count3_re $and$ls180.v:6209$1777_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6210$1781_Y connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6075$1651_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6076$1655_Y + connect \builder_csrbank6_block_count2_re $and$ls180.v:6212$1784_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6213$1788_Y connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6078$1658_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6079$1662_Y + connect \builder_csrbank6_block_count1_re $and$ls180.v:6215$1791_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6216$1795_Y connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6081$1665_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6082$1669_Y + connect \builder_csrbank6_block_count0_re $and$ls180.v:6218$1798_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6219$1802_Y connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] @@ -282086,64 +285241,64 @@ module \ls180 connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6118$1670_Y + connect \builder_csrbank7_sel $eq$ls180.v:6255$1803_Y connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6120$1673_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6121$1677_Y + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6257$1806_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6258$1810_Y connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6123$1680_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6124$1684_Y + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6260$1813_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6261$1817_Y connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6126$1687_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6127$1691_Y + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6263$1820_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6264$1824_Y connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6129$1694_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6130$1698_Y + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6266$1827_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6267$1831_Y connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6132$1701_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6133$1705_Y + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6269$1834_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6270$1838_Y connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6135$1708_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6136$1712_Y + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6272$1841_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6273$1845_Y connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6138$1715_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6139$1719_Y + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6275$1848_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6276$1852_Y connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6141$1722_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6142$1726_Y + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6278$1855_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6279$1859_Y connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6144$1729_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6145$1733_Y + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6281$1862_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6282$1866_Y connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6147$1736_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6148$1740_Y + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6284$1869_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6285$1873_Y connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6150$1743_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6151$1747_Y + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6287$1876_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6288$1880_Y connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6153$1750_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6154$1754_Y + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6290$1883_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6291$1887_Y connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6156$1757_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6157$1761_Y + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6293$1890_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6294$1894_Y connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6159$1764_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6160$1768_Y + connect \builder_csrbank7_dma_done_re $and$ls180.v:6296$1897_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6297$1901_Y connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6162$1771_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6163$1775_Y + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6299$1904_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6300$1908_Y connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6165$1778_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6166$1782_Y + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6302$1911_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6303$1915_Y connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6168$1785_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6169$1789_Y + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6305$1918_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6306$1922_Y connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6171$1792_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6172$1796_Y + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6308$1925_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6309$1929_Y connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6174$1799_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6175$1803_Y + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6311$1932_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6312$1936_Y connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] @@ -282165,54 +285320,54 @@ module \ls180 connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6197$1804_Y + connect \builder_csrbank8_sel $eq$ls180.v:6334$1937_Y connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6199$1807_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6200$1811_Y + connect \builder_csrbank8_card_detect_re $and$ls180.v:6336$1940_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6337$1944_Y connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6202$1814_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6203$1818_Y + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6339$1947_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6340$1951_Y connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6205$1821_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6206$1825_Y + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6342$1954_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6343$1958_Y connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6208$1828_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6209$1832_Y + connect \main_sdphy_init_initialize_re $and$ls180.v:6345$1961_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6346$1965_Y connect \builder_csrbank8_card_detect_w \main_sdphy_status connect \main_sdphy_we \builder_csrbank8_card_detect_we connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6214$1833_Y + connect \builder_csrbank9_sel $eq$ls180.v:6351$1966_Y connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6216$1836_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6217$1840_Y + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6353$1969_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6354$1973_Y connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6219$1843_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6220$1847_Y + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6356$1976_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6357$1980_Y connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6222$1850_Y - connect \main_sdram_command_issue_we $and$ls180.v:6223$1854_Y + connect \main_sdram_command_issue_re $and$ls180.v:6359$1983_Y + connect \main_sdram_command_issue_we $and$ls180.v:6360$1987_Y connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6225$1857_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6226$1861_Y + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6362$1990_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6363$1994_Y connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6228$1864_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6229$1868_Y + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6365$1997_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6366$2001_Y connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6231$1871_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6232$1875_Y + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6368$2004_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6369$2008_Y connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6234$1878_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6235$1882_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6371$2011_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6372$2015_Y connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6237$1885_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6238$1889_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6374$2018_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6375$2022_Y connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6240$1892_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6241$1896_Y + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6377$2025_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6378$2029_Y connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6243$1899_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6244$1903_Y + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6380$2032_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6381$2036_Y connect \main_sdram_sel \main_sdram_storage [0] connect \main_sdram_cke \main_sdram_storage [1] connect \main_sdram_odt \main_sdram_storage [2] @@ -282227,28 +285382,28 @@ module \ls180 connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6259$1904_Y + connect \builder_csrbank10_sel $eq$ls180.v:6396$2037_Y connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6261$1907_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6262$1911_Y + connect \builder_csrbank10_control1_re $and$ls180.v:6398$2040_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6399$2044_Y connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6264$1914_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6265$1918_Y + connect \builder_csrbank10_control0_re $and$ls180.v:6401$2047_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6402$2051_Y connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6267$1921_Y - connect \builder_csrbank10_status_we $and$ls180.v:6268$1925_Y + connect \builder_csrbank10_status_re $and$ls180.v:6404$2054_Y + connect \builder_csrbank10_status_we $and$ls180.v:6405$2058_Y connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6270$1928_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6271$1932_Y + connect \builder_csrbank10_mosi0_re $and$ls180.v:6407$2061_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6408$2065_Y connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6273$1935_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6274$1939_Y + connect \builder_csrbank10_miso_re $and$ls180.v:6410$2068_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6411$2072_Y connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6276$1942_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6277$1946_Y + connect \builder_csrbank10_cs0_re $and$ls180.v:6413$2075_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6414$2079_Y connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6279$1949_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6280$1953_Y + connect \builder_csrbank10_loopback0_re $and$ls180.v:6416$2082_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6417$2086_Y connect \main_spimaster10_length \main_spimaster11_storage [15:8] connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] @@ -282261,34 +285416,34 @@ module \ls180 connect \main_spimaster20_sel \main_spimaster21_storage connect \builder_csrbank10_cs0_w \main_spimaster21_storage connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6299$1955_Y + connect \builder_csrbank11_sel $eq$ls180.v:6436$2088_Y connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6301$1958_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6302$1962_Y + connect \builder_csrbank11_control1_re $and$ls180.v:6438$2091_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6439$2095_Y connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6304$1965_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6305$1969_Y + connect \builder_csrbank11_control0_re $and$ls180.v:6441$2098_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6442$2102_Y connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6307$1972_Y - connect \builder_csrbank11_status_we $and$ls180.v:6308$1976_Y + connect \builder_csrbank11_status_re $and$ls180.v:6444$2105_Y + connect \builder_csrbank11_status_we $and$ls180.v:6445$2109_Y connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6310$1979_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6311$1983_Y + connect \builder_csrbank11_mosi0_re $and$ls180.v:6447$2112_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6448$2116_Y connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6313$1986_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6314$1990_Y + connect \builder_csrbank11_miso_re $and$ls180.v:6450$2119_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6451$2123_Y connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6316$1993_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6317$1997_Y + connect \builder_csrbank11_cs0_re $and$ls180.v:6453$2126_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6454$2130_Y connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6319$2000_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6320$2004_Y + connect \builder_csrbank11_loopback0_re $and$ls180.v:6456$2133_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6457$2137_Y connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6322$2007_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6323$2011_Y + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6459$2140_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6460$2144_Y connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6325$2014_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6326$2018_Y + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6462$2147_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6463$2151_Y connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] @@ -282303,58 +285458,58 @@ module \ls180 connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6347$2020_Y + connect \builder_csrbank12_sel $eq$ls180.v:6484$2153_Y connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6349$2023_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6350$2027_Y + connect \builder_csrbank12_load3_re $and$ls180.v:6486$2156_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6487$2160_Y connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6352$2030_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6353$2034_Y + connect \builder_csrbank12_load2_re $and$ls180.v:6489$2163_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6490$2167_Y connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6355$2037_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6356$2041_Y + connect \builder_csrbank12_load1_re $and$ls180.v:6492$2170_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6493$2174_Y connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6358$2044_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6359$2048_Y + connect \builder_csrbank12_load0_re $and$ls180.v:6495$2177_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6496$2181_Y connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6361$2051_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6362$2055_Y + connect \builder_csrbank12_reload3_re $and$ls180.v:6498$2184_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6499$2188_Y connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6364$2058_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6365$2062_Y + connect \builder_csrbank12_reload2_re $and$ls180.v:6501$2191_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6502$2195_Y connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6367$2065_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6368$2069_Y + connect \builder_csrbank12_reload1_re $and$ls180.v:6504$2198_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6505$2202_Y connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6370$2072_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6371$2076_Y + connect \builder_csrbank12_reload0_re $and$ls180.v:6507$2205_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6508$2209_Y connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6373$2079_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6374$2083_Y + connect \builder_csrbank12_en0_re $and$ls180.v:6510$2212_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6511$2216_Y connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6376$2086_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6377$2090_Y + connect \builder_csrbank12_update_value0_re $and$ls180.v:6513$2219_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6514$2223_Y connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6379$2093_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6380$2097_Y + connect \builder_csrbank12_value3_re $and$ls180.v:6516$2226_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6517$2230_Y connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6382$2100_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6383$2104_Y + connect \builder_csrbank12_value2_re $and$ls180.v:6519$2233_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6520$2237_Y connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6385$2107_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6386$2111_Y + connect \builder_csrbank12_value1_re $and$ls180.v:6522$2240_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6523$2244_Y connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6388$2114_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6389$2118_Y + connect \builder_csrbank12_value0_re $and$ls180.v:6525$2247_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6526$2251_Y connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6391$2121_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6392$2125_Y + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6528$2254_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6529$2258_Y connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6394$2128_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6395$2132_Y + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6531$2261_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6532$2265_Y connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6397$2135_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6398$2139_Y + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6534$2268_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6535$2272_Y connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] @@ -282371,31 +285526,31 @@ module \ls180 connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] connect \main_libresocsim_value_we \builder_csrbank12_value0_we connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6415$2140_Y + connect \builder_csrbank13_sel $eq$ls180.v:6552$2273_Y connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6417$2143_Y - connect \main_uart_rxtx_we $and$ls180.v:6418$2147_Y + connect \main_uart_rxtx_re $and$ls180.v:6554$2276_Y + connect \main_uart_rxtx_we $and$ls180.v:6555$2280_Y connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6420$2150_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6421$2154_Y + connect \builder_csrbank13_txfull_re $and$ls180.v:6557$2283_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6558$2287_Y connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6423$2157_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6424$2161_Y + connect \builder_csrbank13_rxempty_re $and$ls180.v:6560$2290_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6561$2294_Y connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6426$2164_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6427$2168_Y + connect \main_uart_eventmanager_status_re $and$ls180.v:6563$2297_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6564$2301_Y connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6429$2171_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6430$2175_Y + connect \main_uart_eventmanager_pending_re $and$ls180.v:6566$2304_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6567$2308_Y connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6432$2178_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6433$2182_Y + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6569$2311_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6570$2315_Y connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6435$2185_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6436$2189_Y + connect \builder_csrbank13_txempty_re $and$ls180.v:6572$2318_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6573$2322_Y connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6438$2192_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6439$2196_Y + connect \builder_csrbank13_rxfull_re $and$ls180.v:6575$2325_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6576$2329_Y connect \builder_csrbank13_txfull_w \main_uart_txfull_status connect \main_uart_txfull_we \builder_csrbank13_txfull_we connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status @@ -282405,19 +285560,19 @@ module \ls180 connect \main_uart_txempty_we \builder_csrbank13_txempty_we connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6449$2197_Y + connect \builder_csrbank14_sel $eq$ls180.v:6586$2330_Y connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6451$2200_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6452$2204_Y + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6588$2333_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6589$2337_Y connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6454$2207_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6455$2211_Y + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6591$2340_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6592$2344_Y connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6457$2214_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6458$2218_Y + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6594$2347_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6595$2351_Y connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6460$2221_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6461$2225_Y + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6597$2354_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6598$2358_Y connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] @@ -282471,7 +285626,7 @@ module \ls180 connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6515$2239_Y + connect \builder_csr_interconnect_dat_r $or$ls180.v:6652$2372_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -282548,23 +285703,26 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10055$2693_DATA + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10227$2847_DATA + connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10255$2873_DATA + connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10283$2899_DATA + connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10311$2925_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10073$2700_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10329$2932_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10087$2707_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10343$2939_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10101$2714_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10357$2946_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10115$2721_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10371$2953_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10163$2742_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10419$2974_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10177$2749_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10433$2981_DATA end attribute \src "libresoc.v:135159.1-135217.10" attribute \cells_not_processed 1