From: lkcl <lkcl@web>
Date: Thu, 7 Dec 2023 16:05:42 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df5def64800e31e87d8642c8a528ed70b0161a7e;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 25c62d769..c4dc6701e 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -489,7 +489,16 @@ in sequential Program Order, element 0 being the first.
   depending on whether VLi (VL "inclusive") is set.
 
 Thus the new VL comprises a contiguous vector of results, all of which
-pass the testing criteria (equal to zero, less than zero).
+pass the testing criteria (equal to zero, less than zero). Demonstrated
+approximately in pseudocode:
+
+```
+for i in range(VL):
+   GPR[RT+i], CR[i] = operation(GPR[RA+i]... )
+   if test(CR[i]) == failure:
+      VL = i+VLi
+      break
+```
 
 The CR-based data-driven fail-on-first is new and not
 found in ARM SVE or RVV. At the same time it is also