From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 30 Jun 2016 07:58:13 +0000 (+0200)
Subject: Improved ice40_ffinit error reporting
X-Git-Tag: yosys-0.7~189
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df5ebfa0a0fc6d060caaa21b74a2f1a7b4ba0f86;p=yosys.git

Improved ice40_ffinit error reporting
---

diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index db2100381..8a2c30d6a 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -57,6 +57,7 @@ struct Ice40FfinitPass : public Pass {
 			SigMap sigmap(module);
 			pool<Wire*> init_wires;
 			dict<SigBit, State> initbits;
+			dict<SigBit, SigBit> initbit_to_wire;
 			pool<SigBit> handled_initbits;
 
 			for (auto wire : module->selected_wires())
@@ -78,11 +79,14 @@ struct Ice40FfinitPass : public Pass {
 
 					if (initbits.count(bit)) {
 						if (initbits.at(bit) != val)
-							log_error("Conflicting init values for signal %s.\n", log_signal(bit));
+							log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
+									log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
+									log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
 						continue;
 					}
 
 					initbits[bit] = val;
+					initbit_to_wire[bit] = SigBit(wire, i);
 				}
 			}