From: Chad Versace <chad.versace@intel.com>
Date: Tue, 26 Jan 2016 19:01:24 +0000 (-0800)
Subject: anv/meta: Fix sample mask in clear pipelines
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df5f6d824bb566ba19854af7a1134c2fb95edf17;p=mesa.git

anv/meta: Fix sample mask in clear pipelines

Once we begin emitting the correct sample mask,
genX_3DSTATE_SAMPLE_MASK_pack will hit an assertion if the mask contains
too many bits.
---

diff --git a/src/vulkan/anv_meta_clear.c b/src/vulkan/anv_meta_clear.c
index 470b13480d8..ac369e9f9be 100644
--- a/src/vulkan/anv_meta_clear.c
+++ b/src/vulkan/anv_meta_clear.c
@@ -178,7 +178,7 @@ create_pipeline(struct anv_device *device,
             .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
             .rasterizationSamples = 1, /* FINISHME: Multisampling */
             .sampleShadingEnable = false,
-            .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
+            .pSampleMask = (VkSampleMask[]) { 0x1 },
             .alphaToCoverageEnable = false,
             .alphaToOneEnable = false,
          },