From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Dec 2019 17:24:03 +0000 (-0500)
Subject: Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
X-Git-Tag: working-ls180~913
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df626ee7abca3446225dac9179d7e7f380774b2c;p=yosys.git

Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup

Optimise write_xaiger
---

df626ee7abca3446225dac9179d7e7f380774b2c
diff --cc techlibs/ecp5/synth_ecp5.cc
index b71bb2395,b099c25d3..16ff9c57a
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@@ -314,13 -306,17 +314,18 @@@ struct SynthEcp5Pass : public ScriptPas
  			if (abc2 || help_mode) {
  				run("abc", "      (only if -abc2)");
  			}
 -			std::string techmap_args = "-map +/ecp5/latches_map.v";
 +			std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v";
  			if (abc9)
  				techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
 -			run("techmap " + techmap_args);
 +			if (!asyncprld || abc9)
 +				run("techmap " + techmap_args);
  
  			if (abc9) {
+ 				run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+ 				run("wbflip @abc9_boxes");
+ 				run("techmap -autoproc @abc9_boxes");
+ 				run("aigmap @abc9_boxes");
+ 				run("wbflip @abc9_boxes");
  				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
  				if (nowidelut)
  					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");