From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 20 Nov 2019 19:26:59 +0000 (-0800)
Subject: Fix INIT values
X-Git-Tag: working-ls180~881^2^2~166
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df63d75ff35e1441360a4b28a12b32b3d00f1190;p=yosys.git

Fix INIT values
---

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 95546db37..d2c0abeb6 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -96,7 +96,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire $nextQ;
   FDRE_1 #(
-    .INIT(|0),
+    .INIT(INIT),
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
@@ -205,7 +205,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
@@ -226,10 +226,10 @@ module FDSE (output reg Q, input C, CE, D, S);
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   wire $nextQ;
   FDSE_1 #(
-    .INIT(|0),
+    .INIT(INIT),
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );