From: lkcl Date: Thu, 8 Sep 2022 16:58:37 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~602 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df6c4918e7fb9239eba43d7d50f2858a806e7dc1;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 3aeb65859..9d8a484af 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -1,6 +1,4 @@ -# OpenPOWER Foundation External RFC LS001 - -Links +# OPF ISA WG External RFC LS001 08Sep2022 * * @@ -20,13 +18,11 @@ This proposal is to extend the Power ISA with an Abstract RISC-Paradigm Vectorisation Concept that may be applied to **all and any** suitable Scalar instructions, present and future, in the Scalar Power ISA. The Vectorisation System is called "Simple-V" and the Prefix Format -is called "SVP64". - -**Simple-V is not a Traditional Vector ISA and therefore does not add Vector opcodes of any kind**. +is called "SVP64". **Simple-V is not a Traditional Vector ISA and therefore does not add Vector opcodes**. -An ISA Concept similar to Simple-V was originally invented in 1994 by Peter Hsu -(Architect of the MIPS R8000) but was dropped as MIPS did not have an -Out-of-Order Microarchitecture on which to best exploit it. +An ISA Concept similar to Simple-V was originally invented in 1994 by +Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did +not have an Out-of-Order Microarchitecture on which to best exploit it. Simple-V is designed for Embedded Scenarios right the way through Audio/Visual DSPs to 3D GPUs and Supercomputing. As it does **not**