From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 17 Jun 2014 19:49:59 +0000 (+0200)
Subject: Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
X-Git-Tag: yosys-0.4~586
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df76da8fd710394e7ea999e90994483da223f545;p=yosys.git

Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
---

diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index e2c136ddb..3630b57c7 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -43,3 +43,15 @@ end
 
 endmodule
 
+// ------------------------------------------------------
+
+// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
+module test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
+reg [7:0] dint_c [0:7]; 
+always @(posedge clk)
+  begin
+      {dout_a[0], dint_c[3]} <= din_a;
+  end
+assign dout_b = dint_c[3];
+endmodule
+