From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 30 Oct 2019 13:58:25 +0000 (+0100)
Subject: don't cound exact luts in big muxes; futile and fragile
X-Git-Tag: working-ls180~956^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df8390f5df9868b583ce88a4d2ce41511fab2f7b;p=yosys.git

don't cound exact luts in big muxes; futile and fragile
---

diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index 1cb3d53e6..f7e478c87 100644
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -30,7 +30,6 @@ proc
 equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 5 t:LUT4
 select -assert-count 11 t:IBUF
 select -assert-count 1 t:OBUF
 
@@ -42,8 +41,6 @@ proc
 equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 10 t:LUT4
-select -assert-count 1 t:LUT3
 select -assert-count 20 t:IBUF
 select -assert-count 1 t:OBUF