From: Anton Blanchard <anton@linux.ibm.com>
Date: Mon, 7 Dec 2020 23:50:48 +0000 (+1100)
Subject: Add verilator FPGA target
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df8e1ca2a7a4c59ebaf4fb09a485a641c99c7c80;p=microwatt.git

Add verilator FPGA target

Our Makefiles need some work, but for now create an FPGA target:

make FPGA_TARGET=verilator microwatt-verilator

ghdl and yosys can use containers using PODMAN=1 or DOCKER=1
options.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---

diff --git a/Makefile b/Makefile
index 605c2ae..2ee5d57 100644
--- a/Makefile
+++ b/Makefile
@@ -177,6 +177,13 @@ clkgen=fpga/clk_gen_ecp5.vhd
 toplevel=fpga/top-generic.vhdl
 dmi_dtm=dmi_dtm_dummy.vhdl
 
+ifeq ($(FPGA_TARGET), verilator)
+RESET_LOW=true
+CLK_INPUT=50000000
+CLK_FREQUENCY=50000000
+clkgen=fpga/clk_gen_bypass.vhd
+endif
+
 fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 	fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
 	nonrandom.vhdl