From: Kenneth Graunke Date: Tue, 29 Aug 2017 05:00:12 +0000 (-0700) Subject: i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush(). X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df8f4bfc02d631412632a8bef537a2e4cec4945b;p=mesa.git i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush(). Although we're phasing out brw_emit_mi_flush(), we still use it in some places in order to "flush everything". In a number of those places, we write data to a buffer that we may then bind as an image surface, SSBO, or atomic buffer. Those usages require us to flush the data cache. Reviewed-by: Jason Ekstrand --- diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 063b814b9a3..460b8f73b6d 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -449,6 +449,7 @@ brw_emit_mi_flush(struct brw_context *brw) if (devinfo->gen >= 6) { flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | + PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |