From: Tobias Platen <tplaten@posteo.de>
Date: Mon, 15 Feb 2021 17:07:23 +0000 (+0100)
Subject: test case for MMU SPRs: PID and PRTBL
X-Git-Tag: convert-csv-opcode-to-binary~230
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df9704cfc972b4eebf13ab71fa92b7966fe294b5;p=soc.git

test case for MMU SPRs: PID and PRTBL
---

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
index 9d1836e5..5037ceba 100644
--- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
@@ -21,10 +21,14 @@ class MMUTestCase(TestAccumulatorBase):
                 "mtspr 19, 2",     # reg 2 to DAR
                 "mfspr 1, 18",     # DSISR to reg 1
                 "mfspr 2, 19",     # DAR to reg 2
+                "mtspr 48, 3",    # set MMU PID
+                "mtspr 720, 4",    # set MMU PRTBL
                 "lhz 3, 0(1)"      # load some data
               ]
 
         initial_regs = [0] * 32
+        initial_regs[3] = 1
+        initial_regs[4] = 0xDEADBEEF
         #initial_regs[1] = 0xDEADBEEF
 
         #FIXME initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index add184fb..f3b43950 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -332,7 +332,10 @@ class TestRunner(FHDLTestCase):
             traces += [
                 {'comment': 'microwatt_mmu'},
                 'core.fus.mmu0.alu_mmu0.illegal',
-                'core.fus.mmu0.alu_mmu0.debug0[3:0]'
+                'core.fus.mmu0.alu_mmu0.debug0[3:0]',
+                'core.fus.mmu0.alu_mmu0.mmu.state',
+                'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
+                'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]'
             ]
 
         write_gtkw("issuer_simulator.gtkw",