From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 Jul 2020 22:59:34 +0000 (+0100)
Subject: first attempt running cxxsim
X-Git-Tag: div_pipeline~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df9869d547bc2d099f3d515d8aa901174482d547;p=soc.git

first attempt running cxxsim
---

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 6e48cb2c..bbd496ba 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -1,5 +1,10 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.back.pysim import Delay, Settle
+cxxsim = True
+if cxxsim:
+    from nmigen.sim.cxxsim import Simulator
+else:
+    from nmigen.back.pysim import Simulator
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
@@ -256,9 +261,13 @@ class TestRunner(FHDLTestCase):
                     break
 
         sim.add_sync_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                            traces=[]):
+        print (dir(sim))
+        if cxxsim:
             sim.run()
+        else:
+            with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+                                traces=[]):
+                sim.run()
 
     def check_alu_outputs(self, alu, dec2, sim, code):