From: Jiri Gaisler <jiri@gaisler.se>
Date: Thu, 19 Feb 2015 22:31:20 +0000 (+0100)
Subject: sim/erc32: Corrected wrong CPU implementation and version ID in psr
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df9bc4163b1331c8a4dad6830afeff4ff305a20a;p=binutils-gdb.git

sim/erc32: Corrected wrong CPU implementation and version ID in psr
---

diff --git a/sim/erc32/ChangeLog b/sim/erc32/ChangeLog
index 4a316bcde5d..3757e5b1858 100644
--- a/sim/erc32/ChangeLog
+++ b/sim/erc32/ChangeLog
@@ -1,3 +1,7 @@
+2015-02-21  Jiri Gaisler  <jiri@gaisler.se>
+
+	* exec.c (init_regs): erc32 has vendor ID 1 and version ID 1 in %psr.
+
 2015-02-21  Jiri Gaisler  <jiri@gaisler.se>
 
 	* func.c (print_insn_sparc_sis): Add helper function for disassembly.
diff --git a/sim/erc32/exec.c b/sim/erc32/exec.c
index dc86ba3b8a7..07f35861c4b 100644
--- a/sim/erc32/exec.c
+++ b/sim/erc32/exec.c
@@ -2011,7 +2011,7 @@ init_regs(sregs)
     sregs->npc = 4;
     sregs->trap = 0;
     sregs->psr &= 0x00f03fdf;
-    sregs->psr |= 0x080;	/* Set supervisor bit */
+    sregs->psr |= 0x11000080;	/* Set supervisor bit */
     sregs->breakpoint = 0;
     sregs->annul = 0;
     sregs->fpstate = FP_EXE_MODE;