From: lkcl <lkcl@web>
Date: Mon, 26 Oct 2020 16:26:25 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1948
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfa6a48d92b981ea76bcf9a28c1ae1a680833d30;p=libreriscv.git

---

diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn
index 23a06bb6a..7bc116211 100644
--- a/openpower/sv/predication.mdwn
+++ b/openpower/sv/predication.mdwn
@@ -17,11 +17,13 @@
 * must cover up to 64 elements
 * must still work for elwidth over-rides
 
-# Capabilities
+## Additional Capabilities
 
 * two modes, "zeroing" and "non-zeroing". zeroing mode places a zero in the masked-out element results, where non-zeroing leaves the destination (result) element unmodified.
 * predicate must be invertable via an opcode bit (to avoid the need for an instruction which inverts all bits of the predicate mask)
 
+Implementation note: even in in-order microarchitectures it is strongly adviseable to use byte-level write-enable lines on the register file.  This in combination with 8b-bit SIMD element overrides allows, in "non-zeroing" mode, the predicate mask to be directly ANDed with the regfile write-enable lines to achieve the required functionality.  The alternative is to perform a READ-MODIFY-MASK-WRITE cycle which is costly and compromises performance.  Avoided very simply with byte-level write-enable.
+
 # Proposals
 
 ## Adding new predicate register types and associated opcodes