From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 26 Feb 2019 20:18:48 +0000 (-0800)
Subject: Uncomment out more tests
X-Git-Tag: working-ls180~1237^2~250
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfb23a79dd0e2ffbe4f058eadb552d8194540eef;p=yosys.git

Uncomment out more tests
---

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 8a809e480..eca340693 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -63,30 +63,44 @@ always @(io or oe)
 assign io = oe ? ~latch : 8'bz;
 endmodule
 
-// TODO
-//module abc9_test011(inout [7:0] io, input oe);
-//reg [7:0] latch;
-//always @(io or oe)
-//    if (!oe)
-//        latch[3:0] <= io;
-//    else
-//        latch[7:4] <= io;
-//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
-//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
-//endmodule
-
-// TODO
-//module abc9_test012(inout [7:0] io, input oe);
-//abc9_test012_sub sub(io, oe);
-//endmodule
-//
-//module abc9_test012_sub(inout [7:0] io, input oe);
-//reg [7:0] latch;
+module abc9_test011(inout io, input oe);
+reg latch;
+always @(io or oe)
+    if (!oe)
+        latch <= io;
+//assign io = oe ? ~latch : 8'bz;
+endmodule
+
+module abc9_test012(inout io, input oe);
+reg latch;
 //always @(io or oe)
 //    if (!oe)
-//        latch[3:0] <= io;
-//    else
-//        latch[7:4] <= io;
-//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
-//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
-//endmodule
+//        latch <= io;
+assign io = oe ? ~latch : 8'bz;
+endmodule
+
+module abc9_test013(inout [3:0] io, input oe);
+reg [3:0] latch;
+always @(io or oe)
+    if (!oe)
+        latch[3:0] <= io[3:0];
+    else
+        latch[7:4] <= io;
+assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
+assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
+endmodule
+
+module abc9_test014(inout [7:0] io, input oe);
+abc9_test012_sub sub(io, oe);
+endmodule
+
+module abc9_test012_sub(inout [7:0] io, input oe);
+reg [7:0] latch;
+always @(io or oe)
+    if (!oe)
+        latch[3:0] <= io;
+    else
+        latch[7:4] <= io;
+assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
+assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
+endmodule