From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 30 Aug 2014 16:17:22 +0000 (+0200)
Subject: Fixed module->addPmux()
X-Git-Tag: yosys-0.4~196
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfbd7dd15a1520ce0c01d2722aaacbf7b7be71fa;p=yosys.git

Fixed module->addPmux()
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index df4d8b092..7ba6911a2 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1309,7 +1309,6 @@ DEF_METHOD(LogicOr,  1, "$logic_or")
 	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
 		RTLIL::Cell *cell = addCell(name, _type);                 \
 		cell->parameters["\\WIDTH"] = sig_a.size();               \
-		cell->parameters["\\WIDTH"] = sig_b.size();               \
 		if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size();  \
 		cell->setPort("\\A", sig_a);                              \
 		cell->setPort("\\B", sig_b);                              \