From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 22 Jul 2015 19:44:53 +0000 (+0200)
Subject: litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet... 
X-Git-Tag: 24jan2021_ls180~2201
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfc207aacb32d576e13028e1447d4ab1aafe859d;p=litex.git

litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow)
---

diff --git a/misoclib/com/litepcie/common.py b/misoclib/com/litepcie/common.py
index 4f16c7e6..81f75cb7 100644
--- a/misoclib/com/litepcie/common.py
+++ b/misoclib/com/litepcie/common.py
@@ -63,5 +63,5 @@ def interrupt_layout():
 
 
 def dma_layout(dw):
-    layout = [("dat", dw)]
+    layout = [("data", dw)]
     return EndpointDescription(layout, packetized=True)
diff --git a/misoclib/com/litepcie/frontend/dma/reader.py b/misoclib/com/litepcie/frontend/dma/reader.py
index c2bbfe2f..de39e5e8 100644
--- a/misoclib/com/litepcie/frontend/dma/reader.py
+++ b/misoclib/com/litepcie/frontend/dma/reader.py
@@ -70,7 +70,7 @@ class DMAReader(Module, AutoCSR):
         self.comb += [
             fifo.sink.stb.eq(port.sink.stb),
             fifo.sink.sop.eq(port.sink.sop & (port.sink.user_id != last_user_id)),
-            fifo.sink.dat.eq(port.sink.dat),
+            fifo.sink.data.eq(port.sink.dat),
             port.sink.ack.eq(fifo.sink.ack | ~enable),
         ]
         self.comb += Record.connect(fifo.source, self.source)
diff --git a/misoclib/com/litepcie/frontend/dma/writer.py b/misoclib/com/litepcie/frontend/dma/writer.py
index 0522398e..2f6131d0 100644
--- a/misoclib/com/litepcie/frontend/dma/writer.py
+++ b/misoclib/com/litepcie/frontend/dma/writer.py
@@ -28,7 +28,7 @@ class DMAWriter(Module, AutoCSR):
         self.comb += [
             fifo.we.eq(sink.stb & enable),
             sink.ack.eq(fifo.writable & sink.stb & enable),
-            fifo.din.eq(sink.dat),
+            fifo.din.eq(sink.data),
             fifo.reset.eq(~enable)
         ]