From: lkcl <lkcl@web>
Date: Wed, 1 Sep 2021 11:25:37 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~267
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfc6becad556e565dd1f65e2d572c4ed0f737e6d;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 86f2b7b88..549e98ddb 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -269,6 +269,9 @@ Note:
 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
 is reserved for a future implementation of SV
 
+Note that any operation in Power ISA ending in "s" (`fadds`) shall
+perform its operation at **half** the ELWIDTH.  `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32.
+
 ## Elwidth for CRs:
 
 TODO, important, particularly for crops, mfcr and mtcr, what elwidth