From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 Oct 2018 08:58:22 +0000 (+0100)
Subject: c_beqz sv operational
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfca3fcbe376b8989814ecc705b3ed365c0c9016;p=riscv-isa-sim.git

c_beqz sv operational
---

diff --git a/id_regs.py b/id_regs.py
index a631759..3bbd0b8 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -94,7 +94,7 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
                 # RS1 also matches against RVC_FRS1 (etc.)
                 # check letter before match: if "_", skip it.
                 continue
-            if 'RVC_' in pattern and f[x+len(pattern)-1] == 'S':
+            if 'RVC_' in pattern and f[x+len(pattern)] == 'S':
                 # RVC_RS2S also matches against RVC_RS2 (etc.)
                 # check letter at end of match: if "S", skip it.
                 continue
@@ -208,6 +208,8 @@ if __name__ == '__main__':
                 twin_predication = True
             elif insn in ['c_beqz', 'c_bnez']:
                 txt += "\n#define INSN_TYPE_C_BRANCH\n"
+                txt += "\n#define INSN_TYPE_BRANCH\n"
+                is_branch = 'STD' # standard branch
             elif insn in ['c_mv']:
                 twin_predication = True
             elif insn.startswith("c_"):
diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 2f77612..d301b05 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -68,7 +68,11 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   #include INCLUDEFILE
 #else
 #ifdef INSN_TYPE_BRANCH
+#ifdef INSN_TYPE_C_BRANCH
+  sv_pred_entry *r = insn.get_predentry(0, true); // yes, really taken from x0
+#else
   sv_pred_entry *r = insn.get_predentry(s_insn.rs2(), true);
+#endif
   reg_t _target_reg = 0;
   reg_t *target_reg = NULL;
 #endif
@@ -91,7 +95,11 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
     {
       _target_reg = r->regidx;
       target_reg = &_target_reg;
+#ifdef INSN_TYPE_C_BRANCH
+      insn.predicate(0, true, zeroingtarg);
+#else
       insn.predicate(s_insn.rs2(), true, zeroingtarg);
+#endif
       fprintf(stderr, "branch pred reg %ld pred %lx\n",
                        _target_reg, target_pred);
     }
@@ -130,6 +138,10 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   for (int voffs=0; voffs < vlen; voffs++)
   {
     insn.reset_vloop_check();
+#ifdef INSN_C_BEQZ
+        fprintf(stderr, "pre twin reg %s src %d dest %d pred %lx %lx\n",
+            xstr(INSN), *target_reg, *dest_offs, target_pred, dest_pred);
+#endif
 #ifdef INSN_CATEGORY_TWINPREDICATION
     if (*src_offs >= vlen) {
         break;
@@ -183,6 +195,14 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
                 vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rd()),
                 insn._rd(), insn.rvc_lwsp_imm(), READ_REG(sp));
+#endif
+#ifdef INSN_C_BEQZ
+    fprintf(stderr, "pre %s %x vloop %d %d %d" \
+                      "vlen %d stop %d pred %lx rdv %lx rvc_rs1 %d\n",
+                xstr(INSN), INSNCODE, voffs, *target_reg, *dest_offs,
+                vlen, insn.stop_vloop(),
+                dest_pred & (1<<voffs), READ_REG(insn._rvc_rs1s()),
+                insn._rvc_rs1s());
 #endif
       #include INCLUDEFILE
 #ifdef DEST_PREDINT
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 1dd16d7..4ff8ad1 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -72,6 +72,11 @@ reg_t sv_proc_t::get_rs2()
 
 reg_t sv_proc_t::get_rvc_rs1s()
 {
+    fprintf(stderr, "get_rvc_rs1s %d\n", _insn->rvc_rs1s());
+    sv_reg_entry *r = _insn->get_regentry(_insn->_rvc_rs1s(), true);
+    fprintf(stderr, "active %d vec %d map %d\n",
+                r->active, r->isvec, r->regidx);
+
     return (_insn->p->get_state()->XPR[_insn->rvc_rs1s()]);
 }