From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 28 Feb 2022 10:40:06 +0000 (+0100)
Subject: Quick fix
X-Git-Tag: yosys-0.15~4^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfd4c81eac47bd06fc4f419c43e6fe508b4252df;p=yosys.git

Quick fix
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 304dfef13..1ce563ac2 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1304,6 +1304,8 @@ struct SimWorker : SimShared
 					state = 3;
 					break;
 				default:
+					log("Simulating cycle %d.\n", cycle);
+					top->setState(inputs, line);
 					if (cycle) {
 						set_inports(clock, State::S1);
 						set_inports(clockn, State::S0);