From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 26 Sep 2023 10:56:23 +0000 (+0100)
Subject: Added english language description, spaces and brackets for ldu instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfdefe9e7d1fdb1d610f6b72230afed9162aa353;p=openpower-isa.git

Added english language description, spaces and brackets for ldu instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index a87d6332..2ff1a3b0 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -542,6 +542,16 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA)+ (DS||0b00). The doubleword in storage
+    addressed by EA is loaded into RT.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None