From: lkcl <lkcl@web>
Date: Tue, 24 May 2022 09:01:30 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2132
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfe56f029151b4413451d5ba912a14f0e5040cb5;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 61a3e9dbf..087142d00 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -47,8 +47,13 @@ Pseudocode:
             if src1[i] == src2[j]:
                 result[j] |= 1<<i
 
-*(Idea: implement this as a Triangular Schedule, Vertical-First Mode,
-  using `mfcrweird` and `cmpi`)*
+Idea 1: implement this as a Triangular Schedule, Vertical-First Mode,
+  using `mfcrweird` and `cmpi`. first triangular schedule on src1,
+secpnd on src2.
+
+Idea 2: implement using outer loop on varying setvl Horizontal-First
+with `1<<r3` predicate mask for src2 as scalar, creates CR field vector, transfer into INT with mfcrweird then OR into
+result.
 
 ## iota