From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 11 Nov 2022 08:49:52 +0000 (-0800)
Subject: XLEN-ify maddedu
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dfea968f3e63d5088c3bbf139f8fabaad0d1c8f5;p=openpower-isa.git

XLEN-ify maddedu
---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 02bb5d62..c7050133 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -9,10 +9,10 @@ Pseudo-code:
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
-    prod[0:127] <- (RA) * (RB)
-    sum[0:127] <- ([0] * 64 || (RC)) + prod
-    RT <- sum[64:127]
-    RS <- sum[0:63]
+    prod[0:2*XLEN-1] <- (RA) * (RB)
+    sum[0:2*XLEN-1] <- ([0] * XLEN || (RC)) + prod
+    RT <- sum[XLEN:2*XLEN-1]
+    RS <- sum[0:XLEN-1]
 
 Special Registers Altered: