From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 5 Jul 2015 20:49:23 +0000 (+0200)
Subject: use sets for leave_out
X-Git-Tag: 24jan2021_ls180~2212
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e011f9378fc971749dbcc65aafe5f2ca7830f22e;p=litex.git

use sets for leave_out
---

diff --git a/misoclib/com/liteeth/core/mac/core/preamble.py b/misoclib/com/liteeth/core/mac/core/preamble.py
index b761a673..e4d73469 100644
--- a/misoclib/com/liteeth/core/mac/core/preamble.py
+++ b/misoclib/com/liteeth/core/mac/core/preamble.py
@@ -47,7 +47,7 @@ class LiteEthMACPreambleInserter(Module):
             self.source.last_be.eq(self.sink.last_be)
         ]
         fsm.act("COPY",
-            Record.connect(self.sink, self.source, leave_out=["data", "last_be"]),
+            Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
             self.source.sop.eq(0),
 
             If(self.sink.stb & self.sink.eop & self.source.ack,
@@ -140,7 +140,7 @@ class LiteEthMACPreambleChecker(Module):
             self.source.last_be.eq(self.sink.last_be)
         ]
         fsm.act("COPY",
-            Record.connect(self.sink, self.source, leave_out=["data", "last_be"]),
+            Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
             self.source.sop.eq(sop),
             clr_sop.eq(self.source.stb & self.source.ack),
 
diff --git a/misoclib/mem/litesata/frontend/mirroring.py b/misoclib/mem/litesata/frontend/mirroring.py
index 67d60a89..ef1e626f 100644
--- a/misoclib/mem/litesata/frontend/mirroring.py
+++ b/misoclib/mem/litesata/frontend/mirroring.py
@@ -59,8 +59,8 @@ class LiteSATAMirroringTX(Module):
             read_status = Status(read)
             self.submodules += read_status
             self.comb += [
-                Record.connect(sink, read, leave_out=["stb", "ack"]),
-                Record.connect(sink, write, leave_out=["stb", "ack"]),
+                Record.connect(sink, read, leave_out=set(["stb", "ack"])),
+                Record.connect(sink, write, leave_out=set(["stb", "ack"])),
                 read.stb.eq(sink.stb & (sink.read | sink.identify) & ~read_stall),
                 write.stb.eq(sink.stb & sink.write),
                 If(sink.read | sink.identify,
@@ -127,8 +127,8 @@ class LiteSATAMirroringRX(Module):
             sink_status = Status(sinks[i])
             self.submodules += sink_status
             self.comb += [
-                Record.connect(sinks[i], reads[i], leave_out=["stb", "ack"]),
-                Record.connect(sinks[i], write_striper.sinks[i], leave_out=["stb", "ack"]),
+                Record.connect(sinks[i], reads[i], leave_out=set(["stb", "ack"])),
+                Record.connect(sinks[i], write_striper.sinks[i], leave_out=set(["stb", "ack"])),
                 reads[i].stb.eq(sinks[i].stb & ctrl.reading),
                 write_striper.sinks[i].stb.eq(sinks[i].stb & ctrl.writing),
                 sinks[i].ack.eq(reads[i].ack | write_striper.sinks[i].ack),
diff --git a/misoclib/mem/litesata/frontend/striping.py b/misoclib/mem/litesata/frontend/striping.py
index 8c8cba0d..35edd7e8 100644
--- a/misoclib/mem/litesata/frontend/striping.py
+++ b/misoclib/mem/litesata/frontend/striping.py
@@ -39,7 +39,7 @@ class LiteSATAStripingTX(Module):
 
         # split data and ctrl signals (except stb & ack managed in fsm)
         for i, s in enumerate(sources):
-            self.comb += Record.connect(sink, s, leave_out=["stb", "ack", "data"])
+            self.comb += Record.connect(sink, s, leave_out=set(["stb", "ack", "data"]))
             if mirroring_mode:
                 self.comb += s.data.eq(sink.data)
             else:
@@ -82,7 +82,7 @@ class LiteSATAStripingRX(Module):
         )
 
         # use first sink for ctrl signals (except for stb, ack & failed)
-        self.comb += Record.connect(sinks[0], source, leave_out=["stb", "ack", "failed", "data"])
+        self.comb += Record.connect(sinks[0], source, leave_out=set(["stb", "ack", "failed", "data"]))
 		# combine datas
         if mirroring_mode:
             self.comb += source.data.eq(0) # mirroring only used for writes