From: Gabe Black Date: Wed, 5 Feb 2020 00:19:38 +0000 (-0800) Subject: scons,arch: Remove simple scalar compatibility. X-Git-Tag: v20.0.0.0~526 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e01ead41c2d800300745bc65760e9627c2015a01;p=gem5.git scons,arch: Remove simple scalar compatibility. This was primarily in Alpha where disassmbly output could be compatible (default off, probably not usd in a long time), and floating point could be compatible (default on). A small bit had crept into x86 from long ago which is also removed. Change-Id: Ibb68b63787f370259bd1613b393e0b057c007704 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25012 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/SConstruct b/SConstruct index eb3a9e465..d8158fa4f 100755 --- a/SConstruct +++ b/SConstruct @@ -971,9 +971,6 @@ sticky_vars.AddVariables( sorted(CpuModel.dict.keys())), BoolVariable('EFENCE', 'Link with Electric Fence malloc debugger', False), - BoolVariable('SS_COMPATIBLE_FP', - 'Make floating-point results compatible with SimpleScalar', - False), BoolVariable('USE_SSE2', 'Compile for SSE2 (-msse2) to get IEEE FP on x86 hosts', False), @@ -998,9 +995,9 @@ sticky_vars.AddVariables( ) # These variables get exported to #defines in config/*.hh (see src/SConscript). -export_vars += ['USE_FENV', 'SS_COMPATIBLE_FP', 'TARGET_ISA', 'TARGET_GPU_ISA', - 'CP_ANNOTATE', 'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP', - 'PROTOCOL', 'HAVE_PROTOBUF', 'HAVE_VALGRIND', +export_vars += ['USE_FENV', 'TARGET_ISA', 'TARGET_GPU_ISA', 'CP_ANNOTATE', + 'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP', 'PROTOCOL', + 'HAVE_PROTOBUF', 'HAVE_VALGRIND', 'HAVE_PERF_ATTR_EXCLUDE_HOST', 'USE_PNG', 'NUMBER_BITS_PER_SET', 'USE_HDF5'] diff --git a/build_opts/ALPHA b/build_opts/ALPHA index d1f82ce38..f4e8ae3e1 100644 --- a/build_opts/ALPHA +++ b/build_opts/ALPHA @@ -1,4 +1,3 @@ TARGET_ISA = 'alpha' -SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' PROTOCOL = 'MI_example' diff --git a/build_opts/ALPHA_MESI_Two_Level b/build_opts/ALPHA_MESI_Two_Level index 123b85d83..89b0e1b8b 100644 --- a/build_opts/ALPHA_MESI_Two_Level +++ b/build_opts/ALPHA_MESI_Two_Level @@ -1,3 +1,2 @@ -SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' PROTOCOL = 'MESI_Two_Level' diff --git a/build_opts/ALPHA_MOESI_CMP_directory b/build_opts/ALPHA_MOESI_CMP_directory index 816453ea5..ef00ae156 100644 --- a/build_opts/ALPHA_MOESI_CMP_directory +++ b/build_opts/ALPHA_MOESI_CMP_directory @@ -1,3 +1,2 @@ -SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' PROTOCOL = 'MOESI_CMP_directory' diff --git a/build_opts/ALPHA_MOESI_CMP_token b/build_opts/ALPHA_MOESI_CMP_token index 3851c5126..d3a97edc8 100644 --- a/build_opts/ALPHA_MOESI_CMP_token +++ b/build_opts/ALPHA_MOESI_CMP_token @@ -1,3 +1,2 @@ -SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' PROTOCOL = 'MOESI_CMP_token' diff --git a/build_opts/ALPHA_MOESI_hammer b/build_opts/ALPHA_MOESI_hammer index 4639cacda..91e01d61e 100644 --- a/build_opts/ALPHA_MOESI_hammer +++ b/build_opts/ALPHA_MOESI_hammer @@ -1,3 +1,2 @@ -SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' PROTOCOL = 'MOESI_hammer' diff --git a/build_opts/Garnet_standalone b/build_opts/Garnet_standalone index 46ae29a45..df97b5b31 100644 --- a/build_opts/Garnet_standalone +++ b/build_opts/Garnet_standalone @@ -1,4 +1,3 @@ TARGET_ISA = 'alpha' -SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' PROTOCOL = 'Garnet_standalone' diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa index 8f641a4b4..36418615e 100644 --- a/src/arch/alpha/isa/branch.isa +++ b/src/arch/alpha/isa/branch.isa @@ -175,13 +175,6 @@ output decoder {{ ss << ","; } -#ifdef SS_COMPATIBLE_DISASSEMBLY - if (_numSrcRegs == 0 && _numDestRegs == 0) { - printReg(ss, 31); - ss << ","; - } -#endif - Addr target = pc + 4 + disp; std::string str; @@ -200,13 +193,6 @@ output decoder {{ ccprintf(ss, "%-10s ", mnemonic); -#ifdef SS_COMPATIBLE_DISASSEMBLY - if (_numDestRegs == 0) { - printReg(ss, 31); - ss << ","; - } -#endif - if (_numDestRegs > 0) { printReg(ss, _destRegIdx[0]); ss << ","; diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index abf6fb24a..a61db0bca 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -600,19 +600,11 @@ decode OPCODE default Unknown::unknown() { 0xb: decode FA { 31: decode FP_TYPEFUNC { format FloatingPointOperate { -#if SS_COMPATIBLE_FP - 0x0b: sqrts({{ - if (Fb < 0.0) - fault = std::make_shared(); - Fc = sqrt(Fb); - }}, FloatSqrtOp); -#else 0x0b: sqrts({{ if (Fb_sf < 0.0) fault = std::make_shared(); Fc_sf = sqrt(Fb_sf); }}, FloatSqrtOp); -#endif 0x2b: sqrtt({{ if (Fb < 0.0) fault = std::make_shared(); @@ -644,17 +636,10 @@ decode OPCODE default Unknown::unknown() { // check for valid trapping modes here 0,1,5,7: decode FP_TYPEFUNC { format FloatingPointOperate { -#if SS_COMPATIBLE_FP - 0x00: adds({{ Fc = Fa + Fb; }}); - 0x01: subs({{ Fc = Fa - Fb; }}); - 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); - 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); -#else 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }}); 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }}); 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp); 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp); -#endif 0x20: addt({{ Fc = Fa + Fb; }}); 0x21: subt({{ Fc = Fa - Fb; }}); diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa index 6e03f4654..99d13acc5 100644 --- a/src/arch/alpha/isa/fp.isa +++ b/src/arch/alpha/isa/fp.isa @@ -150,7 +150,6 @@ output decoder {{ { std::string mnem_str(mnemonic); -#ifndef SS_COMPATIBLE_DISASSEMBLY std::string suffix(""); suffix += ((_destRegIdx[0].isFloatReg()) ? fpTrappingModeSuffix[trappingMode] @@ -160,7 +159,6 @@ output decoder {{ if (suffix != "") { mnem_str = csprintf("%s/%s", mnemonic, suffix); } -#endif std::stringstream ss; ccprintf(ss, "%-10s ", mnem_str.c_str()); diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 3f7e1a39a..ab145ebf6 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -47,7 +47,6 @@ output header {{ #include "arch/alpha/faults.hh" #include "arch/alpha/types.hh" -#include "config/ss_compatible_fp.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" #include "mem/request.hh" // some constructors use MemReq flags @@ -64,7 +63,6 @@ output decoder {{ #include "base/cprintf.hh" #include "base/fenv.hh" #include "base/loader/symtab.hh" -#include "config/ss_compatible_fp.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() #include "mem/packet.hh" #include "sim/full_system.hh" @@ -83,7 +81,6 @@ output exec {{ #include "arch/generic/memhelpers.hh" #include "base/cp_annotate.hh" #include "base/fenv.hh" -#include "config/ss_compatible_fp.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" #include "mem/packet.hh" @@ -215,10 +212,6 @@ def operands {{ // output header {{ -// uncomment the following to get SimpleScalar-compatible disassembly -// (useful for diffing output traces). -// #define SS_COMPATIBLE_DISASSEMBLY - /** * Base class for all Alpha static instructions. */ @@ -409,11 +402,7 @@ output decoder {{ std::string Nop::generateDisassembly(Addr pc, const SymbolTable *symtab) const { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return originalDisassembly; -#else return csprintf("%-10s (%s)", "nop", originalDisassembly); -#endif } }}; diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa index 69b8a477b..f48cbfee9 100644 --- a/src/arch/alpha/isa/pal.isa +++ b/src/arch/alpha/isa/pal.isa @@ -59,11 +59,7 @@ output decoder {{ EmulatedCallPal::generateDisassembly(Addr pc, const SymbolTable *symtab) const { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return csprintf("%s %s", "call_pal", mnemonic); -#else return csprintf("%-10s %s", "call_pal", mnemonic); -#endif } }}; @@ -179,9 +175,6 @@ output decoder {{ std::string HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB); -#else // HW_LDST_LOCK and HW_LDST_COND are the same bit. const char *lock_str = (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : ""; @@ -193,7 +186,6 @@ output decoder {{ HW_LDST_QUAD ? ",QUAD" : "", HW_LDST_VPTE ? ",VPTE" : "", lock_str); -#endif } }}; diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa index e5a773d70..011a90c3c 100644 --- a/src/arch/alpha/isa/unimp.isa +++ b/src/arch/alpha/isa/unimp.isa @@ -103,11 +103,7 @@ output decoder {{ WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return csprintf("%-10s", mnemonic); -#else return csprintf("%-10s (unimplemented)", mnemonic); -#endif } }}; diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa index 963e07c77..807e40a6a 100644 --- a/src/arch/x86/isa/formats/unimp.isa +++ b/src/arch/x86/isa/formats/unimp.isa @@ -112,11 +112,7 @@ output decoder {{ WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return csprintf("%-10s", mnemonic); -#else return csprintf("%-10s (unimplemented)", mnemonic); -#endif } }};