From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 09:31:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~539
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e035dbaf9a37f672406a7b17f846d9ef7968ac4f;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 3aa447bf5..83ff38bf4 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -114,4 +114,23 @@ Available options to combine:
 Pseudocode for Horizontal-First Mode:
 
 ```
+   if BO[0]:
+       cond_ok = 1
+   else
+       cond_ok = not SVRMmode.ALL
+       for i in range(VL):
+           if predicate[i]:
+               testbit = CR[BI+32+srcstep*4]
+           else if not SVRMmode.sz:
+               continue
+           else testbit = SVRMmode.SNZ
+           el_cond_ok <- ¬(testbit ^ BO[1])
+           if SVRMmode.ALL:
+               if ~el_cond_ok:
+                   break
+               cond_ok &= el_cond_ok
+           else
+               if el_cond_ok:
+                   break
+               cond_ok |= el_cond_ok
 ```