From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Wed, 31 May 2023 19:41:27 +0000 (+0300)
Subject: power_insn: guess extra from reg instead of sel
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e039be3e0ab346a00cde982a61250ee3dc6705e3;p=openpower-isa.git

power_insn: guess extra from reg instead of sel
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 299c57a2..cf22226f 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -405,11 +405,10 @@ class SVP64Record:
 
     @cached_property
     def extras(self):
-        keys = {}
-        for key in ("in1", "in2", "in3", "cr_in", "cr_in2"):
-            keys[key] = _SelType.SRC
-        for key in ("out", "out2", "cr_out"):
-            keys[key] = _SelType.DST
+        keys = (
+            "in1", "in2", "in3", "cr_in", "cr_in2",
+            "out", "out2", "cr_out",
+        )
 
         idxmap = (
             _SVExtra.Idx0,