From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 30 May 2020 18:39:11 +0000 (+0100)
Subject: allow MultiCompUnit outputs to be Records, to capture Data.ok
X-Git-Tag: div_pipeline~732^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e03ddc4293c417e8967d50c9bd33a4da95513380;p=soc.git

allow MultiCompUnit outputs to be Records, to capture Data.ok
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index a8374f75..9518a3f0 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -233,8 +233,12 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         drl = []
         for i in range(self.n_dst):
             name = "data_r%d" % i
-            data_r = Signal(self.cu._get_dstwid(i), name=name, reset_less=True)
-            latchregister(m, self.get_out(i), data_r, alu_pulsem, name + "_l")
+            lro = self.get_out(i)
+            if isinstance(lro, Record):
+                data_r = Record.like(lro, name=name)
+            else:
+                data_r = Signal.like(lro, name=name, reset_less=True)
+            latchregister(m, lro, data_r, alu_pulsem, name + "_l")
             drl.append(data_r)
 
         # pass the operation to the ALU