From: lkcl <lkcl@web>
Date: Sat, 30 Apr 2022 20:14:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2527
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e0449c9bfb7e659a503965a406c5b2ecda9198ba;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 1a8bdc840..5bccb480e 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -70,8 +70,8 @@ CPU ISA.
 
 Vectorisation of the VSX Packed SIMD system makes no sense whatsoever,
 the sole exceptions potentially being any operations with 128-bit
-operands.
-SV effectively *replaces* VSX and provides,
+operands such as `vrlq` (Rotate Quad Word).
+SV effectively *replaces* VSX requiring far less instructions, and provides,
 at the very minimum, predication (which VSX was designed without).
 Thus all VSX Major Opcodes - all of them - are "unused" and must raise
 illegal instruction exceptions in SV Prefix Mode.