From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 18:58:13 +0000 (+0100) Subject: add debug output of DIV results X-Git-Tag: div_pipeline~133 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e04d4a3aa98868f840525fff1a8b32d8332f02ad;p=soc.git add debug output of DIV results --- diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 9041aa6d..af69d9d2 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -215,11 +215,15 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_int_o(res, alu, dec2) yield from ALUHelpers.get_xer_so(res, alu, dec2) + print ("res output", res) + yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) + print ("sim output", sim_o) + ALUHelpers.check_int_o(self, res, sim_o, code) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) ALUHelpers.check_xer_ov(self, res, sim_o, code)