From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 23 May 2013 09:19:33 +0000 (+0200)
Subject: Added missing newline to some error messages
X-Git-Tag: yosys-0.2.0~627
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e04d88cf226df77aab81c05d232250f50b1ea5bc;p=yosys.git

Added missing newline to some error messages
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 732bd5cb9..4e1afe92a 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -73,10 +73,10 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module,
 	log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
 
 	if (tpl->memories.size() != 0)
-		log_error("Technology map yielded memories -> this is not supported.");
+		log_error("Technology map yielded memories -> this is not supported.\n");
 
 	if (tpl->processes.size() != 0)
-		log_error("Technology map yielded processes -> this is not supported.");
+		log_error("Technology map yielded processes -> this is not supported.\n");
 
 	for (auto &it : tpl->wires) {
 		RTLIL::Wire *w = new RTLIL::Wire(*it.second);